From 74e22672d0be099e2e3fa3182b47059e3baf035e Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 3 Mar 2022 06:02:10 -0800 Subject: [PATCH] use register code generated by regz (#23) --- src/core/start.zig | 4 +- src/modules/chips/lpc1768/lpc1768.zig | 102 +- src/modules/chips/lpc1768/registers.zig | 40579 ++++++------- src/modules/chips/nrf52/registers.zig | 37659 +++++------- src/modules/chips/stm32f103/registers.zig | 46002 +++++++------- src/modules/chips/stm32f103/stm32f103.zig | 3 +- src/modules/chips/stm32f303/registers.zig | 63836 +++++++++++--------- src/modules/chips/stm32f303/stm32f303.zig | 13 +- tests/uart-sync.zig | 18 +- 9 files changed, 93419 insertions(+), 94797 deletions(-) diff --git a/src/core/start.zig b/src/core/start.zig index 27242c6..73f33da 100644 --- a/src/core/start.zig +++ b/src/core/start.zig @@ -12,7 +12,9 @@ fn isValidField(field_name: []const u8) bool { const VectorTable = microzig.chip.VectorTable; export const vector_table: VectorTable linksection("microzig_flash_start") = blk: { - var tmp: microzig.chip.VectorTable = .{}; + var tmp: microzig.chip.VectorTable = .{ + .initial_stack_pointer = microzig.config.end_of_stack, + }; if (@hasDecl(app, "interrupts")) { if (@typeInfo(app.interrupts) != .Struct) @compileLog("root.interrupts must be a struct"); diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index edf8614..907b7c9 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -1,9 +1,11 @@ const std = @import("std"); const micro = @import("microzig"); +const chip = @import("registers.zig"); +const regs = chip.registers; + +pub usingnamespace chip; pub const cpu = @import("cpu"); -pub const registers = @import("registers.zig"); -pub const VectorTable = registers.VectorTable; pub const PinTarget = enum(u2) { func00 = 0b00, func01 = 0b01, @@ -26,14 +28,14 @@ pub fn parsePin(comptime spec: []const u8) type { const _regs = struct { const name_suffix = std.fmt.comptimePrint("{d}", .{_port}); - const pinsel_reg = @field(registers.PINCONNECT, sel_reg_name); + const pinsel_reg = @field(regs.PINCONNECT, sel_reg_name); const pinsel_field = std.fmt.comptimePrint("P{d}_{d}", .{ _port, _pin }); - const dir = @field(registers.GPIO, "DIR" ++ name_suffix); - const pin = @field(registers.GPIO, "PIN" ++ name_suffix); - const set = @field(registers.GPIO, "SET" ++ name_suffix); - const clr = @field(registers.GPIO, "CLR" ++ name_suffix); - const mask = @field(registers.GPIO, "MASK" ++ name_suffix); + const dir = @field(regs.GPIO, "DIR" ++ name_suffix); + const pin = @field(regs.GPIO, "PIN" ++ name_suffix); + const set = @field(regs.GPIO, "SET" ++ name_suffix); + const clr = @field(regs.GPIO, "CLR" ++ name_suffix); + const mask = @field(regs.GPIO, "MASK" ++ name_suffix); }; return struct { @@ -48,7 +50,7 @@ pub fn parsePin(comptime spec: []const u8) type { pub fn routePin(comptime pin: type, function: PinTarget) void { var val = pin.regs.pinsel_reg.read(); - @field(val, pin.regs.pinsel_field) = @intToEnum(@TypeOf(@field(val, pin.regs.pinsel_field)), @enumToInt(function)); + @field(val, pin.regs.pinsel_field) = @enumToInt(function); pin.regs.pinsel_reg.write(val); } @@ -77,36 +79,40 @@ pub const gpio = struct { }; pub const uart = struct { - const RegisterDataBitsEnum = std.meta.fieldInfo(@TypeOf(registers.UART0.LCR.*).underlying_type, .WLS).field_type; pub const DataBits = enum(u2) { - five = @enumToInt(RegisterDataBitsEnum.@"5_BIT_CHARACTER_LENG"), - six = @enumToInt(RegisterDataBitsEnum.@"6_BIT_CHARACTER_LENG"), - seven = @enumToInt(RegisterDataBitsEnum.@"7_BIT_CHARACTER_LENG"), - eight = @enumToInt(RegisterDataBitsEnum.@"8_BIT_CHARACTER_LENG"), + five = 0, + six = 1, + seven = 2, + eight = 3, }; - const RegisterStopBitEnum = std.meta.fieldInfo(@TypeOf(registers.UART0.LCR.*).underlying_type, .SBS).field_type; pub const StopBits = enum(u1) { - one = @enumToInt(RegisterStopBitEnum.@"1_STOP_BIT_"), - two = @enumToInt(RegisterStopBitEnum.@"2_STOP_BITS_1_5_IF_"), + one = 0, + two = 1, }; - const RegisterParityEnum = std.meta.fieldInfo(@TypeOf(registers.UART0.LCR.*).underlying_type, .PS).field_type; pub const Parity = enum(u2) { - odd = @enumToInt(RegisterParityEnum.@"ODD_PARITY_NUMBER_O"), - even = @enumToInt(RegisterParityEnum.@"EVEN_PARITY_NUMBER_"), - mark = @enumToInt(RegisterParityEnum.@"FORCED_1_STICK_PARIT"), - space = @enumToInt(RegisterParityEnum.@"FORCED_0_STICK_PARIT"), + odd = 0, + even = 1, + mark = 2, + space = 3, + }; + + pub const CClkDiv = enum(u2) { + four = 0, + one = 1, + two = 2, + eight = 3, }; }; pub fn Uart(comptime index: usize) type { return struct { const UARTn = switch (index) { - 0 => registers.UART0, - 1 => registers.UART1, - 2 => registers.UART2, - 3 => registers.UART3, + 0 => regs.UART0, + 1 => regs.UART1, + 2 => regs.UART2, + 3 => regs.UART3, else => @compileError("LPC1768 has 4 UARTs available."), }; const Self = @This(); @@ -115,33 +121,33 @@ pub fn Uart(comptime index: usize) type { micro.debug.write("0"); switch (index) { 0 => { - registers.SYSCON.PCONP.modify(.{ .PCUART0 = 1 }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = .CCLK_DIV_4 }); + regs.SYSCON.PCONP.modify(.{ .PCUART0 = 1 }); + regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = @enumToInt(uart.CClkDiv.four) }); }, 1 => { - registers.SYSCON.PCONP.modify(.{ .PCUART1 = 1 }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = .CCLK_DIV_4 }); + regs.SYSCON.PCONP.modify(.{ .PCUART1 = 1 }); + regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = @enumToInt(uart.CClkDiv.four) }); }, 2 => { - registers.SYSCON.PCONP.modify(.{ .PCUART2 = 1 }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART2 = .CCLK_DIV_4 }); + regs.SYSCON.PCONP.modify(.{ .PCUART2 = 1 }); + regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART2 = @enumToInt(uart.CClkDiv.four) }); }, 3 => { - registers.SYSCON.PCONP.modify(.{ .PCUART3 = 1 }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART3 = .CCLK_DIV_4 }); + regs.SYSCON.PCONP.modify(.{ .PCUART3 = 1 }); + regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART3 = @enumToInt(uart.CClkDiv.four) }); }, else => unreachable, } micro.debug.write("1"); - UARTn.LCR.write(.{ + UARTn.LCR.modify(.{ // 8N1 - .WLS = @intToEnum(std.meta.fieldInfo(@TypeOf(UARTn.LCR.*).underlying_type, .WLS).field_type, @enumToInt(config.data_bits)), - .SBS = @intToEnum(std.meta.fieldInfo(@TypeOf(UARTn.LCR.*).underlying_type, .SBS).field_type, @enumToInt(config.stop_bits)), - .PE = if (config.parity) |_| .ENABLE_PARITY_GENERA else .DISABLE_PARITY_GENER, - .PS = if (config.parity) |p| @intToEnum(std.meta.fieldInfo(@TypeOf(UARTn.LCR.*).underlying_type, .PS).field_type, @enumToInt(p)) else .ODD_PARITY_NUMBER_O, - .BC = .DISABLE_BREAK_TRANSM, - .DLAB = .ENABLE_ACCESS_TO_DIV, + .WLS = @enumToInt(config.data_bits), + .SBS = @enumToInt(config.stop_bits), + .PE = if (config.parity) |_| @as(u1, 0) else @as(u1, 1), + .PS = if (config.parity) |p| @enumToInt(p) else @enumToInt(uart.Parity.odd), + .BC = 0, + .DLAB = 1, }); micro.debug.write("2"); @@ -158,10 +164,10 @@ pub fn Uart(comptime index: usize) type { const regval = std.math.cast(u16, divider) catch return error.UnsupportedBaudRate; - UARTn.DLL.write(.{ .DLLSB = @truncate(u8, regval >> 0x00) }); - UARTn.DLM.write(.{ .DLMSB = @truncate(u8, regval >> 0x08) }); + UARTn.DLL.modify(.{ .DLLSB = @truncate(u8, regval >> 0x00) }); + UARTn.DLM.modify(.{ .DLMSB = @truncate(u8, regval >> 0x08) }); - UARTn.LCR.modify(.{ .DLAB = .DISABLE_ACCESS_TO_DI }); + UARTn.LCR.modify(.{ .DLAB = 0 }); return Self{}; } @@ -169,8 +175,8 @@ pub fn Uart(comptime index: usize) type { pub fn canWrite(self: Self) bool { _ = self; return switch (UARTn.LSR.read().THRE) { - .VALID => true, - .THR_IS_EMPTY_ => false, + 0 => true, // valid + 1 => false, // is empty }; } pub fn tx(self: Self, ch: u8) void { @@ -181,8 +187,8 @@ pub fn Uart(comptime index: usize) type { pub fn canRead(self: Self) bool { _ = self; return switch (UARTn.LSR.read().RDR) { - .EMPTY => false, - .NOTEMPTY => true, + 0 => false, // empty + 1 => true, // not empty }; } pub fn rx(self: Self) u8 { diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig index e0d36c5..160617f 100644 --- a/src/modules/chips/lpc1768/registers.zig +++ b/src/modules/chips/lpc1768/registers.zig @@ -1,21800 +1,18801 @@ -// generated using svd2zig.py -// DO NOT EDIT -// based on LPC176x5x version 0.2 -const mmio = @import("microzig-mmio").mmio; -const Name = "LPC176x5x"; -pub const WDT = extern struct { - pub const Address: u32 = 0x40000000; - // byte offset: 0 Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer. - pub const MOD = mmio(Address + 0x00000000, 32, packed struct { - WDEN: enum(u1) { // bit offset: 0 desc: Watchdog enable bit. This bit is Set Only. - @"STOP" = 0, // desc: The watchdog timer is stopped. - @"RUN" = 1, // desc: The watchdog timer is running. - }, - WDRESET: enum(u1) { // bit offset: 1 desc: Watchdog reset enable bit. This bit is Set Only. See Table 652. - @"NORESET" = 0, // desc: A watchdog timeout will not cause a chip reset. - @"RESET" = 1, // desc: A watchdog timeout will cause a chip reset. - }, - WDTOF: u1, // bit offset: 2 desc: Watchdog time-out flag. Set when the watchdog timer times out, cleared by software. - WDINT: u1, // bit offset: 3 desc: Watchdog interrupt flag. Cleared by software. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Watchdog timer constant register. The value in this register determines the time-out value. - pub const TC = mmio(Address + 0x00000004, 32, packed struct { - Count: u32, // bit offset: 0 desc: Watchdog time-out interval. - }); - // byte offset: 8 Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. - pub const FEED = mmio(Address + 0x00000008, 32, packed struct { - Feed: u8, // bit offset: 0 desc: Feed value should be 0xAA followed by 0x55. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Watchdog timer value register. This register reads out the current value of the Watchdog timer. - pub const TV = mmio(Address + 0x0000000c, 32, packed struct { - Count: u32, // bit offset: 0 desc: Counter timer value. - }); - // byte offset: 16 Watchdog clock select register. - pub const CLKSEL = mmio(Address + 0x00000010, 32, packed struct { - CLKSEL: enum(u2) { // bit offset: 0 desc: Selects source of WDT clock - @"IRC" = 0, // desc: IRC - @"PCLK" = 1, // desc: Peripheral clock - @"RTCOSC" = 2, // desc: RTC oscillator - // @"RESERVED", // desc: Reserved. - _, // non-exhaustive - }, - // RESERVED: u30, // bit offset: 1 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved29: u1 = 0, - reserved28: u1 = 0, - reserved27: u1 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - LOCK: enum(u1) { // bit offset: 31 desc: If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0. - @"UNLOCKED" = 0, // desc: This bit is set to 0 on any reset. It cannot be cleared by software. - @"LOCKED" = 1, // desc: Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register cannot be modified. - }, - }); -}; -pub const TIMER0 = extern struct { - pub const Address: u32 = 0x40004000; - // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. - pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. - pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. - pub const TC = mmio(Address + 0x00000008, 32, packed struct { - TC: u32, // bit offset: 0 desc: Timer counter value. - }); - // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. - pub const PR = mmio(Address + 0x0000000c, 32, packed struct { - PM: u32, // bit offset: 0 desc: Prescale counter maximum value. - }); - // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. - pub const PC = mmio(Address + 0x00000010, 32, packed struct { - PC: u32, // bit offset: 0 desc: Prescale counter value. - }); - // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. - pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. - }, - MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. - @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled - }, - MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. - pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event - @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event - @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 60 External Match Register. The EMR controls the external match pins. - pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge - @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. - @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. - @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. - }, - CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn - @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn - _, // non-exhaustive - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const TIMER1 = extern struct { - pub const Address: u32 = 0x40008000; - // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. - pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. - pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. - pub const TC = mmio(Address + 0x00000008, 32, packed struct { - TC: u32, // bit offset: 0 desc: Timer counter value. - }); - // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. - pub const PR = mmio(Address + 0x0000000c, 32, packed struct { - PM: u32, // bit offset: 0 desc: Prescale counter maximum value. - }); - // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. - pub const PC = mmio(Address + 0x00000010, 32, packed struct { - PC: u32, // bit offset: 0 desc: Prescale counter value. - }); - // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. - pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. - }, - MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. - @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled - }, - MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. - pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event - @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event - @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 60 External Match Register. The EMR controls the external match pins. - pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge - @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. - @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. - @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. - }, - CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn - @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn - _, // non-exhaustive - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const UART0 = extern struct { - pub const Address: u32 = 0x4000c000; - // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). - pub const RBR = mmio(Address + 0x00000000, 32, packed struct { - RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). - pub const THR = mmio(Address + 0x00000000, 32, packed struct { - THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLL = mmio(Address + 0x00000000, 32, packed struct { - DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLM = mmio(Address + 0x00000004, 32, packed struct { - DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. - @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. - @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. - }, - THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. - @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. - @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. - }, - RXIE: enum(u1) { // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. - @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. - @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTEN: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. - @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. - @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. - }, - ABTOINTEN: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. - @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. - @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. - @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. - @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. - }, - INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). - @"1_RECEIVE_LINE_S" = 3, // desc: 1 - Receive Line Status (RLS). - @"2A__RECEIVE_DATA_AV" = 2, // desc: 2a - Receive Data Available (RDA). - @"2B__CHARACTER_TIME_" = 6, // desc: 2b - Character Time-out Indicator (CTI). - @"3_THRE_INTERRUPT" = 1, // desc: 3 - THRE Interrupt - _, // non-exhaustive - }, - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. - ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. - pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO Enable. - @"UARTN_FIFOS_ARE_DISA" = 0, // desc: UARTn FIFOs are disabled. Must not be used in the application. - @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. - }, - RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. - }, - TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. - }, - DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. - @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). - @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). - @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). - @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. - pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. - @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length - @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length - @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length - @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length - }, - SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select - @"1_STOP_BIT_" = 0, // desc: 1 stop bit. - @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if UnLCR[1:0]=00). - }, - PE: enum(u1) { // bit offset: 3 desc: Parity Enable. - @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. - @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. - }, - PS: enum(u2) { // bit offset: 4 desc: Parity Select - @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. - @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. - @"FORCED_1_STICK_PARIT" = 2, // desc: Forced 1 stick parity. - @"FORCED_0_STICK_PARIT" = 3, // desc: Forced 0 stick parity. - }, - BC: enum(u1) { // bit offset: 6 desc: Break Control - @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. - @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. - }, - DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit - @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. - @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. - pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. - @"EMPTY" = 0, // desc: The UARTn receiver FIFO is empty. - @"NOTEMPTY" = 1, // desc: The UARTn receiver FIFO is not empty. - }, - OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. - @"INACTIVE" = 0, // desc: Overrun error status is inactive. - @"ACTIVE" = 1, // desc: Overrun error status is active. - }, - PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Parity error status is inactive. - @"ACTIVE" = 1, // desc: Parity error status is active. - }, - FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Framing error status is inactive. - @"ACTIVE" = 1, // desc: Framing error status is active. - }, - BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Break interrupt status is inactive. - @"ACTIVE" = 1, // desc: Break interrupt status is active. - }, - THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. - @"VALIDDATA" = 0, // desc: UnTHR contains valid data. - @"EMPTY" = 1, // desc: UnTHR is empty. - }, - TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. - @"VALIDDATA" = 0, // desc: UnTHR and/or the UnTSR contains valid data. - @"EMPTY" = 1, // desc: UnTHR and the UnTSR are empty. - }, - RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. - @"NOERROR" = 0, // desc: UnRBR contains no UARTn RX errors or UnFCR[0]=0. - @"ERRORS" = 1, // desc: UARTn RBR contains at least one UARTn RX error. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { - PAD: u8, // bit offset: 0 desc: A readable, writable byte. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: enum(u1) { // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. - @"AUTO_BAUD_STOP_AUTO" = 0, // desc: Auto-baud stop (auto-baud is not running). - @"AUTO_BAUD_START_AUT" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. - }, - MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. - @"MODE_0_" = 0, // desc: Mode 0. - @"MODE_1_" = 1, // desc: Mode 1. - }, - AUTORESTART: enum(u1) { // bit offset: 2 desc: Restart bit. - @"NO_RESTART_" = 0, // desc: No restart. - @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UARTn Rx falling edge) - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = mmio(Address + 0x00000028, 32, packed struct { - DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. - MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. - pub const TER = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. - pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: enum(u1) { // bit offset: 0 desc: NMM enable. - @"DISABLED" = 0, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. - @"ENABLED" = 1, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation. - }, - RXDIS: enum(u1) { // bit offset: 1 desc: Receiver enable. - @"ENABLED" = 0, // desc: The receiver is enabled. - @"DISABLED" = 1, // desc: The receiver is disabled. - }, - AADEN: enum(u1) { // bit offset: 2 desc: AAD enable. - @"DISABLED" = 0, // desc: Auto Address Detect (AAD) is disabled. - @"ENABLED" = 1, // desc: Auto Address Detect (AAD) is enabled. - }, - // RESERVED: u1, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. - @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. - @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. - }, - OINV: enum(u1) { // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. - @"DIRLOW" = 0, // desc: The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. - @"DIRHIGH" = 1, // desc: The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. - pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { - ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 84 RS-485/EIA-485 direction control delay. - pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { - DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const UART1 = extern struct { - pub const Address: u32 = 0x40010000; - // byte offset: 0 DLAB =0 Receiver Buffer Register. Contains the next received character to be read. - pub const RBR = mmio(Address + 0x00000000, 32, packed struct { - RBR: u8, // bit offset: 0 desc: The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO. - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 DLAB =0. Transmit Holding Register. The next character to be transmitted is written here. - pub const THR = mmio(Address + 0x00000000, 32, packed struct { - THR: u8, // bit offset: 0 desc: Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. - pub const DLL = mmio(Address + 0x00000000, 32, packed struct { - DLLSB: u8, // bit offset: 0 desc: The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. - pub const DLM = mmio(Address + 0x00000004, 32, packed struct { - DLMSB: u8, // bit offset: 0 desc: The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt. - @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. - @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. - }, - THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]. - @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. - @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. - }, - RXIE: enum(u1) { // bit offset: 2 desc: RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. - @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. - @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. - }, - MSIE: enum(u1) { // bit offset: 3 desc: Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]. - @"DISABLE_THE_MODEM_IN" = 0, // desc: Disable the modem interrupt. - @"ENABLE_THE_MODEM_INT" = 1, // desc: Enable the modem interrupt. - }, - // RESERVED: u3, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CTSIE: enum(u1) { // bit offset: 7 desc: CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set. - @"DISABLE_THE_CTS_INTE" = 0, // desc: Disable the CTS interrupt. - @"ENABLE_THE_CTS_INTER" = 1, // desc: Enable the CTS interrupt. - }, - ABEOIE: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. - @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. - @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. - }, - ABTOIE: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. - @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. - @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. - @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. - @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. - }, - INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). - @"RLS" = 3, // desc: 1 - Receive Line Status (RLS). - @"RDA" = 2, // desc: 2a - Receive Data Available (RDA). - @"CTI" = 6, // desc: 2b - Character Time-out Indicator (CTI). - @"THRE" = 1, // desc: 3 - THRE Interrupt. - @"MODEM" = 0, // desc: 4 - Modem Interrupt. - _, // non-exhaustive - }, - // RESERVED: u2, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - FIFOENABLE: u2, // bit offset: 6 desc: Copies of FCR[0]. - ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. - // RESERVED: u22, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 FIFO Control Register. Controls UART1 FIFO usage and modes. - pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO enable. - @"MUST_NOT_BE_USED_IN_" = 0, // desc: Must not be used in the application. - @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs. - }, - RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UART1 FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing. - }, - TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UART1 FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing. - }, - DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1. - // RESERVED: u2, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated. - @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). - @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). - @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). - @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. - pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. - @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length. - @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length. - @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length. - @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length. - }, - SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select. - @"1_STOP_BIT_" = 0, // desc: 1 stop bit. - @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if LCR[1:0]=00). - }, - PE: enum(u1) { // bit offset: 3 desc: Parity Enable. - @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. - @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. - }, - PS: enum(u2) { // bit offset: 4 desc: Parity Select. - @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. - @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. - @"FORCED1STICK_PAR" = 2, // desc: Forced 1 stick parity. - @"FORCED0STICK_PAR" = 3, // desc: Forced 0 stick parity. - }, - BC: enum(u1) { // bit offset: 6 desc: Break Control. - @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. - @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high. - }, - DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit (DLAB) - @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. - @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Modem Control Register. Contains controls for flow control handshaking and loopback mode. - pub const MCR = mmio(Address + 0x00000010, 32, packed struct { - DTRCTRL: u1, // bit offset: 0 desc: DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active. - RTSCTRL: u1, // bit offset: 1 desc: RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. - // RESERVED: u2, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - LMS: enum(u1) { // bit offset: 4 desc: Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR. - @"DISABLE_MODEM_LOOPBA" = 0, // desc: Disable modem loopback mode. - @"ENABLE_MODEM_LOOPBAC" = 1, // desc: Enable modem loopback mode. - }, - // RESERVED: u1, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - RTSEN: enum(u1) { // bit offset: 6 desc: RTS enable. - @"DISABLE_AUTO_RTS_FLO" = 0, // desc: Disable auto-rts flow control. - @"ENABLE_AUTO_RTS_FLOW" = 1, // desc: Enable auto-rts flow control. - }, - CTSEN: enum(u1) { // bit offset: 7 desc: CTS enable. - @"DISABLE_AUTO_CTS_FLO" = 0, // desc: Disable auto-cts flow control. - @"ENABLE_AUTO_CTS_FLOW" = 1, // desc: Enable auto-cts flow control. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. - pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty. - @"EMPTY" = 0, // desc: The UART1 receiver FIFO is empty. - @"NOTEMPTY" = 1, // desc: The UART1 receiver FIFO is not empty. - }, - OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. - @"INACTIVE" = 0, // desc: Overrun error status is inactive. - @"ACTIVE" = 1, // desc: Overrun error status is active. - }, - PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO. - @"INACTIVE" = 0, // desc: Parity error status is inactive. - @"ACTIVE" = 1, // desc: Parity error status is active. - }, - FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO. - @"INACTIVE" = 0, // desc: Framing error status is inactive. - @"ACTIVE" = 1, // desc: Framing error status is active. - }, - BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO. - @"INACTIVE" = 0, // desc: Break interrupt status is inactive. - @"ACTIVE" = 1, // desc: Break interrupt status is active. - }, - THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write. - @"VALID" = 0, // desc: THR contains valid data. - @"THR_IS_EMPTY_" = 1, // desc: THR is empty. - }, - TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. - @"VALID" = 0, // desc: THR and/or the TSR contains valid data. - @"EMPTY" = 1, // desc: THR and the TSR are empty. - }, - RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO. - @"NOERROR" = 0, // desc: RBR contains no UART1 RX errors or FCR[0]=0. - @"ERRORS" = 1, // desc: UART1 RBR contains at least one UART1 RX error. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Modem Status Register. Contains handshake signal status flags. - pub const MSR = mmio(Address + 0x00000018, 32, packed struct { - DCTS: enum(u1) { // bit offset: 0 desc: Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. - @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, CTS. - @"STATE_CHANGE_DETECTE" = 1, // desc: State change detected on modem input, CTS. - }, - DDSR: enum(u1) { // bit offset: 1 desc: Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. - @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, DSR. - @"STATE_CHANGE_DETECTE" = 1, // desc: State change detected on modem input, DSR. - }, - TERI: enum(u1) { // bit offset: 2 desc: Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read. - @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, RI. - @"LOW_TO_HIGH_TRANSITI" = 1, // desc: Low-to-high transition detected on RI. - }, - DDCD: enum(u1) { // bit offset: 3 desc: Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. - @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, DCD. - @"STATE_CHANGE_DETECTE" = 1, // desc: State change detected on modem input, DCD. - }, - CTS: u1, // bit offset: 4 desc: Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. - DSR: u1, // bit offset: 5 desc: Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. - RI: u1, // bit offset: 6 desc: Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. - DCD: u1, // bit offset: 7 desc: Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { - Pad: u8, // bit offset: 0 desc: A readable, writable byte. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: enum(u1) { // bit offset: 0 desc: Auto-baud start bit. This bit is automatically cleared after auto-baud completion. - @"STOP" = 0, // desc: Auto-baud stop (auto-baud is not running). - @"START" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. - }, - MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. - @"MODE_0_" = 0, // desc: Mode 0. - @"MODE_1_" = 1, // desc: Mode 1. - }, - AUTORESTART: enum(u1) { // bit offset: 2 desc: Auto-baud restart bit. - @"NO_RESTART" = 0, // desc: No restart - @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UART1 Rx falling edge) - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only). - @"WRITING_A_0_HAS_NO_I" = 0, // desc: Writing a 0 has no impact. - @"WRITING_A_1_WILL_CLE" = 1, // desc: Writing a 1 will clear the corresponding interrupt in the IIR. - }, - ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only). - @"WRITING_A_0_HAS_NO_I" = 0, // desc: Writing a 0 has no impact. - @"WRITING_A_1_WILL_CLE" = 1, // desc: Writing a 1 will clear the corresponding interrupt in the IIR. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = mmio(Address + 0x00000028, 32, packed struct { - DIVADDVAL: u4, // bit offset: 0 desc: Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate. - MULVAL: u4, // bit offset: 4 desc: Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. - pub const TER = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. - pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: enum(u1) { // bit offset: 0 desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_IN_THIS_MOD" = 1, // desc: Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. - }, - RXDIS: enum(u1) { // bit offset: 1 desc: Receive enable. - @"ENABLED_" = 0, // desc: Enabled. - @"DISABLED_" = 1, // desc: Disabled. - }, - AADEN: enum(u1) { // bit offset: 2 desc: Auto Address Detect (AAD) enable. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - SEL: enum(u1) { // bit offset: 3 desc: Direction control. - @"RTS_IF_DIRECTION_CO" = 0, // desc: RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. - @"DTR_IF_DIRECTION_CO" = 1, // desc: DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. - }, - DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. - @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. - @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. - }, - OINV: enum(u1) { // bit offset: 5 desc: Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. - @"LOW_THE_DIRECTION_C" = 0, // desc: LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. - @"HIGH_THE_DIRECTION_" = 1, // desc: HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. - pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { - ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 84 RS-485/EIA-485 direction control delay. - pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { - DLY: u8, // bit offset: 0 desc: Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const PWM1 = extern struct { - pub const Address: u32 = 0x40018000; - // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending. - pub const IR = mmio(Address + 0x00000000, 32, packed struct { - PWMMR0INT: u1, // bit offset: 0 desc: Interrupt flag for PWM match channel 0. - PWMMR1INT: u1, // bit offset: 1 desc: Interrupt flag for PWM match channel 1. - PWMMR2INT: u1, // bit offset: 2 desc: Interrupt flag for PWM match channel 2. - PWMMR3INT: u1, // bit offset: 3 desc: Interrupt flag for PWM match channel 3. - PWMCAP0INT: u1, // bit offset: 4 desc: Interrupt flag for capture input 0 - PWMCAP1INT: u1, // bit offset: 5 desc: Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR). - // RESERVED: u2, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - PWMMR4INT: u1, // bit offset: 8 desc: Interrupt flag for PWM match channel 4. - PWMMR5INT: u1, // bit offset: 9 desc: Interrupt flag for PWM match channel 5. - PWMMR6INT: u1, // bit offset: 10 desc: Interrupt flag for PWM match channel 6. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. - pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CE: enum(u1) { // bit offset: 0 desc: Counter Enable - @"THE_PWM_TIMER_COUNTE" = 1, // desc: The PWM Timer Counter and PWM Prescale Counter are enabled for counting. - @"THE_COUNTERS_ARE_DIS" = 0, // desc: The counters are disabled. - }, - CR: enum(u1) { // bit offset: 1 desc: Counter Reset - @"THE_PWM_TIMER_COUNTE" = 1, // desc: The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero. - @"CLEAR_RESET_" = 0, // desc: Clear reset. - }, - // RESERVED: u1, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - PWMEN: enum(u1) { // bit offset: 3 desc: PWM Enable - @"PWM_MODE_IS_ENABLED_" = 1, // desc: PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective. - @"TIMER_MODE_IS_ENABLE" = 0, // desc: Timer mode is enabled (counter resets to 0). - }, - MDIS: enum(u1) { // bit offset: 4 desc: Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1). - @"MASTER_USE_PWM0_IS_" = 1, // desc: Master use. PWM0 is the master, and both PWMs are enabled for counting. - @"INDIVIDUAL_USE_THE_" = 0, // desc: Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs. - }, - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. - pub const TC = mmio(Address + 0x00000008, 32, packed struct { - TC: u32, // bit offset: 0 desc: Timer counter value. - }); - // byte offset: 12 Prescale Register. Determines how often the PWM counter is incremented. - pub const PR = mmio(Address + 0x0000000c, 32, packed struct { - PM: u32, // bit offset: 0 desc: Prescale counter maximum value. - }); - // byte offset: 16 Prescale Counter. Prescaler for the main PWM counter. - pub const PC = mmio(Address + 0x00000010, 32, packed struct { - PC: u32, // bit offset: 0 desc: Prescale counter value. - }); - // byte offset: 20 Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs. - pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - PWMMR0I: enum(u1) { // bit offset: 0 desc: Interrupt PWM0 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR0" = 1, // desc: Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC. - }, - PWMMR0R: enum(u1) { // bit offset: 1 desc: Reset PWM0 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR0_THE" = 1, // desc: Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it. - }, - PWMMR0S: enum(u1) { // bit offset: 2 desc: Stop PWM0 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR0_THE_" = 1, // desc: Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. - }, - PWMMR1I: enum(u1) { // bit offset: 3 desc: Interrupt PWM1 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR1" = 1, // desc: Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC. - }, - PWMMR1R: enum(u1) { // bit offset: 4 desc: Reset PWM1 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR1_THE" = 1, // desc: Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it. - }, - PWMMR1S: enum(u1) { // bit offset: 5 desc: Stop PWM1 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR1_THE_" = 1, // desc: Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC. - }, - PWMMR2I: enum(u1) { // bit offset: 6 desc: Interrupt PWM0 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR2" = 1, // desc: Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC. - }, - PWMMR2R: enum(u1) { // bit offset: 7 desc: Reset PWM0 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR2_THE" = 1, // desc: Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it. - }, - PWMMR2S: enum(u1) { // bit offset: 8 desc: Stop PWM0 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR2_THE_" = 1, // desc: Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. - }, - PWMMR3I: enum(u1) { // bit offset: 9 desc: Interrupt PWM3 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR3" = 1, // desc: Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC. - }, - PWMMR3R: enum(u1) { // bit offset: 10 desc: Reset PWM3 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR3_THE" = 1, // desc: Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it. - }, - PWMMR3S: enum(u1) { // bit offset: 11 desc: Stop PWM0 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR3_THE_" = 1, // desc: Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. - }, - PWMMR4I: enum(u1) { // bit offset: 12 desc: Interrupt PWM4 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR4" = 1, // desc: Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC. - }, - PWMMR4R: enum(u1) { // bit offset: 13 desc: Reset PWM4 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR4_THE" = 1, // desc: Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it. - }, - PWMMR4S: enum(u1) { // bit offset: 14 desc: Stop PWM4 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR4_THE_" = 1, // desc: Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC. - }, - PWMMR5I: enum(u1) { // bit offset: 15 desc: Interrupt PWM5 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR5" = 1, // desc: Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC. - }, - PWMMR5R: enum(u1) { // bit offset: 16 desc: Reset PWM5 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR5_THE" = 1, // desc: Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it. - }, - PWMMR5S: enum(u1) { // bit offset: 17 desc: Stop PWM5 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR5_THE_" = 1, // desc: Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC. - }, - PWMMR6I: enum(u1) { // bit offset: 18 desc: Interrupt PWM6 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR6" = 1, // desc: Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC. - }, - PWMMR6R: enum(u1) { // bit offset: 19 desc: Reset PWM6 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR6_THE" = 1, // desc: Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it. - }, - PWMMR6S: enum(u1) { // bit offset: 20 desc: Stop PWM6 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR6_THE_" = 1, // desc: Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC. - }, - // RESERVED: u11, // bit offset: 21 desc: Reserved. Read value is undefined, only zero should be written. - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 32 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event. - pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0_R: enum(u1) { // bit offset: 0 desc: Capture on PWMn_CAP0 rising edge - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"RISING_EDGE_A_SYNCH" = 1, // desc: Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC. - }, - CAP0_F: enum(u1) { // bit offset: 1 desc: Capture on PWMn_CAP0 falling edge - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"FALLING_EDGE_A_SYNC" = 1, // desc: Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC. - }, - CAP0_I: enum(u1) { // bit offset: 2 desc: Interrupt on PWMn_CAP0 event - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"INTERRUPT_A_CR0_LOA" = 1, // desc: Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt. - }, - CAP1_R: enum(u1) { // bit offset: 3 desc: Capture on PWMn_CAP1 rising edge. Reserved for PWM0. - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"RISING_EDGE_A_SYNCH" = 1, // desc: Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC. - }, - CAP1_F: enum(u1) { // bit offset: 4 desc: Capture on PWMn_CAP1 falling edge. Reserved for PWM0. - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"FALLING_EDGE_A_SYNC" = 1, // desc: Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC. - }, - CAP1_I: enum(u1) { // bit offset: 5 desc: Interrupt on PWMn_CAP1 event. Reserved for PWM0. - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"INTERRUPT_A_CR1_LOA" = 1, // desc: Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - PWMSEL2: enum(u1) { // bit offset: 2 desc: PWM[2] output single/double edge mode control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL3: enum(u1) { // bit offset: 3 desc: PWM[3] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL4: enum(u1) { // bit offset: 4 desc: PWM[4] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL5: enum(u1) { // bit offset: 5 desc: PWM[5] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL6: enum(u1) { // bit offset: 6 desc: PWM[6] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - // RESERVED: u2, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - PWMENA1: enum(u1) { // bit offset: 9 desc: PWM[1] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA2: enum(u1) { // bit offset: 10 desc: PWM[2] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA3: enum(u1) { // bit offset: 11 desc: PWM[3] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA4: enum(u1) { // bit offset: 12 desc: PWM[4] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA5: enum(u1) { // bit offset: 13 desc: PWM[5] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA6: enum(u1) { // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - // RESERVED: u17, // bit offset: 15 desc: Unused, always zero. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - PWMSEL2: enum(u1) { // bit offset: 2 desc: PWM[2] output single/double edge mode control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL3: enum(u1) { // bit offset: 3 desc: PWM[3] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL4: enum(u1) { // bit offset: 4 desc: PWM[4] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL5: enum(u1) { // bit offset: 5 desc: PWM[5] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL6: enum(u1) { // bit offset: 6 desc: PWM[6] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - // RESERVED: u2, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - PWMENA1: enum(u1) { // bit offset: 9 desc: PWM[1] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA2: enum(u1) { // bit offset: 10 desc: PWM[2] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA3: enum(u1) { // bit offset: 11 desc: PWM[3] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA4: enum(u1) { // bit offset: 12 desc: PWM[4] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA5: enum(u1) { // bit offset: 13 desc: PWM[5] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA6: enum(u1) { // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - // RESERVED: u17, // bit offset: 15 desc: Unused, always zero. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 64 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR4 = mmio(Address + 0x00000040, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 68 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR5 = mmio(Address + 0x00000044, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 72 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR6 = mmio(Address + 0x00000048, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 76 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. - pub const PCR = mmio(Address + 0x0000004c, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - PWMSEL2: enum(u1) { // bit offset: 2 desc: PWM[2] output single/double edge mode control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL3: enum(u1) { // bit offset: 3 desc: PWM[3] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL4: enum(u1) { // bit offset: 4 desc: PWM[4] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL5: enum(u1) { // bit offset: 5 desc: PWM[5] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL6: enum(u1) { // bit offset: 6 desc: PWM[6] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - // RESERVED: u2, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - PWMENA1: enum(u1) { // bit offset: 9 desc: PWM[1] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA2: enum(u1) { // bit offset: 10 desc: PWM[2] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA3: enum(u1) { // bit offset: 11 desc: PWM[3] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA4: enum(u1) { // bit offset: 12 desc: PWM[4] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA5: enum(u1) { // bit offset: 13 desc: PWM[5] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA6: enum(u1) { // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - // RESERVED: u17, // bit offset: 15 desc: Unused, always zero. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 80 Load Enable Register. Enables use of updated PWM match values. - pub const LER = mmio(Address + 0x00000050, 32, packed struct { - MAT0LATCHEN: u1, // bit offset: 0 desc: Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7. - MAT1LATCHEN: u1, // bit offset: 1 desc: Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details. - MAT2LATCHEN: u1, // bit offset: 2 desc: Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details. - MAT3LATCHEN: u1, // bit offset: 3 desc: Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details. - MAT4LATCHEN: u1, // bit offset: 4 desc: Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details. - MAT5LATCHEN: u1, // bit offset: 5 desc: Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details. - MAT6LATCHEN: u1, // bit offset: 6 desc: Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details. - // RESERVED: u25, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - MOD: enum(u2) { // bit offset: 0 desc: Counter/ Timer Mode - @"TIMER_MODE_THE_TC_I" = 0, // desc: Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register. - @"RISING_EDGE_COUNTER_" = 1, // desc: Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2. - @"FALLING_EDGE_COUNTER" = 2, // desc: Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2. - @"DUAL_EDGE_COUNTER_MO" = 3, // desc: Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2. - }, - CIS: enum(u2) { // bit offset: 2 desc: Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved. - @"FOR_PWM0_00_EQ_PWM0_" = 0, // desc: For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved) - _, // non-exhaustive - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const I2C0 = extern struct { - pub const Address: u32 = 0x4001c000; - // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AA: u1, // bit offset: 2 desc: Assert acknowledge flag. - SI: u1, // bit offset: 3 desc: I2C interrupt flag. - STO: u1, // bit offset: 4 desc: STOP flag. - STA: u1, // bit offset: 5 desc: START flag. - I2EN: u1, // bit offset: 6 desc: I2C interface enable. - // RESERVED: u25, // bit offset: 7 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. - pub const STAT = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: These bits are unused and are always 0. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. - pub const DAT = mmio(Address + 0x00000008, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. - pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { - SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. - pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { - SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AAC: u1, // bit offset: 2 desc: Assert acknowledge Clear bit. - SIC: u1, // bit offset: 3 desc: I2C interrupt Clear bit. - // RESERVED: u1, // bit offset: 4 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - STAC: u1, // bit offset: 5 desc: START flag Clear bit. - I2ENC: u1, // bit offset: 6 desc: I2C interface Disable bit. - // RESERVED: u1, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Monitor mode control register. - pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { - MM_ENA: enum(u1) { // bit offset: 0 desc: Monitor mode enable. - @"MONITOR_MODE_DISABLE" = 0, // desc: Monitor mode disabled. - @"THE_I_2C_MODULE_WILL" = 1, // desc: The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. - }, - ENA_SCL: enum(u1) { // bit offset: 1 desc: SCL output enable. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] - }, - MATCH_ALL: enum(u1) { // bit offset: 2 desc: Select interrupt register match. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from reserved bits is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. - pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 I2C Slave address mask register - pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 I2C Slave address mask register - pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 I2C Slave address mask register - pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 60 I2C Slave address mask register - pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const SPI = extern struct { - pub const Address: u32 = 0x40020000; - // byte offset: 0 SPI Control Register. This register controls the operation of the SPI. - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - BITENABLE: enum(u1) { // bit offset: 2 desc: The SPI controller sends and receives 8 bits of data per transfer. - @"THE_SPI_CONTROLLER_S" = 1, // desc: The SPI controller sends and receives the number of bits selected by bits 11:8. - _, // non-exhaustive - }, - CPHA: enum(u1) { // bit offset: 3 desc: Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending. - @"FIRST_EDGE" = 0, // desc: Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal. - @"SECOND_EDGE" = 1, // desc: Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active. - }, - CPOL: enum(u1) { // bit offset: 4 desc: Clock polarity control. - @"SCK_IS_ACTIVE_HIGH_" = 0, // desc: SCK is active high. - @"SCK_IS_ACTIVE_LOW_" = 1, // desc: SCK is active low. - }, - MSTR: enum(u1) { // bit offset: 5 desc: Master mode select. - @"SLAVE" = 0, // desc: The SPI operates in Slave mode. - @"MASTER" = 1, // desc: The SPI operates in Master mode. - }, - LSBF: enum(u1) { // bit offset: 6 desc: LSB First controls which direction each byte is shifted when transferred. - @"MSB" = 0, // desc: SPI data is transferred MSB (bit 7) first. - @"LSB" = 1, // desc: SPI data is transferred LSB (bit 0) first. - }, - SPIE: enum(u1) { // bit offset: 7 desc: Serial peripheral interrupt enable. - @"INTBLOCK" = 0, // desc: SPI interrupts are inhibited. - @"HWINT" = 1, // desc: A hardware interrupt is generated each time the SPIF or MODF bits are activated. - }, - BITS: enum(u4) { // bit offset: 8 desc: When bit 2 of this register is 1, this field controls the number of bits per transfer: - @"8_BITS_PER_TRANSFER" = 8, // desc: 8 bits per transfer - @"9_BITS_PER_TRANSFER" = 9, // desc: 9 bits per transfer - @"10_BITS_PER_TRANSFER" = 10, // desc: 10 bits per transfer - @"11_BITS_PER_TRANSFER" = 11, // desc: 11 bits per transfer - @"12_BITS_PER_TRANSFER" = 12, // desc: 12 bits per transfer - @"13_BITS_PER_TRANSFER" = 13, // desc: 13 bits per transfer - @"14_BITS_PER_TRANSFER" = 14, // desc: 14 bits per transfer - @"15_BITS_PER_TRANSFER" = 15, // desc: 15 bits per transfer - @"16_BITS_PER_TRANSFER" = 0, // desc: 16 bits per transfer - _, // non-exhaustive - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 SPI Status Register. This register shows the status of the SPI. - pub const SR = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABRT: u1, // bit offset: 3 desc: Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register. - MODF: u1, // bit offset: 4 desc: Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register. - ROVR: u1, // bit offset: 5 desc: Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register. - WCOL: u1, // bit offset: 6 desc: Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register. - SPIF: u1, // bit offset: 7 desc: SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. - pub const DR = mmio(Address + 0x00000008, 32, packed struct { - DATALOW: u8, // bit offset: 0 desc: SPI Bi-directional data port. - DATAHIGH: u8, // bit offset: 8 desc: If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 SPI Clock Counter Register. This register controls the frequency of a master's SCK0. - pub const CCR = mmio(Address + 0x0000000c, 32, packed struct { - COUNTER: u8, // bit offset: 0 desc: SPI0 Clock counter setting. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. - pub const INT = mmio(Address + 0x0000001c, 32, packed struct { - SPIF: u1, // bit offset: 0 desc: SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software. - // RESERVED: u7, // bit offset: 1 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const RTC = extern struct { - pub const Address: u32 = 0x40024000; - // byte offset: 0 Interrupt Location Register - pub const ILR = mmio(Address + 0x00000000, 32, packed struct { - RTCCIF: u1, // bit offset: 0 desc: When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt. - RTCALF: u1, // bit offset: 1 desc: When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt. - // RESERVED: u11, // bit offset: 21 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Clock Control Register - pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - CLKEN: enum(u1) { // bit offset: 0 desc: Clock Enable. - @"THE_TIME_COUNTERS_AR" = 1, // desc: The time counters are enabled. - @"THE_TIME_COUNTERS_AR" = 0, // desc: The time counters are disabled so that they may be initialized. - }, - CTCRST: enum(u1) { // bit offset: 1 desc: CTC Reset. - @"RESET" = 1, // desc: When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software. - @"NO_EFFECT_" = 0, // desc: No effect. - }, - // RESERVED: u2, // bit offset: 2 desc: Internal test mode controls. These bits must be 0 for normal RTC operation. - reserved2: u1 = 0, - reserved1: u1 = 0, - CCALEN: enum(u1) { // bit offset: 4 desc: Calibration counter enable. - @"THE_CALIBRATION_COUN" = 1, // desc: The calibration counter is disabled and reset to zero. - @"THE_CALIBRATION_COUN" = 0, // desc: The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5. - }, - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Counter Increment Interrupt Register - pub const CIIR = mmio(Address + 0x0000000c, 32, packed struct { - IMSEC: u1, // bit offset: 0 desc: When 1, an increment of the Second value generates an interrupt. - IMMIN: u1, // bit offset: 1 desc: When 1, an increment of the Minute value generates an interrupt. - IMHOUR: u1, // bit offset: 2 desc: When 1, an increment of the Hour value generates an interrupt. - IMDOM: u1, // bit offset: 3 desc: When 1, an increment of the Day of Month value generates an interrupt. - IMDOW: u1, // bit offset: 4 desc: When 1, an increment of the Day of Week value generates an interrupt. - IMDOY: u1, // bit offset: 5 desc: When 1, an increment of the Day of Year value generates an interrupt. - IMMON: u1, // bit offset: 6 desc: When 1, an increment of the Month value generates an interrupt. - IMYEAR: u1, // bit offset: 7 desc: When 1, an increment of the Year value generates an interrupt. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Alarm Mask Register - pub const AMR = mmio(Address + 0x00000010, 32, packed struct { - AMRSEC: u1, // bit offset: 0 desc: When 1, the Second value is not compared for the alarm. - AMRMIN: u1, // bit offset: 1 desc: When 1, the Minutes value is not compared for the alarm. - AMRHOUR: u1, // bit offset: 2 desc: When 1, the Hour value is not compared for the alarm. - AMRDOM: u1, // bit offset: 3 desc: When 1, the Day of Month value is not compared for the alarm. - AMRDOW: u1, // bit offset: 4 desc: When 1, the Day of Week value is not compared for the alarm. - AMRDOY: u1, // bit offset: 5 desc: When 1, the Day of Year value is not compared for the alarm. - AMRMON: u1, // bit offset: 6 desc: When 1, the Month value is not compared for the alarm. - AMRYEAR: u1, // bit offset: 7 desc: When 1, the Year value is not compared for the alarm. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Consolidated Time Register 0 - pub const CTIME0 = mmio(Address + 0x00000014, 32, packed struct { - SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 - // RESERVED: u2, // bit offset: 6 desc: Reserved. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - MINUTES: u6, // bit offset: 8 desc: Minutes value in the range of 0 to 59 - // RESERVED: u2, // bit offset: 14 desc: Reserved. The value read from a reserved bit is not defined. - reserved4: u1 = 0, - reserved3: u1 = 0, - HOURS: u5, // bit offset: 16 desc: Hours value in the range of 0 to 23 - // RESERVED: u3, // bit offset: 21 desc: Reserved. The value read from a reserved bit is not defined. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - DOW: u3, // bit offset: 24 desc: Day of week value in the range of 0 to 6 - // RESERVED: u5, // bit offset: 27 desc: Reserved. The value read from a reserved bit is not defined. - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Consolidated Time Register 1 - pub const CTIME1 = mmio(Address + 0x00000018, 32, packed struct { - DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). - // RESERVED: u3, // bit offset: 5 desc: Reserved. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - MONTH: u4, // bit offset: 8 desc: Month value in the range of 1 to 12. - // RESERVED: u4, // bit offset: 12 desc: Reserved. The value read from a reserved bit is not defined. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - YEAR: u12, // bit offset: 16 desc: Year value in the range of 0 to 4095. - // RESERVED: u4, // bit offset: 28 desc: Reserved. The value read from a reserved bit is not defined. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Consolidated Time Register 2 - pub const CTIME2 = mmio(Address + 0x0000001c, 32, packed struct { - DOY: u12, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). - // RESERVED: u20, // bit offset: 12 desc: Reserved. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Seconds Counter - pub const SEC = mmio(Address + 0x00000020, 32, packed struct { - SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 Minutes Register - pub const MIN = mmio(Address + 0x00000024, 32, packed struct { - MINUTES: u6, // bit offset: 0 desc: Minutes value in the range of 0 to 59 - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Hours Register - pub const HRS = mmio(Address + 0x00000028, 32, packed struct { - HOURS: u5, // bit offset: 0 desc: Hours value in the range of 0 to 23 - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Day of Month Register - pub const DOM = mmio(Address + 0x0000002c, 32, packed struct { - DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 Day of Week Register - pub const DOW = mmio(Address + 0x00000030, 32, packed struct { - DOW: u3, // bit offset: 0 desc: Day of week value in the range of 0 to 6. - // RESERVED: u29, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 Day of Year Register - pub const DOY = mmio(Address + 0x00000034, 32, packed struct { - DOY: u9, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). - // RESERVED: u23, // bit offset: 9 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 Months Register - pub const MONTH = mmio(Address + 0x00000038, 32, packed struct { - MONTH: u4, // bit offset: 0 desc: Month value in the range of 1 to 12. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 60 Years Register - pub const YEAR = mmio(Address + 0x0000003c, 32, packed struct { - YEAR: u12, // bit offset: 0 desc: Year value in the range of 0 to 4095. - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 64 Calibration Value Register - pub const CALIBRATION = mmio(Address + 0x00000040, 32, packed struct { - CALVAL: u17, // bit offset: 0 desc: If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0. - CALDIR: enum(u1) { // bit offset: 17 desc: Calibration direction - @"BACKWARD_CALIBRATION" = 1, // desc: Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second. - @"FORWARD_CALIBRATION_" = 0, // desc: Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds. - }, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 68 General Purpose Register 0 - pub const GPREG0 = mmio(Address + 0x00000044, 32, packed struct { - GP: u32, // bit offset: 0 desc: General purpose storage. - }); - // byte offset: 72 General Purpose Register 0 - pub const GPREG1 = mmio(Address + 0x00000048, 32, packed struct { - GP: u32, // bit offset: 0 desc: General purpose storage. - }); - // byte offset: 76 General Purpose Register 0 - pub const GPREG2 = mmio(Address + 0x0000004c, 32, packed struct { - GP: u32, // bit offset: 0 desc: General purpose storage. - }); - // byte offset: 80 General Purpose Register 0 - pub const GPREG3 = mmio(Address + 0x00000050, 32, packed struct { - GP: u32, // bit offset: 0 desc: General purpose storage. - }); - // byte offset: 84 General Purpose Register 0 - pub const GPREG4 = mmio(Address + 0x00000054, 32, packed struct { - GP: u32, // bit offset: 0 desc: General purpose storage. - }); - // byte offset: 88 RTC Auxiliary Enable register - pub const RTC_AUXEN = mmio(Address + 0x00000058, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RTC_OSCFEN: u1, // bit offset: 4 desc: Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5. - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 92 RTC Auxiliary control register - pub const RTC_AUX = mmio(Address + 0x0000005c, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RTC_OSCF: u1, // bit offset: 4 desc: RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag. - // RESERVED: u1, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - RTC_PDOUT: u1, // bit offset: 6 desc: When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode. - // RESERVED: u25, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 96 Alarm value for Seconds - pub const ASEC = mmio(Address + 0x00000060, 32, packed struct { - SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 100 Alarm value for Minutes - pub const AMIN = mmio(Address + 0x00000064, 32, packed struct { - MINUTES: u6, // bit offset: 0 desc: Minutes value in the range of 0 to 59 - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 104 Alarm value for Hours - pub const AHRS = mmio(Address + 0x00000068, 32, packed struct { - HOURS: u5, // bit offset: 0 desc: Hours value in the range of 0 to 23 - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 108 Alarm value for Day of Month - pub const ADOM = mmio(Address + 0x0000006c, 32, packed struct { - DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Alarm value for Day of Week - pub const ADOW = mmio(Address + 0x00000070, 32, packed struct { - DOW: u3, // bit offset: 0 desc: Day of week value in the range of 0 to 6. - // RESERVED: u29, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 116 Alarm value for Day of Year - pub const ADOY = mmio(Address + 0x00000074, 32, packed struct { - DOY: u9, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). - // RESERVED: u23, // bit offset: 9 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 120 Alarm value for Months - pub const AMON = mmio(Address + 0x00000078, 32, packed struct { - MONTH: u4, // bit offset: 0 desc: Month value in the range of 1 to 12. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 124 Alarm value for Year - pub const AYRS = mmio(Address + 0x0000007c, 32, packed struct { - YEAR: u12, // bit offset: 0 desc: Year value in the range of 0 to 4095. - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const GPIOINT = extern struct { - pub const Address: u32 = 0x40028080; - // byte offset: 0 GPIO overall Interrupt Status. - pub const STATUS = mmio(Address + 0x00000000, 32, packed struct { - P0INT: enum(u1) { // bit offset: 0 desc: Port 0 GPIO interrupt pending. - @"NO_PENDING_INTERRUPT" = 0, // desc: No pending interrupts on Port 0. - @"AT_LEAST_ONE_PENDING" = 1, // desc: At least one pending interrupt on Port 0. - }, - // RESERVED: u1, // bit offset: 1 desc: Reserved. The value read from a reserved bit is not defined. - reserved1: u1 = 0, - P2INT: enum(u1) { // bit offset: 2 desc: Port 2 GPIO interrupt pending. - @"NO_PENDING_INTERRUPT" = 0, // desc: No pending interrupts on Port 2. - @"AT_LEAST_ONE_PENDING" = 1, // desc: At least one pending interrupt on Port 2. - }, - // RESERVED: u30, // bit offset: 2 desc: Reserved. The value read from a reserved bit is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 GPIO Interrupt Status for Rising edge for Port 0. - pub const STATR0 = mmio(Address + 0x00000004, 32, packed struct { - P0_0REI: u1, // bit offset: 0 desc: Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_1REI: u1, // bit offset: 1 desc: Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_2REI: u1, // bit offset: 2 desc: Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_3REI: u1, // bit offset: 3 desc: Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_4REI: u1, // bit offset: 4 desc: Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_5REI: u1, // bit offset: 5 desc: Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_6REI: u1, // bit offset: 6 desc: Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_7REI: u1, // bit offset: 7 desc: Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_8REI: u1, // bit offset: 8 desc: Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_9REI: u1, // bit offset: 9 desc: Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_10REI: u1, // bit offset: 10 desc: Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_11REI: u1, // bit offset: 11 desc: Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_12REI: u1, // bit offset: 12 desc: Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_13REI: u1, // bit offset: 13 desc: Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_14REI: u1, // bit offset: 14 desc: Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_15REI: u1, // bit offset: 15 desc: Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_16REI: u1, // bit offset: 16 desc: Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_17REI: u1, // bit offset: 17 desc: Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_18REI: u1, // bit offset: 18 desc: Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_19REI: u1, // bit offset: 19 desc: Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_20REI: u1, // bit offset: 20 desc: Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_21REI: u1, // bit offset: 21 desc: Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_22REI: u1, // bit offset: 22 desc: Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_23REI: u1, // bit offset: 23 desc: Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_24REI: u1, // bit offset: 24 desc: Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_25REI: u1, // bit offset: 25 desc: Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_26REI: u1, // bit offset: 26 desc: Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_27REI: u1, // bit offset: 27 desc: Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_28REI: u1, // bit offset: 28 desc: Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_29REI: u1, // bit offset: 29 desc: Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_30REI: u1, // bit offset: 30 desc: Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 8 GPIO Interrupt Status for Falling edge for Port 0. - pub const STATF0 = mmio(Address + 0x00000008, 32, packed struct { - P0_0FEI: u1, // bit offset: 0 desc: Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_1FEI: u1, // bit offset: 1 desc: Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_2FEI: u1, // bit offset: 2 desc: Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_3FEI: u1, // bit offset: 3 desc: Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_4FEI: u1, // bit offset: 4 desc: Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_5FEI: u1, // bit offset: 5 desc: Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_6FEI: u1, // bit offset: 6 desc: Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_7FEI: u1, // bit offset: 7 desc: Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_8FEI: u1, // bit offset: 8 desc: Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_9FEI: u1, // bit offset: 9 desc: Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_10FEI: u1, // bit offset: 10 desc: Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_11FEI: u1, // bit offset: 11 desc: Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_12FEI: u1, // bit offset: 12 desc: Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_13FEI: u1, // bit offset: 13 desc: Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_14FEI: u1, // bit offset: 14 desc: Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_15FEI: u1, // bit offset: 15 desc: Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_16FEI: u1, // bit offset: 16 desc: Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_17FEI: u1, // bit offset: 17 desc: Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_18FEI: u1, // bit offset: 18 desc: Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_19FEI: u1, // bit offset: 19 desc: Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_20FEI: u1, // bit offset: 20 desc: Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_21FEI: u1, // bit offset: 21 desc: Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_22FEI: u1, // bit offset: 22 desc: Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_23FEI: u1, // bit offset: 23 desc: Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_24FEI: u1, // bit offset: 24 desc: Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_25FEI: u1, // bit offset: 25 desc: Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_26FEI: u1, // bit offset: 26 desc: Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_27FEI: u1, // bit offset: 27 desc: Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_28FEI: u1, // bit offset: 28 desc: Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_29FEI: u1, // bit offset: 29 desc: Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_30FEI: u1, // bit offset: 30 desc: Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 12 GPIO Interrupt Clear. - pub const CLR0 = mmio(Address + 0x0000000c, 32, packed struct { - P0_0CI: u1, // bit offset: 0 desc: Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_1CI: u1, // bit offset: 1 desc: Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_2CI: u1, // bit offset: 2 desc: Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_3CI: u1, // bit offset: 3 desc: Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_4CI: u1, // bit offset: 4 desc: Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_5CI: u1, // bit offset: 5 desc: Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_6CI: u1, // bit offset: 6 desc: Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_7CI: u1, // bit offset: 7 desc: Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_8CI: u1, // bit offset: 8 desc: Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_9CI: u1, // bit offset: 9 desc: Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_10CI: u1, // bit offset: 10 desc: Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_11CI: u1, // bit offset: 11 desc: Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_12CI: u1, // bit offset: 12 desc: Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_13CI: u1, // bit offset: 13 desc: Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_14CI: u1, // bit offset: 14 desc: Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_15CI: u1, // bit offset: 15 desc: Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_16CI: u1, // bit offset: 16 desc: Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_17CI: u1, // bit offset: 17 desc: Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_18CI: u1, // bit offset: 18 desc: Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_19CI: u1, // bit offset: 19 desc: Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_20CI: u1, // bit offset: 20 desc: Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_21CI: u1, // bit offset: 21 desc: Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_22CI: u1, // bit offset: 22 desc: Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_23CI: u1, // bit offset: 23 desc: Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_24CI: u1, // bit offset: 24 desc: Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_25CI: u1, // bit offset: 25 desc: Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_26CI: u1, // bit offset: 26 desc: Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_27CI: u1, // bit offset: 27 desc: Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_28CI: u1, // bit offset: 28 desc: Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_29CI: u1, // bit offset: 29 desc: Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_30CI: u1, // bit offset: 30 desc: Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 16 GPIO Interrupt Enable for Rising edge for Port 0. - pub const ENR0 = mmio(Address + 0x00000010, 32, packed struct { - P0_0ER: u1, // bit offset: 0 desc: Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_1ER: u1, // bit offset: 1 desc: Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_2ER: u1, // bit offset: 2 desc: Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_3ER: u1, // bit offset: 3 desc: Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_4ER: u1, // bit offset: 4 desc: Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_5ER: u1, // bit offset: 5 desc: Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_6ER: u1, // bit offset: 6 desc: Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_7ER: u1, // bit offset: 7 desc: Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_8ER: u1, // bit offset: 8 desc: Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_9ER: u1, // bit offset: 9 desc: Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_10ER: u1, // bit offset: 10 desc: Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_11ER: u1, // bit offset: 11 desc: Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_12ER: u1, // bit offset: 12 desc: Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_13ER: u1, // bit offset: 13 desc: Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_14ER: u1, // bit offset: 14 desc: Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_15ER: u1, // bit offset: 15 desc: Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_16ER: u1, // bit offset: 16 desc: Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_17ER: u1, // bit offset: 17 desc: Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_18ER: u1, // bit offset: 18 desc: Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_19ER: u1, // bit offset: 19 desc: Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_20ER: u1, // bit offset: 20 desc: Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_21ER: u1, // bit offset: 21 desc: Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_22ER: u1, // bit offset: 22 desc: Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_23ER: u1, // bit offset: 23 desc: Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_24ER: u1, // bit offset: 24 desc: Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_25ER: u1, // bit offset: 25 desc: Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_26ER: u1, // bit offset: 26 desc: Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_27ER: u1, // bit offset: 27 desc: Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_28ER: u1, // bit offset: 28 desc: Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_29ER: u1, // bit offset: 29 desc: Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_30ER: u1, // bit offset: 30 desc: Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 20 GPIO Interrupt Enable for Falling edge for Port 0. - pub const ENF0 = mmio(Address + 0x00000014, 32, packed struct { - P0_0EF: u1, // bit offset: 0 desc: Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_1EF: u1, // bit offset: 1 desc: Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_2EF: u1, // bit offset: 2 desc: Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_3EF: u1, // bit offset: 3 desc: Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_4EF: u1, // bit offset: 4 desc: Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_5EF: u1, // bit offset: 5 desc: Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_6EF: u1, // bit offset: 6 desc: Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_7EF: u1, // bit offset: 7 desc: Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_8EF: u1, // bit offset: 8 desc: Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_9EF: u1, // bit offset: 9 desc: Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_10EF: u1, // bit offset: 10 desc: Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_11EF: u1, // bit offset: 11 desc: Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_12EF: u1, // bit offset: 12 desc: Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_13EF: u1, // bit offset: 13 desc: Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_14EF: u1, // bit offset: 14 desc: Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_15EF: u1, // bit offset: 15 desc: Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_16EF: u1, // bit offset: 16 desc: Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_17EF: u1, // bit offset: 17 desc: Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_18EF: u1, // bit offset: 18 desc: Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_19EF: u1, // bit offset: 19 desc: Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_20EF: u1, // bit offset: 20 desc: Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_21EF: u1, // bit offset: 21 desc: Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_22EF: u1, // bit offset: 22 desc: Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_23EF: u1, // bit offset: 23 desc: Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_24EF: u1, // bit offset: 24 desc: Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_25EF: u1, // bit offset: 25 desc: Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_26EF: u1, // bit offset: 26 desc: Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_27EF: u1, // bit offset: 27 desc: Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_28EF: u1, // bit offset: 28 desc: Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_29EF: u1, // bit offset: 29 desc: Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_30EF: u1, // bit offset: 30 desc: Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 36 GPIO Interrupt Status for Rising edge for Port 0. - pub const STATR2 = mmio(Address + 0x00000024, 32, packed struct { - P2_0REI: u1, // bit offset: 0 desc: Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_1REI: u1, // bit offset: 1 desc: Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_2REI: u1, // bit offset: 2 desc: Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_3REI: u1, // bit offset: 3 desc: Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_4REI: u1, // bit offset: 4 desc: Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_5REI: u1, // bit offset: 5 desc: Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_6REI: u1, // bit offset: 6 desc: Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_7REI: u1, // bit offset: 7 desc: Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_8REI: u1, // bit offset: 8 desc: Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_9REI: u1, // bit offset: 9 desc: Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_10REI: u1, // bit offset: 10 desc: Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_11REI: u1, // bit offset: 11 desc: Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_12REI: u1, // bit offset: 12 desc: Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_13REI: u1, // bit offset: 13 desc: Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 GPIO Interrupt Status for Falling edge for Port 0. - pub const STATF2 = mmio(Address + 0x00000028, 32, packed struct { - P2_0FEI: u1, // bit offset: 0 desc: Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_1FEI: u1, // bit offset: 1 desc: Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_2FEI: u1, // bit offset: 2 desc: Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_3FEI: u1, // bit offset: 3 desc: Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_4FEI: u1, // bit offset: 4 desc: Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_5FEI: u1, // bit offset: 5 desc: Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_6FEI: u1, // bit offset: 6 desc: Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_7FEI: u1, // bit offset: 7 desc: Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_8FEI: u1, // bit offset: 8 desc: Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_9FEI: u1, // bit offset: 9 desc: Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_10FEI: u1, // bit offset: 10 desc: Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_11FEI: u1, // bit offset: 11 desc: Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_12FEI: u1, // bit offset: 12 desc: Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_13FEI: u1, // bit offset: 13 desc: Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 GPIO Interrupt Clear. - pub const CLR2 = mmio(Address + 0x0000002c, 32, packed struct { - P2_0CI: u1, // bit offset: 0 desc: Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_1CI: u1, // bit offset: 1 desc: Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_2CI: u1, // bit offset: 2 desc: Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_3CI: u1, // bit offset: 3 desc: Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_4CI: u1, // bit offset: 4 desc: Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_5CI: u1, // bit offset: 5 desc: Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_6CI: u1, // bit offset: 6 desc: Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_7CI: u1, // bit offset: 7 desc: Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_8CI: u1, // bit offset: 8 desc: Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_9CI: u1, // bit offset: 9 desc: Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_10CI: u1, // bit offset: 10 desc: Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_11CI: u1, // bit offset: 11 desc: Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_12CI: u1, // bit offset: 12 desc: Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_13CI: u1, // bit offset: 13 desc: Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 GPIO Interrupt Enable for Rising edge for Port 0. - pub const ENR2 = mmio(Address + 0x00000030, 32, packed struct { - P2_0ER: u1, // bit offset: 0 desc: Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_1ER: u1, // bit offset: 1 desc: Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_2ER: u1, // bit offset: 2 desc: Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_3ER: u1, // bit offset: 3 desc: Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_4ER: u1, // bit offset: 4 desc: Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_5ER: u1, // bit offset: 5 desc: Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_6ER: u1, // bit offset: 6 desc: Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_7ER: u1, // bit offset: 7 desc: Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_8ER: u1, // bit offset: 8 desc: Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_9ER: u1, // bit offset: 9 desc: Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_10ER: u1, // bit offset: 10 desc: Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_11ER: u1, // bit offset: 11 desc: Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_12ER: u1, // bit offset: 12 desc: Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_13ER: u1, // bit offset: 13 desc: Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 GPIO Interrupt Enable for Falling edge for Port 0. - pub const ENF2 = mmio(Address + 0x00000034, 32, packed struct { - P2_0EF: u1, // bit offset: 0 desc: Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_1EF: u1, // bit offset: 1 desc: Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_2EF: u1, // bit offset: 2 desc: Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_3EF: u1, // bit offset: 3 desc: Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_4EF: u1, // bit offset: 4 desc: Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_5EF: u1, // bit offset: 5 desc: Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_6EF: u1, // bit offset: 6 desc: Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_7EF: u1, // bit offset: 7 desc: Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_8EF: u1, // bit offset: 8 desc: Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_9EF: u1, // bit offset: 9 desc: Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_10EF: u1, // bit offset: 10 desc: Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_11EF: u1, // bit offset: 11 desc: Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_12EF: u1, // bit offset: 12 desc: Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_13EF: u1, // bit offset: 13 desc: Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const PINCONNECT = extern struct { - pub const Address: u32 = 0x4002c000; - // byte offset: 0 Pin function select register 0. - pub const PINSEL0 = mmio(Address + 0x00000000, 32, packed struct { - P0_0: enum(u2) { // bit offset: 0 desc: Pin function select P0.0. - @"GPIO_P0" = 0, // desc: GPIO P0.0 - @"RD1" = 1, // desc: RD1 - @"TXD3" = 2, // desc: TXD3 - @"SDA1" = 3, // desc: SDA1 - }, - P0_1: enum(u2) { // bit offset: 2 desc: Pin function select P0.1. - @"GPIO_P0" = 0, // desc: GPIO P0.1 - @"TD1" = 1, // desc: TD1 - @"RXD3" = 2, // desc: RXD3 - @"SCL1" = 3, // desc: SCL1 - }, - P0_2: enum(u2) { // bit offset: 4 desc: Pin function select P0.2. - @"GPIO_P0" = 0, // desc: GPIO P0.2 - @"TXD0" = 1, // desc: TXD0 - @"AD0" = 2, // desc: AD0.7 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P0_3: enum(u2) { // bit offset: 6 desc: Pin function select P0.3. - @"GPIO_P0" = 0, // desc: GPIO P0.3. - @"RXD0" = 1, // desc: RXD0 - @"AD0" = 2, // desc: AD0.6 - // @"RESERVED", // desc: Reserved. - _, // non-exhaustive - }, - P0_4: enum(u2) { // bit offset: 8 desc: Pin function select P0.4. - @"GPIO_P0" = 0, // desc: GPIO P0.4. - @"I2SRX_CLK" = 1, // desc: I2SRX_CLK - @"RD2" = 2, // desc: RD2 - @"CAP2" = 3, // desc: CAP2.0 - }, - P0_5: enum(u2) { // bit offset: 10 desc: Pin function select P0.5. - @"GPIO_P0" = 0, // desc: GPIO P0.5. - @"I2SRX_WS" = 1, // desc: I2SRX_WS - @"TD2" = 2, // desc: TD2 - @"CAP2" = 3, // desc: CAP2.1 - }, - P0_6: enum(u2) { // bit offset: 12 desc: Pin function select P0.6. - @"GPIO_P0" = 0, // desc: GPIO P0.6. - @"I2SRX_SDA" = 1, // desc: I2SRX_SDA - @"SSEL1" = 2, // desc: SSEL1 - @"MAT2" = 3, // desc: MAT2.0 - }, - P0_7: enum(u2) { // bit offset: 14 desc: Pin function select P0.7. - @"GPIO_P0" = 0, // desc: GPIO P0.7. - @"I2STX_CLK" = 1, // desc: I2STX_CLK - @"SCK1" = 2, // desc: SCK1 - @"MAT2" = 3, // desc: MAT2.1 - }, - P0_8: enum(u2) { // bit offset: 16 desc: Pin function select P0.8. - @"GPIO_P0" = 0, // desc: GPIO P0.8. - @"I2STX_WS" = 1, // desc: I2STX_WS - @"MISO1" = 2, // desc: MISO1 - @"MAT2" = 3, // desc: MAT2.2 - }, - P0_9: enum(u2) { // bit offset: 18 desc: Pin function select P0.9. - @"GPIO_P0" = 0, // desc: GPIO P0.9 - @"I2STX_SDA" = 1, // desc: I2STX_SDA - @"MOSI1" = 2, // desc: MOSI1 - @"MAT2" = 3, // desc: MAT2.3 - }, - P0_10: enum(u2) { // bit offset: 20 desc: Pin function select P0.10. - @"GPIO_P0" = 0, // desc: GPIO P0.10 - @"TXD2" = 1, // desc: TXD2 - @"SDA2" = 2, // desc: SDA2 - @"MAT3" = 3, // desc: MAT3.0 - }, - P0_11: enum(u2) { // bit offset: 22 desc: Pin function select P0.11. - @"GPIO_P0" = 0, // desc: GPIO P0.11 - @"RXD2" = 1, // desc: RXD2 - @"SCL2" = 2, // desc: SCL2 - @"MAT3" = 3, // desc: MAT3.1 - }, - // RESERVED: u6, // bit offset: 24 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P0_15: enum(u2) { // bit offset: 30 desc: Pin function select P0.15. - @"GPIO_P0" = 0, // desc: GPIO P0.15 - @"TXD1" = 1, // desc: TXD1 - @"SCK0" = 2, // desc: SCK0 - @"SCK" = 3, // desc: SCK - }, - }); - // byte offset: 4 Pin function select register 1. - pub const PINSEL1 = mmio(Address + 0x00000004, 32, packed struct { - P0_16: enum(u2) { // bit offset: 0 desc: Pin function select P0.16. - @"GPIO_P0" = 0, // desc: GPIO P0.16 - @"RXD1" = 1, // desc: RXD1 - @"SSEL0" = 2, // desc: SSEL0 - @"SSEL" = 3, // desc: SSEL - }, - P0_17: enum(u2) { // bit offset: 2 desc: Pin function select P0.17. - @"GPIO_P0" = 0, // desc: GPIO P0.17 - @"CTS1" = 1, // desc: CTS1 - @"MISO0" = 2, // desc: MISO0 - @"MISO" = 3, // desc: MISO - }, - P0_18: enum(u2) { // bit offset: 4 desc: Pin function select P0.18. - @"GPIO_P0" = 0, // desc: GPIO P0.18 - @"DCD1" = 1, // desc: DCD1 - @"MOSI0" = 2, // desc: MOSI0 - @"MOSI" = 3, // desc: MOSI - }, - P0_19: enum(u2) { // bit offset: 6 desc: Pin function select P019. - @"GPIO_P0" = 0, // desc: GPIO P0.19. - @"DSR1" = 1, // desc: DSR1 - // @"RESERVED", // desc: Reserved - @"SDA1" = 3, // desc: SDA1 - _, // non-exhaustive - }, - P0_20: enum(u2) { // bit offset: 8 desc: Pin function select P0.20. - @"GPIO_P0" = 0, // desc: GPIO P0.20. - @"DTR1" = 1, // desc: DTR1 - // @"RESERVED", // desc: Reserved - @"SCL1" = 3, // desc: SCL1 - _, // non-exhaustive - }, - P0_21: enum(u2) { // bit offset: 10 desc: Pin function select P0.21. - @"GPIO_PORT_0" = 0, // desc: GPIO Port 0.21. - @"RI1" = 1, // desc: RI1 - // @"RESERVED", // desc: Reserved - @"RD1" = 3, // desc: RD1 - _, // non-exhaustive - }, - P0_22: enum(u2) { // bit offset: 12 desc: Pin function select P022 - @"GPIO_P0" = 0, // desc: GPIO P0.22. - @"RTS1" = 1, // desc: RTS1 - // @"RESERVED", // desc: Reserved - @"TD1" = 3, // desc: TD1 - _, // non-exhaustive - }, - P0_23: enum(u2) { // bit offset: 14 desc: Pin function select P023. - @"GPIO_P0" = 0, // desc: GPIO P0.23. - @"AD0" = 1, // desc: AD0.0 - @"I2SRX_CLK" = 2, // desc: I2SRX_CLK - @"CAP3" = 3, // desc: CAP3.0 - }, - P0_24: enum(u2) { // bit offset: 16 desc: Pin function select P0.24. - @"GPIO_P0" = 0, // desc: GPIO P0.24. - @"AD0" = 1, // desc: AD0.1 - @"I2SRX_WS" = 2, // desc: I2SRX_WS - @"CAP3" = 3, // desc: CAP3.1 - }, - P0_25: enum(u2) { // bit offset: 18 desc: Pin function select P0.25. - @"GPIO_P0" = 0, // desc: GPIO P0.25 - @"AD0" = 1, // desc: AD0.2 - @"I2SRX_SDA" = 2, // desc: I2SRX_SDA - @"TXD3" = 3, // desc: TXD3 - }, - P0_26: enum(u2) { // bit offset: 20 desc: Pin function select P0.26. - @"GPIO_P0" = 0, // desc: GPIO P0.26 - @"AD0" = 1, // desc: AD0.3 - @"AOUT" = 2, // desc: AOUT - @"RXD3" = 3, // desc: RXD3 - }, - P0_27: enum(u2) { // bit offset: 22 desc: Pin function select P0.27. - @"GPIO_P0" = 0, // desc: GPIO P0.27 - @"SDA0" = 1, // desc: SDA0 - @"USB_SDA" = 2, // desc: USB_SDA - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P0_28: enum(u2) { // bit offset: 24 desc: Pin function select P0.28. - @"GPIO_P0" = 0, // desc: GPIO P0.28 - @"SCL0" = 1, // desc: SCL0 - @"USB_SCL" = 2, // desc: USB_SCL - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P0_29: enum(u2) { // bit offset: 26 desc: Pin function select P0.29 - @"GPIO_P0" = 0, // desc: GPIO P0.29 - @"USB_DP" = 1, // desc: USB_D+ - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P0_30: enum(u2) { // bit offset: 28 desc: Pin function select P0.30. - @"GPIO_P0" = 0, // desc: GPIO P0.30 - @"USB_DM" = 1, // desc: USB_D- - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - // RESERVED: u2, // bit offset: 30 desc: Reserved - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Pin function select register 2. - pub const PINSEL2 = mmio(Address + 0x00000008, 32, packed struct { - P1_0: enum(u2) { // bit offset: 0 desc: Pin function select P1.0. - @"GPIO_P1" = 0, // desc: GPIO P1.0 - @"ENET_TXD0" = 1, // desc: ENET_TXD0 - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_1: enum(u2) { // bit offset: 2 desc: Pin function select P1.1. - @"GPIO_P1" = 0, // desc: GPIO P1.1 - @"ENET_TXD1" = 1, // desc: ENET_TXD1 - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - // RESERVED: u4, // bit offset: 4 desc: Reserved. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P1_4: enum(u2) { // bit offset: 8 desc: Pin function select P1.4. - @"GPIO_P1" = 0, // desc: GPIO P1.4. - @"ENET_TX_EN" = 1, // desc: ENET_TX_EN - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - // RESERVED: u6, // bit offset: 10 desc: Reserved. - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - P1_8: enum(u2) { // bit offset: 16 desc: Pin function select P1.8. - @"GPIO_P1" = 0, // desc: GPIO P1.8. - @"ENET_CRS" = 1, // desc: ENET_CRS - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_9: enum(u2) { // bit offset: 18 desc: Pin function select P1.9. - @"GPIO_PORT_1" = 0, // desc: GPIO Port 1.9 - @"ENET_RXD0" = 1, // desc: ENET_RXD0 - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_10: enum(u2) { // bit offset: 20 desc: Pin function select P1.10. - @"GPIO_P1" = 0, // desc: GPIO P1.10 - @"ENET_RXD1" = 1, // desc: ENET_RXD1 - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_14: enum(u2) { // bit offset: 22 desc: Pin function select P1.14. - @"GPIO_P1" = 0, // desc: GPIO P1.14 - @"ENET_RX_ER" = 1, // desc: ENET_RX_ER - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - // RESERVED: u6, // bit offset: 24 desc: Reserved. - // RESERVED: u6, // bit offset: 24 desc: Reserved. - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - P1_15: enum(u2) { // bit offset: 30 desc: Pin function select P1.15. - @"GPIO_P1" = 0, // desc: GPIO P1.15 - @"ENET_REF_CLK" = 1, // desc: ENET_REF_CLK - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - }); - // byte offset: 12 Pin function select register 3. - pub const PINSEL3 = mmio(Address + 0x0000000c, 32, packed struct { - P1_16: enum(u2) { // bit offset: 0 desc: Pin function select P1.16. - @"GPIO_P1" = 0, // desc: GPIO P1.16 - @"ENET_MDC" = 1, // desc: ENET_MDC - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_17: enum(u2) { // bit offset: 2 desc: Pin function select P1.17. - @"GPIO_P1" = 0, // desc: GPIO P1.17 - @"ENET_MDIO" = 1, // desc: ENET_MDIO - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_18: enum(u2) { // bit offset: 4 desc: Pin function select P1.18. - @"GPIO_P1" = 0, // desc: GPIO P1.18 - @"USB_UP_LED" = 1, // desc: USB_UP_LED - @"PWM1" = 2, // desc: PWM1.1 - @"CAP1" = 3, // desc: CAP1.0 - }, - P1_19: enum(u2) { // bit offset: 6 desc: Pin function select P1.19. - @"GPIO_P1" = 0, // desc: GPIO P1.19. - @"MCOA0" = 1, // desc: MCOA0 - @"USB_PPWR" = 2, // desc: USB_PPWR - @"CAP1" = 3, // desc: CAP1.1 - }, - P1_20: enum(u2) { // bit offset: 8 desc: Pin function select P1.20. - @"GPIO_P1" = 0, // desc: GPIO P1.20. - @"MCI0" = 1, // desc: MCI0 - @"PWM1" = 2, // desc: PWM1.2 - @"SCK0" = 3, // desc: SCK0 - }, - P1_21: enum(u2) { // bit offset: 10 desc: Pin function select P1.21. - @"GPIO_P1" = 0, // desc: GPIO P1.21. - @"MCABORT" = 1, // desc: MCABORT - @"PWM1" = 2, // desc: PWM1.3 - @"SSEL0" = 3, // desc: SSEL0 - }, - P1_22: enum(u2) { // bit offset: 12 desc: Pin function select P1.22 - @"GPIO_P1" = 0, // desc: GPIO P1.22. - @"MCOB0" = 1, // desc: MCOB0 - @"USB_PWRD" = 2, // desc: USB_PWRD - @"MAT1" = 3, // desc: MAT1.0 - }, - P1_23: enum(u2) { // bit offset: 14 desc: Pin function select P1.23. - @"GPIO_P1" = 0, // desc: GPIO P1.23. - @"MCI1" = 1, // desc: MCI1 - @"PWM1" = 2, // desc: PWM1.4 - @"MISO0" = 3, // desc: MISO0 - }, - P1_24: enum(u2) { // bit offset: 16 desc: Pin function select P1.24. - @"GPIO_P1" = 0, // desc: GPIO P1.24. - @"MCI2" = 1, // desc: MCI2 - @"PWM1" = 2, // desc: PWM1.5 - @"MOSI0" = 3, // desc: MOSI0 - }, - P1_25: enum(u2) { // bit offset: 18 desc: Pin function select P1.25. - @"GPIO_P1" = 0, // desc: GPIO P1.25 - @"MCOA1" = 1, // desc: MCOA1 - // @"RESERVED", // desc: Reserved - @"MAT1" = 3, // desc: MAT1.1 - _, // non-exhaustive - }, - P1_26: enum(u2) { // bit offset: 20 desc: Pin function select P1.26. - @"GPIO_P1" = 0, // desc: GPIO P1.26 - @"MCOB1" = 1, // desc: MCOB1 - @"PWM1" = 2, // desc: PWM1.6 - @"CAP0" = 3, // desc: CAP0.0 - }, - P1_27: enum(u2) { // bit offset: 22 desc: Pin function select P1.27. - @"GPIO_P1" = 0, // desc: GPIO P1.27 - @"CLKOUT" = 1, // desc: CLKOUT - @"USB_OVRCR" = 2, // desc: USB_OVRCR - @"CAP0" = 3, // desc: CAP0.1 - }, - P1_28: enum(u2) { // bit offset: 24 desc: Pin function select P1.28. - @"GPIO_P1" = 0, // desc: GPIO P1.28 - @"MCOA2" = 1, // desc: MCOA2 - @"PCAP1" = 2, // desc: PCAP1.0 - @"MAT0" = 3, // desc: MAT0.0 - }, - P1_29: enum(u2) { // bit offset: 26 desc: Pin function select P1.29 - @"GPIO_P1" = 0, // desc: GPIO P1.29 - @"MCOB2" = 1, // desc: MCOB2 - @"PCAP1" = 2, // desc: PCAP1.1 - @"MAT0" = 3, // desc: MAT0.1 - }, - P1_30: enum(u2) { // bit offset: 28 desc: Pin function select P1.30. - @"GPIO_P1" = 0, // desc: GPIO P1.30 - // @"RESERVED", // desc: Reserved - @"VBUS" = 2, // desc: VBUS - @"AD0" = 3, // desc: AD0.4 - _, // non-exhaustive - }, - P1_31: enum(u2) { // bit offset: 30 desc: Pin function select P1.31. - @"GPIO_PORT_1" = 0, // desc: GPIO Port 1.31 - // @"RESERVED", // desc: Reserved - @"SCK1" = 2, // desc: SCK1 - @"AD0" = 3, // desc: AD0.5 - _, // non-exhaustive - }, - }); - // byte offset: 16 Pin function select register 4 - pub const PINSEL4 = mmio(Address + 0x00000010, 32, packed struct { - P2_0: enum(u2) { // bit offset: 0 desc: Pin function select P2.0. - @"GPIO_P2" = 0, // desc: GPIO P2.0 - @"PWM1" = 1, // desc: PWM1.1 - @"TXD1" = 2, // desc: TXD1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_1: enum(u2) { // bit offset: 2 desc: Pin function select P2.1. - @"GPIO_P2" = 0, // desc: GPIO P2.1 - @"PWM1" = 1, // desc: PWM1.2 - @"RXD1" = 2, // desc: RXD1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_2: enum(u2) { // bit offset: 4 desc: Pin function select P2.2. - @"GPIO_P2" = 0, // desc: GPIO P2.2 - @"PWM1" = 1, // desc: PWM1.3 - @"CTS1" = 2, // desc: CTS1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_3: enum(u2) { // bit offset: 6 desc: Pin function select P2.3. - @"GPIO_P2" = 0, // desc: GPIO P2.3. - @"PWM1" = 1, // desc: PWM1.4 - @"DCD1" = 2, // desc: DCD1 - // @"RESERVED", // desc: Reserved. - _, // non-exhaustive - }, - P2_4: enum(u2) { // bit offset: 8 desc: Pin function select P2.4. - @"GPIO_P2" = 0, // desc: GPIO P2.4. - @"PWM1" = 1, // desc: PWM1.5 - @"DSR1" = 2, // desc: DSR1 - // @"RESERVED", // desc: Reserved. - _, // non-exhaustive - }, - P2_5: enum(u2) { // bit offset: 10 desc: Pin function select P2.5. - @"GPIO_P2" = 0, // desc: GPIO P2.5. - @"PWM1" = 1, // desc: PWM1.6 - @"DTR1" = 2, // desc: DTR1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_6: enum(u2) { // bit offset: 12 desc: Pin function select P2.6. - @"GPIO_P2" = 0, // desc: GPIO P2.6. - @"PCAP1" = 1, // desc: PCAP1.0 - @"RI1" = 2, // desc: RI1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_7: enum(u2) { // bit offset: 14 desc: Pin function select P2.7. - @"GPIO_P2" = 0, // desc: GPIO P2.7. - @"RD2" = 1, // desc: RD2 - @"RTS1" = 2, // desc: RTS1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_8: enum(u2) { // bit offset: 16 desc: Pin function select P2.8. - @"GPIO_P2" = 0, // desc: GPIO P2.8. - @"TD2" = 1, // desc: TD2 - @"TXD2" = 2, // desc: TXD2 - @"ENET_MDC" = 3, // desc: ENET_MDC - }, - P2_9: enum(u2) { // bit offset: 18 desc: Pin function select P2.9. - @"GPIO_P2" = 0, // desc: GPIO P2.9 - @"USB_CONNECT" = 1, // desc: USB_CONNECT - @"RXD2" = 2, // desc: RXD2 - @"ENET_MDIO" = 3, // desc: ENET_MDIO - }, - P2_10: enum(u2) { // bit offset: 20 desc: Pin function select P2.10. - @"GPIO_P2" = 0, // desc: GPIO P2.10 - @"EINT0" = 1, // desc: EINT0 - @"NMI" = 2, // desc: NMI - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_11: enum(u2) { // bit offset: 22 desc: Pin function select P2.11. - @"GPIO_P2" = 0, // desc: GPIO P2.11 - @"EINT1" = 1, // desc: EINT1 - // @"RESERVED", // desc: Reserved - @"I2STX_CLK" = 3, // desc: I2STX_CLK - _, // non-exhaustive - }, - P2_12: enum(u2) { // bit offset: 24 desc: Pin function select P2.12. - @"GPIO_P2" = 0, // desc: GPIO P2.12 - @"EINT2" = 1, // desc: EINT2 - // @"RESERVED", // desc: Reserved - @"I2STX_WS" = 3, // desc: I2STX_WS - _, // non-exhaustive - }, - P2_13: enum(u2) { // bit offset: 26 desc: Pin function select P2.13. - @"GPIO_P2" = 0, // desc: GPIO P2.13 - @"EINT3" = 1, // desc: EINT3 - // @"RESERVED", // desc: Reserved - @"I2STX_SDA" = 3, // desc: I2STX_SDA - _, // non-exhaustive - }, - // RESERVED: u4, // bit offset: 28 desc: Reserved. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Pin function select register 7 - pub const PINSEL7 = mmio(Address + 0x0000001c, 32, packed struct { - // RESERVED: u18, // bit offset: 0 desc: Reserved. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P3_25: enum(u2) { // bit offset: 18 desc: Pin function select P3.25. - @"GPIO_P3" = 0, // desc: GPIO P3.25 - // @"RESERVED", // desc: Reserved - @"MAT0" = 2, // desc: MAT0.0 - @"PWM1" = 3, // desc: PWM1.2 - _, // non-exhaustive - }, - P3_26: enum(u2) { // bit offset: 20 desc: Pin function select P3.26. - @"GPIO_P3" = 0, // desc: GPIO P3.26 - @"STCLK" = 1, // desc: STCLK - @"MAT0" = 2, // desc: MAT0.1 - @"PWM1" = 3, // desc: PWM1.3 - }, - // RESERVED: u10, // bit offset: 22 desc: Reserved. - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 Pin function select register 9 - pub const PINSEL9 = mmio(Address + 0x00000024, 32, packed struct { - // RESERVED: u24, // bit offset: 0 desc: Reserved. - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P4_28: enum(u2) { // bit offset: 24 desc: Pin function select P4.28. - @"GPIO_P4" = 0, // desc: GPIO P4.28 - @"RX_MCLK" = 1, // desc: RX_MCLK - @"MAT2" = 2, // desc: MAT2.0 - @"TXD3" = 3, // desc: TXD3 - }, - P4_29: enum(u2) { // bit offset: 26 desc: Pin function select P4.29. - @"GPIO_P4" = 0, // desc: GPIO P4.29 - @"TX_MCLK" = 1, // desc: TX_MCLK - @"MAT2" = 2, // desc: MAT2.1 - @"RXD3" = 3, // desc: RXD3 - }, - // RESERVED: u4, // bit offset: 28 desc: Reserved. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Pin function select register 10 - pub const PINSEL10 = mmio(Address + 0x00000028, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: Reserved. Software should not write 1 to these bits. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TPIUCTRL: enum(u1) { // bit offset: 3 desc: TPIU interface pins control. - @"DISABLED" = 0, // desc: Disabled. TPIU interface is disabled. - @"ENABLED" = 1, // desc: Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content. - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Software should not write 1 to these bits. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 64 Pin mode select register 0 - pub const PINMODE0 = mmio(Address + 0x00000040, 32, packed struct { - P0_00MODE: enum(u2) { // bit offset: 0 desc: Port 0 pin 0 on-chip pull-up/down resistor control. - @"PULL_UP" = 0, // desc: Pull-up. P0.0 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.0 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.0 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.0 has a pull-down resistor enabled. - }, - P0_01MODE: enum(u2) { // bit offset: 2 desc: Port 0 pin 1 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.1 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.1 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.1 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.1 has a pull-down resistor enabled. - }, - P0_02MODE: enum(u2) { // bit offset: 4 desc: Port 0 pin 2 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.2 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.2 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.2 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.2 has a pull-down resistor enabled. - }, - P0_03MODE: enum(u2) { // bit offset: 6 desc: Port 0 pin 3 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.3 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.3 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.3 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.3 has a pull-down resistor enabled. - }, - P0_04MODE: enum(u2) { // bit offset: 8 desc: Port 0 pin 4 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.4 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.4 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.4 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.4 has a pull-down resistor enabled. - }, - P0_05MODE: enum(u2) { // bit offset: 10 desc: Port 0 pin 5 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.5 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.5 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.5 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.5 has a pull-down resistor enabled. - }, - P0_06MODE: enum(u2) { // bit offset: 12 desc: Port 0 pin 6 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.6 pin has a pull-up resistor enabled. - @"DISABLED" = 1, // desc: Disabled. Repeater. P0.6 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.6 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.6 has a pull-down resistor enabled. - }, - P0_07MODE: enum(u2) { // bit offset: 14 desc: Port 0 pin 7 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.7 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.7 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.7 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.7 has a pull-down resistor enabled. - }, - P0_08MODE: enum(u2) { // bit offset: 16 desc: Port 0 pin 8 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.8 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.8 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.8 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.8 has a pull-down resistor enabled. - }, - P0_09MODE: enum(u2) { // bit offset: 18 desc: Port 0 pin 9 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.9 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.9 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.9 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.9 has a pull-down resistor enabled. - }, - P0_10MODE: enum(u2) { // bit offset: 20 desc: Port 0 pin 10 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.10 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.10 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.10 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.10 has a pull-down resistor enabled. - }, - P0_11MODE: enum(u2) { // bit offset: 22 desc: Port 0 pin 11 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.11 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.11 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.11 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.11 has a pull-down resistor enabled. - }, - // RESERVED: u6, // bit offset: 24 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P0_15MODE: enum(u2) { // bit offset: 30 desc: Port 0 pin 15 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.15 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.15 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.15 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.15 has a pull-down resistor enabled. - }, - }); - // byte offset: 68 Pin mode select register 1 - pub const PINMODE1 = mmio(Address + 0x00000044, 32, packed struct { - P0_16MODE: enum(u2) { // bit offset: 0 desc: Port 1 pin 16 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.16 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.16 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.16 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.16 has a pull-down resistor enabled. - }, - P0_17MODE: enum(u2) { // bit offset: 2 desc: Port 1 pin 17 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.17 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.17 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.17 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.17 has a pull-down resistor enabled. - }, - P0_18MODE: enum(u2) { // bit offset: 4 desc: Port 1 pin 18 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.18 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.18 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.18 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.18 has a pull-down resistor enabled. - }, - P0_19MODE: enum(u2) { // bit offset: 6 desc: Port 1 pin 19 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.19 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.19 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.19 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.19 has a pull-down resistor enabled. - }, - P0_20MODE: enum(u2) { // bit offset: 8 desc: Port 1 pin 20 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.20 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.20 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.20 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.20 has a pull-down resistor enabled. - }, - P0_21MODE: enum(u2) { // bit offset: 10 desc: Port 1 pin 21 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.21 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.21 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.21 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.21 has a pull-down resistor enabled. - }, - P0_22MODE: enum(u2) { // bit offset: 12 desc: Port 1 pin 22 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.22 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.22 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.22 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.22 has a pull-down resistor enabled. - }, - P0_23MODE: enum(u2) { // bit offset: 14 desc: Port 1 pin 23 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.23 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.23 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.23 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.23 has a pull-down resistor enabled. - }, - P0_24MODE: enum(u2) { // bit offset: 16 desc: Port 1 pin 24 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.24 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.24 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.24 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.24 has a pull-down resistor enabled. - }, - P0_25MODE: enum(u2) { // bit offset: 18 desc: Port 1 pin 25 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.25 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.25 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.25 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.25 has a pull-down resistor enabled. - }, - P0_26MODE: enum(u2) { // bit offset: 20 desc: Port 1 pin 26 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.26 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.26 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.26 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.26 has a pull-down resistor enabled. - }, - // RESERVED: u8, // bit offset: 22 desc: Reserved. - // RESERVED: u2, // bit offset: 30 desc: Reserved. - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 72 Pin mode select register 2 - pub const PINMODE2 = mmio(Address + 0x00000048, 32, packed struct { - P1_00MODE: enum(u2) { // bit offset: 0 desc: Port 1 pin 0 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.0 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.0 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.0 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.0 has a pull-down resistor enabled. - }, - P1_01MODE: enum(u2) { // bit offset: 2 desc: Port 1 pin 1 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.1 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.1 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.1 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.1 has a pull-down resistor enabled. - }, - // RESERVED: u4, // bit offset: 4 desc: Reserved. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P1_04MODE: enum(u2) { // bit offset: 8 desc: Port 1 pin 4 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.4 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.4 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.4 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.4 has a pull-down resistor enabled. - }, - // RESERVED: u6, // bit offset: 10 desc: Reserved. - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - P1_08MODE: enum(u2) { // bit offset: 16 desc: Port 1 pin 8 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.8 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.8 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.8 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.8 has a pull-down resistor enabled. - }, - P1_09MODE: enum(u2) { // bit offset: 18 desc: Port 1 pin 9 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.9 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.9 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.9 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.9 has a pull-down resistor enabled. - }, - P1_10MODE: enum(u2) { // bit offset: 20 desc: Port 1 pin 10 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.10 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.10 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.10 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.10 has a pull-down resistor enabled. - }, - // RESERVED: u6, // bit offset: 22 desc: Reserved. - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - P1_14MODE: enum(u2) { // bit offset: 28 desc: Port 1 pin 14 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.14 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.14 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.14 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.14 has a pull-down resistor enabled. - }, - P1_15MODE: enum(u2) { // bit offset: 30 desc: Port 1 pin 15 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.15 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.15 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.15 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.15 has a pull-down resistor enabled. - }, - }); - // byte offset: 76 Pin mode select register 3. - pub const PINMODE3 = mmio(Address + 0x0000004c, 32, packed struct { - P1_16MODE: enum(u2) { // bit offset: 0 desc: Port 1 pin 16 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.16 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.16 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.16 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.16 has a pull-down resistor enabled. - }, - P1_17MODE: enum(u2) { // bit offset: 2 desc: Port 1 pin 17 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.17 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.17 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.17 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.17 has a pull-down resistor enabled. - }, - P1_18MODE: enum(u2) { // bit offset: 4 desc: Port 1 pin 18 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.18 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.18 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.18 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.18 has a pull-down resistor enabled. - }, - P1_19MODE: enum(u2) { // bit offset: 6 desc: Port 1 pin 19 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.19 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.19 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.19 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.19 has a pull-down resistor enabled. - }, - P1_20MODE: enum(u2) { // bit offset: 8 desc: Port 1 pin 20 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.20 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.20 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.20 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.20 has a pull-down resistor enabled. - }, - P1_21MODE: enum(u2) { // bit offset: 10 desc: Port 1 pin 21 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.21 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.21 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.21 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.21 has a pull-down resistor enabled. - }, - P1_22MODE: enum(u2) { // bit offset: 12 desc: Port 1 pin 22 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.22 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.22 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.22 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.22 has a pull-down resistor enabled. - }, - P1_23MODE: enum(u2) { // bit offset: 14 desc: Port 1 pin 23 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.23 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.23 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.23 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.23 has a pull-down resistor enabled. - }, - P1_24MODE: enum(u2) { // bit offset: 16 desc: Port 1 pin 24 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.24 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.24 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.24 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.24 has a pull-down resistor enabled. - }, - P1_25MODE: enum(u2) { // bit offset: 18 desc: Port 1 pin 25 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.25 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.25 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.25 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.25 has a pull-down resistor enabled. - }, - P1_26MODE: enum(u2) { // bit offset: 20 desc: Port 1 pin 26 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.26 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.26 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.26 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.26 has a pull-down resistor enabled. - }, - P1_27MODE: enum(u2) { // bit offset: 22 desc: Port 1 pin 27 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.27 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.27 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.27 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.27 has a pull-down resistor enabled. - }, - P1_28MODE: enum(u2) { // bit offset: 24 desc: Port 1 pin 28 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.28 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.28 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.28 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.28 has a pull-down resistor enabled. - }, - P1_29MODE: enum(u2) { // bit offset: 26 desc: Port 1 pin 29 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.29 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.29 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.29 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.29 has a pull-down resistor enabled. - }, - P1_30MODE: enum(u2) { // bit offset: 28 desc: Port 1 pin 30 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.30 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.30 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.30 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.30 has a pull-down resistor enabled. - }, - P1_31MODE: enum(u2) { // bit offset: 30 desc: Port 1 pin 31 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.31 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.31 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.31 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.31 has a pull-down resistor enabled. - }, - }); - // byte offset: 80 Pin mode select register 4 - pub const PINMODE4 = mmio(Address + 0x00000050, 32, packed struct { - P2_00MODE: enum(u2) { // bit offset: 0 desc: Port 2 pin 0 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.0 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.0 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.0 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.0 has a pull-down resistor enabled. - }, - P2_01MODE: enum(u2) { // bit offset: 2 desc: Port 2 pin 1 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.1 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.1 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.1 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.1 has a pull-down resistor enabled. - }, - P2_02MODE: enum(u2) { // bit offset: 4 desc: Port 2 pin 2 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.2 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.2 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.2 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.2 has a pull-down resistor enabled. - }, - P2_03MODE: enum(u2) { // bit offset: 6 desc: Port 2 pin 3 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.3 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.3 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.3 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.3 has a pull-down resistor enabled. - }, - P2_04MODE: enum(u2) { // bit offset: 8 desc: Port 2 pin 4 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.4 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.4 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.4 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.4 has a pull-down resistor enabled. - }, - P2_05MODE: enum(u2) { // bit offset: 10 desc: Port 2 pin 5 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.5 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.5 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.5 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.5 has a pull-down resistor enabled. - }, - P2_06MODE: enum(u2) { // bit offset: 12 desc: Port 2 pin 6 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.6 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.6 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.6 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.6 has a pull-down resistor enabled. - }, - P2_07MODE: enum(u2) { // bit offset: 14 desc: Port 2 pin 7 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.7 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.7 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.7 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.7 has a pull-down resistor enabled. - }, - P2_08MODE: enum(u2) { // bit offset: 16 desc: Port 2 pin 8 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.8 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.8 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.8 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.8 has a pull-down resistor enabled. - }, - P2_09MODE: enum(u2) { // bit offset: 18 desc: Port 2 pin 9 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.9 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.9 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.9 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.9 has a pull-down resistor enabled. - }, - P2_10MODE: enum(u2) { // bit offset: 20 desc: Port 2 pin 10 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.10 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.10 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.10 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.10 has a pull-down resistor enabled. - }, - P2_11MODE: enum(u2) { // bit offset: 22 desc: Port 2 pin 11 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.11 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.11 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.11 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.11 has a pull-down resistor enabled. - }, - P2_12MODE: enum(u2) { // bit offset: 24 desc: Port 2 pin 12 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.12 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.12 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.12 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.12 has a pull-down resistor enabled. - }, - P2_13MODE: enum(u2) { // bit offset: 26 desc: Port 2 pin 13 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.13 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.13 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.13 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.13 has a pull-down resistor enabled. - }, - // RESERVED: u4, // bit offset: 28 desc: Reserved. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 92 Pin mode select register 7 - pub const PINMODE7 = mmio(Address + 0x0000005c, 32, packed struct { - // RESERVED: u18, // bit offset: 0 desc: Reserved - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P3_25MODE: enum(u2) { // bit offset: 18 desc: Port 3 pin 25 control. - @"PULL_UP" = 0, // desc: Pull-up. P3.25 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P3.25 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P3.25 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P3.25 has a pull-down resistor enabled. - }, - P3_26MODE: enum(u2) { // bit offset: 20 desc: Port 3 pin 26 control. - @"PULL_UP" = 0, // desc: Pull-up. P3.26 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P3.26 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P3.26 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P3.26 has a pull-down resistor enabled. - }, - // RESERVED: u10, // bit offset: 22 desc: Reserved. - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 100 Pin mode select register 9 - pub const PINMODE9 = mmio(Address + 0x00000064, 32, packed struct { - // RESERVED: u24, // bit offset: 0 desc: Reserved. - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P4_28MODE: enum(u2) { // bit offset: 24 desc: Port 4 pin 28 control. - @"PULL_UP" = 0, // desc: Pull-up. P4.28 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P4.28 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P4.28 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P4.28 has a pull-down resistor enabled. - }, - P4_29MODE: enum(u2) { // bit offset: 26 desc: Port 4 pin 29 control. - @"PULL_UP" = 0, // desc: Pull-up. P4.29 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P4.29 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P4.29 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P4.29 has a pull-down resistor enabled. - }, - // RESERVED: u4, // bit offset: 28 desc: Reserved. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 104 Open drain mode control register 0 - pub const PINMODE_OD0 = mmio(Address + 0x00000068, 32, packed struct { - P0_00OD: enum(u1) { // bit offset: 0 desc: Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.0 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.0 pin is in the open drain mode. - }, - P0_01OD: enum(u1) { // bit offset: 1 desc: Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.1 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.1 pin is in the open drain mode. - }, - P0_02OD: enum(u1) { // bit offset: 2 desc: Port 0 pin 2 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.2 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.2 pin is in the open drain mode. - }, - P0_03OD: enum(u1) { // bit offset: 3 desc: Port 0 pin 3 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.3 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.3 pin is in the open drain mode. - }, - P0_04OD: enum(u1) { // bit offset: 4 desc: Port 0 pin 4 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.4 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.4 pin is in the open drain mode. - }, - P0_05OD: enum(u1) { // bit offset: 5 desc: Port 0 pin 5 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.5 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.5 pin is in the open drain mode. - }, - P0_06OD: enum(u1) { // bit offset: 6 desc: Port 0 pin 6 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.6 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.6 pin is in the open drain mode. - }, - P0_07OD: enum(u1) { // bit offset: 7 desc: Port 0 pin 7 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.7 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.7 pin is in the open drain mode. - }, - P0_08OD: enum(u1) { // bit offset: 8 desc: Port 0 pin 8 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.8 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.8 pin is in the open drain mode. - }, - P0_09OD: enum(u1) { // bit offset: 9 desc: Port 0 pin 9 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.9 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.9 pin is in the open drain mode. - }, - P0_10OD: enum(u1) { // bit offset: 10 desc: Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.10 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.10 pin is in the open drain mode. - }, - P0_11OD: enum(u1) { // bit offset: 11 desc: Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.11 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.11 pin is in the open drain mode. - }, - // RESERVED: u3, // bit offset: 12 desc: Reserved. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P0_15OD: enum(u1) { // bit offset: 15 desc: Port 0 pin 15 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.15 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.15 pin is in the open drain mode. - }, - P0_16OD: enum(u1) { // bit offset: 16 desc: Port 0 pin 16 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.16 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.16 pin is in the open drain mode. - }, - P0_17OD: enum(u1) { // bit offset: 17 desc: Port 0 pin 17 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.17 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.17 pin is in the open drain mode. - }, - P0_18OD: enum(u1) { // bit offset: 18 desc: Port 0 pin 18 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.18 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.18 pin is in the open drain mode. - }, - P0_19OD: enum(u1) { // bit offset: 19 desc: Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.19 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.19 pin is in the open drain mode. - }, - P0_20OD: enum(u1) { // bit offset: 20 desc: Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.20 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.20 pin is in the open drain mode. - }, - P0_21OD: enum(u1) { // bit offset: 21 desc: Port 0 pin 21 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.21 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.21 pin is in the open drain mode. - }, - P0_22OD: enum(u1) { // bit offset: 22 desc: Port 0 pin 22 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.22 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.22 pin is in the open drain mode. - }, - P0_23OD: enum(u1) { // bit offset: 23 desc: Port 0 pin 23 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.23 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.23 pin is in the open drain mode. - }, - P0_24OD: enum(u1) { // bit offset: 24 desc: Port 0 pin 24open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.23 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.23 pin is in the open drain mode. - }, - P0_25OD: enum(u1) { // bit offset: 25 desc: Port 0 pin 25 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.25 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.25 pin is in the open drain mode. - }, - P0_26OD: enum(u1) { // bit offset: 26 desc: Port 0 pin 26 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.26 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.26 pin is in the open drain mode. - }, - // RESERVED: u2, // bit offset: 27 desc: Reserved. - reserved5: u1 = 0, - reserved4: u1 = 0, - P0_29OD: enum(u1) { // bit offset: 29 desc: Port 0 pin 29 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.29 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.29 pin is in the open drain mode. - }, - P0_30OD: enum(u1) { // bit offset: 30 desc: Port 0 pin 30 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.30 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.30 pin is in the open drain mode. - }, - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 108 Open drain mode control register 1 - pub const PINMODE_OD1 = mmio(Address + 0x0000006c, 32, packed struct { - P1_00OD: enum(u1) { // bit offset: 0 desc: Port 1 pin 0 open drain mode control. - @"NORMAL" = 0, // desc: Normal. P1.0 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.0 pin is in the open drain mode. - }, - P1_01OD: enum(u1) { // bit offset: 1 desc: Port 1 pin 1 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.1 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.1 pin is in the open drain mode. - }, - // RESERVED: u2, // bit offset: 2 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - P1_04OD: enum(u1) { // bit offset: 4 desc: Port 1 pin 4 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.4 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.4 pin is in the open drain mode. - }, - // RESERVED: u3, // bit offset: 5 desc: Reserved. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - P1_08OD: enum(u1) { // bit offset: 8 desc: Port 1 pin 8 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.8 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.8 pin is in the open drain mode. - }, - P1_09OD: enum(u1) { // bit offset: 9 desc: Port 1 pin 9 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.9 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.9 pin is in the open drain mode. - }, - P1_10OD: enum(u1) { // bit offset: 10 desc: Port 1 pin 10 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.10 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.10 pin is in the open drain mode. - }, - // RESERVED: u3, // bit offset: 11 desc: Reserved. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - P1_14OD: enum(u1) { // bit offset: 14 desc: Port 1 pin 14 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.14 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.14 pin is in the open drain mode. - }, - P1_15OD: enum(u1) { // bit offset: 15 desc: Port 1 pin 15 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.15 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.15 pin is in the open drain mode. - }, - P1_16OD: enum(u1) { // bit offset: 16 desc: Port 1 pin 16 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.16 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.16 pin is in the open drain mode. - }, - P1_17OD: enum(u1) { // bit offset: 17 desc: Port 1 pin 17 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.17 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.17 pin is in the open drain mode. - }, - P1_18OD: enum(u1) { // bit offset: 18 desc: Port 1 pin 18 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.18 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.18 pin is in the open drain mode. - }, - P1_19OD: enum(u1) { // bit offset: 19 desc: Port 1 pin 19 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.19 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.19 pin is in the open drain mode. - }, - P1_20OD: enum(u1) { // bit offset: 20 desc: Port 1 pin 20open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.20 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.20 pin is in the open drain mode. - }, - P1_21OD: enum(u1) { // bit offset: 21 desc: Port 1 pin 21 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.21 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.21 pin is in the open drain mode. - }, - P1_22OD: enum(u1) { // bit offset: 22 desc: Port 1 pin 22 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.22 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.22 pin is in the open drain mode. - }, - P1_23OD: enum(u1) { // bit offset: 23 desc: Port 1 pin 23 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.23 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.23 pin is in the open drain mode. - }, - P1_24OD: enum(u1) { // bit offset: 24 desc: Port 1 pin 24open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.24 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.24 pin is in the open drain mode. - }, - P1_25OD: enum(u1) { // bit offset: 25 desc: Port 1 pin 25 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.25 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.25 pin is in the open drain mode. - }, - P1_26OD: enum(u1) { // bit offset: 26 desc: Port 1 pin 26 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.26 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.26 pin is in the open drain mode. - }, - P1_27OD: enum(u1) { // bit offset: 27 desc: Port 1 pin 27 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.27 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.27 pin is in the open drain mode. - }, - P1_28OD: enum(u1) { // bit offset: 28 desc: Port 1 pin 28 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.28 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.28 pin is in the open drain mode. - }, - P1_29OD: enum(u1) { // bit offset: 29 desc: Port 1 pin 29 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.29 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.29 pin is in the open drain mode. - }, - P1_30OD: enum(u1) { // bit offset: 30 desc: Port 1 pin 30 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.30 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.30 pin is in the open drain mode. - }, - P1_31OD: enum(u1) { // bit offset: 31 desc: Port 1 pin 31 open drain mode control. - @"NORMAL" = 0, // desc: Normal. P1.31 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.31 pin is in the open drain mode. - }, - }); - // byte offset: 112 Open drain mode control register 2 - pub const PINMODE_OD2 = mmio(Address + 0x00000070, 32, packed struct { - P2_00OD: enum(u1) { // bit offset: 0 desc: Port 2 pin 0 open drain mode control. - @"NORMAL" = 0, // desc: Normal. P2.0 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.0 pin is in the open drain mode. - }, - P2_01OD: enum(u1) { // bit offset: 1 desc: Port 2 pin 1 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.1 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.1p in is in the open drain mode. - }, - P2_02OD: enum(u1) { // bit offset: 2 desc: Port 2 pin 2 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.2 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.2 pin is in the open drain mode. - }, - P2_03OD: enum(u1) { // bit offset: 3 desc: Port 2 pin 3 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.3 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.3 pin is in the open drain mode. - }, - P2_04OD: enum(u1) { // bit offset: 4 desc: Port 2 pin 4 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.4 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.4 pin is in the open drain mode. - }, - P2_05OD: enum(u1) { // bit offset: 5 desc: Port 2 pin 5 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.5 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.5 pin is in the open drain mode. - }, - P2_06OD: enum(u1) { // bit offset: 6 desc: Port 2 pin 6 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.6 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.6 pin is in the open drain mode. - }, - P2_07OD: enum(u1) { // bit offset: 7 desc: Port 2 pin 7 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.7 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.7 pin is in the open drain mode. - }, - P2_08OD: enum(u1) { // bit offset: 8 desc: Port 2 pin 8 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.8 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.8 pin is in the open drain mode. - }, - P2_09OD: enum(u1) { // bit offset: 9 desc: Port 2 pin 9 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.9 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.9 pin is in the open drain mode. - }, - P2_10OD: enum(u1) { // bit offset: 10 desc: Port 2 pin 10 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.10 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.10 pin is in the open drain mode. - }, - P2_11OD: enum(u1) { // bit offset: 11 desc: Port 2 pin 11 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.11 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.11 pin is in the open drain mode. - }, - P2_12OD: enum(u1) { // bit offset: 12 desc: Port 2 pin 12 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.12 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.12 pin is in the open drain mode. - }, - P2_13OD: enum(u1) { // bit offset: 13 desc: Port 2 pin 13 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.13 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.13 pin is in the open drain mode. - }, - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 116 Open drain mode control register 3 - pub const PINMODE_OD3 = mmio(Address + 0x00000074, 32, packed struct { - // RESERVED: u25, // bit offset: 0 desc: Reserved. - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P3_25OD: enum(u1) { // bit offset: 25 desc: Port 3 pin 25 open drain mode control. - @"NORMAL" = 0, // desc: Normal. P3.25 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P3.25 pin is in the open drain mode. - }, - P3_26OD: u1, // bit offset: 26 desc: Port 3 pin 26 open drain mode control, see P3.25OD - // RESERVED: u5, // bit offset: 27 desc: Reserved. - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 120 Open drain mode control register 4 - pub const PINMODE_OD4 = mmio(Address + 0x00000078, 32, packed struct { - // RESERVED: u28, // bit offset: 0 desc: Reserved. - reserved28: u1 = 0, - reserved27: u1 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P4_28OD: enum(u1) { // bit offset: 28 desc: Port 4 pin 28 open drain mode control. - @"NORMAL" = 0, // desc: Normal. P4.28 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P4.28 pin is in the open drain mode. - }, - P4_29OD: u1, // bit offset: 29 desc: Port 4 pin 29 open drain mode control, see P4.28OD - // RESERVED: u2, // bit offset: 30 desc: Reserved. - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 124 I2C Pin Configuration register - pub const I2CPADCFG = mmio(Address + 0x0000007c, 32, packed struct { - SDADRV0: enum(u1) { // bit offset: 0 desc: Drive mode control for the SDA0 pin, P0.27. - @"STANDARD" = 0, // desc: Standard. The SDA0 pin is in the standard drive mode. - @"FAST_MODE_PLUS" = 1, // desc: Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode. - }, - SDAI2C0: enum(u1) { // bit offset: 1 desc: I 2C filter mode control for the SDA0 pin, P0.27. - @"ENABLED" = 0, // desc: Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled. - @"DISABLED" = 1, // desc: Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled. - }, - SCLDRV0: enum(u1) { // bit offset: 2 desc: Drive mode control for the SCL0 pin, P0.28. - @"STANDARD" = 0, // desc: Standard. The SCL0 pin is in the standard drive mode. - @"FAST_MODE_PLUS" = 1, // desc: Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode. - }, - SCLI2C0: enum(u1) { // bit offset: 3 desc: I 2C filter mode control for the SCL0 pin, P0.28. - @"ENABLED" = 0, // desc: Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled. - @"DISABLED" = 1, // desc: Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled. - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const SSP1 = extern struct { - pub const Address: u32 = 0x40030000; - // byte offset: 0 Control Register 0. Selects the serial clock rate, bus type, and data size. - pub const CR0 = mmio(Address + 0x00000000, 32, packed struct { - DSS: enum(u4) { // bit offset: 0 desc: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. - @"4_BIT_TRANSFER" = 3, // desc: 4-bit transfer - @"5_BIT_TRANSFER" = 4, // desc: 5-bit transfer - @"6_BIT_TRANSFER" = 5, // desc: 6-bit transfer - @"7_BIT_TRANSFER" = 6, // desc: 7-bit transfer - @"8_BIT_TRANSFER" = 7, // desc: 8-bit transfer - @"9_BIT_TRANSFER" = 8, // desc: 9-bit transfer - @"10_BIT_TRANSFER" = 9, // desc: 10-bit transfer - @"11_BIT_TRANSFER" = 10, // desc: 11-bit transfer - @"12_BIT_TRANSFER" = 11, // desc: 12-bit transfer - @"13_BIT_TRANSFER" = 12, // desc: 13-bit transfer - @"14_BIT_TRANSFER" = 13, // desc: 14-bit transfer - @"15_BIT_TRANSFER" = 14, // desc: 15-bit transfer - @"16_BIT_TRANSFER" = 15, // desc: 16-bit transfer - _, // non-exhaustive - }, - FRF: enum(u2) { // bit offset: 4 desc: Frame Format. - @"SPI" = 0, // desc: SPI - @"TI" = 1, // desc: TI - @"MICROWIRE" = 2, // desc: Microwire - @"THIS_COMBINATION_IS_" = 3, // desc: This combination is not supported and should not be used. - }, - CPOL: enum(u1) { // bit offset: 6 desc: Clock Out Polarity. This bit is only used in SPI mode. - @"BUS_LOW" = 0, // desc: SSP controller maintains the bus clock low between frames. - @"BUS_HIGH" = 1, // desc: SSP controller maintains the bus clock high between frames. - }, - CPHA: enum(u1) { // bit offset: 7 desc: Clock Out Phase. This bit is only used in SPI mode. - @"FIRST_CLOCK" = 0, // desc: SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. - @"SECOND_CLOCK" = 1, // desc: SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. - }, - SCR: u8, // bit offset: 8 desc: Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control Register 1. Selects master/slave and other modes. - pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - LBM: enum(u1) { // bit offset: 0 desc: Loop Back Mode. - @"NORMAL" = 0, // desc: During normal operation. - @"OUPTU" = 1, // desc: Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). - }, - SSE: enum(u1) { // bit offset: 1 desc: SSP Enable. - @"DISABLED" = 0, // desc: The SSP controller is disabled. - @"ENABLED" = 1, // desc: The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. - }, - MS: enum(u1) { // bit offset: 2 desc: Master/Slave Mode.This bit can only be written when the SSE bit is 0. - @"MASTER" = 0, // desc: The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. - @"SLAVE" = 1, // desc: The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. - }, - SOD: u1, // bit offset: 3 desc: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. - pub const DR = mmio(Address + 0x00000008, 32, packed struct { - DATA: u16, // bit offset: 0 desc: Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Status Register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - TFE: u1, // bit offset: 0 desc: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. - TNF: u1, // bit offset: 1 desc: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. - RNE: u1, // bit offset: 2 desc: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. - RFF: u1, // bit offset: 3 desc: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. - BSY: u1, // bit offset: 4 desc: Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Clock Prescale Register - pub const CPSR = mmio(Address + 0x00000010, 32, packed struct { - CPSDVSR: u8, // bit offset: 0 desc: This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Interrupt Mask Set and Clear Register - pub const IMSC = mmio(Address + 0x00000014, 32, packed struct { - RORIM: u1, // bit offset: 0 desc: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTIM: u1, // bit offset: 1 desc: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXIM: u1, // bit offset: 2 desc: Software should set this bit to enable interrupt when the Rx FIFO is at least half full. - TXIM: u1, // bit offset: 3 desc: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Raw Interrupt Status Register - pub const RIS = mmio(Address + 0x00000018, 32, packed struct { - RORRIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTRIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXRIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full. - TXRIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Masked Interrupt Status Register - pub const MIS = mmio(Address + 0x0000001c, 32, packed struct { - RORMIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. - RTMIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXMIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. - TXMIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 SSPICR Interrupt Clear Register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - RORIC: u1, // bit offset: 0 desc: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. - RTIC: u1, // bit offset: 1 desc: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 SSP0 DMA control register - pub const DMACR = mmio(Address + 0x00000024, 32, packed struct { - RXDMAE: u1, // bit offset: 0 desc: Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. - TXDMAE: u1, // bit offset: 1 desc: Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const ADC = extern struct { - pub const Address: u32 = 0x40034000; - // byte offset: 0 A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur. - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - SEL: u8, // bit offset: 0 desc: Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01. - CLKDIV: u8, // bit offset: 8 desc: The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. - BURST: enum(u1) { // bit offset: 16 desc: Burst mode - @"BURST" = 1, // desc: The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start. - @"SW" = 0, // desc: Conversions are software controlled and require 31 clocks. - }, - // RESERVED: u4, // bit offset: 17 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - PDN: enum(u1) { // bit offset: 21 desc: Power down mode - @"POWERED" = 1, // desc: The A/D converter is operational. - @"POWERDOWN" = 0, // desc: The A/D converter is in power-down mode. - }, - // RESERVED: u2, // bit offset: 22 desc: Reserved. Read value is undefined, only zero should be written. - reserved6: u1 = 0, - reserved5: u1 = 0, - START: enum(u3) { // bit offset: 24 desc: When the BURST bit is 0, these bits control whether and when an A/D conversion is started: - @"NO_START_THIS_VALUE" = 0, // desc: No start (this value should be used when clearing PDN to 0). - @"START_CONVERSION_NOW" = 1, // desc: Start conversion now. - @"P2_10" = 2, // desc: Start conversion when the edge selected by bit 27 occurs on the P2[10] pin. - @"P1_27" = 3, // desc: Start conversion when the edge selected by bit 27 occurs on the P1[27] pin. - @"MAT0_1" = 4, // desc: Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin. - @"MAT0_3" = 5, // desc: Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin. - @"MAT1_0" = 6, // desc: Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin. - @"MAT1_1" = 7, // desc: Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin. - }, - EDGE: enum(u1) { // bit offset: 27 desc: This bit is significant only when the START field contains 010-111. In these cases: - @"FALLLING" = 1, // desc: Start conversion on a falling edge on the selected CAP/MAT signal. - @"RISING" = 0, // desc: Start conversion on a rising edge on the selected CAP/MAT signal. - }, - // RESERVED: u4, // bit offset: 28 desc: Reserved. Read value is undefined, only zero should be written. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion. - pub const GDR = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u8, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - CHN: u3, // bit offset: 24 desc: These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...). - // RESERVED: u3, // bit offset: 27 desc: Reserved. Read value is undefined, only zero should be written. - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. - }); - // byte offset: 12 A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. - pub const INTEN = mmio(Address + 0x0000000c, 32, packed struct { - ADINTEN0: enum(u1) { // bit offset: 0 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 0 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 0 will generate an interrupt. - }, - ADINTEN1: enum(u1) { // bit offset: 1 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 1 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 1 will generate an interrupt. - }, - ADINTEN2: enum(u1) { // bit offset: 2 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 2 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 2 will generate an interrupt. - }, - ADINTEN3: enum(u1) { // bit offset: 3 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 3 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 3 will generate an interrupt. - }, - ADINTEN4: enum(u1) { // bit offset: 4 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 4 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 4 will generate an interrupt. - }, - ADINTEN5: enum(u1) { // bit offset: 5 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 5 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 5 will generate an interrupt. - }, - ADINTEN6: enum(u1) { // bit offset: 6 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 6 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 6 will generate an interrupt. - }, - ADINTEN7: enum(u1) { // bit offset: 7 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 7 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 7 will generate an interrupt. - }, - ADGINTEN: enum(u1) { // bit offset: 8 desc: Interrupt enable - @"CHANNELS" = 0, // desc: Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts. - @"GLOBAL" = 1, // desc: The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts. - }, - // RESERVED: u23, // bit offset: 9 desc: Reserved. Read value is undefined, only zero should be written. - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_0 = mmio(Address + 0x00000010, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 20 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_1 = mmio(Address + 0x00000014, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 24 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_2 = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 28 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_3 = mmio(Address + 0x0000001c, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 32 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_4 = mmio(Address + 0x00000020, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 36 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_5 = mmio(Address + 0x00000024, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 40 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_6 = mmio(Address + 0x00000028, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 44 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_7 = mmio(Address + 0x0000002c, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 48 A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag. - pub const STAT = mmio(Address + 0x00000030, 32, packed struct { - DONE0: u1, // bit offset: 0 desc: This bit mirrors the DONE status flag from the result register for A/D channel 0. - DONE1: u1, // bit offset: 1 desc: This bit mirrors the DONE status flag from the result register for A/D channel 1. - DONE2: u1, // bit offset: 2 desc: This bit mirrors the DONE status flag from the result register for A/D channel 2. - DONE3: u1, // bit offset: 3 desc: This bit mirrors the DONE status flag from the result register for A/D channel 3. - DONE4: u1, // bit offset: 4 desc: This bit mirrors the DONE status flag from the result register for A/D channel 4. - DONE5: u1, // bit offset: 5 desc: This bit mirrors the DONE status flag from the result register for A/D channel 5. - DONE6: u1, // bit offset: 6 desc: This bit mirrors the DONE status flag from the result register for A/D channel 6. - DONE7: u1, // bit offset: 7 desc: This bit mirrors the DONE status flag from the result register for A/D channel 7. - OVERRUN0: u1, // bit offset: 8 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0. - OVERRUN1: u1, // bit offset: 9 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1. - OVERRUN2: u1, // bit offset: 10 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2. - OVERRUN3: u1, // bit offset: 11 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3. - OVERRUN4: u1, // bit offset: 12 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4. - OVERRUN5: u1, // bit offset: 13 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5. - OVERRUN6: u1, // bit offset: 14 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6. - OVERRUN7: u1, // bit offset: 15 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7. - ADINT: u1, // bit offset: 16 desc: This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. - // RESERVED: u15, // bit offset: 17 desc: Reserved. Read value is undefined, only zero should be written. - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 ADC trim register. - pub const TRM = mmio(Address + 0x00000034, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ADCOFFS: u4, // bit offset: 4 desc: Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user. - TRIM: u4, // bit offset: 8 desc: written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write. - // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const CANAFRAM = extern struct { - pub const Address: u32 = 0x40038000; - // byte offset: 0 CAN AF ram access register - pub const MASK_0 = mmio(Address + 0x00000000, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 4 CAN AF ram access register - pub const MASK_1 = mmio(Address + 0x00000004, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 8 CAN AF ram access register - pub const MASK_2 = mmio(Address + 0x00000008, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 12 CAN AF ram access register - pub const MASK_3 = mmio(Address + 0x0000000c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 16 CAN AF ram access register - pub const MASK_4 = mmio(Address + 0x00000010, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 20 CAN AF ram access register - pub const MASK_5 = mmio(Address + 0x00000014, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 24 CAN AF ram access register - pub const MASK_6 = mmio(Address + 0x00000018, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 28 CAN AF ram access register - pub const MASK_7 = mmio(Address + 0x0000001c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 32 CAN AF ram access register - pub const MASK_8 = mmio(Address + 0x00000020, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 36 CAN AF ram access register - pub const MASK_9 = mmio(Address + 0x00000024, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 40 CAN AF ram access register - pub const MASK_10 = mmio(Address + 0x00000028, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 44 CAN AF ram access register - pub const MASK_11 = mmio(Address + 0x0000002c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 48 CAN AF ram access register - pub const MASK_12 = mmio(Address + 0x00000030, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 52 CAN AF ram access register - pub const MASK_13 = mmio(Address + 0x00000034, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 56 CAN AF ram access register - pub const MASK_14 = mmio(Address + 0x00000038, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 60 CAN AF ram access register - pub const MASK_15 = mmio(Address + 0x0000003c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 64 CAN AF ram access register - pub const MASK_16 = mmio(Address + 0x00000040, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 68 CAN AF ram access register - pub const MASK_17 = mmio(Address + 0x00000044, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 72 CAN AF ram access register - pub const MASK_18 = mmio(Address + 0x00000048, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 76 CAN AF ram access register - pub const MASK_19 = mmio(Address + 0x0000004c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 80 CAN AF ram access register - pub const MASK_20 = mmio(Address + 0x00000050, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 84 CAN AF ram access register - pub const MASK_21 = mmio(Address + 0x00000054, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 88 CAN AF ram access register - pub const MASK_22 = mmio(Address + 0x00000058, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 92 CAN AF ram access register - pub const MASK_23 = mmio(Address + 0x0000005c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 96 CAN AF ram access register - pub const MASK_24 = mmio(Address + 0x00000060, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 100 CAN AF ram access register - pub const MASK_25 = mmio(Address + 0x00000064, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 104 CAN AF ram access register - pub const MASK_26 = mmio(Address + 0x00000068, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 108 CAN AF ram access register - pub const MASK_27 = mmio(Address + 0x0000006c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 112 CAN AF ram access register - pub const MASK_28 = mmio(Address + 0x00000070, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 116 CAN AF ram access register - pub const MASK_29 = mmio(Address + 0x00000074, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 120 CAN AF ram access register - pub const MASK_30 = mmio(Address + 0x00000078, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 124 CAN AF ram access register - pub const MASK_31 = mmio(Address + 0x0000007c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 128 CAN AF ram access register - pub const MASK_32 = mmio(Address + 0x00000080, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 132 CAN AF ram access register - pub const MASK_33 = mmio(Address + 0x00000084, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 136 CAN AF ram access register - pub const MASK_34 = mmio(Address + 0x00000088, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 140 CAN AF ram access register - pub const MASK_35 = mmio(Address + 0x0000008c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 144 CAN AF ram access register - pub const MASK_36 = mmio(Address + 0x00000090, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 148 CAN AF ram access register - pub const MASK_37 = mmio(Address + 0x00000094, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 152 CAN AF ram access register - pub const MASK_38 = mmio(Address + 0x00000098, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 156 CAN AF ram access register - pub const MASK_39 = mmio(Address + 0x0000009c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 160 CAN AF ram access register - pub const MASK_40 = mmio(Address + 0x000000a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 164 CAN AF ram access register - pub const MASK_41 = mmio(Address + 0x000000a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 168 CAN AF ram access register - pub const MASK_42 = mmio(Address + 0x000000a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 172 CAN AF ram access register - pub const MASK_43 = mmio(Address + 0x000000ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 176 CAN AF ram access register - pub const MASK_44 = mmio(Address + 0x000000b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 180 CAN AF ram access register - pub const MASK_45 = mmio(Address + 0x000000b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 184 CAN AF ram access register - pub const MASK_46 = mmio(Address + 0x000000b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 188 CAN AF ram access register - pub const MASK_47 = mmio(Address + 0x000000bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 192 CAN AF ram access register - pub const MASK_48 = mmio(Address + 0x000000c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 196 CAN AF ram access register - pub const MASK_49 = mmio(Address + 0x000000c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 200 CAN AF ram access register - pub const MASK_50 = mmio(Address + 0x000000c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 204 CAN AF ram access register - pub const MASK_51 = mmio(Address + 0x000000cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 208 CAN AF ram access register - pub const MASK_52 = mmio(Address + 0x000000d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 212 CAN AF ram access register - pub const MASK_53 = mmio(Address + 0x000000d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 216 CAN AF ram access register - pub const MASK_54 = mmio(Address + 0x000000d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 220 CAN AF ram access register - pub const MASK_55 = mmio(Address + 0x000000dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 224 CAN AF ram access register - pub const MASK_56 = mmio(Address + 0x000000e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 228 CAN AF ram access register - pub const MASK_57 = mmio(Address + 0x000000e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 232 CAN AF ram access register - pub const MASK_58 = mmio(Address + 0x000000e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 236 CAN AF ram access register - pub const MASK_59 = mmio(Address + 0x000000ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 240 CAN AF ram access register - pub const MASK_60 = mmio(Address + 0x000000f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 244 CAN AF ram access register - pub const MASK_61 = mmio(Address + 0x000000f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 248 CAN AF ram access register - pub const MASK_62 = mmio(Address + 0x000000f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 252 CAN AF ram access register - pub const MASK_63 = mmio(Address + 0x000000fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 256 CAN AF ram access register - pub const MASK_64 = mmio(Address + 0x00000100, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 260 CAN AF ram access register - pub const MASK_65 = mmio(Address + 0x00000104, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 264 CAN AF ram access register - pub const MASK_66 = mmio(Address + 0x00000108, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 268 CAN AF ram access register - pub const MASK_67 = mmio(Address + 0x0000010c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 272 CAN AF ram access register - pub const MASK_68 = mmio(Address + 0x00000110, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 276 CAN AF ram access register - pub const MASK_69 = mmio(Address + 0x00000114, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 280 CAN AF ram access register - pub const MASK_70 = mmio(Address + 0x00000118, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 284 CAN AF ram access register - pub const MASK_71 = mmio(Address + 0x0000011c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 288 CAN AF ram access register - pub const MASK_72 = mmio(Address + 0x00000120, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 292 CAN AF ram access register - pub const MASK_73 = mmio(Address + 0x00000124, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 296 CAN AF ram access register - pub const MASK_74 = mmio(Address + 0x00000128, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 300 CAN AF ram access register - pub const MASK_75 = mmio(Address + 0x0000012c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 304 CAN AF ram access register - pub const MASK_76 = mmio(Address + 0x00000130, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 308 CAN AF ram access register - pub const MASK_77 = mmio(Address + 0x00000134, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 312 CAN AF ram access register - pub const MASK_78 = mmio(Address + 0x00000138, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 316 CAN AF ram access register - pub const MASK_79 = mmio(Address + 0x0000013c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 320 CAN AF ram access register - pub const MASK_80 = mmio(Address + 0x00000140, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 324 CAN AF ram access register - pub const MASK_81 = mmio(Address + 0x00000144, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 328 CAN AF ram access register - pub const MASK_82 = mmio(Address + 0x00000148, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 332 CAN AF ram access register - pub const MASK_83 = mmio(Address + 0x0000014c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 336 CAN AF ram access register - pub const MASK_84 = mmio(Address + 0x00000150, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 340 CAN AF ram access register - pub const MASK_85 = mmio(Address + 0x00000154, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 344 CAN AF ram access register - pub const MASK_86 = mmio(Address + 0x00000158, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 348 CAN AF ram access register - pub const MASK_87 = mmio(Address + 0x0000015c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 352 CAN AF ram access register - pub const MASK_88 = mmio(Address + 0x00000160, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 356 CAN AF ram access register - pub const MASK_89 = mmio(Address + 0x00000164, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 360 CAN AF ram access register - pub const MASK_90 = mmio(Address + 0x00000168, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 364 CAN AF ram access register - pub const MASK_91 = mmio(Address + 0x0000016c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 368 CAN AF ram access register - pub const MASK_92 = mmio(Address + 0x00000170, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 372 CAN AF ram access register - pub const MASK_93 = mmio(Address + 0x00000174, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 376 CAN AF ram access register - pub const MASK_94 = mmio(Address + 0x00000178, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 380 CAN AF ram access register - pub const MASK_95 = mmio(Address + 0x0000017c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 384 CAN AF ram access register - pub const MASK_96 = mmio(Address + 0x00000180, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 388 CAN AF ram access register - pub const MASK_97 = mmio(Address + 0x00000184, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 392 CAN AF ram access register - pub const MASK_98 = mmio(Address + 0x00000188, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 396 CAN AF ram access register - pub const MASK_99 = mmio(Address + 0x0000018c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 400 CAN AF ram access register - pub const MASK_100 = mmio(Address + 0x00000190, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 404 CAN AF ram access register - pub const MASK_101 = mmio(Address + 0x00000194, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 408 CAN AF ram access register - pub const MASK_102 = mmio(Address + 0x00000198, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 412 CAN AF ram access register - pub const MASK_103 = mmio(Address + 0x0000019c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 416 CAN AF ram access register - pub const MASK_104 = mmio(Address + 0x000001a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 420 CAN AF ram access register - pub const MASK_105 = mmio(Address + 0x000001a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 424 CAN AF ram access register - pub const MASK_106 = mmio(Address + 0x000001a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 428 CAN AF ram access register - pub const MASK_107 = mmio(Address + 0x000001ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 432 CAN AF ram access register - pub const MASK_108 = mmio(Address + 0x000001b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 436 CAN AF ram access register - pub const MASK_109 = mmio(Address + 0x000001b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 440 CAN AF ram access register - pub const MASK_110 = mmio(Address + 0x000001b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 444 CAN AF ram access register - pub const MASK_111 = mmio(Address + 0x000001bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 448 CAN AF ram access register - pub const MASK_112 = mmio(Address + 0x000001c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 452 CAN AF ram access register - pub const MASK_113 = mmio(Address + 0x000001c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 456 CAN AF ram access register - pub const MASK_114 = mmio(Address + 0x000001c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 460 CAN AF ram access register - pub const MASK_115 = mmio(Address + 0x000001cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 464 CAN AF ram access register - pub const MASK_116 = mmio(Address + 0x000001d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 468 CAN AF ram access register - pub const MASK_117 = mmio(Address + 0x000001d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 472 CAN AF ram access register - pub const MASK_118 = mmio(Address + 0x000001d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 476 CAN AF ram access register - pub const MASK_119 = mmio(Address + 0x000001dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 480 CAN AF ram access register - pub const MASK_120 = mmio(Address + 0x000001e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 484 CAN AF ram access register - pub const MASK_121 = mmio(Address + 0x000001e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 488 CAN AF ram access register - pub const MASK_122 = mmio(Address + 0x000001e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 492 CAN AF ram access register - pub const MASK_123 = mmio(Address + 0x000001ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 496 CAN AF ram access register - pub const MASK_124 = mmio(Address + 0x000001f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 500 CAN AF ram access register - pub const MASK_125 = mmio(Address + 0x000001f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 504 CAN AF ram access register - pub const MASK_126 = mmio(Address + 0x000001f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 508 CAN AF ram access register - pub const MASK_127 = mmio(Address + 0x000001fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 512 CAN AF ram access register - pub const MASK_128 = mmio(Address + 0x00000200, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 516 CAN AF ram access register - pub const MASK_129 = mmio(Address + 0x00000204, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 520 CAN AF ram access register - pub const MASK_130 = mmio(Address + 0x00000208, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 524 CAN AF ram access register - pub const MASK_131 = mmio(Address + 0x0000020c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 528 CAN AF ram access register - pub const MASK_132 = mmio(Address + 0x00000210, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 532 CAN AF ram access register - pub const MASK_133 = mmio(Address + 0x00000214, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 536 CAN AF ram access register - pub const MASK_134 = mmio(Address + 0x00000218, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 540 CAN AF ram access register - pub const MASK_135 = mmio(Address + 0x0000021c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 544 CAN AF ram access register - pub const MASK_136 = mmio(Address + 0x00000220, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 548 CAN AF ram access register - pub const MASK_137 = mmio(Address + 0x00000224, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 552 CAN AF ram access register - pub const MASK_138 = mmio(Address + 0x00000228, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 556 CAN AF ram access register - pub const MASK_139 = mmio(Address + 0x0000022c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 560 CAN AF ram access register - pub const MASK_140 = mmio(Address + 0x00000230, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 564 CAN AF ram access register - pub const MASK_141 = mmio(Address + 0x00000234, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 568 CAN AF ram access register - pub const MASK_142 = mmio(Address + 0x00000238, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 572 CAN AF ram access register - pub const MASK_143 = mmio(Address + 0x0000023c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 576 CAN AF ram access register - pub const MASK_144 = mmio(Address + 0x00000240, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 580 CAN AF ram access register - pub const MASK_145 = mmio(Address + 0x00000244, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 584 CAN AF ram access register - pub const MASK_146 = mmio(Address + 0x00000248, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 588 CAN AF ram access register - pub const MASK_147 = mmio(Address + 0x0000024c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 592 CAN AF ram access register - pub const MASK_148 = mmio(Address + 0x00000250, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 596 CAN AF ram access register - pub const MASK_149 = mmio(Address + 0x00000254, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 600 CAN AF ram access register - pub const MASK_150 = mmio(Address + 0x00000258, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 604 CAN AF ram access register - pub const MASK_151 = mmio(Address + 0x0000025c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 608 CAN AF ram access register - pub const MASK_152 = mmio(Address + 0x00000260, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 612 CAN AF ram access register - pub const MASK_153 = mmio(Address + 0x00000264, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 616 CAN AF ram access register - pub const MASK_154 = mmio(Address + 0x00000268, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 620 CAN AF ram access register - pub const MASK_155 = mmio(Address + 0x0000026c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 624 CAN AF ram access register - pub const MASK_156 = mmio(Address + 0x00000270, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 628 CAN AF ram access register - pub const MASK_157 = mmio(Address + 0x00000274, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 632 CAN AF ram access register - pub const MASK_158 = mmio(Address + 0x00000278, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 636 CAN AF ram access register - pub const MASK_159 = mmio(Address + 0x0000027c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 640 CAN AF ram access register - pub const MASK_160 = mmio(Address + 0x00000280, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 644 CAN AF ram access register - pub const MASK_161 = mmio(Address + 0x00000284, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 648 CAN AF ram access register - pub const MASK_162 = mmio(Address + 0x00000288, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 652 CAN AF ram access register - pub const MASK_163 = mmio(Address + 0x0000028c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 656 CAN AF ram access register - pub const MASK_164 = mmio(Address + 0x00000290, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 660 CAN AF ram access register - pub const MASK_165 = mmio(Address + 0x00000294, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 664 CAN AF ram access register - pub const MASK_166 = mmio(Address + 0x00000298, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 668 CAN AF ram access register - pub const MASK_167 = mmio(Address + 0x0000029c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 672 CAN AF ram access register - pub const MASK_168 = mmio(Address + 0x000002a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 676 CAN AF ram access register - pub const MASK_169 = mmio(Address + 0x000002a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 680 CAN AF ram access register - pub const MASK_170 = mmio(Address + 0x000002a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 684 CAN AF ram access register - pub const MASK_171 = mmio(Address + 0x000002ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 688 CAN AF ram access register - pub const MASK_172 = mmio(Address + 0x000002b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 692 CAN AF ram access register - pub const MASK_173 = mmio(Address + 0x000002b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 696 CAN AF ram access register - pub const MASK_174 = mmio(Address + 0x000002b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 700 CAN AF ram access register - pub const MASK_175 = mmio(Address + 0x000002bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 704 CAN AF ram access register - pub const MASK_176 = mmio(Address + 0x000002c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 708 CAN AF ram access register - pub const MASK_177 = mmio(Address + 0x000002c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 712 CAN AF ram access register - pub const MASK_178 = mmio(Address + 0x000002c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 716 CAN AF ram access register - pub const MASK_179 = mmio(Address + 0x000002cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 720 CAN AF ram access register - pub const MASK_180 = mmio(Address + 0x000002d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 724 CAN AF ram access register - pub const MASK_181 = mmio(Address + 0x000002d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 728 CAN AF ram access register - pub const MASK_182 = mmio(Address + 0x000002d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 732 CAN AF ram access register - pub const MASK_183 = mmio(Address + 0x000002dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 736 CAN AF ram access register - pub const MASK_184 = mmio(Address + 0x000002e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 740 CAN AF ram access register - pub const MASK_185 = mmio(Address + 0x000002e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 744 CAN AF ram access register - pub const MASK_186 = mmio(Address + 0x000002e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 748 CAN AF ram access register - pub const MASK_187 = mmio(Address + 0x000002ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 752 CAN AF ram access register - pub const MASK_188 = mmio(Address + 0x000002f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 756 CAN AF ram access register - pub const MASK_189 = mmio(Address + 0x000002f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 760 CAN AF ram access register - pub const MASK_190 = mmio(Address + 0x000002f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 764 CAN AF ram access register - pub const MASK_191 = mmio(Address + 0x000002fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 768 CAN AF ram access register - pub const MASK_192 = mmio(Address + 0x00000300, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 772 CAN AF ram access register - pub const MASK_193 = mmio(Address + 0x00000304, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 776 CAN AF ram access register - pub const MASK_194 = mmio(Address + 0x00000308, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 780 CAN AF ram access register - pub const MASK_195 = mmio(Address + 0x0000030c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 784 CAN AF ram access register - pub const MASK_196 = mmio(Address + 0x00000310, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 788 CAN AF ram access register - pub const MASK_197 = mmio(Address + 0x00000314, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 792 CAN AF ram access register - pub const MASK_198 = mmio(Address + 0x00000318, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 796 CAN AF ram access register - pub const MASK_199 = mmio(Address + 0x0000031c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 800 CAN AF ram access register - pub const MASK_200 = mmio(Address + 0x00000320, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 804 CAN AF ram access register - pub const MASK_201 = mmio(Address + 0x00000324, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 808 CAN AF ram access register - pub const MASK_202 = mmio(Address + 0x00000328, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 812 CAN AF ram access register - pub const MASK_203 = mmio(Address + 0x0000032c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 816 CAN AF ram access register - pub const MASK_204 = mmio(Address + 0x00000330, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 820 CAN AF ram access register - pub const MASK_205 = mmio(Address + 0x00000334, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 824 CAN AF ram access register - pub const MASK_206 = mmio(Address + 0x00000338, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 828 CAN AF ram access register - pub const MASK_207 = mmio(Address + 0x0000033c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 832 CAN AF ram access register - pub const MASK_208 = mmio(Address + 0x00000340, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 836 CAN AF ram access register - pub const MASK_209 = mmio(Address + 0x00000344, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 840 CAN AF ram access register - pub const MASK_210 = mmio(Address + 0x00000348, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 844 CAN AF ram access register - pub const MASK_211 = mmio(Address + 0x0000034c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 848 CAN AF ram access register - pub const MASK_212 = mmio(Address + 0x00000350, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 852 CAN AF ram access register - pub const MASK_213 = mmio(Address + 0x00000354, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 856 CAN AF ram access register - pub const MASK_214 = mmio(Address + 0x00000358, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 860 CAN AF ram access register - pub const MASK_215 = mmio(Address + 0x0000035c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 864 CAN AF ram access register - pub const MASK_216 = mmio(Address + 0x00000360, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 868 CAN AF ram access register - pub const MASK_217 = mmio(Address + 0x00000364, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 872 CAN AF ram access register - pub const MASK_218 = mmio(Address + 0x00000368, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 876 CAN AF ram access register - pub const MASK_219 = mmio(Address + 0x0000036c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 880 CAN AF ram access register - pub const MASK_220 = mmio(Address + 0x00000370, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 884 CAN AF ram access register - pub const MASK_221 = mmio(Address + 0x00000374, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 888 CAN AF ram access register - pub const MASK_222 = mmio(Address + 0x00000378, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 892 CAN AF ram access register - pub const MASK_223 = mmio(Address + 0x0000037c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 896 CAN AF ram access register - pub const MASK_224 = mmio(Address + 0x00000380, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 900 CAN AF ram access register - pub const MASK_225 = mmio(Address + 0x00000384, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 904 CAN AF ram access register - pub const MASK_226 = mmio(Address + 0x00000388, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 908 CAN AF ram access register - pub const MASK_227 = mmio(Address + 0x0000038c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 912 CAN AF ram access register - pub const MASK_228 = mmio(Address + 0x00000390, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 916 CAN AF ram access register - pub const MASK_229 = mmio(Address + 0x00000394, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 920 CAN AF ram access register - pub const MASK_230 = mmio(Address + 0x00000398, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 924 CAN AF ram access register - pub const MASK_231 = mmio(Address + 0x0000039c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 928 CAN AF ram access register - pub const MASK_232 = mmio(Address + 0x000003a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 932 CAN AF ram access register - pub const MASK_233 = mmio(Address + 0x000003a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 936 CAN AF ram access register - pub const MASK_234 = mmio(Address + 0x000003a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 940 CAN AF ram access register - pub const MASK_235 = mmio(Address + 0x000003ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 944 CAN AF ram access register - pub const MASK_236 = mmio(Address + 0x000003b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 948 CAN AF ram access register - pub const MASK_237 = mmio(Address + 0x000003b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 952 CAN AF ram access register - pub const MASK_238 = mmio(Address + 0x000003b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 956 CAN AF ram access register - pub const MASK_239 = mmio(Address + 0x000003bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 960 CAN AF ram access register - pub const MASK_240 = mmio(Address + 0x000003c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 964 CAN AF ram access register - pub const MASK_241 = mmio(Address + 0x000003c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 968 CAN AF ram access register - pub const MASK_242 = mmio(Address + 0x000003c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 972 CAN AF ram access register - pub const MASK_243 = mmio(Address + 0x000003cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 976 CAN AF ram access register - pub const MASK_244 = mmio(Address + 0x000003d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 980 CAN AF ram access register - pub const MASK_245 = mmio(Address + 0x000003d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 984 CAN AF ram access register - pub const MASK_246 = mmio(Address + 0x000003d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 988 CAN AF ram access register - pub const MASK_247 = mmio(Address + 0x000003dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 992 CAN AF ram access register - pub const MASK_248 = mmio(Address + 0x000003e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 996 CAN AF ram access register - pub const MASK_249 = mmio(Address + 0x000003e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1000 CAN AF ram access register - pub const MASK_250 = mmio(Address + 0x000003e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1004 CAN AF ram access register - pub const MASK_251 = mmio(Address + 0x000003ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1008 CAN AF ram access register - pub const MASK_252 = mmio(Address + 0x000003f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1012 CAN AF ram access register - pub const MASK_253 = mmio(Address + 0x000003f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1016 CAN AF ram access register - pub const MASK_254 = mmio(Address + 0x000003f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1020 CAN AF ram access register - pub const MASK_255 = mmio(Address + 0x000003fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1024 CAN AF ram access register - pub const MASK_256 = mmio(Address + 0x00000400, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1028 CAN AF ram access register - pub const MASK_257 = mmio(Address + 0x00000404, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1032 CAN AF ram access register - pub const MASK_258 = mmio(Address + 0x00000408, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1036 CAN AF ram access register - pub const MASK_259 = mmio(Address + 0x0000040c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1040 CAN AF ram access register - pub const MASK_260 = mmio(Address + 0x00000410, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1044 CAN AF ram access register - pub const MASK_261 = mmio(Address + 0x00000414, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1048 CAN AF ram access register - pub const MASK_262 = mmio(Address + 0x00000418, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1052 CAN AF ram access register - pub const MASK_263 = mmio(Address + 0x0000041c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1056 CAN AF ram access register - pub const MASK_264 = mmio(Address + 0x00000420, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1060 CAN AF ram access register - pub const MASK_265 = mmio(Address + 0x00000424, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1064 CAN AF ram access register - pub const MASK_266 = mmio(Address + 0x00000428, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1068 CAN AF ram access register - pub const MASK_267 = mmio(Address + 0x0000042c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1072 CAN AF ram access register - pub const MASK_268 = mmio(Address + 0x00000430, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1076 CAN AF ram access register - pub const MASK_269 = mmio(Address + 0x00000434, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1080 CAN AF ram access register - pub const MASK_270 = mmio(Address + 0x00000438, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1084 CAN AF ram access register - pub const MASK_271 = mmio(Address + 0x0000043c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1088 CAN AF ram access register - pub const MASK_272 = mmio(Address + 0x00000440, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1092 CAN AF ram access register - pub const MASK_273 = mmio(Address + 0x00000444, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1096 CAN AF ram access register - pub const MASK_274 = mmio(Address + 0x00000448, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1100 CAN AF ram access register - pub const MASK_275 = mmio(Address + 0x0000044c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1104 CAN AF ram access register - pub const MASK_276 = mmio(Address + 0x00000450, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1108 CAN AF ram access register - pub const MASK_277 = mmio(Address + 0x00000454, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1112 CAN AF ram access register - pub const MASK_278 = mmio(Address + 0x00000458, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1116 CAN AF ram access register - pub const MASK_279 = mmio(Address + 0x0000045c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1120 CAN AF ram access register - pub const MASK_280 = mmio(Address + 0x00000460, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1124 CAN AF ram access register - pub const MASK_281 = mmio(Address + 0x00000464, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1128 CAN AF ram access register - pub const MASK_282 = mmio(Address + 0x00000468, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1132 CAN AF ram access register - pub const MASK_283 = mmio(Address + 0x0000046c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1136 CAN AF ram access register - pub const MASK_284 = mmio(Address + 0x00000470, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1140 CAN AF ram access register - pub const MASK_285 = mmio(Address + 0x00000474, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1144 CAN AF ram access register - pub const MASK_286 = mmio(Address + 0x00000478, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1148 CAN AF ram access register - pub const MASK_287 = mmio(Address + 0x0000047c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1152 CAN AF ram access register - pub const MASK_288 = mmio(Address + 0x00000480, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1156 CAN AF ram access register - pub const MASK_289 = mmio(Address + 0x00000484, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1160 CAN AF ram access register - pub const MASK_290 = mmio(Address + 0x00000488, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1164 CAN AF ram access register - pub const MASK_291 = mmio(Address + 0x0000048c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1168 CAN AF ram access register - pub const MASK_292 = mmio(Address + 0x00000490, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1172 CAN AF ram access register - pub const MASK_293 = mmio(Address + 0x00000494, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1176 CAN AF ram access register - pub const MASK_294 = mmio(Address + 0x00000498, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1180 CAN AF ram access register - pub const MASK_295 = mmio(Address + 0x0000049c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1184 CAN AF ram access register - pub const MASK_296 = mmio(Address + 0x000004a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1188 CAN AF ram access register - pub const MASK_297 = mmio(Address + 0x000004a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1192 CAN AF ram access register - pub const MASK_298 = mmio(Address + 0x000004a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1196 CAN AF ram access register - pub const MASK_299 = mmio(Address + 0x000004ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1200 CAN AF ram access register - pub const MASK_300 = mmio(Address + 0x000004b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1204 CAN AF ram access register - pub const MASK_301 = mmio(Address + 0x000004b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1208 CAN AF ram access register - pub const MASK_302 = mmio(Address + 0x000004b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1212 CAN AF ram access register - pub const MASK_303 = mmio(Address + 0x000004bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1216 CAN AF ram access register - pub const MASK_304 = mmio(Address + 0x000004c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1220 CAN AF ram access register - pub const MASK_305 = mmio(Address + 0x000004c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1224 CAN AF ram access register - pub const MASK_306 = mmio(Address + 0x000004c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1228 CAN AF ram access register - pub const MASK_307 = mmio(Address + 0x000004cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1232 CAN AF ram access register - pub const MASK_308 = mmio(Address + 0x000004d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1236 CAN AF ram access register - pub const MASK_309 = mmio(Address + 0x000004d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1240 CAN AF ram access register - pub const MASK_310 = mmio(Address + 0x000004d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1244 CAN AF ram access register - pub const MASK_311 = mmio(Address + 0x000004dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1248 CAN AF ram access register - pub const MASK_312 = mmio(Address + 0x000004e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1252 CAN AF ram access register - pub const MASK_313 = mmio(Address + 0x000004e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1256 CAN AF ram access register - pub const MASK_314 = mmio(Address + 0x000004e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1260 CAN AF ram access register - pub const MASK_315 = mmio(Address + 0x000004ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1264 CAN AF ram access register - pub const MASK_316 = mmio(Address + 0x000004f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1268 CAN AF ram access register - pub const MASK_317 = mmio(Address + 0x000004f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1272 CAN AF ram access register - pub const MASK_318 = mmio(Address + 0x000004f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1276 CAN AF ram access register - pub const MASK_319 = mmio(Address + 0x000004fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1280 CAN AF ram access register - pub const MASK_320 = mmio(Address + 0x00000500, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1284 CAN AF ram access register - pub const MASK_321 = mmio(Address + 0x00000504, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1288 CAN AF ram access register - pub const MASK_322 = mmio(Address + 0x00000508, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1292 CAN AF ram access register - pub const MASK_323 = mmio(Address + 0x0000050c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1296 CAN AF ram access register - pub const MASK_324 = mmio(Address + 0x00000510, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1300 CAN AF ram access register - pub const MASK_325 = mmio(Address + 0x00000514, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1304 CAN AF ram access register - pub const MASK_326 = mmio(Address + 0x00000518, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1308 CAN AF ram access register - pub const MASK_327 = mmio(Address + 0x0000051c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1312 CAN AF ram access register - pub const MASK_328 = mmio(Address + 0x00000520, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1316 CAN AF ram access register - pub const MASK_329 = mmio(Address + 0x00000524, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1320 CAN AF ram access register - pub const MASK_330 = mmio(Address + 0x00000528, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1324 CAN AF ram access register - pub const MASK_331 = mmio(Address + 0x0000052c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1328 CAN AF ram access register - pub const MASK_332 = mmio(Address + 0x00000530, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1332 CAN AF ram access register - pub const MASK_333 = mmio(Address + 0x00000534, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1336 CAN AF ram access register - pub const MASK_334 = mmio(Address + 0x00000538, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1340 CAN AF ram access register - pub const MASK_335 = mmio(Address + 0x0000053c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1344 CAN AF ram access register - pub const MASK_336 = mmio(Address + 0x00000540, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1348 CAN AF ram access register - pub const MASK_337 = mmio(Address + 0x00000544, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1352 CAN AF ram access register - pub const MASK_338 = mmio(Address + 0x00000548, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1356 CAN AF ram access register - pub const MASK_339 = mmio(Address + 0x0000054c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1360 CAN AF ram access register - pub const MASK_340 = mmio(Address + 0x00000550, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1364 CAN AF ram access register - pub const MASK_341 = mmio(Address + 0x00000554, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1368 CAN AF ram access register - pub const MASK_342 = mmio(Address + 0x00000558, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1372 CAN AF ram access register - pub const MASK_343 = mmio(Address + 0x0000055c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1376 CAN AF ram access register - pub const MASK_344 = mmio(Address + 0x00000560, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1380 CAN AF ram access register - pub const MASK_345 = mmio(Address + 0x00000564, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1384 CAN AF ram access register - pub const MASK_346 = mmio(Address + 0x00000568, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1388 CAN AF ram access register - pub const MASK_347 = mmio(Address + 0x0000056c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1392 CAN AF ram access register - pub const MASK_348 = mmio(Address + 0x00000570, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1396 CAN AF ram access register - pub const MASK_349 = mmio(Address + 0x00000574, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1400 CAN AF ram access register - pub const MASK_350 = mmio(Address + 0x00000578, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1404 CAN AF ram access register - pub const MASK_351 = mmio(Address + 0x0000057c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1408 CAN AF ram access register - pub const MASK_352 = mmio(Address + 0x00000580, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1412 CAN AF ram access register - pub const MASK_353 = mmio(Address + 0x00000584, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1416 CAN AF ram access register - pub const MASK_354 = mmio(Address + 0x00000588, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1420 CAN AF ram access register - pub const MASK_355 = mmio(Address + 0x0000058c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1424 CAN AF ram access register - pub const MASK_356 = mmio(Address + 0x00000590, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1428 CAN AF ram access register - pub const MASK_357 = mmio(Address + 0x00000594, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1432 CAN AF ram access register - pub const MASK_358 = mmio(Address + 0x00000598, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1436 CAN AF ram access register - pub const MASK_359 = mmio(Address + 0x0000059c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1440 CAN AF ram access register - pub const MASK_360 = mmio(Address + 0x000005a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1444 CAN AF ram access register - pub const MASK_361 = mmio(Address + 0x000005a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1448 CAN AF ram access register - pub const MASK_362 = mmio(Address + 0x000005a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1452 CAN AF ram access register - pub const MASK_363 = mmio(Address + 0x000005ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1456 CAN AF ram access register - pub const MASK_364 = mmio(Address + 0x000005b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1460 CAN AF ram access register - pub const MASK_365 = mmio(Address + 0x000005b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1464 CAN AF ram access register - pub const MASK_366 = mmio(Address + 0x000005b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1468 CAN AF ram access register - pub const MASK_367 = mmio(Address + 0x000005bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1472 CAN AF ram access register - pub const MASK_368 = mmio(Address + 0x000005c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1476 CAN AF ram access register - pub const MASK_369 = mmio(Address + 0x000005c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1480 CAN AF ram access register - pub const MASK_370 = mmio(Address + 0x000005c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1484 CAN AF ram access register - pub const MASK_371 = mmio(Address + 0x000005cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1488 CAN AF ram access register - pub const MASK_372 = mmio(Address + 0x000005d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1492 CAN AF ram access register - pub const MASK_373 = mmio(Address + 0x000005d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1496 CAN AF ram access register - pub const MASK_374 = mmio(Address + 0x000005d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1500 CAN AF ram access register - pub const MASK_375 = mmio(Address + 0x000005dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1504 CAN AF ram access register - pub const MASK_376 = mmio(Address + 0x000005e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1508 CAN AF ram access register - pub const MASK_377 = mmio(Address + 0x000005e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1512 CAN AF ram access register - pub const MASK_378 = mmio(Address + 0x000005e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1516 CAN AF ram access register - pub const MASK_379 = mmio(Address + 0x000005ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1520 CAN AF ram access register - pub const MASK_380 = mmio(Address + 0x000005f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1524 CAN AF ram access register - pub const MASK_381 = mmio(Address + 0x000005f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1528 CAN AF ram access register - pub const MASK_382 = mmio(Address + 0x000005f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1532 CAN AF ram access register - pub const MASK_383 = mmio(Address + 0x000005fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1536 CAN AF ram access register - pub const MASK_384 = mmio(Address + 0x00000600, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1540 CAN AF ram access register - pub const MASK_385 = mmio(Address + 0x00000604, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1544 CAN AF ram access register - pub const MASK_386 = mmio(Address + 0x00000608, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1548 CAN AF ram access register - pub const MASK_387 = mmio(Address + 0x0000060c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1552 CAN AF ram access register - pub const MASK_388 = mmio(Address + 0x00000610, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1556 CAN AF ram access register - pub const MASK_389 = mmio(Address + 0x00000614, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1560 CAN AF ram access register - pub const MASK_390 = mmio(Address + 0x00000618, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1564 CAN AF ram access register - pub const MASK_391 = mmio(Address + 0x0000061c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1568 CAN AF ram access register - pub const MASK_392 = mmio(Address + 0x00000620, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1572 CAN AF ram access register - pub const MASK_393 = mmio(Address + 0x00000624, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1576 CAN AF ram access register - pub const MASK_394 = mmio(Address + 0x00000628, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1580 CAN AF ram access register - pub const MASK_395 = mmio(Address + 0x0000062c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1584 CAN AF ram access register - pub const MASK_396 = mmio(Address + 0x00000630, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1588 CAN AF ram access register - pub const MASK_397 = mmio(Address + 0x00000634, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1592 CAN AF ram access register - pub const MASK_398 = mmio(Address + 0x00000638, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1596 CAN AF ram access register - pub const MASK_399 = mmio(Address + 0x0000063c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1600 CAN AF ram access register - pub const MASK_400 = mmio(Address + 0x00000640, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1604 CAN AF ram access register - pub const MASK_401 = mmio(Address + 0x00000644, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1608 CAN AF ram access register - pub const MASK_402 = mmio(Address + 0x00000648, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1612 CAN AF ram access register - pub const MASK_403 = mmio(Address + 0x0000064c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1616 CAN AF ram access register - pub const MASK_404 = mmio(Address + 0x00000650, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1620 CAN AF ram access register - pub const MASK_405 = mmio(Address + 0x00000654, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1624 CAN AF ram access register - pub const MASK_406 = mmio(Address + 0x00000658, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1628 CAN AF ram access register - pub const MASK_407 = mmio(Address + 0x0000065c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1632 CAN AF ram access register - pub const MASK_408 = mmio(Address + 0x00000660, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1636 CAN AF ram access register - pub const MASK_409 = mmio(Address + 0x00000664, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1640 CAN AF ram access register - pub const MASK_410 = mmio(Address + 0x00000668, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1644 CAN AF ram access register - pub const MASK_411 = mmio(Address + 0x0000066c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1648 CAN AF ram access register - pub const MASK_412 = mmio(Address + 0x00000670, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1652 CAN AF ram access register - pub const MASK_413 = mmio(Address + 0x00000674, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1656 CAN AF ram access register - pub const MASK_414 = mmio(Address + 0x00000678, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1660 CAN AF ram access register - pub const MASK_415 = mmio(Address + 0x0000067c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1664 CAN AF ram access register - pub const MASK_416 = mmio(Address + 0x00000680, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1668 CAN AF ram access register - pub const MASK_417 = mmio(Address + 0x00000684, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1672 CAN AF ram access register - pub const MASK_418 = mmio(Address + 0x00000688, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1676 CAN AF ram access register - pub const MASK_419 = mmio(Address + 0x0000068c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1680 CAN AF ram access register - pub const MASK_420 = mmio(Address + 0x00000690, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1684 CAN AF ram access register - pub const MASK_421 = mmio(Address + 0x00000694, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1688 CAN AF ram access register - pub const MASK_422 = mmio(Address + 0x00000698, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1692 CAN AF ram access register - pub const MASK_423 = mmio(Address + 0x0000069c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1696 CAN AF ram access register - pub const MASK_424 = mmio(Address + 0x000006a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1700 CAN AF ram access register - pub const MASK_425 = mmio(Address + 0x000006a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1704 CAN AF ram access register - pub const MASK_426 = mmio(Address + 0x000006a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1708 CAN AF ram access register - pub const MASK_427 = mmio(Address + 0x000006ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1712 CAN AF ram access register - pub const MASK_428 = mmio(Address + 0x000006b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1716 CAN AF ram access register - pub const MASK_429 = mmio(Address + 0x000006b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1720 CAN AF ram access register - pub const MASK_430 = mmio(Address + 0x000006b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1724 CAN AF ram access register - pub const MASK_431 = mmio(Address + 0x000006bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1728 CAN AF ram access register - pub const MASK_432 = mmio(Address + 0x000006c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1732 CAN AF ram access register - pub const MASK_433 = mmio(Address + 0x000006c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1736 CAN AF ram access register - pub const MASK_434 = mmio(Address + 0x000006c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1740 CAN AF ram access register - pub const MASK_435 = mmio(Address + 0x000006cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1744 CAN AF ram access register - pub const MASK_436 = mmio(Address + 0x000006d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1748 CAN AF ram access register - pub const MASK_437 = mmio(Address + 0x000006d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1752 CAN AF ram access register - pub const MASK_438 = mmio(Address + 0x000006d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1756 CAN AF ram access register - pub const MASK_439 = mmio(Address + 0x000006dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1760 CAN AF ram access register - pub const MASK_440 = mmio(Address + 0x000006e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1764 CAN AF ram access register - pub const MASK_441 = mmio(Address + 0x000006e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1768 CAN AF ram access register - pub const MASK_442 = mmio(Address + 0x000006e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1772 CAN AF ram access register - pub const MASK_443 = mmio(Address + 0x000006ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1776 CAN AF ram access register - pub const MASK_444 = mmio(Address + 0x000006f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1780 CAN AF ram access register - pub const MASK_445 = mmio(Address + 0x000006f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1784 CAN AF ram access register - pub const MASK_446 = mmio(Address + 0x000006f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1788 CAN AF ram access register - pub const MASK_447 = mmio(Address + 0x000006fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1792 CAN AF ram access register - pub const MASK_448 = mmio(Address + 0x00000700, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1796 CAN AF ram access register - pub const MASK_449 = mmio(Address + 0x00000704, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1800 CAN AF ram access register - pub const MASK_450 = mmio(Address + 0x00000708, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1804 CAN AF ram access register - pub const MASK_451 = mmio(Address + 0x0000070c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1808 CAN AF ram access register - pub const MASK_452 = mmio(Address + 0x00000710, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1812 CAN AF ram access register - pub const MASK_453 = mmio(Address + 0x00000714, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1816 CAN AF ram access register - pub const MASK_454 = mmio(Address + 0x00000718, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1820 CAN AF ram access register - pub const MASK_455 = mmio(Address + 0x0000071c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1824 CAN AF ram access register - pub const MASK_456 = mmio(Address + 0x00000720, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1828 CAN AF ram access register - pub const MASK_457 = mmio(Address + 0x00000724, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1832 CAN AF ram access register - pub const MASK_458 = mmio(Address + 0x00000728, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1836 CAN AF ram access register - pub const MASK_459 = mmio(Address + 0x0000072c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1840 CAN AF ram access register - pub const MASK_460 = mmio(Address + 0x00000730, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1844 CAN AF ram access register - pub const MASK_461 = mmio(Address + 0x00000734, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1848 CAN AF ram access register - pub const MASK_462 = mmio(Address + 0x00000738, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1852 CAN AF ram access register - pub const MASK_463 = mmio(Address + 0x0000073c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1856 CAN AF ram access register - pub const MASK_464 = mmio(Address + 0x00000740, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1860 CAN AF ram access register - pub const MASK_465 = mmio(Address + 0x00000744, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1864 CAN AF ram access register - pub const MASK_466 = mmio(Address + 0x00000748, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1868 CAN AF ram access register - pub const MASK_467 = mmio(Address + 0x0000074c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1872 CAN AF ram access register - pub const MASK_468 = mmio(Address + 0x00000750, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1876 CAN AF ram access register - pub const MASK_469 = mmio(Address + 0x00000754, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1880 CAN AF ram access register - pub const MASK_470 = mmio(Address + 0x00000758, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1884 CAN AF ram access register - pub const MASK_471 = mmio(Address + 0x0000075c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1888 CAN AF ram access register - pub const MASK_472 = mmio(Address + 0x00000760, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1892 CAN AF ram access register - pub const MASK_473 = mmio(Address + 0x00000764, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1896 CAN AF ram access register - pub const MASK_474 = mmio(Address + 0x00000768, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1900 CAN AF ram access register - pub const MASK_475 = mmio(Address + 0x0000076c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1904 CAN AF ram access register - pub const MASK_476 = mmio(Address + 0x00000770, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1908 CAN AF ram access register - pub const MASK_477 = mmio(Address + 0x00000774, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1912 CAN AF ram access register - pub const MASK_478 = mmio(Address + 0x00000778, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1916 CAN AF ram access register - pub const MASK_479 = mmio(Address + 0x0000077c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1920 CAN AF ram access register - pub const MASK_480 = mmio(Address + 0x00000780, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1924 CAN AF ram access register - pub const MASK_481 = mmio(Address + 0x00000784, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1928 CAN AF ram access register - pub const MASK_482 = mmio(Address + 0x00000788, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1932 CAN AF ram access register - pub const MASK_483 = mmio(Address + 0x0000078c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1936 CAN AF ram access register - pub const MASK_484 = mmio(Address + 0x00000790, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1940 CAN AF ram access register - pub const MASK_485 = mmio(Address + 0x00000794, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1944 CAN AF ram access register - pub const MASK_486 = mmio(Address + 0x00000798, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1948 CAN AF ram access register - pub const MASK_487 = mmio(Address + 0x0000079c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1952 CAN AF ram access register - pub const MASK_488 = mmio(Address + 0x000007a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1956 CAN AF ram access register - pub const MASK_489 = mmio(Address + 0x000007a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1960 CAN AF ram access register - pub const MASK_490 = mmio(Address + 0x000007a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1964 CAN AF ram access register - pub const MASK_491 = mmio(Address + 0x000007ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1968 CAN AF ram access register - pub const MASK_492 = mmio(Address + 0x000007b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1972 CAN AF ram access register - pub const MASK_493 = mmio(Address + 0x000007b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1976 CAN AF ram access register - pub const MASK_494 = mmio(Address + 0x000007b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1980 CAN AF ram access register - pub const MASK_495 = mmio(Address + 0x000007bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1984 CAN AF ram access register - pub const MASK_496 = mmio(Address + 0x000007c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1988 CAN AF ram access register - pub const MASK_497 = mmio(Address + 0x000007c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1992 CAN AF ram access register - pub const MASK_498 = mmio(Address + 0x000007c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1996 CAN AF ram access register - pub const MASK_499 = mmio(Address + 0x000007cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2000 CAN AF ram access register - pub const MASK_500 = mmio(Address + 0x000007d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2004 CAN AF ram access register - pub const MASK_501 = mmio(Address + 0x000007d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2008 CAN AF ram access register - pub const MASK_502 = mmio(Address + 0x000007d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2012 CAN AF ram access register - pub const MASK_503 = mmio(Address + 0x000007dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2016 CAN AF ram access register - pub const MASK_504 = mmio(Address + 0x000007e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2020 CAN AF ram access register - pub const MASK_505 = mmio(Address + 0x000007e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2024 CAN AF ram access register - pub const MASK_506 = mmio(Address + 0x000007e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2028 CAN AF ram access register - pub const MASK_507 = mmio(Address + 0x000007ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2032 CAN AF ram access register - pub const MASK_508 = mmio(Address + 0x000007f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2036 CAN AF ram access register - pub const MASK_509 = mmio(Address + 0x000007f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2040 CAN AF ram access register - pub const MASK_510 = mmio(Address + 0x000007f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2044 CAN AF ram access register - pub const MASK_511 = mmio(Address + 0x000007fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); -}; -pub const CANAF = extern struct { - pub const Address: u32 = 0x4003c000; - // byte offset: 0 Acceptance Filter Register - pub const AFMR = mmio(Address + 0x00000000, 32, packed struct { - ACCOFF: u1, // bit offset: 0 desc: if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored. - ACCBP: u1, // bit offset: 1 desc: All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers. - EFCAN: enum(u1) { // bit offset: 2 desc: FullCAN mode - @"SOFTWARE_MUST_READ_A" = 0, // desc: Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers. - @"THE_ACCEPTANCE_FILTE" = 1, // desc: The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Standard Frame Individual Start Address Register - pub const SFF_SA = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - SFF_SA: u9, // bit offset: 2 desc: The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Standard Frame Group Start Address Register - pub const SFF_GRP_SA = mmio(Address + 0x00000008, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - SFF_GRP_SA: u10, // bit offset: 2 desc: The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. - // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Extended Frame Start Address Register - pub const EFF_SA = mmio(Address + 0x0000000c, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - EFF_SA: u9, // bit offset: 2 desc: The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Extended Frame Group Start Address Register - pub const EFF_GRP_SA = mmio(Address + 0x00000010, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - EFF_GRP_SA: u10, // bit offset: 2 desc: The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. - // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 End of AF Tables register - pub const ENDOFTABLE = mmio(Address + 0x00000014, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - ENDOFTABLE: u10, // bit offset: 2 desc: The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table. - // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 LUT Error Address register - pub const LUTERRAD = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - LUTERRAD: u9, // bit offset: 2 desc: It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 LUT Error Register - pub const LUTERR = mmio(Address + 0x0000001c, 32, packed struct { - LUTERR: u1, // bit offset: 0 desc: This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC. - // RESERVED: u31, // bit offset: 1 desc: Reserved, the value read from a reserved bit is not defined. - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 FullCAN interrupt enable register - pub const FCANIE = mmio(Address + 0x00000020, 32, packed struct { - FCANIE: u1, // bit offset: 0 desc: Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. - // RESERVED: u31, // bit offset: 1 desc: Reserved. Read value is undefined, only zero should be written. - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 FullCAN interrupt and capture register0 - pub const FCANIC0 = mmio(Address + 0x00000024, 32, packed struct { - INTPND: u32, // bit offset: 0 desc: FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31. - }); - // byte offset: 40 FullCAN interrupt and capture register1 - pub const FCANIC1 = mmio(Address + 0x00000028, 32, packed struct { - IntPnd32: u32, // bit offset: 0 desc: FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63. - }); -}; -pub const CCAN = extern struct { - pub const Address: u32 = 0x40040000; - // byte offset: 0 CAN Central Transmit Status Register - pub const TXSR = mmio(Address + 0x00000000, 32, packed struct { - TS1: u1, // bit offset: 0 desc: When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). - TS2: u1, // bit offset: 1 desc: When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) - // RESERVED: u6, // bit offset: 2 desc: Reserved, the value read from a reserved bit is not defined. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TBS1: u1, // bit offset: 8 desc: When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR). - TBS2: u1, // bit offset: 9 desc: When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR). - // RESERVED: u6, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - TCS1: u1, // bit offset: 16 desc: When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR). - TCS2: u1, // bit offset: 17 desc: When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR). - // RESERVED: u14, // bit offset: 18 desc: Reserved, the value read from a reserved bit is not defined. - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 CAN Central Receive Status Register - pub const RXSR = mmio(Address + 0x00000004, 32, packed struct { - RS1: u1, // bit offset: 0 desc: When 1, CAN1 is receiving a message (same as RS in CAN1GSR). - RS2: u1, // bit offset: 1 desc: When 1, CAN2 is receiving a message (same as RS in CAN2GSR). - // RESERVED: u6, // bit offset: 2 desc: Reserved, the value read from a reserved bit is not defined. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RB1: u1, // bit offset: 8 desc: When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR). - RB2: u1, // bit offset: 9 desc: When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR). - // RESERVED: u6, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - DOS1: u1, // bit offset: 16 desc: When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR). - DOS2: u1, // bit offset: 17 desc: When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR). - // RESERVED: u14, // bit offset: 18 desc: Reserved, the value read from a reserved bit is not defined. - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 CAN Central Miscellaneous Register - pub const MSR = mmio(Address + 0x00000008, 32, packed struct { - E1: u1, // bit offset: 0 desc: When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR) - E2: u1, // bit offset: 1 desc: When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR) - // RESERVED: u6, // bit offset: 2 desc: Reserved, the value read from a reserved bit is not defined. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - BS1: u1, // bit offset: 8 desc: When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR). - BS2: u1, // bit offset: 9 desc: When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR). - // RESERVED: u22, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const CAN1 = extern struct { - pub const Address: u32 = 0x40044000; - // byte offset: 0 Controls the operating mode of the CAN Controller. - pub const MOD = mmio(Address + 0x00000000, 32, packed struct { - RM: enum(u1) { // bit offset: 0 desc: Reset Mode. - @"NORMAL_THE_CAN_CONTR" = 0, // desc: Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written. - @"RESET_CAN_OPERATION" = 1, // desc: Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted. - }, - LOM: enum(u1) { // bit offset: 1 desc: Listen Only Mode. - @"NORMAL_THE_CAN_CONT" = 0, // desc: Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value. - @"LISTEN_ONLY_THE_CON" = 1, // desc: Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging. - }, - STM: enum(u1) { // bit offset: 2 desc: Self Test Mode. - @"NORMAL_A_TRANSMITTE" = 0, // desc: Normal. A transmitted message must be acknowledged to be considered successful. - @"SELF_TEST_THE_CONTR" = 1, // desc: Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR. - }, - TPM: enum(u1) { // bit offset: 3 desc: Transmit Priority Mode. - @"CAN_ID_THE_TRANSMIT" = 0, // desc: CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier. - @"LOCAL_PRIORITY_THE_" = 1, // desc: Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer. - }, - SM: enum(u1) { // bit offset: 4 desc: Sleep Mode. - @"WAKE_UP_NORMAL_OPER" = 0, // desc: Wake-up. Normal operation. - @"SLEEP_THE_CAN_CONTR" = 1, // desc: Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565. - }, - RPM: enum(u1) { // bit offset: 5 desc: Receive Polarity Mode. - @"LOW_ACTIVE_RD_INPUT" = 0, // desc: Low active. RD input is active Low (dominant bit = 0). - @"HIGH_ACTIVE_RD_INPU" = 1, // desc: High active. RD input is active High (dominant bit = 1) -- reverse polarity. - }, - // RESERVED: u1, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - TM: enum(u1) { // bit offset: 7 desc: Test Mode. - @"DISABLED_NORMAL_OPE" = 0, // desc: Disabled. Normal operation. - @"ENABLED_THE_TD_PIN_" = 1, // desc: Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Command bits that affect the state of the CAN Controller - pub const CMR = mmio(Address + 0x00000004, 32, packed struct { - TR: enum(u1) { // bit offset: 0 desc: Transmission Request. - @"ABSENT_NO_TRANSMISSI" = 0, // desc: Absent.No transmission request. - @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB)) - }, - AT: enum(u1) { // bit offset: 1 desc: Abort Transmission. - @"NO_ACTION_DO_NOT_AB" = 0, // desc: No action. Do not abort the transmission. - @"PRESENT_IF_NOT_ALRE" = 1, // desc: Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled. - }, - RRB: enum(u1) { // bit offset: 2 desc: Release Receive Buffer. - @"NO_ACTION_DO_NOT_RE" = 0, // desc: No action. Do not release the receive buffer. - @"RELEASED_THE_INFORM" = 1, // desc: Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s). - }, - CDO: enum(u1) { // bit offset: 3 desc: Clear Data Overrun. - @"NO_ACTION_DO_NOT_CL" = 0, // desc: No action. Do not clear the data overrun bit. - @"CLEAR_THE_DATA_OVER" = 1, // desc: Clear. The Data Overrun bit in Status Register(s) is cleared. - }, - SRR: enum(u1) { // bit offset: 4 desc: Self Reception Request. - @"ABSENT_NO_SELF_RECE" = 0, // desc: Absent. No self reception request. - @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter. - }, - STB1: enum(u1) { // bit offset: 5 desc: Select Tx Buffer 1. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 1 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 1 is selected for transmission. - }, - STB2: enum(u1) { // bit offset: 6 desc: Select Tx Buffer 2. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 2 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 2 is selected for transmission. - }, - STB3: enum(u1) { // bit offset: 7 desc: Select Tx Buffer 3. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 3 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 3 is selected for transmission. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1. - pub const GSR = mmio(Address + 0x00000008, 32, packed struct { - RBS: enum(u1) { // bit offset: 0 desc: Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. - @"EMPTY_NO_MESSAGE_IS" = 0, // desc: Empty. No message is available. - @"FULL_AT_LEAST_ONE_C" = 1, // desc: Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available. - }, - DOS: enum(u1) { // bit offset: 1 desc: Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. - @"ABSENT_NO_DATA_OVER" = 0, // desc: Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset). - @"OVERRUN_A_MESSAGE_W" = 1, // desc: Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer). - }, - TBS: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status. - @"LOCKED_AT_LEAST_ONE" = 0, // desc: Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s). - @"RELEASED_ALL_THREE_" = 1, // desc: Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS: enum(u1) { // bit offset: 3 desc: Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. - @"INCOMPLETE_AT_LEAST" = 0, // desc: Incomplete. At least one requested transmission has not been successfully completed yet. - @"COMPLETE_ALL_REQUES" = 1, // desc: Complete. All requested transmission(s) has (have) been successfully completed. - }, - RS: enum(u1) { // bit offset: 4 desc: Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. - @"RECEIVE_THE_CAN_CON" = 1, // desc: Receive. The CAN controller is receiving a message. - }, - TS: enum(u1) { // bit offset: 5 desc: Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN controller is sending a message. - }, - ES: enum(u1) { // bit offset: 6 desc: Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). - @"OK_BOTH_ERROR_COUNT" = 0, // desc: OK. Both error counters are below the Error Warning Limit. - @"ERROR_ONE_OR_BOTH_O" = 1, // desc: Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register. - }, - BS: enum(u1) { // bit offset: 7 desc: Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. - @"BUS_ON_THE_CAN_CONT" = 0, // desc: Bus-on. The CAN Controller is involved in bus activities - @"BUS_OFF_THE_CAN_CON" = 1, // desc: Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255. - }, - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RXERR: u8, // bit offset: 16 desc: The current value of the Rx Error Counter (an 8-bit value). - TXERR: u8, // bit offset: 24 desc: The current value of the Tx Error Counter (an 8-bit value). - }); - // byte offset: 12 Interrupt status, Arbitration Lost Capture, Error Code Capture - pub const ICR = mmio(Address + 0x0000000c, 32, packed struct { - RI: enum(u1) { // bit offset: 0 desc: Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI1: enum(u1) { // bit offset: 1 desc: Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - EI: enum(u1) { // bit offset: 2 desc: Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - DOI: enum(u1) { // bit offset: 3 desc: Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - WUI: enum(u1) { // bit offset: 4 desc: Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - EPI: enum(u1) { // bit offset: 5 desc: Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - ALI: enum(u1) { // bit offset: 6 desc: Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - BEI: enum(u1) { // bit offset: 7 desc: Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - IDI: enum(u1) { // bit offset: 8 desc: ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI2: enum(u1) { // bit offset: 9 desc: Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI3: enum(u1) { // bit offset: 10 desc: Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ERRBIT4_0: u5, // bit offset: 16 desc: Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. - ERRDIR: enum(u1) { // bit offset: 21 desc: When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. - @"ERROR_OCCURRED_DURIN" = 0, // desc: Error occurred during transmitting. - @"ERROR_OCCURRED_DURIN" = 1, // desc: Error occurred during receiving. - }, - ERRC1_0: enum(u2) { // bit offset: 22 desc: When the CAN controller detects a bus error, the type of error is captured in this field: - @"BIT_ERROR" = 0, // desc: Bit error - @"FORM_ERROR" = 1, // desc: Form error - @"STUFF_ERROR" = 2, // desc: Stuff error - @"OTHER_ERROR" = 3, // desc: Other error - }, - ALCBIT: u8, // bit offset: 24 desc: Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again. - }); - // byte offset: 16 Interrupt Enable - pub const IER = mmio(Address + 0x00000010, 32, packed struct { - RIE: u1, // bit offset: 0 desc: Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. - TIE1: u1, // bit offset: 1 desc: Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - EIE: u1, // bit offset: 2 desc: Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. - DOIE: u1, // bit offset: 3 desc: Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. - WUIE: u1, // bit offset: 4 desc: Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. - EPIE: u1, // bit offset: 5 desc: Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. - ALIE: u1, // bit offset: 6 desc: Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. - BEIE: u1, // bit offset: 7 desc: Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. - IDIE: u1, // bit offset: 8 desc: ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. - TIE2: u1, // bit offset: 9 desc: Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - TIE3: u1, // bit offset: 10 desc: Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Bus Timing. Can only be written when RM in CANMOD is 1. - pub const BTR = mmio(Address + 0x00000014, 32, packed struct { - BRP: u10, // bit offset: 0 desc: Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock. - // RESERVED: u4, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SJW: u2, // bit offset: 14 desc: The Synchronization Jump Width is (this value plus one) CAN clocks. - TESG1: u4, // bit offset: 16 desc: The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. - TESG2: u3, // bit offset: 20 desc: The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. - SAM: enum(u1) { // bit offset: 23 desc: Sampling - @"THE_BUS_IS_SAMPLED_O" = 0, // desc: The bus is sampled once (recommended for high speed buses) - @"THE_BUS_IS_SAMPLED_3" = 1, // desc: The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line) - }, - // RESERVED: u8, // bit offset: 24 desc: Reserved. Read value is undefined, only zero should be written. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Error Warning Limit. Can only be written when RM in CANMOD is 1. - pub const EWL = mmio(Address + 0x00000018, 32, packed struct { - EWL: u8, // bit offset: 0 desc: During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Status Register - pub const SR = mmio(Address + 0x0000001c, 32, packed struct { - RBS_1: u1, // bit offset: 0 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_1: u1, // bit offset: 1 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS1_1: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status 1. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS1_1: enum(u1) { // bit offset: 3 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 1 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed. - }, - RS_1: u1, // bit offset: 4 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS1_1: enum(u1) { // bit offset: 5 desc: Transmit Status 1. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 1. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 1. - }, - ES_1: u1, // bit offset: 6 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_1: u1, // bit offset: 7 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_2: u1, // bit offset: 8 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_2: u1, // bit offset: 9 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS2_2: enum(u1) { // bit offset: 10 desc: Transmit Buffer Status 2. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS2_2: enum(u1) { // bit offset: 11 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 2 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed. - }, - RS_2: u1, // bit offset: 12 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS2_2: enum(u1) { // bit offset: 13 desc: Transmit Status 2. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 2. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 2. - }, - ES_2: u1, // bit offset: 14 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_2: u1, // bit offset: 15 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_3: u1, // bit offset: 16 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_3: u1, // bit offset: 17 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS3_3: enum(u1) { // bit offset: 18 desc: Transmit Buffer Status 3. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS3_3: enum(u1) { // bit offset: 19 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 3 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed. - }, - RS_3: u1, // bit offset: 20 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS3_3: enum(u1) { // bit offset: 21 desc: Transmit Status 3. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 3. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 3. - }, - ES_3: u1, // bit offset: 22 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_3: u1, // bit offset: 23 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - // RESERVED: u8, // bit offset: 24 desc: Reserved, the value read from a reserved bit is not defined. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Receive frame status. Can only be written when RM in CANMOD is 1. - pub const RFS = mmio(Address + 0x00000020, 32, packed struct { - IDINDEX: u10, // bit offset: 0 desc: ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values. - BP: u1, // bit offset: 10 desc: If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. - // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - RTR: u1, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. - FF: u1, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. - }); - // byte offset: 36 Received Identifier. Can only be written when RM in CANMOD is 1. - pub const RID = mmio(Address + 0x00000024, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18. - // RESERVED: u21, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Received data bytes 1-4. Can only be written when RM in CANMOD is 1. - pub const RDA = mmio(Address + 0x00000028, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message. - DATA2: u8, // bit offset: 8 desc: Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message. - DATA3: u8, // bit offset: 16 desc: Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message. - DATA4: u8, // bit offset: 24 desc: Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message. - }); - // byte offset: 44 Received data bytes 5-8. Can only be written when RM in CANMOD is 1. - pub const RDB = mmio(Address + 0x0000002c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message. - DATA6: u8, // bit offset: 8 desc: Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message. - DATA7: u8, // bit offset: 16 desc: Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message. - DATA8: u8, // bit offset: 24 desc: Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message. - }); - // byte offset: 48 Transmit frame info (Tx Buffer ) - pub const TFI1 = mmio(Address + 0x00000030, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 52 Transmit Identifier (Tx Buffer) - pub const TID1 = mmio(Address + 0x00000034, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA1 = mmio(Address + 0x00000038, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 60 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB1 = mmio(Address + 0x0000003c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); - // byte offset: 64 Transmit frame info (Tx Buffer ) - pub const TFI2 = mmio(Address + 0x00000040, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 68 Transmit Identifier (Tx Buffer) - pub const TID2 = mmio(Address + 0x00000044, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 72 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA2 = mmio(Address + 0x00000048, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 76 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB2 = mmio(Address + 0x0000004c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); - // byte offset: 80 Transmit frame info (Tx Buffer ) - pub const TFI3 = mmio(Address + 0x00000050, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 84 Transmit Identifier (Tx Buffer) - pub const TID3 = mmio(Address + 0x00000054, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 88 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA3 = mmio(Address + 0x00000058, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 92 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB3 = mmio(Address + 0x0000005c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); -}; -pub const CAN2 = extern struct { - pub const Address: u32 = 0x40048000; - // byte offset: 0 Controls the operating mode of the CAN Controller. - pub const MOD = mmio(Address + 0x00000000, 32, packed struct { - RM: enum(u1) { // bit offset: 0 desc: Reset Mode. - @"NORMAL_THE_CAN_CONTR" = 0, // desc: Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written. - @"RESET_CAN_OPERATION" = 1, // desc: Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted. - }, - LOM: enum(u1) { // bit offset: 1 desc: Listen Only Mode. - @"NORMAL_THE_CAN_CONT" = 0, // desc: Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value. - @"LISTEN_ONLY_THE_CON" = 1, // desc: Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging. - }, - STM: enum(u1) { // bit offset: 2 desc: Self Test Mode. - @"NORMAL_A_TRANSMITTE" = 0, // desc: Normal. A transmitted message must be acknowledged to be considered successful. - @"SELF_TEST_THE_CONTR" = 1, // desc: Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR. - }, - TPM: enum(u1) { // bit offset: 3 desc: Transmit Priority Mode. - @"CAN_ID_THE_TRANSMIT" = 0, // desc: CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier. - @"LOCAL_PRIORITY_THE_" = 1, // desc: Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer. - }, - SM: enum(u1) { // bit offset: 4 desc: Sleep Mode. - @"WAKE_UP_NORMAL_OPER" = 0, // desc: Wake-up. Normal operation. - @"SLEEP_THE_CAN_CONTR" = 1, // desc: Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565. - }, - RPM: enum(u1) { // bit offset: 5 desc: Receive Polarity Mode. - @"LOW_ACTIVE_RD_INPUT" = 0, // desc: Low active. RD input is active Low (dominant bit = 0). - @"HIGH_ACTIVE_RD_INPU" = 1, // desc: High active. RD input is active High (dominant bit = 1) -- reverse polarity. - }, - // RESERVED: u1, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - TM: enum(u1) { // bit offset: 7 desc: Test Mode. - @"DISABLED_NORMAL_OPE" = 0, // desc: Disabled. Normal operation. - @"ENABLED_THE_TD_PIN_" = 1, // desc: Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Command bits that affect the state of the CAN Controller - pub const CMR = mmio(Address + 0x00000004, 32, packed struct { - TR: enum(u1) { // bit offset: 0 desc: Transmission Request. - @"ABSENT_NO_TRANSMISSI" = 0, // desc: Absent.No transmission request. - @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB)) - }, - AT: enum(u1) { // bit offset: 1 desc: Abort Transmission. - @"NO_ACTION_DO_NOT_AB" = 0, // desc: No action. Do not abort the transmission. - @"PRESENT_IF_NOT_ALRE" = 1, // desc: Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled. - }, - RRB: enum(u1) { // bit offset: 2 desc: Release Receive Buffer. - @"NO_ACTION_DO_NOT_RE" = 0, // desc: No action. Do not release the receive buffer. - @"RELEASED_THE_INFORM" = 1, // desc: Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s). - }, - CDO: enum(u1) { // bit offset: 3 desc: Clear Data Overrun. - @"NO_ACTION_DO_NOT_CL" = 0, // desc: No action. Do not clear the data overrun bit. - @"CLEAR_THE_DATA_OVER" = 1, // desc: Clear. The Data Overrun bit in Status Register(s) is cleared. - }, - SRR: enum(u1) { // bit offset: 4 desc: Self Reception Request. - @"ABSENT_NO_SELF_RECE" = 0, // desc: Absent. No self reception request. - @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter. - }, - STB1: enum(u1) { // bit offset: 5 desc: Select Tx Buffer 1. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 1 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 1 is selected for transmission. - }, - STB2: enum(u1) { // bit offset: 6 desc: Select Tx Buffer 2. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 2 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 2 is selected for transmission. - }, - STB3: enum(u1) { // bit offset: 7 desc: Select Tx Buffer 3. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 3 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 3 is selected for transmission. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1. - pub const GSR = mmio(Address + 0x00000008, 32, packed struct { - RBS: enum(u1) { // bit offset: 0 desc: Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. - @"EMPTY_NO_MESSAGE_IS" = 0, // desc: Empty. No message is available. - @"FULL_AT_LEAST_ONE_C" = 1, // desc: Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available. - }, - DOS: enum(u1) { // bit offset: 1 desc: Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. - @"ABSENT_NO_DATA_OVER" = 0, // desc: Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset). - @"OVERRUN_A_MESSAGE_W" = 1, // desc: Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer). - }, - TBS: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status. - @"LOCKED_AT_LEAST_ONE" = 0, // desc: Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s). - @"RELEASED_ALL_THREE_" = 1, // desc: Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS: enum(u1) { // bit offset: 3 desc: Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. - @"INCOMPLETE_AT_LEAST" = 0, // desc: Incomplete. At least one requested transmission has not been successfully completed yet. - @"COMPLETE_ALL_REQUES" = 1, // desc: Complete. All requested transmission(s) has (have) been successfully completed. - }, - RS: enum(u1) { // bit offset: 4 desc: Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. - @"RECEIVE_THE_CAN_CON" = 1, // desc: Receive. The CAN controller is receiving a message. - }, - TS: enum(u1) { // bit offset: 5 desc: Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN controller is sending a message. - }, - ES: enum(u1) { // bit offset: 6 desc: Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). - @"OK_BOTH_ERROR_COUNT" = 0, // desc: OK. Both error counters are below the Error Warning Limit. - @"ERROR_ONE_OR_BOTH_O" = 1, // desc: Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register. - }, - BS: enum(u1) { // bit offset: 7 desc: Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. - @"BUS_ON_THE_CAN_CONT" = 0, // desc: Bus-on. The CAN Controller is involved in bus activities - @"BUS_OFF_THE_CAN_CON" = 1, // desc: Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255. - }, - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RXERR: u8, // bit offset: 16 desc: The current value of the Rx Error Counter (an 8-bit value). - TXERR: u8, // bit offset: 24 desc: The current value of the Tx Error Counter (an 8-bit value). - }); - // byte offset: 12 Interrupt status, Arbitration Lost Capture, Error Code Capture - pub const ICR = mmio(Address + 0x0000000c, 32, packed struct { - RI: enum(u1) { // bit offset: 0 desc: Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI1: enum(u1) { // bit offset: 1 desc: Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - EI: enum(u1) { // bit offset: 2 desc: Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - DOI: enum(u1) { // bit offset: 3 desc: Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - WUI: enum(u1) { // bit offset: 4 desc: Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - EPI: enum(u1) { // bit offset: 5 desc: Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - ALI: enum(u1) { // bit offset: 6 desc: Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - BEI: enum(u1) { // bit offset: 7 desc: Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - IDI: enum(u1) { // bit offset: 8 desc: ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI2: enum(u1) { // bit offset: 9 desc: Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI3: enum(u1) { // bit offset: 10 desc: Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ERRBIT4_0: u5, // bit offset: 16 desc: Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. - ERRDIR: enum(u1) { // bit offset: 21 desc: When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. - @"ERROR_OCCURRED_DURIN" = 0, // desc: Error occurred during transmitting. - @"ERROR_OCCURRED_DURIN" = 1, // desc: Error occurred during receiving. - }, - ERRC1_0: enum(u2) { // bit offset: 22 desc: When the CAN controller detects a bus error, the type of error is captured in this field: - @"BIT_ERROR" = 0, // desc: Bit error - @"FORM_ERROR" = 1, // desc: Form error - @"STUFF_ERROR" = 2, // desc: Stuff error - @"OTHER_ERROR" = 3, // desc: Other error - }, - ALCBIT: u8, // bit offset: 24 desc: Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again. - }); - // byte offset: 16 Interrupt Enable - pub const IER = mmio(Address + 0x00000010, 32, packed struct { - RIE: u1, // bit offset: 0 desc: Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. - TIE1: u1, // bit offset: 1 desc: Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - EIE: u1, // bit offset: 2 desc: Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. - DOIE: u1, // bit offset: 3 desc: Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. - WUIE: u1, // bit offset: 4 desc: Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. - EPIE: u1, // bit offset: 5 desc: Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. - ALIE: u1, // bit offset: 6 desc: Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. - BEIE: u1, // bit offset: 7 desc: Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. - IDIE: u1, // bit offset: 8 desc: ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. - TIE2: u1, // bit offset: 9 desc: Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - TIE3: u1, // bit offset: 10 desc: Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Bus Timing. Can only be written when RM in CANMOD is 1. - pub const BTR = mmio(Address + 0x00000014, 32, packed struct { - BRP: u10, // bit offset: 0 desc: Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock. - // RESERVED: u4, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SJW: u2, // bit offset: 14 desc: The Synchronization Jump Width is (this value plus one) CAN clocks. - TESG1: u4, // bit offset: 16 desc: The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. - TESG2: u3, // bit offset: 20 desc: The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. - SAM: enum(u1) { // bit offset: 23 desc: Sampling - @"THE_BUS_IS_SAMPLED_O" = 0, // desc: The bus is sampled once (recommended for high speed buses) - @"THE_BUS_IS_SAMPLED_3" = 1, // desc: The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line) - }, - // RESERVED: u8, // bit offset: 24 desc: Reserved. Read value is undefined, only zero should be written. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Error Warning Limit. Can only be written when RM in CANMOD is 1. - pub const EWL = mmio(Address + 0x00000018, 32, packed struct { - EWL: u8, // bit offset: 0 desc: During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Status Register - pub const SR = mmio(Address + 0x0000001c, 32, packed struct { - RBS_1: u1, // bit offset: 0 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_1: u1, // bit offset: 1 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS1_1: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status 1. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS1_1: enum(u1) { // bit offset: 3 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 1 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed. - }, - RS_1: u1, // bit offset: 4 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS1_1: enum(u1) { // bit offset: 5 desc: Transmit Status 1. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 1. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 1. - }, - ES_1: u1, // bit offset: 6 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_1: u1, // bit offset: 7 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_2: u1, // bit offset: 8 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_2: u1, // bit offset: 9 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS2_2: enum(u1) { // bit offset: 10 desc: Transmit Buffer Status 2. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS2_2: enum(u1) { // bit offset: 11 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 2 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed. - }, - RS_2: u1, // bit offset: 12 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS2_2: enum(u1) { // bit offset: 13 desc: Transmit Status 2. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 2. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 2. - }, - ES_2: u1, // bit offset: 14 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_2: u1, // bit offset: 15 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_3: u1, // bit offset: 16 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_3: u1, // bit offset: 17 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS3_3: enum(u1) { // bit offset: 18 desc: Transmit Buffer Status 3. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS3_3: enum(u1) { // bit offset: 19 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 3 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed. - }, - RS_3: u1, // bit offset: 20 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS3_3: enum(u1) { // bit offset: 21 desc: Transmit Status 3. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 3. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 3. - }, - ES_3: u1, // bit offset: 22 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_3: u1, // bit offset: 23 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - // RESERVED: u8, // bit offset: 24 desc: Reserved, the value read from a reserved bit is not defined. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Receive frame status. Can only be written when RM in CANMOD is 1. - pub const RFS = mmio(Address + 0x00000020, 32, packed struct { - IDINDEX: u10, // bit offset: 0 desc: ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values. - BP: u1, // bit offset: 10 desc: If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. - // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - RTR: u1, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. - FF: u1, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. - }); - // byte offset: 36 Received Identifier. Can only be written when RM in CANMOD is 1. - pub const RID = mmio(Address + 0x00000024, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18. - // RESERVED: u21, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Received data bytes 1-4. Can only be written when RM in CANMOD is 1. - pub const RDA = mmio(Address + 0x00000028, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message. - DATA2: u8, // bit offset: 8 desc: Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message. - DATA3: u8, // bit offset: 16 desc: Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message. - DATA4: u8, // bit offset: 24 desc: Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message. - }); - // byte offset: 44 Received data bytes 5-8. Can only be written when RM in CANMOD is 1. - pub const RDB = mmio(Address + 0x0000002c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message. - DATA6: u8, // bit offset: 8 desc: Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message. - DATA7: u8, // bit offset: 16 desc: Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message. - DATA8: u8, // bit offset: 24 desc: Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message. - }); - // byte offset: 48 Transmit frame info (Tx Buffer ) - pub const TFI1 = mmio(Address + 0x00000030, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 52 Transmit Identifier (Tx Buffer) - pub const TID1 = mmio(Address + 0x00000034, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA1 = mmio(Address + 0x00000038, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 60 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB1 = mmio(Address + 0x0000003c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); - // byte offset: 64 Transmit frame info (Tx Buffer ) - pub const TFI2 = mmio(Address + 0x00000040, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 68 Transmit Identifier (Tx Buffer) - pub const TID2 = mmio(Address + 0x00000044, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 72 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA2 = mmio(Address + 0x00000048, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 76 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB2 = mmio(Address + 0x0000004c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); - // byte offset: 80 Transmit frame info (Tx Buffer ) - pub const TFI3 = mmio(Address + 0x00000050, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 84 Transmit Identifier (Tx Buffer) - pub const TID3 = mmio(Address + 0x00000054, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 88 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA3 = mmio(Address + 0x00000058, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 92 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB3 = mmio(Address + 0x0000005c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); -}; -pub const I2C1 = extern struct { - pub const Address: u32 = 0x4005c000; - // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AA: u1, // bit offset: 2 desc: Assert acknowledge flag. - SI: u1, // bit offset: 3 desc: I2C interrupt flag. - STO: u1, // bit offset: 4 desc: STOP flag. - STA: u1, // bit offset: 5 desc: START flag. - I2EN: u1, // bit offset: 6 desc: I2C interface enable. - // RESERVED: u25, // bit offset: 7 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. - pub const STAT = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: These bits are unused and are always 0. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. - pub const DAT = mmio(Address + 0x00000008, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. - pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { - SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. - pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { - SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AAC: u1, // bit offset: 2 desc: Assert acknowledge Clear bit. - SIC: u1, // bit offset: 3 desc: I2C interrupt Clear bit. - // RESERVED: u1, // bit offset: 4 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - STAC: u1, // bit offset: 5 desc: START flag Clear bit. - I2ENC: u1, // bit offset: 6 desc: I2C interface Disable bit. - // RESERVED: u1, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Monitor mode control register. - pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { - MM_ENA: enum(u1) { // bit offset: 0 desc: Monitor mode enable. - @"MONITOR_MODE_DISABLE" = 0, // desc: Monitor mode disabled. - @"THE_I_2C_MODULE_WILL" = 1, // desc: The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. - }, - ENA_SCL: enum(u1) { // bit offset: 1 desc: SCL output enable. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] - }, - MATCH_ALL: enum(u1) { // bit offset: 2 desc: Select interrupt register match. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from reserved bits is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. - pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 I2C Slave address mask register - pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 I2C Slave address mask register - pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 I2C Slave address mask register - pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 60 I2C Slave address mask register - pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const SSP0 = extern struct { - pub const Address: u32 = 0x40088000; - // byte offset: 0 Control Register 0. Selects the serial clock rate, bus type, and data size. - pub const CR0 = mmio(Address + 0x00000000, 32, packed struct { - DSS: enum(u4) { // bit offset: 0 desc: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. - @"4_BIT_TRANSFER" = 3, // desc: 4-bit transfer - @"5_BIT_TRANSFER" = 4, // desc: 5-bit transfer - @"6_BIT_TRANSFER" = 5, // desc: 6-bit transfer - @"7_BIT_TRANSFER" = 6, // desc: 7-bit transfer - @"8_BIT_TRANSFER" = 7, // desc: 8-bit transfer - @"9_BIT_TRANSFER" = 8, // desc: 9-bit transfer - @"10_BIT_TRANSFER" = 9, // desc: 10-bit transfer - @"11_BIT_TRANSFER" = 10, // desc: 11-bit transfer - @"12_BIT_TRANSFER" = 11, // desc: 12-bit transfer - @"13_BIT_TRANSFER" = 12, // desc: 13-bit transfer - @"14_BIT_TRANSFER" = 13, // desc: 14-bit transfer - @"15_BIT_TRANSFER" = 14, // desc: 15-bit transfer - @"16_BIT_TRANSFER" = 15, // desc: 16-bit transfer - _, // non-exhaustive - }, - FRF: enum(u2) { // bit offset: 4 desc: Frame Format. - @"SPI" = 0, // desc: SPI - @"TI" = 1, // desc: TI - @"MICROWIRE" = 2, // desc: Microwire - @"THIS_COMBINATION_IS_" = 3, // desc: This combination is not supported and should not be used. - }, - CPOL: enum(u1) { // bit offset: 6 desc: Clock Out Polarity. This bit is only used in SPI mode. - @"BUS_LOW" = 0, // desc: SSP controller maintains the bus clock low between frames. - @"BUS_HIGH" = 1, // desc: SSP controller maintains the bus clock high between frames. - }, - CPHA: enum(u1) { // bit offset: 7 desc: Clock Out Phase. This bit is only used in SPI mode. - @"FIRST_CLOCK" = 0, // desc: SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. - @"SECOND_CLOCK" = 1, // desc: SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. - }, - SCR: u8, // bit offset: 8 desc: Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control Register 1. Selects master/slave and other modes. - pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - LBM: enum(u1) { // bit offset: 0 desc: Loop Back Mode. - @"NORMAL" = 0, // desc: During normal operation. - @"OUPTU" = 1, // desc: Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). - }, - SSE: enum(u1) { // bit offset: 1 desc: SSP Enable. - @"DISABLED" = 0, // desc: The SSP controller is disabled. - @"ENABLED" = 1, // desc: The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. - }, - MS: enum(u1) { // bit offset: 2 desc: Master/Slave Mode.This bit can only be written when the SSE bit is 0. - @"MASTER" = 0, // desc: The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. - @"SLAVE" = 1, // desc: The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. - }, - SOD: u1, // bit offset: 3 desc: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. - pub const DR = mmio(Address + 0x00000008, 32, packed struct { - DATA: u16, // bit offset: 0 desc: Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Status Register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - TFE: u1, // bit offset: 0 desc: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. - TNF: u1, // bit offset: 1 desc: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. - RNE: u1, // bit offset: 2 desc: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. - RFF: u1, // bit offset: 3 desc: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. - BSY: u1, // bit offset: 4 desc: Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Clock Prescale Register - pub const CPSR = mmio(Address + 0x00000010, 32, packed struct { - CPSDVSR: u8, // bit offset: 0 desc: This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Interrupt Mask Set and Clear Register - pub const IMSC = mmio(Address + 0x00000014, 32, packed struct { - RORIM: u1, // bit offset: 0 desc: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTIM: u1, // bit offset: 1 desc: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXIM: u1, // bit offset: 2 desc: Software should set this bit to enable interrupt when the Rx FIFO is at least half full. - TXIM: u1, // bit offset: 3 desc: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Raw Interrupt Status Register - pub const RIS = mmio(Address + 0x00000018, 32, packed struct { - RORRIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTRIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXRIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full. - TXRIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Masked Interrupt Status Register - pub const MIS = mmio(Address + 0x0000001c, 32, packed struct { - RORMIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. - RTMIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXMIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. - TXMIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 SSPICR Interrupt Clear Register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - RORIC: u1, // bit offset: 0 desc: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. - RTIC: u1, // bit offset: 1 desc: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 SSP0 DMA control register - pub const DMACR = mmio(Address + 0x00000024, 32, packed struct { - RXDMAE: u1, // bit offset: 0 desc: Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. - TXDMAE: u1, // bit offset: 1 desc: Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const DAC = extern struct { - pub const Address: u32 = 0x4008c000; - // byte offset: 0 D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit. - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u6, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - VALUE: u10, // bit offset: 6 desc: After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN. - BIAS: enum(u1) { // bit offset: 16 desc: Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet. - @"FAST" = 0, // desc: The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz. - @"SLOW" = 1, // desc: The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz. - }, - // RESERVED: u15, // bit offset: 17 desc: Reserved. Read value is undefined, only zero should be written. - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DAC Control register. This register controls DMA and timer operation. - pub const CTRL = mmio(Address + 0x00000004, 32, packed struct { - INT_DMA_REQ: enum(u1) { // bit offset: 0 desc: DMA interrupt request - @"CLEAR_ON_ANY_WRITE_T" = 0, // desc: Clear on any write to the DACR register. - @"SET_BY_HARDWARE_WHEN" = 1, // desc: Set by hardware when the timer times out. - }, - DBLBUF_ENA: enum(u1) { // bit offset: 1 desc: Double buffering - @"DISABLE" = 0, // desc: Disable - @"ENABLE_WHEN_THIS_BI" = 1, // desc: Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter. - }, - CNT_ENA: enum(u1) { // bit offset: 2 desc: Time-out counter operation - @"DISABLE" = 0, // desc: Disable - @"ENABLE" = 1, // desc: Enable - }, - DMA_ENA: enum(u1) { // bit offset: 3 desc: DMA access - @"DISABLE" = 0, // desc: Disable - @"ENABLE_DMA_BURST_RE" = 1, // desc: Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672). - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer. - pub const CNTVAL = mmio(Address + 0x00000008, 32, packed struct { - VALUE: u16, // bit offset: 0 desc: 16-bit reload value for the DAC interrupt/DMA timer. - // RESERVED: u16, // bit offset: 16 desc: Reserved - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const TIMER2 = extern struct { - pub const Address: u32 = 0x40090000; - // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. - pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. - pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. - pub const TC = mmio(Address + 0x00000008, 32, packed struct { - TC: u32, // bit offset: 0 desc: Timer counter value. - }); - // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. - pub const PR = mmio(Address + 0x0000000c, 32, packed struct { - PM: u32, // bit offset: 0 desc: Prescale counter maximum value. - }); - // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. - pub const PC = mmio(Address + 0x00000010, 32, packed struct { - PC: u32, // bit offset: 0 desc: Prescale counter value. - }); - // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. - pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. - }, - MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. - @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled - }, - MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. - pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event - @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event - @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 60 External Match Register. The EMR controls the external match pins. - pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge - @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. - @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. - @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. - }, - CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn - @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn - _, // non-exhaustive - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const TIMER3 = extern struct { - pub const Address: u32 = 0x40094000; - // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. - pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. - pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. - pub const TC = mmio(Address + 0x00000008, 32, packed struct { - TC: u32, // bit offset: 0 desc: Timer counter value. - }); - // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. - pub const PR = mmio(Address + 0x0000000c, 32, packed struct { - PM: u32, // bit offset: 0 desc: Prescale counter maximum value. - }); - // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. - pub const PC = mmio(Address + 0x00000010, 32, packed struct { - PC: u32, // bit offset: 0 desc: Prescale counter value. - }); - // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. - pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. - }, - MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. - @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled - }, - MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. - pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event - @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event - @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 60 External Match Register. The EMR controls the external match pins. - pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge - @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. - @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. - @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. - }, - CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn - @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn - _, // non-exhaustive - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const UART2 = extern struct { - pub const Address: u32 = 0x40098000; - // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). - pub const RBR = mmio(Address + 0x00000000, 32, packed struct { - RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). - pub const THR = mmio(Address + 0x00000000, 32, packed struct { - THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLL = mmio(Address + 0x00000000, 32, packed struct { - DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLM = mmio(Address + 0x00000004, 32, packed struct { - DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. - @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. - @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. - }, - THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. - @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. - @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. - }, - RXIE: enum(u1) { // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. - @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. - @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTEN: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. - @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. - @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. - }, - ABTOINTEN: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. - @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. - @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. - @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. - @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. - }, - INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). - @"1_RECEIVE_LINE_S" = 3, // desc: 1 - Receive Line Status (RLS). - @"2A__RECEIVE_DATA_AV" = 2, // desc: 2a - Receive Data Available (RDA). - @"2B__CHARACTER_TIME_" = 6, // desc: 2b - Character Time-out Indicator (CTI). - @"3_THRE_INTERRUPT" = 1, // desc: 3 - THRE Interrupt - _, // non-exhaustive - }, - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. - ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. - pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO Enable. - @"UARTN_FIFOS_ARE_DISA" = 0, // desc: UARTn FIFOs are disabled. Must not be used in the application. - @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. - }, - RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. - }, - TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. - }, - DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. - @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). - @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). - @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). - @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. - pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. - @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length - @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length - @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length - @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length - }, - SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select - @"1_STOP_BIT_" = 0, // desc: 1 stop bit. - @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if UnLCR[1:0]=00). - }, - PE: enum(u1) { // bit offset: 3 desc: Parity Enable. - @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. - @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. - }, - PS: enum(u2) { // bit offset: 4 desc: Parity Select - @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. - @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. - @"FORCED_1_STICK_PARIT" = 2, // desc: Forced 1 stick parity. - @"FORCED_0_STICK_PARIT" = 3, // desc: Forced 0 stick parity. - }, - BC: enum(u1) { // bit offset: 6 desc: Break Control - @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. - @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. - }, - DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit - @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. - @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. - pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. - @"EMPTY" = 0, // desc: The UARTn receiver FIFO is empty. - @"NOTEMPTY" = 1, // desc: The UARTn receiver FIFO is not empty. - }, - OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. - @"INACTIVE" = 0, // desc: Overrun error status is inactive. - @"ACTIVE" = 1, // desc: Overrun error status is active. - }, - PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Parity error status is inactive. - @"ACTIVE" = 1, // desc: Parity error status is active. - }, - FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Framing error status is inactive. - @"ACTIVE" = 1, // desc: Framing error status is active. - }, - BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Break interrupt status is inactive. - @"ACTIVE" = 1, // desc: Break interrupt status is active. - }, - THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. - @"VALIDDATA" = 0, // desc: UnTHR contains valid data. - @"EMPTY" = 1, // desc: UnTHR is empty. - }, - TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. - @"VALIDDATA" = 0, // desc: UnTHR and/or the UnTSR contains valid data. - @"EMPTY" = 1, // desc: UnTHR and the UnTSR are empty. - }, - RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. - @"NOERROR" = 0, // desc: UnRBR contains no UARTn RX errors or UnFCR[0]=0. - @"ERRORS" = 1, // desc: UARTn RBR contains at least one UARTn RX error. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { - PAD: u8, // bit offset: 0 desc: A readable, writable byte. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: enum(u1) { // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. - @"AUTO_BAUD_STOP_AUTO" = 0, // desc: Auto-baud stop (auto-baud is not running). - @"AUTO_BAUD_START_AUT" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. - }, - MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. - @"MODE_0_" = 0, // desc: Mode 0. - @"MODE_1_" = 1, // desc: Mode 1. - }, - AUTORESTART: enum(u1) { // bit offset: 2 desc: Restart bit. - @"NO_RESTART_" = 0, // desc: No restart. - @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UARTn Rx falling edge) - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = mmio(Address + 0x00000028, 32, packed struct { - DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. - MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. - pub const TER = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. - pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: enum(u1) { // bit offset: 0 desc: NMM enable. - @"DISABLED" = 0, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. - @"ENABLED" = 1, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation. - }, - RXDIS: enum(u1) { // bit offset: 1 desc: Receiver enable. - @"ENABLED" = 0, // desc: The receiver is enabled. - @"DISABLED" = 1, // desc: The receiver is disabled. - }, - AADEN: enum(u1) { // bit offset: 2 desc: AAD enable. - @"DISABLED" = 0, // desc: Auto Address Detect (AAD) is disabled. - @"ENABLED" = 1, // desc: Auto Address Detect (AAD) is enabled. - }, - // RESERVED: u1, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. - @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. - @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. - }, - OINV: enum(u1) { // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. - @"DIRLOW" = 0, // desc: The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. - @"DIRHIGH" = 1, // desc: The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. - pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { - ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 84 RS-485/EIA-485 direction control delay. - pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { - DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const UART3 = extern struct { - pub const Address: u32 = 0x4009c000; - // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). - pub const RBR = mmio(Address + 0x00000000, 32, packed struct { - RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). - pub const THR = mmio(Address + 0x00000000, 32, packed struct { - THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLL = mmio(Address + 0x00000000, 32, packed struct { - DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLM = mmio(Address + 0x00000004, 32, packed struct { - DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. - @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. - @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. - }, - THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. - @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. - @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. - }, - RXIE: enum(u1) { // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. - @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. - @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTEN: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. - @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. - @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. - }, - ABTOINTEN: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. - @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. - @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. - @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. - @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. - }, - INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). - @"1_RECEIVE_LINE_S" = 3, // desc: 1 - Receive Line Status (RLS). - @"2A__RECEIVE_DATA_AV" = 2, // desc: 2a - Receive Data Available (RDA). - @"2B__CHARACTER_TIME_" = 6, // desc: 2b - Character Time-out Indicator (CTI). - @"3_THRE_INTERRUPT" = 1, // desc: 3 - THRE Interrupt - _, // non-exhaustive - }, - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. - ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. - pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO Enable. - @"UARTN_FIFOS_ARE_DISA" = 0, // desc: UARTn FIFOs are disabled. Must not be used in the application. - @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. - }, - RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. - }, - TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. - }, - DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. - @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). - @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). - @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). - @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. - pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. - @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length - @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length - @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length - @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length - }, - SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select - @"1_STOP_BIT_" = 0, // desc: 1 stop bit. - @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if UnLCR[1:0]=00). - }, - PE: enum(u1) { // bit offset: 3 desc: Parity Enable. - @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. - @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. - }, - PS: enum(u2) { // bit offset: 4 desc: Parity Select - @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. - @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. - @"FORCED_1_STICK_PARIT" = 2, // desc: Forced 1 stick parity. - @"FORCED_0_STICK_PARIT" = 3, // desc: Forced 0 stick parity. - }, - BC: enum(u1) { // bit offset: 6 desc: Break Control - @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. - @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. - }, - DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit - @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. - @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. - pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. - @"EMPTY" = 0, // desc: The UARTn receiver FIFO is empty. - @"NOTEMPTY" = 1, // desc: The UARTn receiver FIFO is not empty. - }, - OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. - @"INACTIVE" = 0, // desc: Overrun error status is inactive. - @"ACTIVE" = 1, // desc: Overrun error status is active. - }, - PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Parity error status is inactive. - @"ACTIVE" = 1, // desc: Parity error status is active. - }, - FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Framing error status is inactive. - @"ACTIVE" = 1, // desc: Framing error status is active. - }, - BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Break interrupt status is inactive. - @"ACTIVE" = 1, // desc: Break interrupt status is active. - }, - THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. - @"VALIDDATA" = 0, // desc: UnTHR contains valid data. - @"EMPTY" = 1, // desc: UnTHR is empty. - }, - TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. - @"VALIDDATA" = 0, // desc: UnTHR and/or the UnTSR contains valid data. - @"EMPTY" = 1, // desc: UnTHR and the UnTSR are empty. - }, - RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. - @"NOERROR" = 0, // desc: UnRBR contains no UARTn RX errors or UnFCR[0]=0. - @"ERRORS" = 1, // desc: UARTn RBR contains at least one UARTn RX error. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { - PAD: u8, // bit offset: 0 desc: A readable, writable byte. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: enum(u1) { // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. - @"AUTO_BAUD_STOP_AUTO" = 0, // desc: Auto-baud stop (auto-baud is not running). - @"AUTO_BAUD_START_AUT" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. - }, - MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. - @"MODE_0_" = 0, // desc: Mode 0. - @"MODE_1_" = 1, // desc: Mode 1. - }, - AUTORESTART: enum(u1) { // bit offset: 2 desc: Restart bit. - @"NO_RESTART_" = 0, // desc: No restart. - @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UARTn Rx falling edge) - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = mmio(Address + 0x00000028, 32, packed struct { - DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. - MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. - pub const TER = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. - pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: enum(u1) { // bit offset: 0 desc: NMM enable. - @"DISABLED" = 0, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. - @"ENABLED" = 1, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation. - }, - RXDIS: enum(u1) { // bit offset: 1 desc: Receiver enable. - @"ENABLED" = 0, // desc: The receiver is enabled. - @"DISABLED" = 1, // desc: The receiver is disabled. - }, - AADEN: enum(u1) { // bit offset: 2 desc: AAD enable. - @"DISABLED" = 0, // desc: Auto Address Detect (AAD) is disabled. - @"ENABLED" = 1, // desc: Auto Address Detect (AAD) is enabled. - }, - // RESERVED: u1, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. - @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. - @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. - }, - OINV: enum(u1) { // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. - @"DIRLOW" = 0, // desc: The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. - @"DIRHIGH" = 1, // desc: The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. - pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { - ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 84 RS-485/EIA-485 direction control delay. - pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { - DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const I2C2 = extern struct { - pub const Address: u32 = 0x400a0000; - // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AA: u1, // bit offset: 2 desc: Assert acknowledge flag. - SI: u1, // bit offset: 3 desc: I2C interrupt flag. - STO: u1, // bit offset: 4 desc: STOP flag. - STA: u1, // bit offset: 5 desc: START flag. - I2EN: u1, // bit offset: 6 desc: I2C interface enable. - // RESERVED: u25, // bit offset: 7 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. - pub const STAT = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: These bits are unused and are always 0. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. - pub const DAT = mmio(Address + 0x00000008, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. - pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { - SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. - pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { - SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AAC: u1, // bit offset: 2 desc: Assert acknowledge Clear bit. - SIC: u1, // bit offset: 3 desc: I2C interrupt Clear bit. - // RESERVED: u1, // bit offset: 4 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - STAC: u1, // bit offset: 5 desc: START flag Clear bit. - I2ENC: u1, // bit offset: 6 desc: I2C interface Disable bit. - // RESERVED: u1, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Monitor mode control register. - pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { - MM_ENA: enum(u1) { // bit offset: 0 desc: Monitor mode enable. - @"MONITOR_MODE_DISABLE" = 0, // desc: Monitor mode disabled. - @"THE_I_2C_MODULE_WILL" = 1, // desc: The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. - }, - ENA_SCL: enum(u1) { // bit offset: 1 desc: SCL output enable. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] - }, - MATCH_ALL: enum(u1) { // bit offset: 2 desc: Select interrupt register match. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from reserved bits is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. - pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 I2C Slave address mask register - pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 I2C Slave address mask register - pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 I2C Slave address mask register - pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 60 I2C Slave address mask register - pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const I2S = extern struct { - pub const Address: u32 = 0x400a8000; - // byte offset: 0 I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. - pub const DAO = mmio(Address + 0x00000000, 32, packed struct { - WORDWIDTH: enum(u2) { // bit offset: 0 desc: Selects the number of bytes in data as follows: - @"8_BIT_DATA" = 0, // desc: 8-bit data - @"16_BIT_DATA" = 1, // desc: 16-bit data - @"32_BIT_DATA" = 3, // desc: 32-bit data - _, // non-exhaustive - }, - MONO: u1, // bit offset: 2 desc: When 1, data is of monaural format. When 0, the data is in stereo format. - STOP: u1, // bit offset: 3 desc: When 1, disables accesses on FIFOs, places the transmit channel in mute mode. - RESET: u1, // bit offset: 4 desc: When 1, asynchronously resets the transmit channel and FIFO. - WS_SEL: u1, // bit offset: 5 desc: When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE. - WS_HALFPERIOD: u9, // bit offset: 6 desc: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. - MUTE: u1, // bit offset: 15 desc: When 1, the transmit channel sends only zeroes. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. - pub const DAI = mmio(Address + 0x00000004, 32, packed struct { - WORDWIDTH: enum(u2) { // bit offset: 0 desc: Selects the number of bytes in data as follows: - @"8_BIT_DATA" = 0, // desc: 8-bit data - @"16_BIT_DATA" = 1, // desc: 16-bit data - @"32_BIT_DATA" = 3, // desc: 32-bit data - _, // non-exhaustive - }, - MONO: u1, // bit offset: 2 desc: When 1, data is of monaural format. When 0, the data is in stereo format. - STOP: u1, // bit offset: 3 desc: When 1, disables accesses on FIFOs, places the transmit channel in mute mode. - RESET: u1, // bit offset: 4 desc: When 1, asynchronously reset the transmit channel and FIFO. - WS_SEL: u1, // bit offset: 5 desc: When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE. - WS_HALFPERIOD: u9, // bit offset: 6 desc: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. - // RESERVED: u17, // bit offset: 15 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. - pub const TXFIFO = mmio(Address + 0x00000008, 32, packed struct { - I2STXFIFO: u32, // bit offset: 0 desc: 8 x 32-bit transmit FIFO. - }); - // byte offset: 12 I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. - pub const RXFIFO = mmio(Address + 0x0000000c, 32, packed struct { - I2SRXFIFO: u32, // bit offset: 0 desc: 8 x 32-bit transmit FIFO. - }); - // byte offset: 16 I2S Status Feedback Register. Contains status information about the I2S interface. - pub const STATE = mmio(Address + 0x00000010, 32, packed struct { - IRQ: u1, // bit offset: 0 desc: This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register. - DMAREQ1: u1, // bit offset: 1 desc: This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register. - DMAREQ2: u1, // bit offset: 2 desc: This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register. - // RESERVED: u5, // bit offset: 3 desc: Reserved. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RX_LEVEL: u4, // bit offset: 8 desc: Reflects the current level of the Receive FIFO. - // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - TX_LEVEL: u4, // bit offset: 16 desc: Reflects the current level of the Transmit FIFO. - // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 I2S DMA Configuration Register 1. Contains control information for DMA request 1. - pub const DMA1 = mmio(Address + 0x00000014, 32, packed struct { - RX_DMA1_ENABLE: u1, // bit offset: 0 desc: When 1, enables DMA1 for I2S receive. - TX_DMA1_ENABLE: u1, // bit offset: 1 desc: When 1, enables DMA1 for I2S transmit. - // RESERVED: u6, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RX_DEPTH_DMA1: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA1. - // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - TX_DEPTH_DMA1: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA1. - // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 I2S DMA Configuration Register 2. Contains control information for DMA request 2. - pub const DMA2 = mmio(Address + 0x00000018, 32, packed struct { - RX_DMA2_ENABLE: u1, // bit offset: 0 desc: When 1, enables DMA1 for I2S receive. - TX_DMA2_ENABLE: u1, // bit offset: 1 desc: When 1, enables DMA1 for I2S transmit. - // RESERVED: u6, // bit offset: 2 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RX_DEPTH_DMA2: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA2. - // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - TX_DEPTH_DMA2: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA2. - // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. - pub const IRQ = mmio(Address + 0x0000001c, 32, packed struct { - RX_IRQ_ENABLE: u1, // bit offset: 0 desc: When 1, enables I2S receive interrupt. - TX_IRQ_ENABLE: u1, // bit offset: 1 desc: When 1, enables I2S transmit interrupt. - // RESERVED: u6, // bit offset: 2 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RX_DEPTH_IRQ: u4, // bit offset: 8 desc: Set the FIFO level on which to create an irq request. - // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - TX_DEPTH_IRQ: u4, // bit offset: 16 desc: Set the FIFO level on which to create an irq request. - // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. - pub const TXRATE = mmio(Address + 0x00000020, 32, packed struct { - Y_DIVIDER: u8, // bit offset: 0 desc: I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. - X_DIVIDER: u8, // bit offset: 8 desc: I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. - pub const RXRATE = mmio(Address + 0x00000024, 32, packed struct { - Y_DIVIDER: u8, // bit offset: 0 desc: I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. - X_DIVIDER: u8, // bit offset: 8 desc: I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. - pub const TXBITRATE = mmio(Address + 0x00000028, 32, packed struct { - TX_BITRATE: u6, // bit offset: 0 desc: I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock. - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. - pub const RXBITRATE = mmio(Address + 0x0000002c, 32, packed struct { - RX_BITRATE: u6, // bit offset: 0 desc: I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock. - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 I2S Transmit mode control. - pub const TXMODE = mmio(Address + 0x00000030, 32, packed struct { - TXCLKSEL: enum(u2) { // bit offset: 0 desc: Clock source selection for the transmit bit clock divider. - @"SELECT_THE_TX_FRACTI" = 0, // desc: Select the TX fractional rate divider clock output as the source - @"SELECT_THE_RX_MCLK_S" = 2, // desc: Select the RX_MCLK signal as the TX_MCLK clock source - _, // non-exhaustive - }, - TX4PIN: u1, // bit offset: 2 desc: Transmit 4-pin mode selection. When 1, enables 4-pin mode. - TXMCENA: u1, // bit offset: 3 desc: Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 I2S Receive mode control. - pub const RXMODE = mmio(Address + 0x00000034, 32, packed struct { - RXCLKSEL: enum(u2) { // bit offset: 0 desc: Clock source selection for the receive bit clock divider. - @"SELECT_THE_RX_FRACTI" = 0, // desc: Select the RX fractional rate divider clock output as the source - @"SELECT_THE_TX_MCLK_S" = 2, // desc: Select the TX_MCLK signal as the RX_MCLK clock source - _, // non-exhaustive - }, - RX4PIN: u1, // bit offset: 2 desc: Receive 4-pin mode selection. When 1, enables 4-pin mode. - RXMCENA: u1, // bit offset: 3 desc: Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const RITIMER = extern struct { - pub const Address: u32 = 0x400b0000; - // byte offset: 0 Compare register - pub const COMPVAL = mmio(Address + 0x00000000, 32, packed struct { - RICOMP: u32, // bit offset: 0 desc: Compare register. Holds the compare value which is compared to the counter. - }); - // byte offset: 4 Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. - pub const MASK = mmio(Address + 0x00000004, 32, packed struct { - RIMASK: u32, // bit offset: 0 desc: Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true). - }); - // byte offset: 8 Control register. - pub const CTRL = mmio(Address + 0x00000008, 32, packed struct { - RITINT: enum(u1) { // bit offset: 0 desc: Interrupt flag - @"THIS_BIT_IS_SET_TO_1" = 1, // desc: This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect. - @"THE_COUNTER_VALUE_DO" = 0, // desc: The counter value does not equal the masked compare value. - }, - RITENCLR: enum(u1) { // bit offset: 1 desc: Timer enable clear - @"THE_TIMER_WILL_BE_CL" = 1, // desc: The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag. - @"THE_TIMER_WILL_NOT_B" = 0, // desc: The timer will not be cleared to 0. - }, - RITENBR: enum(u1) { // bit offset: 2 desc: Timer enable for debug - @"THE_TIMER_IS_HALTED_" = 1, // desc: The timer is halted when the processor is halted for debugging. - @"DEBUG_HAS_NO_EFFECT_" = 0, // desc: Debug has no effect on the timer operation. - }, - RITEN: enum(u1) { // bit offset: 3 desc: Timer enable. - @"TIMER_ENABLED_THIS_" = 1, // desc: Timer enabled. This can be overruled by a debug halt if enabled in bit 2. - @"TIMER_DISABLED_" = 0, // desc: Timer disabled. - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 32-bit counter - pub const COUNTER = mmio(Address + 0x0000000c, 32, packed struct { - RICOUNTER: u32, // bit offset: 0 desc: 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software. - }); -}; -pub const MCPWM = extern struct { - pub const Address: u32 = 0x400b8000; - // byte offset: 0 PWM Control read address - pub const CON = mmio(Address + 0x00000000, 32, packed struct { - RUN0: enum(u1) { // bit offset: 0 desc: Stops/starts timer channel 0. - @"STOP_" = 0, // desc: Stop. - @"RUN_" = 1, // desc: Run. - }, - CENTER0: enum(u1) { // bit offset: 1 desc: Edge/center aligned operation for channel 0. - @"EDGE_ALIGNED_" = 0, // desc: Edge-aligned. - @"CENTER_ALIGNED_" = 1, // desc: Center-aligned. - }, - POLA0: enum(u1) { // bit offset: 2 desc: Selects polarity of the MCOA0 and MCOB0 pins. - @"PASSIVE_STATE_IS_LOW" = 0, // desc: Passive state is LOW, active state is HIGH. - @"PASSIVE_STATE_IS_HIG" = 1, // desc: Passive state is HIGH, active state is LOW. - }, - DTE0: enum(u1) { // bit offset: 3 desc: Controls the dead-time feature for channel 0. - @"DEAD_TIME_DISABLED_" = 0, // desc: Dead-time disabled. - @"DEAD_TIME_ENABLED_" = 1, // desc: Dead-time enabled. - }, - DISUP0: enum(u1) { // bit offset: 4 desc: Enable/disable updates of functional registers for channel 0 (see Section 24.8.2). - @"UPDATE" = 0, // desc: Functional registers are updated from the write registers at the end of each PWM cycle. - @"NOUPDATE" = 1, // desc: Functional registers remain the same as long as the timer is running. - }, - // RESERVED: u3, // bit offset: 5 desc: Reserved. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RUN1: enum(u1) { // bit offset: 8 desc: Stops/starts timer channel 1. - @"STOP_" = 0, // desc: Stop. - @"RUN_" = 1, // desc: Run. - }, - CENTER1: enum(u1) { // bit offset: 9 desc: Edge/center aligned operation for channel 1. - @"EDGE_ALIGNED_" = 0, // desc: Edge-aligned. - @"CENTER_ALIGNED_" = 1, // desc: Center-aligned. - }, - POLA1: enum(u1) { // bit offset: 10 desc: Selects polarity of the MCOA1 and MCOB1 pins. - @"PASSIVE_STATE_IS_LOW" = 0, // desc: Passive state is LOW, active state is HIGH. - @"PASSIVE_STATE_IS_HIG" = 1, // desc: Passive state is HIGH, active state is LOW. - }, - DTE1: enum(u1) { // bit offset: 11 desc: Controls the dead-time feature for channel 1. - @"DEAD_TIME_DISABLED_" = 0, // desc: Dead-time disabled. - @"DEAD_TIME_ENABLED_" = 1, // desc: Dead-time enabled. - }, - DISUP1: enum(u1) { // bit offset: 12 desc: Enable/disable updates of functional registers for channel 1 (see Section 24.8.2). - @"UPDATE" = 0, // desc: Functional registers are updated from the write registers at the end of each PWM cycle. - @"NOUPDATE" = 1, // desc: Functional registers remain the same as long as the timer is running. - }, - // RESERVED: u3, // bit offset: 13 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - RUN2: enum(u1) { // bit offset: 16 desc: Stops/starts timer channel 2. - @"STOP_" = 0, // desc: Stop. - @"RUN_" = 1, // desc: Run. - }, - CENTER2: enum(u1) { // bit offset: 17 desc: Edge/center aligned operation for channel 2. - @"EDGE_ALIGNED_" = 0, // desc: Edge-aligned. - @"CENTER_ALIGNED_" = 1, // desc: Center-aligned. - }, - POLA2: enum(u1) { // bit offset: 18 desc: Selects polarity of the MCOA2 and MCOB2 pins. - @"PASSIVE_STATE_IS_LOW" = 0, // desc: Passive state is LOW, active state is HIGH. - @"PASSIVE_STATE_IS_HIG" = 1, // desc: Passive state is HIGH, active state is LOW. - }, - DTE2: enum(u1) { // bit offset: 19 desc: Controls the dead-time feature for channel 1. - @"DEAD_TIME_DISABLED_" = 0, // desc: Dead-time disabled. - @"DEAD_TIME_ENABLED_" = 1, // desc: Dead-time enabled. - }, - DISUP2: enum(u1) { // bit offset: 20 desc: Enable/disable updates of functional registers for channel 2 (see Section 24.8.2). - @"UPDATE" = 0, // desc: Functional registers are updated from the write registers at the end of each PWM cycle. - @"NOUPDATE" = 1, // desc: Functional registers remain the same as long as the timer is running. - }, - // RESERVED: u8, // bit offset: 21 desc: Reserved. - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - INVBDC: enum(u1) { // bit offset: 29 desc: Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode. - @"OPPOSITE" = 0, // desc: The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time). - @"SAME" = 1, // desc: The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6) - }, - ACMODE: enum(u1) { // bit offset: 30 desc: 3-phase AC mode select (see Section 24.8.7). - @"3_PHASE_AC_MODE_OFF" = 0, // desc: 3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register. - @"3_PHASE_AC_MODE_ON_" = 1, // desc: 3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0. - }, - DCMODE: enum(u1) { // bit offset: 31 desc: 3-phase DC mode select (see Section 24.8.6). - @"3_PHASE_DC_MODE_OFF" = 0, // desc: 3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1) - @"3_PHASE_DC_MODE_ON_" = 1, // desc: 3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs. - }, - }); - // byte offset: 4 PWM Control set address - pub const CON_SET = mmio(Address + 0x00000004, 32, packed struct { - RUN0_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in the CON register. - CENTER0_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in the CON register. - POLA0_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in the CON register. - DTE0_SET: u1, // bit offset: 3 desc: Writing a one sets the corresponding bit in the CON register. - DISUP0_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in the CON register. - // RESERVED: u3, // bit offset: 5 desc: Writing a one sets the corresponding bit in the CON register. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RUN1_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bit in the CON register. - CENTER1_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in the CON register. - POLA1_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in the CON register. - DTE1_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bit in the CON register. - DISUP1_SET: u1, // bit offset: 12 desc: Writing a one sets the corresponding bit in the CON register. - // RESERVED: u3, // bit offset: 13 desc: Writing a one sets the corresponding bit in the CON register. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - RUN2_SET: u1, // bit offset: 16 desc: Writing a one sets the corresponding bit in the CON register. - CENTER2_SET: u1, // bit offset: 17 desc: Writing a one sets the corresponding bit in the CON register. - POLA2_SET: u1, // bit offset: 18 desc: Writing a one sets the corresponding bit in the CON register. - DTE2_SET: u1, // bit offset: 19 desc: Writing a one sets the corresponding bit in the CON register. - DISUP2_SET: u1, // bit offset: 20 desc: Writing a one sets the corresponding bit in the CON register. - // RESERVED: u8, // bit offset: 21 desc: Writing a one sets the corresponding bit in the CON register. - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - INVBDC_SET: u1, // bit offset: 29 desc: Writing a one sets the corresponding bit in the CON register. - ACMODE_SET: u1, // bit offset: 30 desc: Writing a one sets the corresponding bit in the CON register. - DCMODE_SET: u1, // bit offset: 31 desc: Writing a one sets the corresponding bit in the CON register. - }); - // byte offset: 8 PWM Control clear address - pub const CON_CLR = mmio(Address + 0x00000008, 32, packed struct { - RUN0_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in the CON register. - CENTER0_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in the CON register. - POLA0_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in the CON register. - DTE0_CLR: u1, // bit offset: 3 desc: Writing a one clears the corresponding bit in the CON register. - DISUP0_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in the CON register. - // RESERVED: u3, // bit offset: 5 desc: Writing a one clears the corresponding bit in the CON register. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RUN1_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in the CON register. - CENTER1_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in the CON register. - POLA1_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in the CON register. - DTE1_CLR: u1, // bit offset: 11 desc: Writing a one clears the corresponding bit in the CON register. - DISUP1_CLR: u1, // bit offset: 12 desc: Writing a one clears the corresponding bit in the CON register. - // RESERVED: u3, // bit offset: 13 desc: Writing a one clears the corresponding bit in the CON register. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - RUN2_CLR: u1, // bit offset: 16 desc: Writing a one clears the corresponding bit in the CON register. - CENTER2_CLR: u1, // bit offset: 17 desc: Writing a one clears the corresponding bit in the CON register. - POLA2_CLR: u1, // bit offset: 18 desc: Writing a one clears the corresponding bit in the CON register. - DTE2_CLR: u1, // bit offset: 19 desc: Writing a one clears the corresponding bit in the CON register. - DISUP2_CLR: u1, // bit offset: 20 desc: Writing a one clears the corresponding bit in the CON register. - // RESERVED: u8, // bit offset: 21 desc: Writing a one clears the corresponding bit in the CON register. - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - INVBDC_CLR: u1, // bit offset: 29 desc: Writing a one clears the corresponding bit in the CON register. - ACMOD_CLR: u1, // bit offset: 30 desc: Writing a one clears the corresponding bit in the CON register. - DCMODE_CLR: u1, // bit offset: 31 desc: Writing a one clears the corresponding bit in the CON register. - }); - // byte offset: 12 Capture Control read address - pub const CAPCON = mmio(Address + 0x0000000c, 32, packed struct { - CAP0MCI0_RE: u1, // bit offset: 0 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. - CAP0MCI0_FE: u1, // bit offset: 1 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. - CAP0MCI1_RE: u1, // bit offset: 2 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. - CAP0MCI1_FE: u1, // bit offset: 3 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. - CAP0MCI2_RE: u1, // bit offset: 4 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. - CAP0MCI2_FE: u1, // bit offset: 5 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. - CAP1MCI0_RE: u1, // bit offset: 6 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. - CAP1MCI0_FE: u1, // bit offset: 7 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. - CAP1MCI1_RE: u1, // bit offset: 8 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. - CAP1MCI1_FE: u1, // bit offset: 9 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. - CAP1MCI2_RE: u1, // bit offset: 10 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. - CAP1MCI2_FE: u1, // bit offset: 11 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. - CAP2MCI0_RE: u1, // bit offset: 12 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. - CAP2MCI0_FE: u1, // bit offset: 13 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. - CAP2MCI1_RE: u1, // bit offset: 14 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. - CAP2MCI1_FE: u1, // bit offset: 15 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. - CAP2MCI2_RE: u1, // bit offset: 16 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. - CAP2MCI2_FE: u1, // bit offset: 17 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. - RT0: u1, // bit offset: 18 desc: If this bit is 1, TC0 is reset by a channel 0 capture event. - RT1: u1, // bit offset: 19 desc: If this bit is 1, TC1 is reset by a channel 1 capture event. - RT2: u1, // bit offset: 20 desc: If this bit is 1, TC2 is reset by a channel 2 capture event. - // RESERVED: u11, // bit offset: 21 desc: Reserved. - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Capture Control set address - pub const CAPCON_SET = mmio(Address + 0x00000010, 32, packed struct { - CAP0MCI0_RE_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI0_FE_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI1_RE_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI1_FE_SET: u1, // bit offset: 3 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI2_RE_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI2_FE_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI0_RE_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI0_FE_SET: u1, // bit offset: 7 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI1_RE_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI1_FE_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI2_RE_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI2_FE_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI0_RE_SET: u1, // bit offset: 12 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI0_FE_SET: u1, // bit offset: 13 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI1_RE_SET: u1, // bit offset: 14 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI1_FE_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI2_RE_SET: u1, // bit offset: 16 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI2_FE_SET: u1, // bit offset: 17 desc: Writing a one sets the corresponding bits in the CAPCON register. - RT0_SET: u1, // bit offset: 18 desc: Writing a one sets the corresponding bits in the CAPCON register. - RT1_SET: u1, // bit offset: 19 desc: Writing a one sets the corresponding bits in the CAPCON register. - RT2_SET: u1, // bit offset: 20 desc: Writing a one sets the corresponding bits in the CAPCON register. - // RESERVED: u11, // bit offset: 21 desc: Reserved. - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Event Control clear address - pub const CAPCON_CLR = mmio(Address + 0x00000014, 32, packed struct { - CAP0MCI0_RE_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI0_FE_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI1_RE_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI1_FE_CLR: u1, // bit offset: 3 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI2_RE_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI2_FE_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI0_RE_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI0_FE_CLR: u1, // bit offset: 7 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI1_RE_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI1_FE_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI2_RE_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI2_FE_CLR: u1, // bit offset: 11 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI0_RE_CLR: u1, // bit offset: 12 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI0_FE_CLR: u1, // bit offset: 13 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI1_RE_CLR: u1, // bit offset: 14 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI1_FE_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI2_RE_CLR: u1, // bit offset: 16 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI2_FE_CLR: u1, // bit offset: 17 desc: Writing a one clears the corresponding bits in the CAPCON register. - RT0_CLR: u1, // bit offset: 18 desc: Writing a one clears the corresponding bits in the CAPCON register. - RT1_CLR: u1, // bit offset: 19 desc: Writing a one clears the corresponding bits in the CAPCON register. - RT2_CLR: u1, // bit offset: 20 desc: Writing a one clears the corresponding bits in the CAPCON register. - // RESERVED: u11, // bit offset: 21 desc: Reserved. - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Timer Counter register - pub const TC_0 = mmio(Address + 0x00000018, 32, packed struct { - MCTC: u32, // bit offset: 0 desc: Timer/Counter value. - }); - // byte offset: 28 Timer Counter register - pub const TC_1 = mmio(Address + 0x0000001c, 32, packed struct { - MCTC: u32, // bit offset: 0 desc: Timer/Counter value. - }); - // byte offset: 32 Timer Counter register - pub const TC_2 = mmio(Address + 0x00000020, 32, packed struct { - MCTC: u32, // bit offset: 0 desc: Timer/Counter value. - }); - // byte offset: 36 Limit register - pub const LIM_0 = mmio(Address + 0x00000024, 32, packed struct { - MCLIM: u32, // bit offset: 0 desc: Limit value. - }); - // byte offset: 40 Limit register - pub const LIM_1 = mmio(Address + 0x00000028, 32, packed struct { - MCLIM: u32, // bit offset: 0 desc: Limit value. - }); - // byte offset: 44 Limit register - pub const LIM_2 = mmio(Address + 0x0000002c, 32, packed struct { - MCLIM: u32, // bit offset: 0 desc: Limit value. - }); - // byte offset: 48 Match register - pub const MAT_0 = mmio(Address + 0x00000030, 32, packed struct { - MCMAT: u32, // bit offset: 0 desc: Match value. - }); - // byte offset: 52 Match register - pub const MAT_1 = mmio(Address + 0x00000034, 32, packed struct { - MCMAT: u32, // bit offset: 0 desc: Match value. - }); - // byte offset: 56 Match register - pub const MAT_2 = mmio(Address + 0x00000038, 32, packed struct { - MCMAT: u32, // bit offset: 0 desc: Match value. - }); - // byte offset: 60 Dead time register - pub const DT = mmio(Address + 0x0000003c, 32, packed struct { - DT0: u10, // bit offset: 0 desc: Dead time for channel 0.[1] - DT1: u10, // bit offset: 10 desc: Dead time for channel 1.[2] - DT2: u10, // bit offset: 20 desc: Dead time for channel 2.[2] - // RESERVED: u2, // bit offset: 30 desc: reserved - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 64 Communication Pattern register - pub const CP = mmio(Address + 0x00000040, 32, packed struct { - CCPA0: enum(u1) { // bit offset: 0 desc: Communication pattern output A, channel 0. - @"MCOA0_PASSIVE_" = 0, // desc: MCOA0 passive. - @"INTERNAL_MCOA0_" = 1, // desc: internal MCOA0. - }, - CCPB0: enum(u1) { // bit offset: 1 desc: Communication pattern output B, channel 0. - @"MCOB0_PASSIVE_" = 0, // desc: MCOB0 passive. - @"MCOB0_TRACKS_INTERNA" = 1, // desc: MCOB0 tracks internal MCOA0. - }, - CCPA1: enum(u1) { // bit offset: 2 desc: Communication pattern output A, channel 1. - @"MCOA1_PASSIVE_" = 0, // desc: MCOA1 passive. - @"MCOA1_TRACKS_INTERNA" = 1, // desc: MCOA1 tracks internal MCOA0. - }, - CCPB1: enum(u1) { // bit offset: 3 desc: Communication pattern output B, channel 1. - @"MCOB1_PASSIVE_" = 0, // desc: MCOB1 passive. - @"MCOB1_TRACKS_INTERNA" = 1, // desc: MCOB1 tracks internal MCOA0. - }, - CCPA2: enum(u1) { // bit offset: 4 desc: Communication pattern output A, channel 2. - @"MCOA2_PASSIVE_" = 0, // desc: MCOA2 passive. - @"MCOA2_TRACKS_INTERNA" = 1, // desc: MCOA2 tracks internal MCOA0. - }, - CCPB2: enum(u1) { // bit offset: 5 desc: Communication pattern output B, channel 2. - @"MCOB2_PASSIVE_" = 0, // desc: MCOB2 passive. - @"MCOB2_TRACKS_INTERNA" = 1, // desc: MCOB2 tracks internal MCOA0. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 68 Capture register - pub const CAP_0 = mmio(Address + 0x00000044, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Current TC value at a capture event. - }); - // byte offset: 72 Capture register - pub const CAP_1 = mmio(Address + 0x00000048, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Current TC value at a capture event. - }); - // byte offset: 76 Capture register - pub const CAP_2 = mmio(Address + 0x0000004c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Current TC value at a capture event. - }); - // byte offset: 80 Interrupt Enable read address - pub const INTEN = mmio(Address + 0x00000050, 32, packed struct { - ILIM0: enum(u1) { // bit offset: 0 desc: Limit interrupt for channel 0. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - IMAT0: enum(u1) { // bit offset: 1 desc: Match interrupt for channel 0. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - ICAP0: enum(u1) { // bit offset: 2 desc: Capture interrupt for channel 0. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1: enum(u1) { // bit offset: 4 desc: Limit interrupt for channel 1. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - IMAT1: enum(u1) { // bit offset: 5 desc: Match interrupt for channel 1. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - ICAP1: enum(u1) { // bit offset: 6 desc: Capture interrupt for channel 1. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved2: u1 = 0, - ILIM2: enum(u1) { // bit offset: 8 desc: Limit interrupt for channel 2. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - IMAT2: enum(u1) { // bit offset: 9 desc: Match interrupt for channel 2. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - ICAP2: enum(u1) { // bit offset: 10 desc: Capture interrupt for channel 2. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - // RESERVED: u4, // bit offset: 11 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - ABORT: enum(u1) { // bit offset: 15 desc: Fast abort interrupt. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 84 Interrupt Enable set address - pub const INTEN_SET = mmio(Address + 0x00000054, 32, packed struct { - ILIM0_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT0_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP0_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT1_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP1_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved3: u1 = 0, - reserved2: u1 = 0, - ILIM2_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT2_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP2_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - // RESERVED: u3, // bit offset: 12 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - ABORT_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 88 Interrupt Enable clear address - pub const INTEN_CLR = mmio(Address + 0x00000058, 32, packed struct { - ILIM0_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT0_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP0_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT1_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP1_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved2: u1 = 0, - ILIM2_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT2_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP2_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u4, // bit offset: 11 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - ABORT_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 92 Count Control read address - pub const CNTCON = mmio(Address + 0x0000005c, 32, packed struct { - TC0MCI0_RE: enum(u1) { // bit offset: 0 desc: Counter 0 rising edge mode, channel 0. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 0. - @"RISING" = 1, // desc: If MODE0 is 1, counter 0 advances on a rising edge on MCI0. - }, - TC0MCI0_FE: enum(u1) { // bit offset: 1 desc: Counter 0 falling edge mode, channel 0. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 0. - @"FALLING" = 1, // desc: If MODE0 is 1, counter 0 advances on a falling edge on MCI0. - }, - TC0MCI1_RE: enum(u1) { // bit offset: 2 desc: Counter 0 rising edge mode, channel 1. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI1 does not affect counter 0. - @"RISING" = 1, // desc: If MODE0 is 1, counter 0 advances on a rising edge on MCI1. - }, - TC0MCI1_FE: enum(u1) { // bit offset: 3 desc: Counter 0 falling edge mode, channel 1. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI1 does not affect counter 0. - @"FALLING" = 1, // desc: If MODE0 is 1, counter 0 advances on a falling edge on MCI1. - }, - TC0MCI2_RE: enum(u1) { // bit offset: 4 desc: Counter 0 rising edge mode, channel 2. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 0. - @"RISING" = 1, // desc: If MODE0 is 1, counter 0 advances on a rising edge on MCI2. - }, - TC0MCI2_FE: enum(u1) { // bit offset: 5 desc: Counter 0 falling edge mode, channel 2. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 0. - @"FALLLING" = 1, // desc: If MODE0 is 1, counter 0 advances on a falling edge on MCI2. - }, - TC1MCI0_RE: enum(u1) { // bit offset: 6 desc: Counter 1 rising edge mode, channel 0. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 1. - @"RISING" = 1, // desc: If MODE1 is 1, counter 1 advances on a rising edge on MCI0. - }, - TC1MCI0_FE: enum(u1) { // bit offset: 7 desc: Counter 1 falling edge mode, channel 0. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 1. - @"FALLING" = 1, // desc: If MODE1 is 1, counter 1 advances on a falling edge on MCI0. - }, - TC1MCI1_RE: enum(u1) { // bit offset: 8 desc: Counter 1 rising edge mode, channel 1. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI1 does not affect counter 1. - @"RISING" = 1, // desc: If MODE1 is 1, counter 1 advances on a rising edge on MCI1. - }, - TC1MCI1_FE: enum(u1) { // bit offset: 9 desc: Counter 1 falling edge mode, channel 1. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 1. - @"FALLING" = 1, // desc: If MODE1 is 1, counter 1 advances on a falling edge on MCI1. - }, - TC1MCI2_RE: enum(u1) { // bit offset: 10 desc: Counter 1 rising edge mode, channel 2. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI2 does not affect counter 1. - @"RISING" = 1, // desc: If MODE1 is 1, counter 1 advances on a rising edge on MCI2. - }, - TC1MCI2_FE: enum(u1) { // bit offset: 11 desc: Counter 1 falling edge mode, channel 2. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI2 does not affect counter 1. - @"FALLING" = 1, // desc: If MODE1 is 1, counter 1 advances on a falling edge on MCI2. - }, - TC2MCI0_RE: enum(u1) { // bit offset: 12 desc: Counter 2 rising edge mode, channel 0. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 2. - @"RISING" = 1, // desc: If MODE2 is 1, counter 2 advances on a rising edge on MCI0. - }, - TC2MCI0_FE: enum(u1) { // bit offset: 13 desc: Counter 2 falling edge mode, channel 0. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 2. - @"FALLING" = 1, // desc: If MODE2 is 1, counter 2 advances on a falling edge on MCI0. - }, - TC2MCI1_RE: enum(u1) { // bit offset: 14 desc: Counter 2 rising edge mode, channel 1. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI1 does not affect counter 2. - @"RISING" = 1, // desc: If MODE2 is 1, counter 2 advances on a rising edge on MCI1. - }, - TC2MCI1_FE: enum(u1) { // bit offset: 15 desc: Counter 2 falling edge mode, channel 1. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI1 does not affect counter 2. - @"FALLING" = 1, // desc: If MODE2 is 1, counter 2 advances on a falling edge on MCI1. - }, - TC2MCI2_RE: enum(u1) { // bit offset: 16 desc: Counter 2 rising edge mode, channel 2. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI2 does not affect counter 2. - @"RISIING" = 1, // desc: If MODE2 is 1, counter 2 advances on a rising edge on MCI2. - }, - TC2MCI2_FE: enum(u1) { // bit offset: 17 desc: Counter 2 falling edge mode, channel 2. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI2 does not affect counter 2. - @"FALLING" = 1, // desc: If MODE2 is 1, counter 2 advances on a falling edge on MCI2. - }, - // RESERVED: u11, // bit offset: 18 desc: Reserved. - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CNTR0: enum(u1) { // bit offset: 29 desc: Channel 0 counter/timer mode. - @"CHANNEL_0_IS_IN_TIME" = 0, // desc: Channel 0 is in timer mode. - @"CHANNEL_0_IS_IN_COUN" = 1, // desc: Channel 0 is in counter mode. - }, - CNTR1: enum(u1) { // bit offset: 30 desc: Channel 1 counter/timer mode. - @"CHANNEL_1_IS_IN_TIME" = 0, // desc: Channel 1 is in timer mode. - @"CHANNEL_1_IS_IN_COUN" = 1, // desc: Channel 1 is in counter mode. - }, - CNTR2: enum(u1) { // bit offset: 31 desc: Channel 2 counter/timer mode. - @"CHANNEL_2_IS_IN_TIME" = 0, // desc: Channel 2 is in timer mode. - @"CHANNEL_2_IS_IN_COUN" = 1, // desc: Channel 2 is in counter mode. - }, - }); - // byte offset: 96 Count Control set address - pub const CNTCON_SET = mmio(Address + 0x00000060, 32, packed struct { - TC0MCI0_RE_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI0_FE_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI1_RE_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI1_FE_SET: u1, // bit offset: 3 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI2_RE_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI2_FE_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI0_RE_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI0_FE_SET: u1, // bit offset: 7 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI1_RE_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI1_FE_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI2_RE_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI2_FE_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI0_RE_SET: u1, // bit offset: 12 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI0_FE_SET: u1, // bit offset: 13 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI1_RE_SET: u1, // bit offset: 14 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI1_FE_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI2_RE_SET: u1, // bit offset: 16 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI2_FE_SET: u1, // bit offset: 17 desc: Writing a one sets the corresponding bit in the CNTCON register. - // RESERVED: u11, // bit offset: 18 desc: Reserved. - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CNTR0_SET: u1, // bit offset: 29 desc: Writing a one sets the corresponding bit in the CNTCON register. - CNTR1_SET: u1, // bit offset: 30 desc: Writing a one sets the corresponding bit in the CNTCON register. - CNTR2_SET: u1, // bit offset: 31 desc: Writing a one sets the corresponding bit in the CNTCON register. - }); - // byte offset: 100 Count Control clear address - pub const CNTCON_CLR = mmio(Address + 0x00000064, 32, packed struct { - TC0MCI0_RE_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI0_FE_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI1_RE_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI1_FE_CLR: u1, // bit offset: 3 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI2_RE: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI2_FE_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI0_RE_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI0_FE_CLR: u1, // bit offset: 7 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI1_RE_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI1_FE_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI2_RE_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI2_FE_CLR: u1, // bit offset: 11 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI0_RE_CLR: u1, // bit offset: 12 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI0_FE_CLR: u1, // bit offset: 13 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI1_RE_CLR: u1, // bit offset: 14 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI1_FE_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI2_RE_CLR: u1, // bit offset: 16 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI2_FE_CLR: u1, // bit offset: 17 desc: Writing a one clears the corresponding bit in the CNTCON register. - // RESERVED: u11, // bit offset: 18 desc: Reserved. - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CNTR0_CLR: u1, // bit offset: 29 desc: Writing a one clears the corresponding bit in the CNTCON register. - CNTR1_CLR: u1, // bit offset: 30 desc: Writing a one clears the corresponding bit in the CNTCON register. - CNTR2_CLR: u1, // bit offset: 31 desc: Writing a one clears the corresponding bit in the CNTCON register. - }); - // byte offset: 104 Interrupt flags read address - pub const INTF = mmio(Address + 0x00000068, 32, packed struct { - ILIM0_F: enum(u1) { // bit offset: 0 desc: Limit interrupt flag for channel 0. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - IMAT0_F: enum(u1) { // bit offset: 1 desc: Match interrupt flag for channel 0. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - ICAP0_F: enum(u1) { // bit offset: 2 desc: Capture interrupt flag for channel 0. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1_F: enum(u1) { // bit offset: 4 desc: Limit interrupt flag for channel 1. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - IMAT1_F: enum(u1) { // bit offset: 5 desc: Match interrupt flag for channel 1. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - ICAP1_F: enum(u1) { // bit offset: 6 desc: Capture interrupt flag for channel 1. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved2: u1 = 0, - ILIM2_F: enum(u1) { // bit offset: 8 desc: Limit interrupt flag for channel 2. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - IMAT2_F: enum(u1) { // bit offset: 9 desc: Match interrupt flag for channel 2. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - ICAP2_F: enum(u1) { // bit offset: 10 desc: Capture interrupt flag for channel 2. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - // RESERVED: u4, // bit offset: 11 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - ABORT_F: enum(u1) { // bit offset: 15 desc: Fast abort interrupt flag. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 108 Interrupt flags set address - pub const INTF_SET = mmio(Address + 0x0000006c, 32, packed struct { - ILIM0_F_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - IMAT0_F_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - ICAP0_F_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1_F_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - IMAT1_F_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - ICAP1_F_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved2: u1 = 0, - ILIM2_F_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - IMAT2_F_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - ICAP2_F_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - // RESERVED: u4, // bit offset: 11 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - ABORT_F_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Interrupt flags clear address - pub const INTF_CLR = mmio(Address + 0x00000070, 32, packed struct { - ILIM0_F_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request. - IMAT0_F_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP0_F_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1_F_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT1_F_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP1_F_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved2: u1 = 0, - ILIM2_F_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT2_F_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP2_F_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u4, // bit offset: 11 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - ABORT_F_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 116 Capture clear address - pub const CAP_CLR = mmio(Address + 0x00000074, 32, packed struct { - CAP_CLR0: u1, // bit offset: 0 desc: Writing a 1 to this bit clears the CAP0 register. - CAP_CLR1: u1, // bit offset: 1 desc: Writing a 1 to this bit clears the CAP1 register. - CAP_CLR2: u1, // bit offset: 2 desc: Writing a 1 to this bit clears the CAP2 register. - // RESERVED: u29, // bit offset: 3 desc: Reserved - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const QEI = extern struct { - pub const Address: u32 = 0x400bc000; - // byte offset: 0 Control register - pub const CON = mmio(Address + 0x00000000, 32, packed struct { - RESP: u1, // bit offset: 0 desc: Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared. - RESPI: u1, // bit offset: 1 desc: Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared. - RESV: u1, // bit offset: 2 desc: Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared. - RESI: u1, // bit offset: 3 desc: Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Status register - pub const STAT = mmio(Address + 0x00000004, 32, packed struct { - DIR: u1, // bit offset: 0 desc: Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597. - // RESERVED: u31, // bit offset: 1 desc: Reserved. Read value is undefined, only zero should be written. - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Configuration register - pub const CONF = mmio(Address + 0x00000008, 32, packed struct { - DIRINV: u1, // bit offset: 0 desc: Direction invert. When 1, complements the DIR bit. - SIGMODE: u1, // bit offset: 1 desc: Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal. - CAPMODE: u1, // bit offset: 2 desc: Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range. - INVINX: u1, // bit offset: 3 desc: Invert Index. When 1, inverts the sense of the index input. - CRESPI: u1, // bit offset: 4 desc: Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration). - // RESERVED: u11, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - INXGATE: u4, // bit offset: 16 desc: Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index. - // RESERVED: u12, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Position register - pub const POS = mmio(Address + 0x0000000c, 32, packed struct { - POS: u32, // bit offset: 0 desc: Current position value. - }); - // byte offset: 16 Maximum position register - pub const MAXPOS = mmio(Address + 0x00000010, 32, packed struct { - MAXPOS: u32, // bit offset: 0 desc: Current maximum position value. - }); - // byte offset: 20 Position compare register 0 - pub const CMPOS0 = mmio(Address + 0x00000014, 32, packed struct { - PCMP0: u32, // bit offset: 0 desc: Position compare value 0. - }); - // byte offset: 24 Position compare register 1 - pub const CMPOS1 = mmio(Address + 0x00000018, 32, packed struct { - PCMP1: u32, // bit offset: 0 desc: Position compare value 1. - }); - // byte offset: 28 Position compare register 2 - pub const CMPOS2 = mmio(Address + 0x0000001c, 32, packed struct { - PCMP2: u32, // bit offset: 0 desc: Position compare value 2. - }); - // byte offset: 32 Index count register 0 - pub const INXCNT = mmio(Address + 0x00000020, 32, packed struct { - ENCPOS: u32, // bit offset: 0 desc: Current index counter value. - }); - // byte offset: 36 Index compare register 0 - pub const INXCMP0 = mmio(Address + 0x00000024, 32, packed struct { - ICMP0: u32, // bit offset: 0 desc: Index compare value 0. - }); - // byte offset: 40 Velocity timer reload register - pub const LOAD = mmio(Address + 0x00000028, 32, packed struct { - VELLOAD: u32, // bit offset: 0 desc: Current velocity timer load value. - }); - // byte offset: 44 Velocity timer register - pub const TIME = mmio(Address + 0x0000002c, 32, packed struct { - VELVAL: u32, // bit offset: 0 desc: Current velocity timer value. - }); - // byte offset: 48 Velocity counter register - pub const VEL = mmio(Address + 0x00000030, 32, packed struct { - VELPC: u32, // bit offset: 0 desc: Current velocity pulse count. - }); - // byte offset: 52 Velocity capture register - pub const CAP = mmio(Address + 0x00000034, 32, packed struct { - VELCAP: u32, // bit offset: 0 desc: Last velocity capture. - }); - // byte offset: 56 Velocity compare register - pub const VELCOMP = mmio(Address + 0x00000038, 32, packed struct { - VELPC: u32, // bit offset: 0 desc: Compare velocity pulse count. - }); - // byte offset: 60 Digital filter register - pub const FILTER = mmio(Address + 0x0000003c, 32, packed struct { - FILTA: u32, // bit offset: 0 desc: Digital filter sampling delay. - }); - // byte offset: 4056 Interrupt enable clear register - pub const IEC = mmio(Address + 0x00000fd8, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: Writing a 1 disables the INX_Int interrupt in the QEIIE register. - TIM_INT: u1, // bit offset: 1 desc: Writing a 1 disables the TIN_Int interrupt in the QEIIE register. - VELC_INT: u1, // bit offset: 2 desc: Writing a 1 disables the VELC_Int interrupt in the QEIIE register. - DIR_INT: u1, // bit offset: 3 desc: Writing a 1 disables the DIR_Int interrupt in the QEIIE register. - ERR_INT: u1, // bit offset: 4 desc: Writing a 1 disables the ERR_Int interrupt in the QEIIE register. - ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register. - POS0_INT: u1, // bit offset: 6 desc: Writing a 1 disables the POS0_Int interrupt in the QEIIE register. - POS1_INT: u1, // bit offset: 7 desc: Writing a 1 disables the POS1_Int interrupt in the QEIIE register. - POS2_INT: u1, // bit offset: 8 desc: Writing a 1 disables the POS2_Int interrupt in the QEIIE register. - REV0_INT: u1, // bit offset: 9 desc: Writing a 1 disables the REV0_Int interrupt in the QEIIE register. - POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register. - POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register. - POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register. - REV1_INT: u1, // bit offset: 13 desc: Writing a 1 disables the REV1_Int interrupt in the QEIIE register. - REV2_INT: u1, // bit offset: 14 desc: Writing a 1 disables the REV2_Int interrupt in the QEIIE register. - MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4060 Interrupt enable set register - pub const IES = mmio(Address + 0x00000fdc, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: Writing a 1 enables the INX_Int interrupt in the QEIIE register. - TIM_INT: u1, // bit offset: 1 desc: Writing a 1 enables the TIN_Int interrupt in the QEIIE register. - VELC_INT: u1, // bit offset: 2 desc: Writing a 1 enables the VELC_Int interrupt in the QEIIE register. - DIR_INT: u1, // bit offset: 3 desc: Writing a 1 enables the DIR_Int interrupt in the QEIIE register. - ERR_INT: u1, // bit offset: 4 desc: Writing a 1 enables the ERR_Int interrupt in the QEIIE register. - ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register. - POS0_INT: u1, // bit offset: 6 desc: Writing a 1 enables the POS0_Int interrupt in the QEIIE register. - POS1_INT: u1, // bit offset: 7 desc: Writing a 1 enables the POS1_Int interrupt in the QEIIE register. - POS2_INT: u1, // bit offset: 8 desc: Writing a 1 enables the POS2_Int interrupt in the QEIIE register. - REV0_INT: u1, // bit offset: 9 desc: Writing a 1 enables the REV0_Int interrupt in the QEIIE register. - POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register. - POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register. - POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register. - REV1_INT: u1, // bit offset: 13 desc: Writing a 1 enables the REV1_Int interrupt in the QEIIE register. - REV2_INT: u1, // bit offset: 14 desc: Writing a 1 enables the REV2_Int interrupt in the QEIIE register. - MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4064 Interrupt status register - pub const INTSTAT = mmio(Address + 0x00000fe0, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: Indicates that an index pulse was detected. - TIM_INT: u1, // bit offset: 1 desc: Indicates that a velocity timer overflow occurred - VELC_INT: u1, // bit offset: 2 desc: Indicates that captured velocity is less than compare velocity. - DIR_INT: u1, // bit offset: 3 desc: Indicates that a change of direction was detected. - ERR_INT: u1, // bit offset: 4 desc: Indicates that an encoder phase error was detected. - ENCLK_INT: u1, // bit offset: 5 desc: Indicates that and encoder clock pulse was detected. - POS0_INT: u1, // bit offset: 6 desc: Indicates that the position 0 compare value is equal to the current position. - POS1_INT: u1, // bit offset: 7 desc: Indicates that the position 1compare value is equal to the current position. - POS2_INT: u1, // bit offset: 8 desc: Indicates that the position 2 compare value is equal to the current position. - REV0_INT: u1, // bit offset: 9 desc: Indicates that the index compare 0 value is equal to the current index count. - POS0REV_INT: u1, // bit offset: 10 desc: Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set. - POS1REV_INT: u1, // bit offset: 11 desc: Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set. - POS2REV_INT: u1, // bit offset: 12 desc: Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set. - REV1_INT: u1, // bit offset: 13 desc: Indicates that the index compare 1value is equal to the current index count. - REV2_INT: u1, // bit offset: 14 desc: Indicates that the index compare 2 value is equal to the current index count. - MAXPOS_INT: u1, // bit offset: 15 desc: Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4068 Interrupt enable register - pub const IE = mmio(Address + 0x00000fe4, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: When 1, the INX_Int interrupt is enabled. - TIM_INT: u1, // bit offset: 1 desc: When 1, the TIN_Int interrupt is enabled. - VELC_INT: u1, // bit offset: 2 desc: When 1, the VELC_Int interrupt is enabled. - DIR_INT: u1, // bit offset: 3 desc: When 1, the DIR_Int interrupt is enabled. - ERR_INT: u1, // bit offset: 4 desc: When 1, the ERR_Int interrupt is enabled. - ENCLK_INT: u1, // bit offset: 5 desc: When 1, the ENCLK_Int interrupt is enabled. - POS0_INT: u1, // bit offset: 6 desc: When 1, the POS0_Int interrupt is enabled. - POS1_INT: u1, // bit offset: 7 desc: When 1, the POS1_Int interrupt is enabled. - POS2_INT: u1, // bit offset: 8 desc: When 1, the POS2_Int interrupt is enabled. - REV0_INT: u1, // bit offset: 9 desc: When 1, the REV0_Int interrupt is enabled. - POS0REV_INT: u1, // bit offset: 10 desc: When 1, the POS0REV_Int interrupt is enabled. - POS1REV_INT: u1, // bit offset: 11 desc: When 1, the POS1REV_Int interrupt is enabled. - POS2REV_INT: u1, // bit offset: 12 desc: When 1, the POS2REV_Int interrupt is enabled. - REV1_INT: u1, // bit offset: 13 desc: When 1, the REV1_Int interrupt is enabled. - REV2_INT: u1, // bit offset: 14 desc: When 1, the REV2_Int interrupt is enabled. - MAXPOS_INT: u1, // bit offset: 15 desc: When 1, the MAXPOS_Int interrupt is enabled. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4072 Interrupt status clear register - pub const CLR = mmio(Address + 0x00000fe8, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: Writing a 1 clears the INX_Int bit in QEIINTSTAT. - TIM_INT: u1, // bit offset: 1 desc: Writing a 1 clears the TIN_Int bit in QEIINTSTAT. - VELC_INT: u1, // bit offset: 2 desc: Writing a 1 clears the VELC_Int bit in QEIINTSTAT. - DIR_INT: u1, // bit offset: 3 desc: Writing a 1 clears the DIR_Int bit in QEIINTSTAT. - ERR_INT: u1, // bit offset: 4 desc: Writing a 1 clears the ERR_Int bit in QEIINTSTAT. - ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT. - POS0_INT: u1, // bit offset: 6 desc: Writing a 1 clears the POS0_Int bit in QEIINTSTAT. - POS1_INT: u1, // bit offset: 7 desc: Writing a 1 clears the POS1_Int bit in QEIINTSTAT. - POS2_INT: u1, // bit offset: 8 desc: Writing a 1 clears the POS2_Int bit in QEIINTSTAT. - REV0_INT: u1, // bit offset: 9 desc: Writing a 1 clears the REV0_Int bit in QEIINTSTAT. - POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT. - POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT. - POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT. - REV1_INT: u1, // bit offset: 13 desc: Writing a 1 clears the REV1_Int bit in QEIINTSTAT. - REV2_INT: u1, // bit offset: 14 desc: Writing a 1 clears the REV2_Int bit in QEIINTSTAT. - MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4076 Interrupt status set register - pub const SET = mmio(Address + 0x00000fec, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: Writing a 1 sets the INX_Int bit in QEIINTSTAT. - TIM_INT: u1, // bit offset: 1 desc: Writing a 1 sets the TIN_Int bit in QEIINTSTAT. - VELC_INT: u1, // bit offset: 2 desc: Writing a 1 sets the VELC_Int bit in QEIINTSTAT. - DIR_INT: u1, // bit offset: 3 desc: Writing a 1 sets the DIR_Int bit in QEIINTSTAT. - ERR_INT: u1, // bit offset: 4 desc: Writing a 1 sets the ERR_Int bit in QEIINTSTAT. - ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT. - POS0_INT: u1, // bit offset: 6 desc: Writing a 1 sets the POS0_Int bit in QEIINTSTAT. - POS1_INT: u1, // bit offset: 7 desc: Writing a 1 sets the POS1_Int bit in QEIINTSTAT. - POS2_INT: u1, // bit offset: 8 desc: Writing a 1 sets the POS2_Int bit in QEIINTSTAT. - REV0_INT: u1, // bit offset: 9 desc: Writing a 1 sets the REV0_Int bit in QEIINTSTAT. - POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT. - POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT. - POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT. - REV1_INT: u1, // bit offset: 13 desc: Writing a 1 sets the REV1_Int bit in QEIINTSTAT. - REV2_INT: u1, // bit offset: 14 desc: Writing a 1 sets the REV2_Int bit in QEIINTSTAT. - MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const SYSCON = extern struct { - pub const Address: u32 = 0x400fc000; - // byte offset: 0 Flash Accelerator Configuration Register. Controls flash access timing. - pub const FLASHCFG = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u12, // bit offset: 0 desc: Reserved, user software should not change these bits from the reset value. - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - FLASHTIM: enum(u4) { // bit offset: 12 desc: Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved. - @"1CLK" = 0, // desc: Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock. - @"2CLK" = 1, // desc: Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock. - @"3CLK" = 2, // desc: Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock. - @"4CLK" = 3, // desc: Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock. - @"5CLK" = 4, // desc: Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only. - @"6CLK" = 5, // desc: Flash accesses use 6 CPU clocks. This safe setting will work under any conditions. - _, // non-exhaustive - }, - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 128 PLL0 Control Register - pub const PLL0CON = mmio(Address + 0x00000080, 32, packed struct { - PLLE0: u1, // bit offset: 0 desc: PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register. - PLLC0: u1, // bit offset: 1 desc: PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register. - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 132 PLL0 Configuration Register - pub const PLL0CFG = mmio(Address + 0x00000084, 32, packed struct { - MSEL0: u15, // bit offset: 0 desc: PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware. - // RESERVED: u1, // bit offset: 15 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved1: u1 = 0, - NSEL0: u8, // bit offset: 16 desc: PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32. - // RESERVED: u8, // bit offset: 24 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 136 PLL0 Status Register - pub const PLL0STAT = mmio(Address + 0x00000088, 32, packed struct { - MSEL0: u15, // bit offset: 0 desc: Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier. - // RESERVED: u1, // bit offset: 15 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved1: u1 = 0, - NSEL0: u8, // bit offset: 16 desc: Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider. - PLLE0_STAT: u1, // bit offset: 24 desc: Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered. - PLLC0_STAT: u1, // bit offset: 25 desc: Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered. - PLOCK0: u1, // bit offset: 26 desc: Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details. - // RESERVED: u5, // bit offset: 27 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 140 PLL0 Feed Register - pub const PLL0FEED = mmio(Address + 0x0000008c, 32, packed struct { - PLL0FEED: u8, // bit offset: 0 desc: The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 160 PLL1 Control Register - pub const PLL1CON = mmio(Address + 0x000000a0, 32, packed struct { - PLLE1: u1, // bit offset: 0 desc: PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency. - PLLC1: u1, // bit offset: 1 desc: PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register. - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 164 PLL1 Configuration Register - pub const PLL1CFG = mmio(Address + 0x000000a4, 32, packed struct { - MSEL1: u5, // bit offset: 0 desc: PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations. - PSEL1: u2, // bit offset: 5 desc: PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations. - // RESERVED: u25, // bit offset: 7 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 168 PLL1 Status Register - pub const PLL1STAT = mmio(Address + 0x000000a8, 32, packed struct { - MSEL1: u5, // bit offset: 0 desc: Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1. - PSEL1: u2, // bit offset: 5 desc: Read-back for the PLL1 Divider value. This is the value currently used by PLL1. - // RESERVED: u1, // bit offset: 7 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved1: u1 = 0, - PLLE1_STAT: u1, // bit offset: 8 desc: Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated. - PLLC1_STAT: u1, // bit offset: 9 desc: Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated. - PLOCK1: u1, // bit offset: 10 desc: Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency. - // RESERVED: u21, // bit offset: 11 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 172 PLL1 Feed Register - pub const PLL1FEED = mmio(Address + 0x000000ac, 32, packed struct { - PLL1FEED: u8, // bit offset: 0 desc: The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 192 Power Control Register - pub const PCON = mmio(Address + 0x000000c0, 32, packed struct { - PM0: u1, // bit offset: 0 desc: Power mode control bit 0. This bit controls entry to the Power-down mode. - PM1: u1, // bit offset: 1 desc: Power mode control bit 1. This bit controls entry to the Deep Power-down mode. - BODRPM: u1, // bit offset: 2 desc: Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection. - BOGD: u1, // bit offset: 3 desc: Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit. - // RESERVED: u5, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - BORD: u1, // bit offset: 4 desc: Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SMFLAG: u1, // bit offset: 8 desc: Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit. - DSFLAG: u1, // bit offset: 9 desc: Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit. - PDFLAG: u1, // bit offset: 10 desc: Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit. - DPDFLAG: u1, // bit offset: 11 desc: Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit. - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 196 Power Control for Peripherals Register - pub const PCONP = mmio(Address + 0x000000c4, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. - reserved1: u1 = 0, - PCTIM0: u1, // bit offset: 1 desc: Timer/Counter 0 power/clock control bit. - PCTIM1: u1, // bit offset: 2 desc: Timer/Counter 1 power/clock control bit. - PCUART0: u1, // bit offset: 3 desc: UART0 power/clock control bit. - PCUART1: u1, // bit offset: 4 desc: UART1 power/clock control bit. - // RESERVED: u1, // bit offset: 5 desc: Reserved. - reserved2: u1 = 0, - PCPWM1: u1, // bit offset: 6 desc: PWM1 power/clock control bit. - PCI2C0: u1, // bit offset: 7 desc: The I2C0 interface power/clock control bit. - PCSPI: u1, // bit offset: 8 desc: The SPI interface power/clock control bit. - PCRTC: u1, // bit offset: 9 desc: The RTC power/clock control bit. - PCSSP1: u1, // bit offset: 10 desc: The SSP 1 interface power/clock control bit. - // RESERVED: u1, // bit offset: 11 desc: Reserved. - reserved3: u1 = 0, - PCADC: u1, // bit offset: 12 desc: A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN. - PCCAN1: u1, // bit offset: 13 desc: CAN Controller 1 power/clock control bit. - PCCAN2: u1, // bit offset: 14 desc: CAN Controller 2 power/clock control bit. - PCGPIO: u1, // bit offset: 15 desc: Power/clock control bit for IOCON, GPIO, and GPIO interrupts. - PCRIT: u1, // bit offset: 16 desc: Repetitive Interrupt Timer power/clock control bit. - PCMCPWM: u1, // bit offset: 17 desc: Motor Control PWM - PCQEI: u1, // bit offset: 18 desc: Quadrature Encoder Interface power/clock control bit. - PCI2C1: u1, // bit offset: 19 desc: The I2C1 interface power/clock control bit. - // RESERVED: u1, // bit offset: 20 desc: Reserved. - reserved4: u1 = 0, - PCSSP0: u1, // bit offset: 21 desc: The SSP0 interface power/clock control bit. - PCTIM2: u1, // bit offset: 22 desc: Timer 2 power/clock control bit. - PCTIM3: u1, // bit offset: 23 desc: Timer 3 power/clock control bit. - PCUART2: u1, // bit offset: 24 desc: UART 2 power/clock control bit. - PCUART3: u1, // bit offset: 25 desc: UART 3 power/clock control bit. - PCI2C2: u1, // bit offset: 26 desc: I2C interface 2 power/clock control bit. - PCI2S: u1, // bit offset: 27 desc: I2S interface power/clock control bit. - // RESERVED: u1, // bit offset: 28 desc: Reserved. - reserved5: u1 = 0, - PCGPDMA: u1, // bit offset: 29 desc: GPDMA function power/clock control bit. - PCENET: u1, // bit offset: 30 desc: Ethernet block power/clock control bit. - PCUSB: u1, // bit offset: 31 desc: USB interface power/clock control bit. - }); - // byte offset: 260 CPU Clock Configuration Register - pub const CCLKCFG = mmio(Address + 0x00000104, 32, packed struct { - CCLKSEL: u8, // bit offset: 0 desc: Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 264 USB Clock Configuration Register - pub const USBCLKCFG = mmio(Address + 0x00000108, 32, packed struct { - USBSEL: u4, // bit offset: 0 desc: Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 268 Clock Source Select Register - pub const CLKSRCSEL = mmio(Address + 0x0000010c, 32, packed struct { - CLKSRC: enum(u2) { // bit offset: 0 desc: Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device. - @"SELECTS_THE_INTERNAL" = 0, // desc: Selects the Internal RC oscillator as the PLL0 clock source (default). - @"SELECTS_THE_MAIN_OSC" = 1, // desc: Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s. - @"SELECTS_THE_RTC_OSCI" = 2, // desc: Selects the RTC oscillator as the PLL0 clock source. - // @"RESERVED", // desc: Reserved, do not use this setting. - _, // non-exhaustive - }, - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 272 Allows clearing the current CAN channel sleep state as well as reading that state. - pub const CANSLEEPCLR = mmio(Address + 0x00000110, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - CAN1SLEEP: u1, // bit offset: 1 desc: Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1. - CAN2SLEEP: u1, // bit offset: 2 desc: Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2. - // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 276 Allows reading the wake-up state of the CAN channels. - pub const CANWAKEFLAGS = mmio(Address + 0x00000114, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - CAN1WAKE: u1, // bit offset: 1 desc: Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit. - CAN2WAKE: u1, // bit offset: 2 desc: Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit. - // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 320 External Interrupt Flag Register - pub const EXTINT = mmio(Address + 0x00000140, 32, packed struct { - EINT0: u1, // bit offset: 0 desc: In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. - EINT1: u1, // bit offset: 1 desc: In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. - EINT2: u1, // bit offset: 2 desc: In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. - EINT3: u1, // bit offset: 3 desc: In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 328 External Interrupt Mode register - pub const EXTMODE = mmio(Address + 0x00000148, 32, packed struct { - EXTMODE0: enum(u1) { // bit offset: 0 desc: External interrupt 0 EINT0 mode. - @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT0. - @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT0 is edge sensitive. - }, - EXTMODE1: enum(u1) { // bit offset: 1 desc: External interrupt 1 EINT1 mode. - @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT1. - @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT1 is edge sensitive. - }, - EXTMODE2: enum(u1) { // bit offset: 2 desc: External interrupt 2 EINT2 mode. - @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT2. - @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT2 is edge sensitive. - }, - EXTMODE3: enum(u1) { // bit offset: 3 desc: External interrupt 3 EINT3 mode. - @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT3. - @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT3 is edge sensitive. - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 332 External Interrupt Polarity Register - pub const EXTPOLAR = mmio(Address + 0x0000014c, 32, packed struct { - EXTPOLAR0: enum(u1) { // bit offset: 0 desc: External interrupt 0 EINT0 polarity. - @"FALLING_EDGE" = 0, // desc: Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0). - @"RISING_EDGE" = 1, // desc: Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0). - }, - EXTPOLAR1: enum(u1) { // bit offset: 1 desc: External interrupt 1 EINT1 polarity. - @"FALLING_EDGE" = 0, // desc: Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1). - @"RISING_EDGE" = 1, // desc: Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1). - }, - EXTPOLAR2: enum(u1) { // bit offset: 2 desc: External interrupt 2 EINT2 polarity. - @"FALLING_EDGE" = 0, // desc: Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2). - @"RISING_EDGE" = 1, // desc: Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2). - }, - EXTPOLAR3: enum(u1) { // bit offset: 3 desc: External interrupt 3 EINT3 polarity. - @"FALLING_EDGE" = 0, // desc: Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3). - @"RISING_EDGE" = 1, // desc: Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3). - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 384 Reset Source Identification Register - pub const RSID = mmio(Address + 0x00000180, 32, packed struct { - POR: u1, // bit offset: 0 desc: Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset. - EXTR: u1, // bit offset: 1 desc: Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR. - WDTR: u1, // bit offset: 2 desc: This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR. - BODR: u1, // bit offset: 3 desc: This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 416 System control and status - pub const SCS = mmio(Address + 0x000001a0, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - OSCRANGE: enum(u1) { // bit offset: 4 desc: Main oscillator range select. - @"LOW" = 0, // desc: Low. The frequency range of the main oscillator is 1 MHz to 20 MHz. - @"HIGH" = 1, // desc: High. The frequency range of the main oscillator is 15 MHz to 25 MHz. - }, - OSCEN: enum(u1) { // bit offset: 5 desc: Main oscillator enable. - @"DISABLED" = 0, // desc: Disabled. The main oscillator is disabled. - @"ENABLED" = 1, // desc: Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins. - }, - OSCSTAT: enum(u1) { // bit offset: 6 desc: Main oscillator status. - @"NOT_READY" = 0, // desc: Not ready. The main oscillator is not ready to be used as a clock source. - @"READY" = 1, // desc: Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit. - }, - // RESERVED: u25, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 424 Peripheral Clock Selection register 0. - pub const PCLKSEL0 = mmio(Address + 0x000001a8, 32, packed struct { - PCLK_WDT: enum(u2) { // bit offset: 0 desc: Peripheral clock selection for WDT. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_TIMER0: enum(u2) { // bit offset: 2 desc: Peripheral clock selection for TIMER0. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_TIMER1: enum(u2) { // bit offset: 4 desc: Peripheral clock selection for TIMER1. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_UART0: enum(u2) { // bit offset: 6 desc: Peripheral clock selection for UART0. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_UART1: enum(u2) { // bit offset: 8 desc: Peripheral clock selection for UART1. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - // RESERVED: u2, // bit offset: 10 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - PCLK_PWM1: enum(u2) { // bit offset: 12 desc: Peripheral clock selection for PWM1. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_I2C0: enum(u2) { // bit offset: 14 desc: Peripheral clock selection for I2C0. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_SPI: enum(u2) { // bit offset: 16 desc: Peripheral clock selection for SPI. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - // RESERVED: u2, // bit offset: 18 desc: Reserved. - reserved4: u1 = 0, - reserved3: u1 = 0, - PCLK_SSP1: enum(u2) { // bit offset: 20 desc: Peripheral clock selection for SSP1. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_DAC: enum(u2) { // bit offset: 22 desc: Peripheral clock selection for DAC. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_ADC: enum(u2) { // bit offset: 24 desc: Peripheral clock selection for ADC. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_CAN1: enum(u2) { // bit offset: 26 desc: Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_6" = 3, // desc: CCLK div 6. PCLK_peripheral = CCLK/6. - }, - PCLK_CAN2: enum(u2) { // bit offset: 28 desc: Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_6" = 3, // desc: CCLK div 6. PCLK_peripheral = CCLK/6, - }, - PCLK_ACF: enum(u2) { // bit offset: 30 desc: Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_6" = 3, // desc: CCLK div 6. PCLK_peripheral = CCLK/6 - }, - }); - // byte offset: 428 Peripheral Clock Selection register 1. - pub const PCLKSEL1 = mmio(Address + 0x000001ac, 32, packed struct { - PCLK_QEI: enum(u2) { // bit offset: 0 desc: Peripheral clock selection for the Quadrature Encoder Interface. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_GPIOINT: enum(u2) { // bit offset: 2 desc: Peripheral clock selection for GPIO interrupts. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_PCB: enum(u2) { // bit offset: 4 desc: Peripheral clock selection for the Pin Connect block. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_I2C1: enum(u2) { // bit offset: 6 desc: Peripheral clock selection for I2C1. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - // RESERVED: u2, // bit offset: 8 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - PCLK_SSP0: enum(u2) { // bit offset: 10 desc: Peripheral clock selection for SSP0. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_TIMER2: enum(u2) { // bit offset: 12 desc: Peripheral clock selection for TIMER2. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_TIMER3: enum(u2) { // bit offset: 14 desc: Peripheral clock selection for TIMER3. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_UART2: enum(u2) { // bit offset: 16 desc: Peripheral clock selection for UART2. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_UART3: enum(u2) { // bit offset: 18 desc: Peripheral clock selection for UART3. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_I2C2: enum(u2) { // bit offset: 20 desc: Peripheral clock selection for I2C2. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_I2S: enum(u2) { // bit offset: 22 desc: Peripheral clock selection for I2S. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - // RESERVED: u2, // bit offset: 24 desc: Reserved. - reserved4: u1 = 0, - reserved3: u1 = 0, - PCLK_RIT: enum(u2) { // bit offset: 26 desc: Peripheral clock selection for Repetitive Interrupt Timer. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_SYSCON: enum(u2) { // bit offset: 28 desc: Peripheral clock selection for the System Control block. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_MC: enum(u2) { // bit offset: 30 desc: Peripheral clock selection for the Motor Control PWM. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - }); - // byte offset: 448 USB Interrupt Status - pub const USBINTST = mmio(Address + 0x000001c0, 32, packed struct { - USB_INT_REQ_LP: u1, // bit offset: 0 desc: Low priority interrupt line status. This bit is read-only. - USB_INT_REQ_HP: u1, // bit offset: 1 desc: High priority interrupt line status. This bit is read-only. - USB_INT_REQ_DMA: u1, // bit offset: 2 desc: DMA interrupt line status. This bit is read-only. - USB_HOST_INT: u1, // bit offset: 3 desc: USB host interrupt line status. This bit is read-only. - USB_ATX_INT: u1, // bit offset: 4 desc: External ATX interrupt line status. This bit is read-only. - USB_OTG_INT: u1, // bit offset: 5 desc: OTG interrupt line status. This bit is read-only. - USB_I2C_INT: u1, // bit offset: 6 desc: I2C module interrupt line status. This bit is read-only. - // RESERVED: u1, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - USB_NEED_CLK: u1, // bit offset: 8 desc: USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only. - // RESERVED: u22, // bit offset: 9 desc: Reserved. Read value is undefined, only zero should be written. - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - EN_USB_INTS: u1, // bit offset: 31 desc: Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines. - }); - // byte offset: 452 Selects between alternative requests on DMA channels 0 through 7 and 10 through 15 - pub const DMACREQSEL = mmio(Address + 0x000001c4, 32, packed struct { - DMASEL08: u1, // bit offset: 0 desc: Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected. - DMASEL09: u1, // bit offset: 1 desc: Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected. - DMASEL10: u1, // bit offset: 2 desc: Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected. - DMASEL11: u1, // bit offset: 3 desc: Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected. - DMASEL12: u1, // bit offset: 4 desc: Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected. - DMASEL13: u1, // bit offset: 5 desc: Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected. - DMASEL14: u1, // bit offset: 6 desc: Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected. - DMASEL15: u1, // bit offset: 7 desc: Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 456 Clock Output Configuration Register - pub const CLKOUTCFG = mmio(Address + 0x000001c8, 32, packed struct { - CLKOUTSEL: enum(u4) { // bit offset: 0 desc: Selects the clock source for the CLKOUT function. Other values are reserved. Do not use. - @"SELECTS_THE_CPU_CLOC" = 0, // desc: Selects the CPU clock as the CLKOUT source. - @"SELECTS_THE_MAIN_OSC" = 1, // desc: Selects the main oscillator as the CLKOUT source. - @"SELECTS_THE_INTERNAL" = 2, // desc: Selects the Internal RC oscillator as the CLKOUT source. - @"SELECTS_THE_USB_CLOC" = 3, // desc: Selects the USB clock as the CLKOUT source. - @"SELECTS_THE_RTC_OSCI" = 4, // desc: Selects the RTC oscillator as the CLKOUT source. - _, // non-exhaustive - }, - CLKOUTDIV: u4, // bit offset: 4 desc: Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16. - CLKOUT_EN: u1, // bit offset: 8 desc: CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. - CLKOUT_ACT: u1, // bit offset: 9 desc: CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped. - // RESERVED: u22, // bit offset: 10 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const EMAC = extern struct { - pub const Address: u32 = 0x50000000; - // byte offset: 0 MAC configuration register 1. - pub const MAC1 = mmio(Address + 0x00000000, 32, packed struct { - RXENABLE: u1, // bit offset: 0 desc: RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream. - PARF: u1, // bit offset: 1 desc: PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames. - RXFLOWCTRL: u1, // bit offset: 2 desc: RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored. - TXFLOWCTRL: u1, // bit offset: 3 desc: TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked. - LOOPBACK: u1, // bit offset: 4 desc: Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation. - // RESERVED: u3, // bit offset: 5 desc: Unused - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESETTX: u1, // bit offset: 8 desc: Setting this bit will put the Transmit Function logic in reset. - RESETMCSTX: u1, // bit offset: 9 desc: Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control. - RESETRX: u1, // bit offset: 10 desc: Setting this bit will put the Ethernet receive logic in reset. - RESETMCSRX: u1, // bit offset: 11 desc: Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control. - // RESERVED: u2, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - SIMRESET: u1, // bit offset: 14 desc: SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function. - SOFTRESET: u1, // bit offset: 15 desc: SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 MAC configuration register 2. - pub const MAC2 = mmio(Address + 0x00000004, 32, packed struct { - FULLDUPLEX: u1, // bit offset: 0 desc: When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode. - FLC: u1, // bit offset: 1 desc: FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame. - HFEN: u1, // bit offset: 2 desc: HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received. - DELAYEDCRC: u1, // bit offset: 3 desc: DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header. - CRCEN: u1, // bit offset: 4 desc: CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC. - PADCRCEN: u1, // bit offset: 5 desc: PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function. - VLANPADEN: u1, // bit offset: 6 desc: VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared. - AUTODETPADEN: u1, // bit offset: 7 desc: AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared. - PPENF: u1, // bit offset: 8 desc: PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed. - LPENF: u1, // bit offset: 9 desc: LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard. - // RESERVED: u2, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - NOBACKOFF: u1, // bit offset: 12 desc: When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard. - BP_NOBACKOFF: u1, // bit offset: 13 desc: BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent. - EXCESSDEFER: u1, // bit offset: 14 desc: When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached. - // RESERVED: u17, // bit offset: 15 desc: Reserved. Read value is undefined, only zero should be written. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Back-to-Back Inter-Packet-Gap register. - pub const IPGT = mmio(Address + 0x00000008, 32, packed struct { - BTOBINTEGAP: u7, // bit offset: 0 desc: BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). - // RESERVED: u25, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Non Back-to-Back Inter-Packet-Gap register. - pub const IPGR = mmio(Address + 0x0000000c, 32, packed struct { - NBTOBINTEGAP2: u7, // bit offset: 0 desc: NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). - // RESERVED: u1, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - NBTOBINTEGAP1: u7, // bit offset: 8 desc: NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d) - // RESERVED: u17, // bit offset: 15 desc: Reserved. Read value is undefined, only zero should be written. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Collision window / Retry register. - pub const CLRT = mmio(Address + 0x00000010, 32, packed struct { - RETRANSMAX: u4, // bit offset: 0 desc: RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5. - // RESERVED: u4, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - COLLWIN: u6, // bit offset: 8 desc: COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD. - // RESERVED: u18, // bit offset: 14 desc: Reserved. Read value is undefined, only zero should be written. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Maximum Frame register. - pub const MAXF = mmio(Address + 0x00000014, 32, packed struct { - MAXFLEN: u16, // bit offset: 0 desc: MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 PHY Support register. - pub const SUPP = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u8, // bit offset: 0 desc: Unused - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SPEED: u1, // bit offset: 8 desc: This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. - // RESERVED: u23, // bit offset: 9 desc: Unused - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Test register. - pub const TEST = mmio(Address + 0x0000001c, 32, packed struct { - SCPQ: u1, // bit offset: 0 desc: SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. - TESTPAUSE: u1, // bit offset: 1 desc: This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received. - TESTBP: u1, // bit offset: 2 desc: TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure. - // RESERVED: u29, // bit offset: 3 desc: Unused - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 MII Mgmt Configuration register. - pub const MCFG = mmio(Address + 0x00000020, 32, packed struct { - SCANINC: u1, // bit offset: 0 desc: SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY. - SUPPPREAMBLE: u1, // bit offset: 1 desc: SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble. - CLOCKSEL: u4, // bit offset: 2 desc: CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field. - // RESERVED: u9, // bit offset: 6 desc: Unused - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESETMIIMGMT: u1, // bit offset: 15 desc: RESET MII MGMT. This bit resets the MII Management hardware. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 MII Mgmt Command register. - pub const MCMD = mmio(Address + 0x00000024, 32, packed struct { - READ: u1, // bit offset: 0 desc: This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data). - SCAN: u1, // bit offset: 1 desc: This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example. - // RESERVED: u30, // bit offset: 2 desc: Unused - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 MII Mgmt Address register. - pub const MADR = mmio(Address + 0x00000028, 32, packed struct { - REGADDR: u5, // bit offset: 0 desc: REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed. - // RESERVED: u3, // bit offset: 5 desc: Unused - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - PHYADDR: u5, // bit offset: 8 desc: PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved). - // RESERVED: u19, // bit offset: 13 desc: Unused - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 MII Mgmt Write Data register. - pub const MWTD = mmio(Address + 0x0000002c, 32, packed struct { - WRITEDATA: u16, // bit offset: 0 desc: WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR). - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 MII Mgmt Read Data register. - pub const MRDD = mmio(Address + 0x00000030, 32, packed struct { - READDATA: u16, // bit offset: 0 desc: READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 MII Mgmt Indicators register. - pub const MIND = mmio(Address + 0x00000034, 32, packed struct { - BUSY: u1, // bit offset: 0 desc: When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle. - SCANNING: u1, // bit offset: 1 desc: When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress. - NOTVALID: u1, // bit offset: 2 desc: When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid. - MIILINKFAIL: u1, // bit offset: 3 desc: When 1 is returned - indicates that an MII Mgmt link fail has occurred. - // RESERVED: u28, // bit offset: 4 desc: Unused - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 64 Station Address 0 register. - pub const SA0 = mmio(Address + 0x00000040, 32, packed struct { - SADDR2: u8, // bit offset: 0 desc: STATION ADDRESS, 2nd octet. This field holds the second octet of the station address. - SADDR1: u8, // bit offset: 8 desc: STATION ADDRESS, 1st octet. This field holds the first octet of the station address. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 68 Station Address 1 register. - pub const SA1 = mmio(Address + 0x00000044, 32, packed struct { - SADDR4: u8, // bit offset: 0 desc: STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address. - SADDR3: u8, // bit offset: 8 desc: STATION ADDRESS, 3rd octet. This field holds the third octet of the station address. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 72 Station Address 2 register. - pub const SA2 = mmio(Address + 0x00000048, 32, packed struct { - SADDR6: u8, // bit offset: 0 desc: STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address. - SADDR5: u8, // bit offset: 8 desc: STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 256 Command register. - pub const COMMAND = mmio(Address + 0x00000100, 32, packed struct { - RXENABLE: u1, // bit offset: 0 desc: Enable receive. - TXENABLE: u1, // bit offset: 1 desc: Enable transmit. - // RESERVED: u1, // bit offset: 2 desc: Unused - reserved1: u1 = 0, - REGRESET: u1, // bit offset: 3 desc: When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately. - TXRESET: u1, // bit offset: 4 desc: When a 1 is written, the transmit datapath is reset. - RXRESET: u1, // bit offset: 5 desc: When a 1 is written, the receive datapath is reset. - PASSRUNTFRAME: u1, // bit offset: 6 desc: When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out. - PASSRXFILTER: u1, // bit offset: 7 desc: When set to 1 , disables receive filtering i.e. all frames received are written to memory. - TXFLOWCONTROL: u1, // bit offset: 8 desc: Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex. - RMII: u1, // bit offset: 9 desc: When set to 1 , RMII mode is selected; if 0, MII mode is selected. - FULLDUPLEX: u1, // bit offset: 10 desc: When set to 1 , indicates full duplex operation. - // RESERVED: u21, // bit offset: 11 desc: Unused - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 260 Status register. - pub const STATUS = mmio(Address + 0x00000104, 32, packed struct { - RXSTATUS: u1, // bit offset: 0 desc: If 1, the receive channel is active. If 0, the receive channel is inactive. - TXSTATUS: u1, // bit offset: 1 desc: If 1, the transmit channel is active. If 0, the transmit channel is inactive. - // RESERVED: u30, // bit offset: 2 desc: Unused - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 264 Receive descriptor base address register. - pub const RXDESCRIPTOR = mmio(Address + 0x00000108, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Fixed to 00 - reserved2: u1 = 0, - reserved1: u1 = 0, - RXDESCRIPTOR: u30, // bit offset: 2 desc: MSBs of receive descriptor base address. - }); - // byte offset: 268 Receive status base address register. - pub const RXSTATUS = mmio(Address + 0x0000010c, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: Fixed to 000 - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RXSTATUS: u29, // bit offset: 3 desc: MSBs of receive status base address. - }); - // byte offset: 272 Receive number of descriptors register. - pub const RXDESCRIPTORNUMBER = mmio(Address + 0x00000110, 32, packed struct { - RXDESCRIPTORN: u16, // bit offset: 0 desc: RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 276 Receive produce index register. - pub const RXPRODUCEINDEX = mmio(Address + 0x00000114, 32, packed struct { - RXPRODUCEIX: u16, // bit offset: 0 desc: Index of the descriptor that is going to be filled next by the receive datapath. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 280 Receive consume index register. - pub const RXCONSUMEINDEX = mmio(Address + 0x00000118, 32, packed struct { - RXCONSUMEIX: u16, // bit offset: 0 desc: Index of the descriptor that is going to be processed next by the receive - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 284 Transmit descriptor base address register. - pub const TXDESCRIPTOR = mmio(Address + 0x0000011c, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Fixed to 00 - reserved2: u1 = 0, - reserved1: u1 = 0, - TXD: u30, // bit offset: 2 desc: TxDescriptor. MSBs of transmit descriptor base address. - }); - // byte offset: 288 Transmit status base address register. - pub const TXSTATUS = mmio(Address + 0x00000120, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Fixed to 00 - reserved2: u1 = 0, - reserved1: u1 = 0, - TXSTAT: u30, // bit offset: 2 desc: TxStatus. MSBs of transmit status base address. - }); - // byte offset: 292 Transmit number of descriptors register. - pub const TXDESCRIPTORNUMBER = mmio(Address + 0x00000124, 32, packed struct { - TXDN: u16, // bit offset: 0 desc: TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 296 Transmit produce index register. - pub const TXPRODUCEINDEX = mmio(Address + 0x00000128, 32, packed struct { - TXPI: u16, // bit offset: 0 desc: TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 300 Transmit consume index register. - pub const TXCONSUMEINDEX = mmio(Address + 0x0000012c, 32, packed struct { - TXCI: u16, // bit offset: 0 desc: TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 344 Transmit status vector 0 register. - pub const TSV0 = mmio(Address + 0x00000158, 32, packed struct { - CRCERR: u1, // bit offset: 0 desc: CRC error. The attached CRC in the packet did not match the internally generated CRC. - LCE: u1, // bit offset: 1 desc: Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. - LOR: u1, // bit offset: 2 desc: Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. - DONE: u1, // bit offset: 3 desc: Transmission of packet was completed. - MULTICAST: u1, // bit offset: 4 desc: Packet's destination was a multicast address. - BROADCAST: u1, // bit offset: 5 desc: Packet's destination was a broadcast address. - PACKETDEFER: u1, // bit offset: 6 desc: Packet was deferred for at least one attempt, but less than an excessive defer. - EXDF: u1, // bit offset: 7 desc: Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode. - EXCOL: u1, // bit offset: 8 desc: Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions. - LCOL: u1, // bit offset: 9 desc: Late Collision. Collision occurred beyond collision window, 512 bit times. - GIANT: u1, // bit offset: 10 desc: Byte count in frame was greater than can be represented in the transmit byte count field in TSV1. - UNDERRUN: u1, // bit offset: 11 desc: Host side caused buffer underrun. - TOTALBYTES: u16, // bit offset: 12 desc: The total number of bytes transferred including collided attempts. - CONTROLFRAME: u1, // bit offset: 28 desc: The frame was a control frame. - PAUSE: u1, // bit offset: 29 desc: The frame was a control frame with a valid PAUSE opcode. - BACKPRESSURE: u1, // bit offset: 30 desc: Carrier-sense method backpressure was previously applied. - VLAN: u1, // bit offset: 31 desc: Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. - }); - // byte offset: 348 Transmit status vector 1 register. - pub const TSV1 = mmio(Address + 0x0000015c, 32, packed struct { - TBC: u16, // bit offset: 0 desc: Transmit byte count. The total number of bytes in the frame, not counting the collided bytes. - TCC: u4, // bit offset: 16 desc: Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented. - // RESERVED: u12, // bit offset: 20 desc: Unused - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 352 Receive status vector register. - pub const RSV = mmio(Address + 0x00000160, 32, packed struct { - RBC: u16, // bit offset: 0 desc: Received byte count. Indicates length of received frame. - PPI: u1, // bit offset: 16 desc: Packet previously ignored. Indicates that a packet was dropped. - RXDVSEEN: u1, // bit offset: 17 desc: RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet. - CESEEN: u1, // bit offset: 18 desc: Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected. - RCV: u1, // bit offset: 19 desc: Receive code violation. Indicates that received PHY data does not represent a valid receive code. - CRCERR: u1, // bit offset: 20 desc: CRC error. The attached CRC in the packet did not match the internally generated CRC. - LCERR: u1, // bit offset: 21 desc: Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. - LOR: u1, // bit offset: 22 desc: Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. - ROK: u1, // bit offset: 23 desc: Receive OK. The packet had valid CRC and no symbol errors. - MULTICAST: u1, // bit offset: 24 desc: The packet destination was a multicast address. - BROADCAST: u1, // bit offset: 25 desc: The packet destination was a broadcast address. - DRIBBLENIBBLE: u1, // bit offset: 26 desc: Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out. - CONTROLFRAME: u1, // bit offset: 27 desc: The frame was a control frame. - PAUSE: u1, // bit offset: 28 desc: The frame was a control frame with a valid PAUSE opcode. - UO: u1, // bit offset: 29 desc: Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode. - VLAN: u1, // bit offset: 30 desc: Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. - // RESERVED: u1, // bit offset: 31 desc: Unused - padding1: u1 = 0, - }); - // byte offset: 368 Flow control counter register. - pub const FLOWCONTROLCOUNTER = mmio(Address + 0x00000170, 32, packed struct { - MC: u16, // bit offset: 0 desc: MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame. - PT: u16, // bit offset: 16 desc: PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles. - }); - // byte offset: 372 Flow control status register. - pub const FLOWCONTROLSTATUS = mmio(Address + 0x00000174, 32, packed struct { - MCC: u16, // bit offset: 0 desc: MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 512 Receive filter control register. - pub const RXFILTERCTRL = mmio(Address + 0x00000200, 32, packed struct { - AUE: u1, // bit offset: 0 desc: AcceptUnicastEn. When set to 1, all unicast frames are accepted. - ABE: u1, // bit offset: 1 desc: AcceptBroadcastEn. When set to 1, all broadcast frames are accepted. - AME: u1, // bit offset: 2 desc: AcceptMulticastEn. When set to 1, all multicast frames are accepted. - AUHE: u1, // bit offset: 3 desc: AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted. - AMHE: u1, // bit offset: 4 desc: AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted. - APE: u1, // bit offset: 5 desc: AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted. - // RESERVED: u6, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - MPEW: u1, // bit offset: 12 desc: MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match. - RFEW: u1, // bit offset: 13 desc: RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match. - // RESERVED: u18, // bit offset: 14 desc: Unused - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 516 Receive filter WoL status register. - pub const RXFILTERWOLSTATUS = mmio(Address + 0x00000204, 32, packed struct { - AUW: u1, // bit offset: 0 desc: AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL. - ABW: u1, // bit offset: 1 desc: AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL. - AMW: u1, // bit offset: 2 desc: AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL. - AUHW: u1, // bit offset: 3 desc: AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL. - AMHW: u1, // bit offset: 4 desc: AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL. - APW: u1, // bit offset: 5 desc: AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL. - // RESERVED: u1, // bit offset: 6 desc: Unused - reserved1: u1 = 0, - RFW: u1, // bit offset: 7 desc: RxFilterWoL. When the value is 1, the receive filter caused WoL. - MPW: u1, // bit offset: 8 desc: MagicPacketWoL. When the value is 1, the magic packet filter caused WoL. - // RESERVED: u23, // bit offset: 9 desc: Unused - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 520 Receive filter WoL clear register. - pub const RXFILTERWOLCLEAR = mmio(Address + 0x00000208, 32, packed struct { - AUWCLR: u1, // bit offset: 0 desc: AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - ABWCLR: u1, // bit offset: 1 desc: AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - AMWCLR: u1, // bit offset: 2 desc: AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - AUHWCLR: u1, // bit offset: 3 desc: AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - AMHWCLR: u1, // bit offset: 4 desc: AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - APWCLR: u1, // bit offset: 5 desc: AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - // RESERVED: u1, // bit offset: 6 desc: Unused - reserved1: u1 = 0, - RFWCLR: u1, // bit offset: 7 desc: RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - MPWCLR: u1, // bit offset: 8 desc: MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - // RESERVED: u23, // bit offset: 9 desc: Unused - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 528 Hash filter table LSBs register. - pub const HASHFILTERL = mmio(Address + 0x00000210, 32, packed struct { - HFL: u32, // bit offset: 0 desc: HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering. - }); - // byte offset: 532 Hash filter table MSBs register. - pub const HASHFILTERH = mmio(Address + 0x00000214, 32, packed struct { - HFH: u32, // bit offset: 0 desc: Bits 63:32 of the imperfect filter hash table for receive filtering. - }); - // byte offset: 4064 Interrupt status register. - pub const INTSTATUS = mmio(Address + 0x00000fe0, 32, packed struct { - RXOVERRUNINT: u1, // bit offset: 0 desc: Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error. - RXERRORINT: u1, // bit offset: 1 desc: Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun. - RXFINISHEDINT: u1, // bit offset: 2 desc: Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - RXDONEINT: u1, // bit offset: 3 desc: Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. - TXUNDERRUNINT: u1, // bit offset: 4 desc: Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error. - TXERRORINT: u1, // bit offset: 5 desc: Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun. - TXFINISHEDINT: u1, // bit offset: 6 desc: Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - TXDONEINT: u1, // bit offset: 7 desc: Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. - // RESERVED: u4, // bit offset: 8 desc: Unused - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SOFTINT: u1, // bit offset: 12 desc: Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register. - WAKEUPINT: u1, // bit offset: 13 desc: Interrupt triggered by a Wake-up event detected by the receive filter. - // RESERVED: u18, // bit offset: 14 desc: Unused - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4068 Interrupt enable register. - pub const INTENABLE = mmio(Address + 0x00000fe4, 32, packed struct { - RXOVERRUNINTEN: u1, // bit offset: 0 desc: Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations. - RXERRORINTEN: u1, // bit offset: 1 desc: Enable for interrupt trigger on receive errors. - RXFINISHEDINTEN: u1, // bit offset: 2 desc: Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - RXDONEINTEN: u1, // bit offset: 3 desc: Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. - TXUNDERRUNINTEN: u1, // bit offset: 4 desc: Enable for interrupt trigger on transmit buffer or descriptor underrun situations. - TXERRORINTEN: u1, // bit offset: 5 desc: Enable for interrupt trigger on transmit errors. - TXFINISHEDINTEN: u1, // bit offset: 6 desc: Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - TXDONEINTEN: u1, // bit offset: 7 desc: Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. - // RESERVED: u4, // bit offset: 8 desc: Unused - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SOFTINTEN: u1, // bit offset: 12 desc: Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register. - WAKEUPINTEN: u1, // bit offset: 13 desc: Enable for interrupt triggered by a Wake-up event detected by the receive filter. - // RESERVED: u18, // bit offset: 14 desc: Unused - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4072 Interrupt clear register. - pub const INTCLEAR = mmio(Address + 0x00000fe8, 32, packed struct { - RXOVERRUNINTCLR: u1, // bit offset: 0 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - RXERRORINTCLR: u1, // bit offset: 1 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - RXFINISHEDINTCLR: u1, // bit offset: 2 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - RXDONEINTCLR: u1, // bit offset: 3 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXUNDERRUNINTCLR: u1, // bit offset: 4 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXERRORINTCLR: u1, // bit offset: 5 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXFINISHEDINTCLR: u1, // bit offset: 6 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXDONEINTCLR: u1, // bit offset: 7 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - // RESERVED: u4, // bit offset: 8 desc: Unused - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SOFTINTCLR: u1, // bit offset: 12 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - WAKEUPINTCLR: u1, // bit offset: 13 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - // RESERVED: u18, // bit offset: 14 desc: Unused - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4076 Interrupt set register. - pub const INTSET = mmio(Address + 0x00000fec, 32, packed struct { - RXOVERRUNINTSET: u1, // bit offset: 0 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - RXERRORINTSET: u1, // bit offset: 1 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - RXFINISHEDINTSET: u1, // bit offset: 2 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - RXDONEINTSET: u1, // bit offset: 3 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXUNDERRUNINTSET: u1, // bit offset: 4 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXERRORINTSET: u1, // bit offset: 5 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXFINISHEDINTSET: u1, // bit offset: 6 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXDONEINTSET: u1, // bit offset: 7 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - // RESERVED: u4, // bit offset: 8 desc: Unused - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SOFTINTSET: u1, // bit offset: 12 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - WAKEUPINTSET: u1, // bit offset: 13 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - // RESERVED: u18, // bit offset: 14 desc: Unused - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4084 Power-down register. - pub const POWERDOWN = mmio(Address + 0x00000ff4, 32, packed struct { - // RESERVED: u31, // bit offset: 0 desc: Unused - reserved31: u1 = 0, - reserved30: u1 = 0, - reserved29: u1 = 0, - reserved28: u1 = 0, - reserved27: u1 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - PD: u1, // bit offset: 31 desc: PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register. - }); -}; -pub const GPDMA = extern struct { - pub const Address: u32 = 0x50004000; - // byte offset: 0 DMA Interrupt Status Register - pub const INTSTAT = mmio(Address + 0x00000000, 32, packed struct { - INTSTAT0: u1, // bit offset: 0 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT1: u1, // bit offset: 1 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT2: u1, // bit offset: 2 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT3: u1, // bit offset: 3 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT4: u1, // bit offset: 4 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT5: u1, // bit offset: 5 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT6: u1, // bit offset: 6 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT7: u1, // bit offset: 7 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DMA Interrupt Terminal Count Request Status Register - pub const INTTCSTAT = mmio(Address + 0x00000004, 32, packed struct { - INTTCSTAT0: u1, // bit offset: 0 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT1: u1, // bit offset: 1 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT2: u1, // bit offset: 2 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT3: u1, // bit offset: 3 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT4: u1, // bit offset: 4 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT5: u1, // bit offset: 5 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT6: u1, // bit offset: 6 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT7: u1, // bit offset: 7 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DMA Interrupt Terminal Count Request Clear Register - pub const INTTCCLEAR = mmio(Address + 0x00000008, 32, packed struct { - INTTCCLEAR0: u1, // bit offset: 0 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR1: u1, // bit offset: 1 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR2: u1, // bit offset: 2 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR3: u1, // bit offset: 3 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR4: u1, // bit offset: 4 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR5: u1, // bit offset: 5 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR6: u1, // bit offset: 6 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR7: u1, // bit offset: 7 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 DMA Interrupt Error Status Register - pub const INTERRSTAT = mmio(Address + 0x0000000c, 32, packed struct { - INTERRSTAT0: u1, // bit offset: 0 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT1: u1, // bit offset: 1 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT2: u1, // bit offset: 2 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT3: u1, // bit offset: 3 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT4: u1, // bit offset: 4 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT5: u1, // bit offset: 5 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT6: u1, // bit offset: 6 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT7: u1, // bit offset: 7 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 DMA Interrupt Error Clear Register - pub const INTERRCLR = mmio(Address + 0x00000010, 32, packed struct { - INTERRCLR0: u1, // bit offset: 0 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR1: u1, // bit offset: 1 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR2: u1, // bit offset: 2 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR3: u1, // bit offset: 3 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR4: u1, // bit offset: 4 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR5: u1, // bit offset: 5 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR6: u1, // bit offset: 6 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR7: u1, // bit offset: 7 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 DMA Raw Interrupt Terminal Count Status Register - pub const RAWINTTCSTAT = mmio(Address + 0x00000014, 32, packed struct { - RAWINTTCSTAT0: u1, // bit offset: 0 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT1: u1, // bit offset: 1 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT2: u1, // bit offset: 2 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT3: u1, // bit offset: 3 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT4: u1, // bit offset: 4 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT5: u1, // bit offset: 5 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT6: u1, // bit offset: 6 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT7: u1, // bit offset: 7 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 DMA Raw Error Interrupt Status Register - pub const RAWINTERRSTAT = mmio(Address + 0x00000018, 32, packed struct { - RAWINTERRSTAT0: u1, // bit offset: 0 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT1: u1, // bit offset: 1 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT2: u1, // bit offset: 2 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT3: u1, // bit offset: 3 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT4: u1, // bit offset: 4 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT5: u1, // bit offset: 5 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT6: u1, // bit offset: 6 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT7: u1, // bit offset: 7 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 DMA Enabled Channel Register - pub const ENBLDCHNS = mmio(Address + 0x0000001c, 32, packed struct { - ENABLEDCHANNELS0: u1, // bit offset: 0 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS1: u1, // bit offset: 1 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS2: u1, // bit offset: 2 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS3: u1, // bit offset: 3 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS4: u1, // bit offset: 4 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS5: u1, // bit offset: 5 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS6: u1, // bit offset: 6 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS7: u1, // bit offset: 7 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 DMA Software Burst Request Register - pub const SOFTBREQ = mmio(Address + 0x00000020, 32, packed struct { - SOFTBREQ0: u1, // bit offset: 0 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ1: u1, // bit offset: 1 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ2: u1, // bit offset: 2 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ3: u1, // bit offset: 3 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ4: u1, // bit offset: 4 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ5: u1, // bit offset: 5 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ6: u1, // bit offset: 6 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ7: u1, // bit offset: 7 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ8: u1, // bit offset: 8 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ9: u1, // bit offset: 9 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ10: u1, // bit offset: 10 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ11: u1, // bit offset: 11 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ12: u1, // bit offset: 12 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ13: u1, // bit offset: 13 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ14: u1, // bit offset: 14 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ15: u1, // bit offset: 15 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 DMA Software Single Request Register - pub const SOFTSREQ = mmio(Address + 0x00000024, 32, packed struct { - SOFTSREQ0: u1, // bit offset: 0 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ1: u1, // bit offset: 1 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ2: u1, // bit offset: 2 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ3: u1, // bit offset: 3 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ4: u1, // bit offset: 4 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ5: u1, // bit offset: 5 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ6: u1, // bit offset: 6 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ7: u1, // bit offset: 7 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ8: u1, // bit offset: 8 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ9: u1, // bit offset: 9 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ10: u1, // bit offset: 10 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ11: u1, // bit offset: 11 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ12: u1, // bit offset: 12 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ13: u1, // bit offset: 13 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ14: u1, // bit offset: 14 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ15: u1, // bit offset: 15 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read undefined. Write reserved bits as zero. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 DMA Software Last Burst Request Register - pub const SOFTLBREQ = mmio(Address + 0x00000028, 32, packed struct { - SOFTLBREQ0: u1, // bit offset: 0 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ1: u1, // bit offset: 1 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ2: u1, // bit offset: 2 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ3: u1, // bit offset: 3 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ4: u1, // bit offset: 4 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ5: u1, // bit offset: 5 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ6: u1, // bit offset: 6 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ7: u1, // bit offset: 7 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ8: u1, // bit offset: 8 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ9: u1, // bit offset: 9 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ10: u1, // bit offset: 10 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ11: u1, // bit offset: 11 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ12: u1, // bit offset: 12 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ13: u1, // bit offset: 13 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ14: u1, // bit offset: 14 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ15: u1, // bit offset: 15 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 DMA Software Last Single Request Register - pub const SOFTLSREQ = mmio(Address + 0x0000002c, 32, packed struct { - SOFTLSREQ0: u1, // bit offset: 0 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ1: u1, // bit offset: 1 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ2: u1, // bit offset: 2 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ3: u1, // bit offset: 3 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ4: u1, // bit offset: 4 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ5: u1, // bit offset: 5 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ6: u1, // bit offset: 6 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ7: u1, // bit offset: 7 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ8: u1, // bit offset: 8 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ9: u1, // bit offset: 9 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ10: u1, // bit offset: 10 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ11: u1, // bit offset: 11 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ12: u1, // bit offset: 12 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ13: u1, // bit offset: 13 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ14: u1, // bit offset: 14 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ15: u1, // bit offset: 15 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 DMA Configuration Register - pub const CONFIG = mmio(Address + 0x00000030, 32, packed struct { - E: u1, // bit offset: 0 desc: DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled. - M: u1, // bit offset: 1 desc: AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode. - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 DMA Synchronization Register - pub const SYNC = mmio(Address + 0x00000034, 32, packed struct { - DMACSYNC0: u1, // bit offset: 0 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC1: u1, // bit offset: 1 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC2: u1, // bit offset: 2 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC3: u1, // bit offset: 3 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC4: u1, // bit offset: 4 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC5: u1, // bit offset: 5 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC6: u1, // bit offset: 6 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC7: u1, // bit offset: 7 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC8: u1, // bit offset: 8 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC9: u1, // bit offset: 9 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC10: u1, // bit offset: 10 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC11: u1, // bit offset: 11 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC12: u1, // bit offset: 12 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC13: u1, // bit offset: 13 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC14: u1, // bit offset: 14 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC15: u1, // bit offset: 15 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 256 DMA Channel 0 Source Address Register - pub const SRCADDR0 = mmio(Address + 0x00000100, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 260 DMA Channel 0 Destination Address Register - pub const DESTADDR0 = mmio(Address + 0x00000104, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 264 DMA Channel 0 Linked List Item Register - pub const LLI0 = mmio(Address + 0x00000108, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 268 DMA Channel 0 Control Register - pub const CONTROL0 = mmio(Address + 0x0000010c, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 272 DMA Channel 0 Configuration Register[1] - pub const CONFIG0 = mmio(Address + 0x00000110, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 288 DMA Channel 0 Source Address Register - pub const SRCADDR1 = mmio(Address + 0x00000120, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 292 DMA Channel 0 Destination Address Register - pub const DESTADDR1 = mmio(Address + 0x00000124, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 296 DMA Channel 0 Linked List Item Register - pub const LLI1 = mmio(Address + 0x00000128, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 300 DMA Channel 0 Control Register - pub const CONTROL1 = mmio(Address + 0x0000012c, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 304 DMA Channel 0 Configuration Register[1] - pub const CONFIG1 = mmio(Address + 0x00000130, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 320 DMA Channel 0 Source Address Register - pub const SRCADDR2 = mmio(Address + 0x00000140, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 324 DMA Channel 0 Destination Address Register - pub const DESTADDR2 = mmio(Address + 0x00000144, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 328 DMA Channel 0 Linked List Item Register - pub const LLI2 = mmio(Address + 0x00000148, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 332 DMA Channel 0 Control Register - pub const CONTROL2 = mmio(Address + 0x0000014c, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 336 DMA Channel 0 Configuration Register[1] - pub const CONFIG2 = mmio(Address + 0x00000150, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 352 DMA Channel 0 Source Address Register - pub const SRCADDR3 = mmio(Address + 0x00000160, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 356 DMA Channel 0 Destination Address Register - pub const DESTADDR3 = mmio(Address + 0x00000164, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 360 DMA Channel 0 Linked List Item Register - pub const LLI3 = mmio(Address + 0x00000168, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 364 DMA Channel 0 Control Register - pub const CONTROL3 = mmio(Address + 0x0000016c, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 368 DMA Channel 0 Configuration Register[1] - pub const CONFIG3 = mmio(Address + 0x00000170, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 384 DMA Channel 0 Source Address Register - pub const SRCADDR4 = mmio(Address + 0x00000180, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 388 DMA Channel 0 Destination Address Register - pub const DESTADDR4 = mmio(Address + 0x00000184, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 392 DMA Channel 0 Linked List Item Register - pub const LLI4 = mmio(Address + 0x00000188, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 396 DMA Channel 0 Control Register - pub const CONTROL4 = mmio(Address + 0x0000018c, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 400 DMA Channel 0 Configuration Register[1] - pub const CONFIG4 = mmio(Address + 0x00000190, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 416 DMA Channel 0 Source Address Register - pub const SRCADDR5 = mmio(Address + 0x000001a0, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 420 DMA Channel 0 Destination Address Register - pub const DESTADDR5 = mmio(Address + 0x000001a4, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 424 DMA Channel 0 Linked List Item Register - pub const LLI5 = mmio(Address + 0x000001a8, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 428 DMA Channel 0 Control Register - pub const CONTROL5 = mmio(Address + 0x000001ac, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 432 DMA Channel 0 Configuration Register[1] - pub const CONFIG5 = mmio(Address + 0x000001b0, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 448 DMA Channel 0 Source Address Register - pub const SRCADDR6 = mmio(Address + 0x000001c0, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 452 DMA Channel 0 Destination Address Register - pub const DESTADDR6 = mmio(Address + 0x000001c4, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 456 DMA Channel 0 Linked List Item Register - pub const LLI6 = mmio(Address + 0x000001c8, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 460 DMA Channel 0 Control Register - pub const CONTROL6 = mmio(Address + 0x000001cc, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 464 DMA Channel 0 Configuration Register[1] - pub const CONFIG6 = mmio(Address + 0x000001d0, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 480 DMA Channel 0 Source Address Register - pub const SRCADDR7 = mmio(Address + 0x000001e0, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 484 DMA Channel 0 Destination Address Register - pub const DESTADDR7 = mmio(Address + 0x000001e4, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 488 DMA Channel 0 Linked List Item Register - pub const LLI7 = mmio(Address + 0x000001e8, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 492 DMA Channel 0 Control Register - pub const CONTROL7 = mmio(Address + 0x000001ec, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 496 DMA Channel 0 Configuration Register[1] - pub const CONFIG7 = mmio(Address + 0x000001f0, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const USB = extern struct { - pub const Address: u32 = 0x50008000; - // byte offset: 220 USB Receive Packet Length - pub const RXPLEN = mmio(Address + 0x000000dc, 32, packed struct { - PKT_LNGTH: u10, // bit offset: 0 desc: The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt. - DV: enum(u1) { // bit offset: 10 desc: Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet. - @"DATA_IS_INVALID_" = 0, // desc: Data is invalid. - @"DATA_IS_VALID_" = 1, // desc: Data is valid. - }, - PKT_RDY: u1, // bit offset: 11 desc: The PKT_LNGTH field is valid and the packet is ready for reading. - // RESERVED: u20, // bit offset: 12 desc: Reserved. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 256 OTG Interrupt Status - pub const INTST = mmio(Address + 0x00000100, 32, packed struct { - TMR: u1, // bit offset: 0 desc: Timer time-out. - REMOVE_PU: u1, // bit offset: 1 desc: Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor. - HNP_FAILURE: u1, // bit offset: 2 desc: HNP failed. This bit is set by hardware to indicate that the HNP switching has failed. - HNP_SUCCESS: u1, // bit offset: 3 desc: HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 260 OTG Interrupt Enable - pub const INTEN = mmio(Address + 0x00000104, 32, packed struct { - TMR_EN: u1, // bit offset: 0 desc: 1 = enable the corresponding bit in the IntSt register. - REMOVE_PU_EN: u1, // bit offset: 1 desc: 1 = enable the corresponding bit in the IntSt register. - HNP_FAILURE_EN: u1, // bit offset: 2 desc: 1 = enable the corresponding bit in the IntSt register. - HNP_SUCCES_EN: u1, // bit offset: 3 desc: 1 = enable the corresponding bit in the IntSt register. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 264 OTG Interrupt Set - pub const INTSET = mmio(Address + 0x00000108, 32, packed struct { - TMR_SET: u1, // bit offset: 0 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. - REMOVE_PU_SET: u1, // bit offset: 1 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. - HNP_FAILURE_SET: u1, // bit offset: 2 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. - HNP_SUCCES_SET: u1, // bit offset: 3 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 268 OTG Interrupt Clear - pub const INTCLR = mmio(Address + 0x0000010c, 32, packed struct { - TMR_CLR: u1, // bit offset: 0 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - REMOVE_PU_CLR: u1, // bit offset: 1 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - HNP_FAILURE_CLR: u1, // bit offset: 2 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - HNP_SUCCES_CLR: u1, // bit offset: 3 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 272 OTG Status and Control and USB port select - pub const STCTRL = mmio(Address + 0x00000110, 32, packed struct { - PORT_FUNC: u2, // bit offset: 0 desc: Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2. - TMR_SCALE: u2, // bit offset: 2 desc: Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved - TMR_MODE: u1, // bit offset: 4 desc: Timer mode selection. 0: monoshot 1: free running - TMR_EN: u1, // bit offset: 5 desc: Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0. - TMR_RST: u1, // bit offset: 6 desc: Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled. - // RESERVED: u1, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - B_HNP_TRACK: u1, // bit offset: 8 desc: Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. - A_HNP_TRACK: u1, // bit offset: 9 desc: Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. - PU_REMOVED: u1, // bit offset: 10 desc: When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. - // RESERVED: u5, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - TMR_CNT: u16, // bit offset: 16 desc: Current timer count value. - }); - // byte offset: 276 OTG Timer - pub const TMR = mmio(Address + 0x00000114, 32, packed struct { - TIMEOUT_CNT: u16, // bit offset: 0 desc: The TMR interrupt is set when TMR_CNT reaches this value. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 512 USB Device Interrupt Status - pub const DEVINTST = mmio(Address + 0x00000200, 32, packed struct { - FRAME: u1, // bit offset: 0 desc: The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. - EP_FAST: u1, // bit offset: 1 desc: Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit. - EP_SLOW: u1, // bit offset: 2 desc: Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit. - DEV_STAT: u1, // bit offset: 3 desc: Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366. - CCEMPTY: u1, // bit offset: 4 desc: The command code register (USBCmdCode) is empty (New command can be written). - CDFULL: u1, // bit offset: 5 desc: Command data register (USBCmdData) is full (Data can be read now). - RxENDPKT: u1, // bit offset: 6 desc: The current packet in the endpoint buffer is transferred to the CPU. - TxENDPKT: u1, // bit offset: 7 desc: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). - EP_RLZED: u1, // bit offset: 8 desc: Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed. - ERR_INT: u1, // bit offset: 9 desc: Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368 - // RESERVED: u22, // bit offset: 10 desc: Reserved. The value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 516 USB Device Interrupt Enable - pub const DEVINTEN = mmio(Address + 0x00000204, 32, packed struct { - FRAMEEN: u1, // bit offset: 0 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_FASTEN: u1, // bit offset: 1 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_SLOWEN: u1, // bit offset: 2 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - DEV_STATEN: u1, // bit offset: 3 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - CCEMPTYEN: u1, // bit offset: 4 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - CDFULLEN: u1, // bit offset: 5 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - RxENDPKTEN: u1, // bit offset: 6 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - TxENDPKTEN: u1, // bit offset: 7 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_RLZEDEN: u1, // bit offset: 8 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - ERR_INTEN: u1, // bit offset: 9 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - // RESERVED: u22, // bit offset: 10 desc: Reserved - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 520 USB Device Interrupt Clear - pub const DEVINTCLR = mmio(Address + 0x00000208, 32, packed struct { - FRAMECLR: u1, // bit offset: 0 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - EP_FASTCLR: u1, // bit offset: 1 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - EP_SLOWCLR: u1, // bit offset: 2 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - DEV_STATCLR: u1, // bit offset: 3 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - CCEMPTYCLR: u1, // bit offset: 4 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - CDFULLCLR: u1, // bit offset: 5 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - RxENDPKTCLR: u1, // bit offset: 6 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - TxENDPKTCLR: u1, // bit offset: 7 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - EP_RLZEDCLR: u1, // bit offset: 8 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - ERR_INTCLR: u1, // bit offset: 9 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - // RESERVED: u22, // bit offset: 10 desc: Reserved - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 524 USB Device Interrupt Set - pub const DEVINTSET = mmio(Address + 0x0000020c, 32, packed struct { - FRAMESET: u1, // bit offset: 0 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - EP_FASTSET: u1, // bit offset: 1 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - EP_SLOWSET: u1, // bit offset: 2 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - DEV_STATSET: u1, // bit offset: 3 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - CCEMPTYSET: u1, // bit offset: 4 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - CDFULLSET: u1, // bit offset: 5 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - RxENDPKTSET: u1, // bit offset: 6 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - TxENDPKTSET: u1, // bit offset: 7 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - EP_RLZEDSET: u1, // bit offset: 8 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - ERR_INTSET: u1, // bit offset: 9 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - // RESERVED: u22, // bit offset: 10 desc: Reserved - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 528 USB Command Code - pub const CMDCODE = mmio(Address + 0x00000210, 32, packed struct { - // RESERVED: u8, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CMD_PHASE: enum(u8) { // bit offset: 8 desc: The command phase: - @"READ" = 2, // desc: Read - @"WRITE" = 1, // desc: Write - @"COMMAND" = 5, // desc: Command - _, // non-exhaustive - }, - CMD_CODE_WDATA: u8, // bit offset: 16 desc: This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA). - // RESERVED: u8, // bit offset: 24 desc: Reserved. Read value is undefined, only zero should be written. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 532 USB Command Data - pub const CMDDATA = mmio(Address + 0x00000214, 32, packed struct { - CMD_RDATA: u8, // bit offset: 0 desc: Command Read Data. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 536 USB Receive Data - pub const RXDATA = mmio(Address + 0x00000218, 32, packed struct { - RX_DATA: u32, // bit offset: 0 desc: Data received. - }); - // byte offset: 540 USB Transmit Data - pub const TXDATA = mmio(Address + 0x0000021c, 32, packed struct { - TX_DATA: u32, // bit offset: 0 desc: Transmit Data. - }); - // byte offset: 548 USB Transmit Packet Length - pub const TXPLEN = mmio(Address + 0x00000224, 32, packed struct { - PKT_LNGTH: u10, // bit offset: 0 desc: The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 552 USB Control - pub const CTRL = mmio(Address + 0x00000228, 32, packed struct { - RD_EN: enum(u1) { // bit offset: 0 desc: Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - WR_EN: enum(u1) { // bit offset: 1 desc: Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - LOG_ENDPOINT: u4, // bit offset: 2 desc: Logical Endpoint number. - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 556 USB Device Interrupt Priority - pub const DEVINTPRI = mmio(Address + 0x0000022c, 32, packed struct { - FRAME: enum(u1) { // bit offset: 0 desc: Frame interrupt routing - @"LP" = 0, // desc: FRAME interrupt is routed to USB_INT_REQ_LP. - @"HP" = 1, // desc: FRAME interrupt is routed to USB_INT_REQ_HP. - }, - EP_FAST: enum(u1) { // bit offset: 1 desc: Fast endpoint interrupt routing - @"LP" = 0, // desc: EP_FAST interrupt is routed to USB_INT_REQ_LP. - @"HP" = 1, // desc: EP_FAST interrupt is routed to USB_INT_REQ_HP. - }, - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 560 USB Endpoint Interrupt Status - pub const EPINTST = mmio(Address + 0x00000230, 32, packed struct { - EPST0: u1, // bit offset: 0 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST1: u1, // bit offset: 1 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST2: u1, // bit offset: 2 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST3: u1, // bit offset: 3 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST4: u1, // bit offset: 4 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST5: u1, // bit offset: 5 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST6: u1, // bit offset: 6 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST7: u1, // bit offset: 7 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST8: u1, // bit offset: 8 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST9: u1, // bit offset: 9 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST10: u1, // bit offset: 10 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST11: u1, // bit offset: 11 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST12: u1, // bit offset: 12 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST13: u1, // bit offset: 13 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST14: u1, // bit offset: 14 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST15: u1, // bit offset: 15 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST16: u1, // bit offset: 16 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST17: u1, // bit offset: 17 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST18: u1, // bit offset: 18 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST19: u1, // bit offset: 19 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST20: u1, // bit offset: 20 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST21: u1, // bit offset: 21 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST22: u1, // bit offset: 22 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST23: u1, // bit offset: 23 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST24: u1, // bit offset: 24 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST25: u1, // bit offset: 25 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST26: u1, // bit offset: 26 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST27: u1, // bit offset: 27 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST28: u1, // bit offset: 28 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST29: u1, // bit offset: 29 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST30: u1, // bit offset: 30 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST31: u1, // bit offset: 31 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - }); - // byte offset: 564 USB Endpoint Interrupt Enable - pub const EPINTEN = mmio(Address + 0x00000234, 32, packed struct { - EPEN0: u1, // bit offset: 0 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN1: u1, // bit offset: 1 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN2: u1, // bit offset: 2 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN3: u1, // bit offset: 3 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN4: u1, // bit offset: 4 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN5: u1, // bit offset: 5 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN6: u1, // bit offset: 6 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN7: u1, // bit offset: 7 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN8: u1, // bit offset: 8 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN9: u1, // bit offset: 9 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN10: u1, // bit offset: 10 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN11: u1, // bit offset: 11 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN12: u1, // bit offset: 12 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN13: u1, // bit offset: 13 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN14: u1, // bit offset: 14 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN15: u1, // bit offset: 15 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN16: u1, // bit offset: 16 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN17: u1, // bit offset: 17 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN18: u1, // bit offset: 18 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN19: u1, // bit offset: 19 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN20: u1, // bit offset: 20 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN21: u1, // bit offset: 21 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN22: u1, // bit offset: 22 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN23: u1, // bit offset: 23 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN24: u1, // bit offset: 24 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN25: u1, // bit offset: 25 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN26: u1, // bit offset: 26 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN27: u1, // bit offset: 27 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN28: u1, // bit offset: 28 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN29: u1, // bit offset: 29 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN30: u1, // bit offset: 30 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN31: u1, // bit offset: 31 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - }); - // byte offset: 568 USB Endpoint Interrupt Clear - pub const EPINTCLR = mmio(Address + 0x00000238, 32, packed struct { - EPCLR0: u1, // bit offset: 0 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR1: u1, // bit offset: 1 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR2: u1, // bit offset: 2 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR3: u1, // bit offset: 3 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR4: u1, // bit offset: 4 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR5: u1, // bit offset: 5 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR6: u1, // bit offset: 6 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR7: u1, // bit offset: 7 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR8: u1, // bit offset: 8 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR9: u1, // bit offset: 9 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR10: u1, // bit offset: 10 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR11: u1, // bit offset: 11 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR12: u1, // bit offset: 12 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR13: u1, // bit offset: 13 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR14: u1, // bit offset: 14 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR15: u1, // bit offset: 15 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR16: u1, // bit offset: 16 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR17: u1, // bit offset: 17 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR18: u1, // bit offset: 18 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR19: u1, // bit offset: 19 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR20: u1, // bit offset: 20 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR21: u1, // bit offset: 21 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR22: u1, // bit offset: 22 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR23: u1, // bit offset: 23 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR24: u1, // bit offset: 24 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR25: u1, // bit offset: 25 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR26: u1, // bit offset: 26 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR27: u1, // bit offset: 27 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR28: u1, // bit offset: 28 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR29: u1, // bit offset: 29 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR30: u1, // bit offset: 30 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR31: u1, // bit offset: 31 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - }); - // byte offset: 572 USB Endpoint Interrupt Set - pub const EPINTSET = mmio(Address + 0x0000023c, 32, packed struct { - EPSET0: u1, // bit offset: 0 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET1: u1, // bit offset: 1 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET2: u1, // bit offset: 2 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET3: u1, // bit offset: 3 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET4: u1, // bit offset: 4 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET5: u1, // bit offset: 5 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET6: u1, // bit offset: 6 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET7: u1, // bit offset: 7 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET8: u1, // bit offset: 8 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET9: u1, // bit offset: 9 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET10: u1, // bit offset: 10 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET11: u1, // bit offset: 11 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET12: u1, // bit offset: 12 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET13: u1, // bit offset: 13 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET14: u1, // bit offset: 14 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET15: u1, // bit offset: 15 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET16: u1, // bit offset: 16 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET17: u1, // bit offset: 17 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET18: u1, // bit offset: 18 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET19: u1, // bit offset: 19 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET20: u1, // bit offset: 20 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET21: u1, // bit offset: 21 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET22: u1, // bit offset: 22 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET23: u1, // bit offset: 23 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET24: u1, // bit offset: 24 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET25: u1, // bit offset: 25 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET26: u1, // bit offset: 26 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET27: u1, // bit offset: 27 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET28: u1, // bit offset: 28 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET29: u1, // bit offset: 29 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET30: u1, // bit offset: 30 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET31: u1, // bit offset: 31 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - }); - // byte offset: 576 USB Endpoint Priority - pub const EPINTPRI = mmio(Address + 0x00000240, 32, packed struct { - EPPRI0: u1, // bit offset: 0 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI1: u1, // bit offset: 1 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI2: u1, // bit offset: 2 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI3: u1, // bit offset: 3 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI4: u1, // bit offset: 4 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI5: u1, // bit offset: 5 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI6: u1, // bit offset: 6 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI7: u1, // bit offset: 7 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI8: u1, // bit offset: 8 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI9: u1, // bit offset: 9 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI10: u1, // bit offset: 10 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI11: u1, // bit offset: 11 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI12: u1, // bit offset: 12 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI13: u1, // bit offset: 13 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI14: u1, // bit offset: 14 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI15: u1, // bit offset: 15 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI16: u1, // bit offset: 16 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI17: u1, // bit offset: 17 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI18: u1, // bit offset: 18 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI19: u1, // bit offset: 19 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI20: u1, // bit offset: 20 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI21: u1, // bit offset: 21 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI22: u1, // bit offset: 22 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI23: u1, // bit offset: 23 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI24: u1, // bit offset: 24 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI25: u1, // bit offset: 25 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI26: u1, // bit offset: 26 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI27: u1, // bit offset: 27 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI28: u1, // bit offset: 28 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI29: u1, // bit offset: 29 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI30: u1, // bit offset: 30 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI31: u1, // bit offset: 31 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - }); - // byte offset: 580 USB Realize Endpoint - pub const REEP = mmio(Address + 0x00000244, 32, packed struct { - EPR0: u1, // bit offset: 0 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR1: u1, // bit offset: 1 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR2: u1, // bit offset: 2 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR3: u1, // bit offset: 3 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR4: u1, // bit offset: 4 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR5: u1, // bit offset: 5 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR6: u1, // bit offset: 6 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR7: u1, // bit offset: 7 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR8: u1, // bit offset: 8 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR9: u1, // bit offset: 9 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR10: u1, // bit offset: 10 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR11: u1, // bit offset: 11 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR12: u1, // bit offset: 12 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR13: u1, // bit offset: 13 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR14: u1, // bit offset: 14 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR15: u1, // bit offset: 15 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR16: u1, // bit offset: 16 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR17: u1, // bit offset: 17 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR18: u1, // bit offset: 18 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR19: u1, // bit offset: 19 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR20: u1, // bit offset: 20 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR21: u1, // bit offset: 21 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR22: u1, // bit offset: 22 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR23: u1, // bit offset: 23 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR24: u1, // bit offset: 24 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR25: u1, // bit offset: 25 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR26: u1, // bit offset: 26 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR27: u1, // bit offset: 27 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR28: u1, // bit offset: 28 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR29: u1, // bit offset: 29 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR30: u1, // bit offset: 30 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR31: u1, // bit offset: 31 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - }); - // byte offset: 584 USB Endpoint Index - pub const EPIND = mmio(Address + 0x00000248, 32, packed struct { - PHY_EP: u5, // bit offset: 0 desc: Physical endpoint number (0-31) - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 588 USB MaxPacketSize - pub const MAXPSIZE = mmio(Address + 0x0000024c, 32, packed struct { - MPS: u10, // bit offset: 0 desc: The maximum packet size value. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 592 USB DMA Request Status - pub const DMARST = mmio(Address + 0x00000250, 32, packed struct { - EPRST0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0). - EPRST1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0). - EPRST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - }); - // byte offset: 596 USB DMA Request Clear - pub const DMARCLR = mmio(Address + 0x00000254, 32, packed struct { - EPRCLR0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). - EPRCLR1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). - EPRCLR2: u1, // bit offset: 2 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR3: u1, // bit offset: 3 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR4: u1, // bit offset: 4 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR5: u1, // bit offset: 5 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR6: u1, // bit offset: 6 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR7: u1, // bit offset: 7 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR8: u1, // bit offset: 8 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR9: u1, // bit offset: 9 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR10: u1, // bit offset: 10 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR11: u1, // bit offset: 11 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR12: u1, // bit offset: 12 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR13: u1, // bit offset: 13 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR14: u1, // bit offset: 14 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR15: u1, // bit offset: 15 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR16: u1, // bit offset: 16 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR17: u1, // bit offset: 17 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR18: u1, // bit offset: 18 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR19: u1, // bit offset: 19 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR20: u1, // bit offset: 20 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR21: u1, // bit offset: 21 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR22: u1, // bit offset: 22 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR23: u1, // bit offset: 23 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR24: u1, // bit offset: 24 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR25: u1, // bit offset: 25 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR26: u1, // bit offset: 26 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR27: u1, // bit offset: 27 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR28: u1, // bit offset: 28 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR29: u1, // bit offset: 29 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR30: u1, // bit offset: 30 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR31: u1, // bit offset: 31 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - }); - // byte offset: 600 USB DMA Request Set - pub const DMARSET = mmio(Address + 0x00000258, 32, packed struct { - EPRSET0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). - EPRSET1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). - EPRSET2: u1, // bit offset: 2 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET3: u1, // bit offset: 3 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET4: u1, // bit offset: 4 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET5: u1, // bit offset: 5 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET6: u1, // bit offset: 6 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET7: u1, // bit offset: 7 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET8: u1, // bit offset: 8 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET9: u1, // bit offset: 9 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET10: u1, // bit offset: 10 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET11: u1, // bit offset: 11 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET12: u1, // bit offset: 12 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET13: u1, // bit offset: 13 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET14: u1, // bit offset: 14 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET15: u1, // bit offset: 15 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET16: u1, // bit offset: 16 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET17: u1, // bit offset: 17 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET18: u1, // bit offset: 18 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET19: u1, // bit offset: 19 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET20: u1, // bit offset: 20 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET21: u1, // bit offset: 21 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET22: u1, // bit offset: 22 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET23: u1, // bit offset: 23 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET24: u1, // bit offset: 24 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET25: u1, // bit offset: 25 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET26: u1, // bit offset: 26 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET27: u1, // bit offset: 27 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET28: u1, // bit offset: 28 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET29: u1, // bit offset: 29 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET30: u1, // bit offset: 30 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET31: u1, // bit offset: 31 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - }); - // byte offset: 640 USB UDCA Head - pub const UDCAH = mmio(Address + 0x00000280, 32, packed struct { - // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - UDCA_ADDR: u25, // bit offset: 7 desc: Start address of the UDCA. - }); - // byte offset: 644 USB Endpoint DMA Status - pub const EPDMAST = mmio(Address + 0x00000284, 32, packed struct { - EP_DMA_ST0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0). - EP_DMA_ST1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). - EP_DMA_ST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - }); - // byte offset: 648 USB Endpoint DMA Enable - pub const EPDMAEN = mmio(Address + 0x00000288, 32, packed struct { - EP_DMA_EN0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0). - EP_DMA_EN1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). - EP_DMA_EN: u30, // bit offset: 2 desc: Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx. - }); - // byte offset: 652 USB Endpoint DMA Disable - pub const EPDMADIS = mmio(Address + 0x0000028c, 32, packed struct { - EP_DMA_DIS0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0). - EP_DMA_DIS1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0). - EP_DMA_DIS2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - }); - // byte offset: 656 USB DMA Interrupt Status - pub const DMAINTST = mmio(Address + 0x00000290, 32, packed struct { - EOT: enum(u1) { // bit offset: 0 desc: End of Transfer Interrupt bit. - @"ALL_BITS_IN_THE_USBE" = 0, // desc: All bits in the USBEoTIntSt register are 0. - @"AT_LEAST_ONE_BIT_IN_" = 1, // desc: At least one bit in the USBEoTIntSt is set. - }, - NDDR: enum(u1) { // bit offset: 1 desc: New DD Request Interrupt bit. - @"ALL_BITS_IN_THE_USBN" = 0, // desc: All bits in the USBNDDRIntSt register are 0. - @"AT_LEAST_ONE_BIT_IN_" = 1, // desc: At least one bit in the USBNDDRIntSt is set. - }, - ERR: enum(u1) { // bit offset: 2 desc: System Error Interrupt bit. - @"ALL_BITS_IN_THE_USBS" = 0, // desc: All bits in the USBSysErrIntSt register are 0. - @"AT_LEAST_ONE_BIT_IN_" = 1, // desc: At least one bit in the USBSysErrIntSt is set. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from a reserved bit is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 660 USB DMA Interrupt Enable - pub const DMAINTEN = mmio(Address + 0x00000294, 32, packed struct { - EOT: enum(u1) { // bit offset: 0 desc: End of Transfer Interrupt enable bit. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - NDDR: enum(u1) { // bit offset: 1 desc: New DD Request Interrupt enable bit. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - ERR: enum(u1) { // bit offset: 2 desc: System Error Interrupt enable bit. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 672 USB End of Transfer Interrupt Status - pub const EOTINTST = mmio(Address + 0x000002a0, 32, packed struct { - EPTXINTST0: u1, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST1: u1, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - }); - // byte offset: 676 USB End of Transfer Interrupt Clear - pub const EOTINTCLR = mmio(Address + 0x000002a4, 32, packed struct { - EPTXINTCLR0: u1, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR1: u1, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR2: u1, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR3: u1, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR4: u1, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR5: u1, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR6: u1, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR7: u1, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR8: u1, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR9: u1, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR10: u1, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR11: u1, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR12: u1, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR13: u1, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR14: u1, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR15: u1, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR16: u1, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR17: u1, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR18: u1, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR19: u1, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR20: u1, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR21: u1, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR22: u1, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR23: u1, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR24: u1, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR25: u1, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR26: u1, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR27: u1, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR28: u1, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR29: u1, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR30: u1, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR31: u1, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - }); - // byte offset: 680 USB End of Transfer Interrupt Set - pub const EOTINTSET = mmio(Address + 0x000002a8, 32, packed struct { - EPTXINTSET0: u1, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET1: u1, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET2: u1, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET3: u1, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET4: u1, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET5: u1, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET6: u1, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET7: u1, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET8: u1, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET9: u1, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET10: u1, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET11: u1, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET12: u1, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET13: u1, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET14: u1, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET15: u1, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET16: u1, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET17: u1, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET18: u1, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET19: u1, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET20: u1, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET21: u1, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET22: u1, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET23: u1, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET24: u1, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET25: u1, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET26: u1, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET27: u1, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET28: u1, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET29: u1, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET30: u1, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET31: u1, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - }); - // byte offset: 684 USB New DD Request Interrupt Status - pub const NDDRINTST = mmio(Address + 0x000002ac, 32, packed struct { - EPNDDINTST0: u1, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST1: u1, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - }); - // byte offset: 688 USB New DD Request Interrupt Clear - pub const NDDRINTCLR = mmio(Address + 0x000002b0, 32, packed struct { - EPNDDINTCLR0: u1, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR1: u1, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR2: u1, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR3: u1, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR4: u1, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR5: u1, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR6: u1, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR7: u1, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR8: u1, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR9: u1, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR10: u1, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR11: u1, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR12: u1, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR13: u1, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR14: u1, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR15: u1, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR16: u1, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR17: u1, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR18: u1, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR19: u1, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR20: u1, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR21: u1, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR22: u1, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR23: u1, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR24: u1, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR25: u1, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR26: u1, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR27: u1, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR28: u1, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR29: u1, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR30: u1, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR31: u1, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - }); - // byte offset: 692 USB New DD Request Interrupt Set - pub const NDDRINTSET = mmio(Address + 0x000002b4, 32, packed struct { - EPNDDINTSET0: u1, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET1: u1, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET2: u1, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET3: u1, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET4: u1, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET5: u1, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET6: u1, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET7: u1, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET8: u1, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET9: u1, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET10: u1, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET11: u1, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET12: u1, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET13: u1, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET14: u1, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET15: u1, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET16: u1, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET17: u1, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET18: u1, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET19: u1, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET20: u1, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET21: u1, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET22: u1, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET23: u1, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET24: u1, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET25: u1, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET26: u1, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET27: u1, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET28: u1, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET29: u1, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET30: u1, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET31: u1, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - }); - // byte offset: 696 USB System Error Interrupt Status - pub const SYSERRINTST = mmio(Address + 0x000002b8, 32, packed struct { - EPERRINTST0: u1, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST1: u1, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - }); - // byte offset: 700 USB System Error Interrupt Clear - pub const SYSERRINTCLR = mmio(Address + 0x000002bc, 32, packed struct { - EPERRINTCLR0: u1, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR1: u1, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR2: u1, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR3: u1, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR4: u1, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR5: u1, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR6: u1, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR7: u1, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR8: u1, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR9: u1, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR10: u1, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR11: u1, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR12: u1, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR13: u1, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR14: u1, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR15: u1, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR16: u1, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR17: u1, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR18: u1, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR19: u1, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR20: u1, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR21: u1, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR22: u1, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR23: u1, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR24: u1, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR25: u1, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR26: u1, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR27: u1, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR28: u1, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR29: u1, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR30: u1, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR31: u1, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - }); - // byte offset: 704 USB System Error Interrupt Set - pub const SYSERRINTSET = mmio(Address + 0x000002c0, 32, packed struct { - EPERRINTSET0: u1, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET1: u1, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET2: u1, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET3: u1, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET4: u1, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET5: u1, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET6: u1, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET7: u1, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET8: u1, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET9: u1, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET10: u1, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET11: u1, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET12: u1, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET13: u1, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET14: u1, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET15: u1, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET16: u1, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET17: u1, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET18: u1, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET19: u1, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET20: u1, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET21: u1, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET22: u1, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET23: u1, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET24: u1, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET25: u1, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET26: u1, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET27: u1, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET28: u1, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET29: u1, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET30: u1, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET31: u1, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - }); - // byte offset: 768 I2C Receive - pub const I2C_RX = mmio(Address + 0x00000300, 32, packed struct { - RXDATA: u8, // bit offset: 0 desc: Receive data. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 768 I2C Transmit - pub const I2C_WO = mmio(Address + 0x00000300, 32, packed struct { - TXDATA: u8, // bit offset: 0 desc: Transmit data. - START: u1, // bit offset: 8 desc: When 1, issue a START condition before transmitting this byte. - STOP: u1, // bit offset: 9 desc: When 1, issue a STOP condition after transmitting this byte. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 772 I2C Status - pub const I2C_STS = mmio(Address + 0x00000304, 32, packed struct { - TDI: enum(u1) { // bit offset: 0 desc: Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions. - @"NOT_COMPLETE" = 0, // desc: Transaction has not completed. - @"COMPLETE" = 1, // desc: Transaction completed. - }, - AFI: enum(u1) { // bit offset: 1 desc: Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register. - @"NO_ARBITRATION_FAILU" = 0, // desc: No arbitration failure on last transmission. - @"ARBITRATION_FAILURE_" = 1, // desc: Arbitration failure occurred on last transmission. - }, - NAI: enum(u1) { // bit offset: 2 desc: No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO. - @"ACKNOWLEDGE_RCVD" = 0, // desc: Last transmission received an acknowledge. - @"NO_ACKNOWLEDGE_RCVD" = 1, // desc: Last transmission did not receive an acknowledge. - }, - DRMI: enum(u1) { // bit offset: 3 desc: Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO. - @"BUSY" = 0, // desc: Master transmitter does not need data. - @"NEED_DATA" = 1, // desc: Master transmitter needs data. - }, - DRSI: enum(u1) { // bit offset: 4 desc: Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO. - @"BUSY" = 0, // desc: Slave transmitter does not need data. - @"NEED_DATA" = 1, // desc: Slave transmitter needs data. - }, - Active: u1, // bit offset: 5 desc: Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.. - SCL: u1, // bit offset: 6 desc: The current value of the SCL signal. - SDA: u1, // bit offset: 7 desc: The current value of the SDA signal. - RFF: enum(u1) { // bit offset: 8 desc: Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it. - @"RX_FIFO_IS_NOT_FULL" = 0, // desc: RX FIFO is not full - @"RX_FIFO_IS_FULL" = 1, // desc: RX FIFO is full - }, - RFE: enum(u1) { // bit offset: 9 desc: Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data. - @"DATA" = 0, // desc: RX FIFO contains data. - @"EMPTY" = 1, // desc: RX FIFO is empty - }, - TFF: enum(u1) { // bit offset: 10 desc: Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full. - @"TX_FIFO_IS_NOT_FULL_" = 0, // desc: TX FIFO is not full. - @"TX_FIFO_IS_FULL" = 1, // desc: TX FIFO is full - }, - TFE: enum(u1) { // bit offset: 11 desc: Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data. - @"VALID_DATA" = 0, // desc: TX FIFO contains valid data. - @"EMPTY" = 1, // desc: TX FIFO is empty - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 776 I2C Control - pub const I2C_CTL = mmio(Address + 0x00000308, 32, packed struct { - TDIE: enum(u1) { // bit offset: 0 desc: Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition. - @"DISABLE_THE_TDI_INTE" = 0, // desc: Disable the TDI interrupt. - @"ENABLE_THE_TDI_INTER" = 1, // desc: Enable the TDI interrupt. - }, - AFIE: enum(u1) { // bit offset: 1 desc: Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device. - @"DISABLE_THE_AFI_" = 0, // desc: Disable the AFI. - @"ENABLE_THE_AFI_" = 1, // desc: Enable the AFI. - }, - NAIE: enum(u1) { // bit offset: 2 desc: Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged. - @"DISABLE_THE_NAI_" = 0, // desc: Disable the NAI. - @"ENABLE_THE_NAI_" = 1, // desc: Enable the NAI. - }, - DRMIE: enum(u1) { // bit offset: 3 desc: Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low. - @"DISABLE_THE_DRMI_INT" = 0, // desc: Disable the DRMI interrupt. - @"ENABLE_THE_DRMI_INTE" = 1, // desc: Enable the DRMI interrupt. - }, - DRSIE: enum(u1) { // bit offset: 4 desc: Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low. - @"DISABLE_THE_DRSI_INT" = 0, // desc: Disable the DRSI interrupt. - @"ENABLE_THE_DRSI_INTE" = 1, // desc: Enable the DRSI interrupt. - }, - REFIE: enum(u1) { // bit offset: 5 desc: Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data. - @"DISABLE_THE_RFFI_" = 0, // desc: Disable the RFFI. - @"ENABLE_THE_RFFI_" = 1, // desc: Enable the RFFI. - }, - RFDAIE: enum(u1) { // bit offset: 6 desc: Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty). - @"DISABLE_THE_DAI_" = 0, // desc: Disable the DAI. - @"ENABLE_THE_DAI_" = 1, // desc: Enable the DAI. - }, - TFFIE: enum(u1) { // bit offset: 7 desc: Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register. - @"DISABLE_THE_TFFI_" = 0, // desc: Disable the TFFI. - @"ENABLE_THE_TFFI_" = 1, // desc: Enable the TFFI. - }, - SRST: enum(u1) { // bit offset: 8 desc: Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset. - @"NO_RESET" = 0, // desc: No reset. - @"RESET" = 1, // desc: Reset the I2C to idle state. Self clearing. - }, - // RESERVED: u23, // bit offset: 9 desc: Reserved. Read value is undefined, only zero should be written. - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 780 I2C Clock High - pub const I2C_CLKHI = mmio(Address + 0x0000030c, 32, packed struct { - CDHI: u8, // bit offset: 0 desc: Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 784 I2C Clock Low - pub const I2C_CLKLO = mmio(Address + 0x00000310, 32, packed struct { - CDLO: u8, // bit offset: 0 desc: Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4084 USB Clock Control - pub const USBCLKCTRL = mmio(Address + 0x00000ff4, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - DEV_CLK_EN: u1, // bit offset: 1 desc: Device clock enable. Enables the usbclk input to the device controller - // RESERVED: u1, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - PORTSEL_CLK_EN: u1, // bit offset: 3 desc: Port select register clock enable. - AHB_CLK_EN: u1, // bit offset: 4 desc: AHB clock enable - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4084 OTG clock controller - pub const OTGCLKCTRL = mmio(Address + 0x00000ff4, 32, packed struct { - HOST_CLK_EN: enum(u1) { // bit offset: 0 desc: Host clock enable - @"DISABLE_THE_HOST_CLO" = 0, // desc: Disable the Host clock. - @"ENABLE_THE_HOST_CLOC" = 1, // desc: Enable the Host clock. - }, - DEV_CLK_EN: enum(u1) { // bit offset: 1 desc: Device clock enable - @"DISABLE_THE_DEVICE_C" = 0, // desc: Disable the Device clock. - @"ENABLE_THE_DEVICE_CL" = 1, // desc: Enable the Device clock. - }, - I2C_CLK_EN: enum(u1) { // bit offset: 2 desc: I2C clock enable - @"DISABLE_THE_I2C_CLOC" = 0, // desc: Disable the I2C clock. - @"ENABLE_THE_I2C_CLOCK" = 1, // desc: Enable the I2C clock. - }, - OTG_CLK_EN: enum(u1) { // bit offset: 3 desc: OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register. - @"DISABLE_THE_OTG_CLOC" = 0, // desc: Disable the OTG clock. - @"ENABLE_THE_OTG_CLOCK" = 1, // desc: Enable the OTG clock. - }, - AHB_CLK_EN: enum(u1) { // bit offset: 4 desc: AHB master clock enable - @"DISABLE_THE_AHB_CLOC" = 0, // desc: Disable the AHB clock. - @"ENABLE_THE_AHB_CLOCK" = 1, // desc: Enable the AHB clock. - }, - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4088 USB Clock Status - pub const USBCLKST = mmio(Address + 0x00000ff8, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - DEV_CLK_ON: u1, // bit offset: 1 desc: Device clock on. The usbclk input to the device controller is active . - // RESERVED: u1, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - PORTSEL_CLK_ON: u1, // bit offset: 3 desc: Port select register clock on. - AHB_CLK_ON: u1, // bit offset: 4 desc: AHB clock on. - // RESERVED: u27, // bit offset: 5 desc: Reserved. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4088 OTG clock status - pub const OTGCLKST = mmio(Address + 0x00000ff8, 32, packed struct { - HOST_CLK_ON: enum(u1) { // bit offset: 0 desc: Host clock status. - @"HOST_CLOCK_IS_NOT_AV" = 0, // desc: Host clock is not available. - @"HOST_CLOCK_IS_AVAILA" = 1, // desc: Host clock is available. - }, - DEV_CLK_ON: enum(u1) { // bit offset: 1 desc: Device clock status. - @"DEVICE_CLOCK_IS_NOT_" = 0, // desc: Device clock is not available. - @"DEVICE_CLOCK_IS_AVAI" = 1, // desc: Device clock is available. - }, - I2C_CLK_ON: enum(u1) { // bit offset: 2 desc: I2C clock status. - @"I2C_CLOCK_IS_NOT_AVA" = 0, // desc: I2C clock is not available. - @"I2C_CLOCK_IS_AVAILAB" = 1, // desc: I2C clock is available. - }, - OTG_CLK_ON: enum(u1) { // bit offset: 3 desc: OTG clock status. - @"OTG_CLOCK_IS_NOT_AVA" = 0, // desc: OTG clock is not available. - @"OTG_CLOCK_IS_AVAILAB" = 1, // desc: OTG clock is available. - }, - AHB_CLK_ON: enum(u1) { // bit offset: 4 desc: AHB master clock status. - @"AHB_CLOCK_IS_NOT_AVA" = 0, // desc: AHB clock is not available. - @"AHB_CLOCK_IS_AVAILAB" = 1, // desc: AHB clock is available. - }, - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); +// this file is generated by regz +// +// device: LPC176x5x +// cpu: CM3 + +pub const VectorTable = struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + WDT: InterruptVector = unhandled, + TIMER0: InterruptVector = unhandled, + TIMER1: InterruptVector = unhandled, + TIMER2: InterruptVector = unhandled, + TIMER3: InterruptVector = unhandled, + UART0: InterruptVector = unhandled, + UART1: InterruptVector = unhandled, + UART2: InterruptVector = unhandled, + UART3: InterruptVector = unhandled, + PWM1: InterruptVector = unhandled, + I2C0: InterruptVector = unhandled, + I2C1: InterruptVector = unhandled, + I2C2: InterruptVector = unhandled, + SPI: InterruptVector = unhandled, + SSP0: InterruptVector = unhandled, + SSP1: InterruptVector = unhandled, + PLL0: InterruptVector = unhandled, + RTC: InterruptVector = unhandled, + EINT0: InterruptVector = unhandled, + EINT1: InterruptVector = unhandled, + EINT2: InterruptVector = unhandled, + EINT3: InterruptVector = unhandled, + ADC: InterruptVector = unhandled, + BOD: InterruptVector = unhandled, + USB: InterruptVector = unhandled, + CAN: InterruptVector = unhandled, + DMA: InterruptVector = unhandled, + I2S: InterruptVector = unhandled, + ENET: InterruptVector = unhandled, + RIT: InterruptVector = unhandled, + MCPWM: InterruptVector = unhandled, + QEI: InterruptVector = unhandled, + PLL1: InterruptVector = unhandled, + USBActivity: InterruptVector = unhandled, + CANActivity: InterruptVector = unhandled, }; -pub const GPIO = extern struct { - pub const Address: u32 = 0x2009c000; - // byte offset: 0 GPIO Port Direction control register. - pub const DIR0 = mmio(Address + 0x00000000, 32, packed struct { - PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - }); - // byte offset: 16 Mask register for Port. - pub const MASK0 = mmio(Address + 0x00000010, 32, packed struct { - PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - }); - // byte offset: 20 Port Pin value register using FIOMASK. - pub const PIN0 = mmio(Address + 0x00000014, 32, packed struct { - PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 24 Port Output Set register using FIOMASK. - pub const SET0 = mmio(Address + 0x00000018, 32, packed struct { - PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 28 Port Output Clear register using FIOMASK. - pub const CLR0 = mmio(Address + 0x0000001c, 32, packed struct { - PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - }); - // byte offset: 32 GPIO Port Direction control register. - pub const DIR1 = mmio(Address + 0x00000020, 32, packed struct { - PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - }); - // byte offset: 48 Mask register for Port. - pub const MASK1 = mmio(Address + 0x00000030, 32, packed struct { - PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - }); - // byte offset: 52 Port Pin value register using FIOMASK. - pub const PIN1 = mmio(Address + 0x00000034, 32, packed struct { - PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 56 Port Output Set register using FIOMASK. - pub const SET1 = mmio(Address + 0x00000038, 32, packed struct { - PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 60 Port Output Clear register using FIOMASK. - pub const CLR1 = mmio(Address + 0x0000003c, 32, packed struct { - PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - }); - // byte offset: 64 GPIO Port Direction control register. - pub const DIR2 = mmio(Address + 0x00000040, 32, packed struct { - PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - }); - // byte offset: 80 Mask register for Port. - pub const MASK2 = mmio(Address + 0x00000050, 32, packed struct { - PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - }); - // byte offset: 84 Port Pin value register using FIOMASK. - pub const PIN2 = mmio(Address + 0x00000054, 32, packed struct { - PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 88 Port Output Set register using FIOMASK. - pub const SET2 = mmio(Address + 0x00000058, 32, packed struct { - PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 92 Port Output Clear register using FIOMASK. - pub const CLR2 = mmio(Address + 0x0000005c, 32, packed struct { - PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - }); - // byte offset: 96 GPIO Port Direction control register. - pub const DIR3 = mmio(Address + 0x00000060, 32, packed struct { - PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - }); - // byte offset: 112 Mask register for Port. - pub const MASK3 = mmio(Address + 0x00000070, 32, packed struct { - PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - }); - // byte offset: 116 Port Pin value register using FIOMASK. - pub const PIN3 = mmio(Address + 0x00000074, 32, packed struct { - PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 120 Port Output Set register using FIOMASK. - pub const SET3 = mmio(Address + 0x00000078, 32, packed struct { - PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 124 Port Output Clear register using FIOMASK. - pub const CLR3 = mmio(Address + 0x0000007c, 32, packed struct { - PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - }); - // byte offset: 128 GPIO Port Direction control register. - pub const DIR4 = mmio(Address + 0x00000080, 32, packed struct { - PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - }); - // byte offset: 144 Mask register for Port. - pub const MASK4 = mmio(Address + 0x00000090, 32, packed struct { - PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - }); - // byte offset: 148 Port Pin value register using FIOMASK. - pub const PIN4 = mmio(Address + 0x00000094, 32, packed struct { - PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 152 Port Output Set register using FIOMASK. - pub const SET4 = mmio(Address + 0x00000098, 32, packed struct { - PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 156 Port Output Clear register using FIOMASK. - pub const CLR4 = mmio(Address + 0x0000009c, 32, packed struct { - PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - }); + +pub const registers = struct { + /// Watchdog Timer (WDT) + pub const WDT = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// Watchdog mode register. This register determines the basic mode and status of + /// the Watchdog Timer. + pub const MOD = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog enable bit. This bit is Set Only. + WDEN: u1, + /// Watchdog reset enable bit. This bit is Set Only. See Table 652. + WDRESET: u1, + /// Watchdog time-out flag. Set when the watchdog timer times out, cleared by + /// software. + WDTOF: u1, + /// Watchdog interrupt flag. Cleared by software. + WDINT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x0); + + /// address: 0x40000004 + /// Watchdog timer constant register. The value in this register determines the + /// time-out value. + pub const TC = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog time-out interval. + Count: u32, + }), base_address + 0x4); + + /// address: 0x40000008 + /// Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register + /// reloads the Watchdog timer with the value contained in WDTC. + pub const FEED = @intToPtr(*volatile Mmio(32, packed struct { + /// Feed value should be 0xAA followed by 0x55. + Feed: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4000000c + /// Watchdog timer value register. This register reads out the current value of the + /// Watchdog timer. + pub const TV = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter timer value. + Count: u32, + }), base_address + 0xc); + + /// address: 0x40000010 + /// Watchdog clock select register. + pub const CLKSEL = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects source of WDT clock + CLKSEL: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + reserved28: u1, + /// If this bit is set to one writing to this register does not affect bit 0. The + /// clock source can only be changed by first clearing this bit, then writing the + /// new value of bit 0. + LOCK: u1, + }), base_address + 0x10); + }; + /// Timer0/1/2/3 + pub const TIMER0 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004000 + /// Interrupt Register. The IR can be written to clear interrupts. The IR can be + /// read to identify which of eight possible interrupt sources are pending. + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag for match channel 0. + MR0INT: u1, + /// Interrupt flag for match channel 1. + MR1INT: u1, + /// Interrupt flag for match channel 2. + MR2INT: u1, + /// Interrupt flag for match channel 3. + MR3INT: u1, + /// Interrupt flag for capture channel 0 event. + CR0INT: u1, + /// Interrupt flag for capture channel 1 event. + CR1INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x0); + + /// address: 0x40004004 + /// Timer Control Register. The TCR is used to control the Timer Counter functions. + /// The Timer Counter can be disabled or reset through the TCR. + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + /// When one, the Timer Counter and Prescale Counter are enabled for counting. When + /// zero, the counters are disabled. + CEN: u1, + /// When one, the Timer Counter and the Prescale Counter are synchronously reset on + /// the next positive edge of PCLK. The counters remain reset until TCR[1] is + /// returned to zero. + CRST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x4); + + /// address: 0x40004008 + /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is + /// controlled through the TCR. + pub const TC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000400c + /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the + /// next clock increments the TC and clears the PC. + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescale counter maximum value. + PM: u32, + }), base_address + 0xc); + + /// address: 0x40004010 + /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value + /// stored in PR. When the value in PR is reached, the TC is incremented and the PC + /// is cleared. The PC is observable and controllable through the bus interface. + pub const PC = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40004014 + /// Match Control Register. The MCR is used to control if an interrupt is generated + /// and if the TC is reset when a Match occurs. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt on MR0 + MR0I: u1, + /// Reset on MR0 + MR0R: u1, + /// Stop on MR0 + MR0S: u1, + /// Interrupt on MR1 + MR1I: u1, + /// Reset on MR1 + MR1R: u1, + /// Stop on MR1 + MR1S: u1, + /// Interrupt on MR2 + MR2I: u1, + /// Reset on MR2 + MR2R: u1, + /// Stop on MR2. + MR2S: u1, + /// Interrupt on MR3 + MR3I: u1, + /// Reset on MR3 + MR3R: u1, + /// Stop on MR3 + MR3S: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x14); + + /// address: 0x40004018 + /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both + /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x18); + + /// address: 0x40004028 + /// Capture Control Register. The CCR controls which edges of the capture inputs are + /// used to load the Capture Registers and whether or not an interrupt is generated + /// when a capture takes place. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture on CAPn.0 rising edge + CAP0RE: u1, + /// Capture on CAPn.0 falling edge + CAP0FE: u1, + /// Interrupt on CAPn.0 event + CAP0I: u1, + /// Capture on CAPn.1 rising edge + CAP1RE: u1, + /// Capture on CAPn.1 falling edge + CAP1FE: u1, + /// Interrupt on CAPn.1 event + CAP1I: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x4000402c + /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on + /// the CAPn.0 input. + pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Timer counter capture value. + CAP: u32, + }), base_address + 0x2c); + + /// address: 0x4000403c + /// External Match Register. The EMR controls the external match pins. + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { + /// External Match 0. When a match occurs between the TC and MR0, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM0: u1, + /// External Match 1. When a match occurs between the TC and MR1, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this + /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM1: u1, + /// External Match 2. When a match occurs between the TC and MR2, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM2: u1, + /// External Match 3. When a match occurs between the TC and MR3, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM3: u1, + /// External Match Control 0. Determines the functionality of External Match 0. + EMC0: u2, + /// External Match Control 1. Determines the functionality of External Match 1. + EMC1: u2, + /// External Match Control 2. Determines the functionality of External Match 2. + EMC2: u2, + /// External Match Control 3. Determines the functionality of External Match 3. + EMC3: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x3c); + + /// address: 0x40004070 + /// Count Control Register. The CTCR selects between Timer and Counter mode, and in + /// Counter mode selects the signal and edge(s) for counting. + pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter/Timer Mode This field selects which rising PCLK edges can increment + /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). + /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale + /// Register. + CTMODE: u2, + /// Count Input Select When bits 1:0 in this register are not 00, these bits select + /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a + /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture + /// Control Register (TnCCR) must be programmed as 000. However, capture and/or + /// interrupt can be selected for the other 3 CAPn inputs in the same timer. + CINSEL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x70); + }; + pub const TIMER1 = struct { + pub const base_address = 0x40008000; + + /// address: 0x40008000 + /// Interrupt Register. The IR can be written to clear interrupts. The IR can be + /// read to identify which of eight possible interrupt sources are pending. + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag for match channel 0. + MR0INT: u1, + /// Interrupt flag for match channel 1. + MR1INT: u1, + /// Interrupt flag for match channel 2. + MR2INT: u1, + /// Interrupt flag for match channel 3. + MR3INT: u1, + /// Interrupt flag for capture channel 0 event. + CR0INT: u1, + /// Interrupt flag for capture channel 1 event. + CR1INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x0); + + /// address: 0x40008004 + /// Timer Control Register. The TCR is used to control the Timer Counter functions. + /// The Timer Counter can be disabled or reset through the TCR. + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + /// When one, the Timer Counter and Prescale Counter are enabled for counting. When + /// zero, the counters are disabled. + CEN: u1, + /// When one, the Timer Counter and the Prescale Counter are synchronously reset on + /// the next positive edge of PCLK. The counters remain reset until TCR[1] is + /// returned to zero. + CRST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x4); + + /// address: 0x40008008 + /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is + /// controlled through the TCR. + pub const TC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000800c + /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the + /// next clock increments the TC and clears the PC. + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescale counter maximum value. + PM: u32, + }), base_address + 0xc); + + /// address: 0x40008010 + /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value + /// stored in PR. When the value in PR is reached, the TC is incremented and the PC + /// is cleared. The PC is observable and controllable through the bus interface. + pub const PC = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40008014 + /// Match Control Register. The MCR is used to control if an interrupt is generated + /// and if the TC is reset when a Match occurs. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt on MR0 + MR0I: u1, + /// Reset on MR0 + MR0R: u1, + /// Stop on MR0 + MR0S: u1, + /// Interrupt on MR1 + MR1I: u1, + /// Reset on MR1 + MR1R: u1, + /// Stop on MR1 + MR1S: u1, + /// Interrupt on MR2 + MR2I: u1, + /// Reset on MR2 + MR2R: u1, + /// Stop on MR2. + MR2S: u1, + /// Interrupt on MR3 + MR3I: u1, + /// Reset on MR3 + MR3R: u1, + /// Stop on MR3 + MR3S: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x14); + + /// address: 0x40008018 + /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both + /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x18); + + /// address: 0x40008028 + /// Capture Control Register. The CCR controls which edges of the capture inputs are + /// used to load the Capture Registers and whether or not an interrupt is generated + /// when a capture takes place. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture on CAPn.0 rising edge + CAP0RE: u1, + /// Capture on CAPn.0 falling edge + CAP0FE: u1, + /// Interrupt on CAPn.0 event + CAP0I: u1, + /// Capture on CAPn.1 rising edge + CAP1RE: u1, + /// Capture on CAPn.1 falling edge + CAP1FE: u1, + /// Interrupt on CAPn.1 event + CAP1I: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x4000802c + /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on + /// the CAPn.0 input. + pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Timer counter capture value. + CAP: u32, + }), base_address + 0x2c); + + /// address: 0x4000803c + /// External Match Register. The EMR controls the external match pins. + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { + /// External Match 0. When a match occurs between the TC and MR0, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM0: u1, + /// External Match 1. When a match occurs between the TC and MR1, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this + /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM1: u1, + /// External Match 2. When a match occurs between the TC and MR2, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM2: u1, + /// External Match 3. When a match occurs between the TC and MR3, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM3: u1, + /// External Match Control 0. Determines the functionality of External Match 0. + EMC0: u2, + /// External Match Control 1. Determines the functionality of External Match 1. + EMC1: u2, + /// External Match Control 2. Determines the functionality of External Match 2. + EMC2: u2, + /// External Match Control 3. Determines the functionality of External Match 3. + EMC3: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x3c); + + /// address: 0x40008070 + /// Count Control Register. The CTCR selects between Timer and Counter mode, and in + /// Counter mode selects the signal and edge(s) for counting. + pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter/Timer Mode This field selects which rising PCLK edges can increment + /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). + /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale + /// Register. + CTMODE: u2, + /// Count Input Select When bits 1:0 in this register are not 00, these bits select + /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a + /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture + /// Control Register (TnCCR) must be programmed as 000. However, capture and/or + /// interrupt can be selected for the other 3 CAPn inputs in the same timer. + CINSEL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x70); + }; + /// UART0/2/3 + pub const UART0 = struct { + pub const base_address = 0x4000c000; + + /// address: 0x4000c000 + /// Receiver Buffer Register. Contains the next received character to be read (DLAB + /// =0). + pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Receiver Buffer Register contains the oldest received byte in the + /// UARTn Rx FIFO. + RBR: u8, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4000c000 + /// Transmit Holding Regiter. The next character to be transmitted is written here + /// (DLAB =0). + pub const THR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing to the UARTn Transmit Holding Register causes the data to be stored in + /// the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the + /// FIFO and the transmitter is available. + THR: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4000c000 + /// Divisor Latch LSB. Least significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines + /// the baud rate of the UARTn. + DLLSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4000c004 + /// Divisor Latch MSB. Most significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines + /// the baud rate of the UARTn. + DLMSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x4000c004 + /// Interrupt Enable Register. Contains individual interrupt enable bits for the 7 + /// potential UART interrupts (DLAB =0). + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It + /// also controls the Character Receive Time-out interrupt. + RBRIE: u1, + /// THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this + /// can be read from UnLSR[5]. + THREIE: u1, + /// RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. + /// The status of this interrupt can be read from UnLSR[4:1]. + RXIE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// Enables the end of auto-baud interrupt. + ABEOINTEN: u1, + /// Enables the auto-baud time-out interrupt. + ABTOINTEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x4); + + /// address: 0x4000c008 + /// Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be + /// determined by evaluating UnIIR[3:1]. + INTSTATUS: u1, + /// Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to + /// the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below + /// are reserved (000,100,101,111). + INTID: u3, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// Copies of UnFCR[0]. + FIFOENABLE: u2, + /// End of auto-baud interrupt. True if auto-baud has finished successfully and + /// interrupt is enabled. + ABEOINT: u1, + /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is + /// enabled. + ABTOINT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x8); + + /// address: 0x4000c008 + /// FIFO Control Register. Controls UART FIFO usage and modes. + pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO Enable. + FIFOEN: u1, + /// RX FIFO Reset. + RXFIFORES: u1, + /// TX FIFO Reset. + TXFIFORES: u1, + /// DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit + /// selects the DMA mode. See Section 18.6.6.1. + DMAMODE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// RX Trigger Level. These two bits determine how many receiver UARTn FIFO + /// characters must be written before an interrupt or DMA request is activated. + RXTRIGLVL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4000c00c + /// Line Control Register. Contains controls for frame formatting and break + /// generation. + pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Word Length Select. + WLS: u2, + /// Stop Bit Select + SBS: u1, + /// Parity Enable. + PE: u1, + /// Parity Select + PS: u2, + /// Break Control + BC: u1, + /// Divisor Latch Access Bit + DLAB: u1, + /// Reserved. Read value is undefined, only zero should be written. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x4000c014 + /// Line Status Register. Contains flags for transmit and receive status, including + /// line errors. + pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character + /// and is cleared when the UARTn RBR FIFO is empty. + RDR: u1, + /// Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR + /// read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character + /// assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will + /// not be overwritten and the character in the UARTn RSR will be lost. + OE: u1, + /// Parity Error. When the parity bit of a received character is in the wrong state, + /// a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error + /// detection is dependent on UnFCR[0]. Note: A parity error is associated with the + /// character at the top of the UARTn RBR FIFO. + PE: u1, + /// Framing Error. When the stop bit of a received character is a logic 0, a framing + /// error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error + /// detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx + /// will attempt to resynchronize to the data and assume that the bad stop bit is + /// actually an early start bit. However, it cannot be assumed that the next + /// received byte will be correct even if there is no Framing Error. Note: A framing + /// error is associated with the character at the top of the UARTn RBR FIFO. + FE: u1, + /// Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one + /// full character transmission (start, data, parity, stop), a break interrupt + /// occurs. Once the break condition has been detected, the receiver goes idle until + /// RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The + /// time of break detection is dependent on UnFCR[0]. Note: The break interrupt is + /// associated with the character at the top of the UARTn RBR FIFO. + BI: u1, + /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an + /// empty UARTn THR and is cleared on a UnTHR write. + THRE: u1, + /// Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is + /// cleared when either the UnTSR or the UnTHR contain valid data. + TEMT: u1, + /// Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as + /// framing error, parity error or break interrupt, is loaded into the UnRBR. This + /// bit is cleared when the UnLSR register is read and there are no subsequent + /// errors in the UARTn FIFO. + RXFE: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x14); + + /// address: 0x4000c01c + /// Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + /// A readable, writable byte. + PAD: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x1c); + + /// address: 0x4000c020 + /// Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit. This bit is automatically cleared after auto-baud completion. + START: u1, + /// Auto-baud mode select bit. + MODE: u1, + /// Restart bit. + AUTORESTART: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABEOINTCLR: u1, + /// Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABTOINTCLR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x20); + + /// address: 0x4000c028 + /// Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud-rate generation pre-scaler divisor value. If this field is 0, fractional + /// baud-rate generator will not impact the UARTn baudrate. + DIVADDVAL: u4, + /// Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for + /// UARTn to operate properly, regardless of whether the fractional baud-rate + /// generator is used or not. + MULVAL: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x4000c030 + /// Transmit Enable Register. Turns off UART transmitter for use with software flow + /// control. + pub const TER = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u7, + /// When this bit is 1, as it is after a Reset, data written to the THR is output on + /// the TXD pin as soon as any preceding data has been sent. If this bit is cleared + /// to 0 while a character is being sent, the transmission of that character is + /// completed, but no further characters are sent until this bit is set again. In + /// other words, a 0 in this bit blocks the transfer of characters from the THR or + /// TX FIFO into the transmit shift register. Software implementing + /// software-handshaking can clear this bit when it receives an XOFF character + /// (DC3). Software can set this bit again when it receives an XON (DC1) character. + TXEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x30); + + /// address: 0x4000c04c + /// RS-485/EIA-485 Control. Contains controls to configure various aspects of + /// RS-485/EIA-485 modes. + pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// NMM enable. + NMMEN: u1, + /// Receiver enable. + RXDIS: u1, + /// AAD enable. + AADEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Direction control enable. + DCTRL: u1, + /// Direction control pin polarity. This bit reverses the polarity of the direction + /// control signal on the Un_OE pin. + OINV: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x4c); + + /// address: 0x4000c050 + /// RS-485/EIA-485 address match. Contains the address match value for + /// RS-485/EIA-485 mode. + pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the address match value. + ADRMATCH: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x50); + + /// address: 0x4000c054 + /// RS-485/EIA-485 direction control delay. + pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the direction control (UnOE) delay value. This register works in + /// conjunction with an 8-bit counter. + DLY: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x54); + }; + /// UART1 + pub const UART1 = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// DLAB =0 Receiver Buffer Register. Contains the next received character to be + /// read. + pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { + /// The UART1 Receiver Buffer Register contains the oldest received byte in the + /// UART1 RX FIFO. + RBR: u8, + /// Reserved, the value read from a reserved bit is not defined. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40010000 + /// DLAB =0. Transmit Holding Register. The next character to be transmitted is + /// written here. + pub const THR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing to the UART1 Transmit Holding Register causes the data to be stored in + /// the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the + /// FIFO and the transmitter is available. + THR: u8, + /// Reserved. Read value is undefined, only zero should be written. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40010000 + /// DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor + /// value. The full divisor is used to generate a baud rate from the fractional rate + /// divider. + pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { + /// The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines + /// the baud rate of the UART1. + DLLSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40010004 + /// DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor + /// value. The full divisor is used to generate a baud rate from the fractional rate + /// divider. + pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { + /// The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines + /// the baud rate of the UART1. + DLMSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40010004 + /// DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits + /// for the 7 potential UART1 interrupts. + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It + /// also controls the Character Receive Time-out interrupt. + RBRIE: u1, + /// THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this + /// interrupt can be read from LSR[5]. + THREIE: u1, + /// RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The + /// status of this interrupt can be read from LSR[4:1]. + RXIE: u1, + /// Modem Status Interrupt Enable. Enables the modem interrupt. The status of this + /// interrupt can be read from MSR[3:0]. + MSIE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u3, + /// CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the + /// modem status interrupt generation on a CTS1 signal transition. If auto-cts mode + /// is disabled a CTS1 transition will generate an interrupt if Modem Status + /// Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition + /// will generate a Modem Status Interrupt unless the interrupt has been disabled by + /// clearing the IER[3] bit in the IER register. In auto-cts mode a transition on + /// the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits + /// are set. + CTSIE: u1, + /// Enables the end of auto-baud interrupt. + ABEOIE: u1, + /// Enables the auto-baud time-out interrupt. + ABTOIE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x4); + + /// address: 0x40010008 + /// Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt status. Note that IIR[0] is active low. The pending interrupt can be + /// determined by evaluating IIR[3:1]. + INTSTATUS: u1, + /// Interrupt identification. IER[3:1] identifies an interrupt corresponding to the + /// UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are + /// reserved (100,101,111). + INTID: u3, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Copies of FCR[0]. + FIFOENABLE: u2, + /// End of auto-baud interrupt. True if auto-baud has finished successfully and + /// interrupt is enabled. + ABEOINT: u1, + /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is + /// enabled. + ABTOINT: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x8); + + /// address: 0x40010008 + /// FIFO Control Register. Controls UART1 FIFO usage and modes. + pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO enable. + FIFOEN: u1, + /// RX FIFO Reset. + RXFIFORES: u1, + /// TX FIFO Reset. + TXFIFORES: u1, + /// DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this + /// bit selects the DMA mode. See Section 36.6.6.1. + DMAMODE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// RX Trigger Level. These two bits determine how many receiver UART1 FIFO + /// characters must be written before an interrupt is activated. + RXTRIGLVL: u2, + /// Reserved, user software should not write ones to reserved bits. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4001000c + /// Line Control Register. Contains controls for frame formatting and break + /// generation. + pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Word Length Select. + WLS: u2, + /// Stop Bit Select. + SBS: u1, + /// Parity Enable. + PE: u1, + /// Parity Select. + PS: u2, + /// Break Control. + BC: u1, + /// Divisor Latch Access Bit (DLAB) + DLAB: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40010010 + /// Modem Control Register. Contains controls for flow control handshaking and + /// loopback mode. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem + /// loopback mode is active. + DTRCTRL: u1, + /// RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem + /// loopback mode is active. + RTSCTRL: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Loopback Mode Select. The modem loopback mode provides a mechanism to perform + /// diagnostic loopback testing. Serial data from the transmitter is connected + /// internally to serial input of the receiver. Input pin, RXD1, has no effect on + /// loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, + /// DSR, RI and DCD) are disconnected externally. Externally, the modem outputs + /// (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to + /// the 4 modem inputs. As a result of these connections, the upper 4 bits of the + /// MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs + /// in normal mode. This permits modem status interrupts to be generated in loopback + /// mode by writing the lower 4 bits of MCR. + LMS: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// RTS enable. + RTSEN: u1, + /// CTS enable. + CTSEN: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x10); + + /// address: 0x40010014 + /// Line Status Register. Contains flags for transmit and receive status, including + /// line errors. + pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is + /// cleared when the UART1 RBR FIFO is empty. + RDR: u1, + /// Overrun Error. The overrun error condition is set as soon as it occurs. An LSR + /// read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled + /// and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be + /// overwritten and the character in the UART1 RSR will be lost. + OE: u1, + /// Parity Error. When the parity bit of a received character is in the wrong state, + /// a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection + /// is dependent on FCR[0]. Note: A parity error is associated with the character at + /// the top of the UART1 RBR FIFO. + PE: u1, + /// Framing Error. When the stop bit of a received character is a logic 0, a framing + /// error occurs. An LSR read clears LSR[3]. The time of the framing error detection + /// is dependent on FCR0. Upon detection of a framing error, the RX will attempt to + /// resynchronize to the data and assume that the bad stop bit is actually an early + /// start bit. However, it cannot be assumed that the next received byte will be + /// correct even if there is no Framing Error. Note: A framing error is associated + /// with the character at the top of the UART1 RBR FIFO. + FE: u1, + /// Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one + /// full character transmission (start, data, parity, stop), a break interrupt + /// occurs. Once the break condition has been detected, the receiver goes idle until + /// RXD1 goes to marking state (all ones). An LSR read clears this status bit. The + /// time of break detection is dependent on FCR[0]. Note: The break interrupt is + /// associated with the character at the top of the UART1 RBR FIFO. + BI: u1, + /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an + /// empty UART1 THR and is cleared on a THR write. + THRE: u1, + /// Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared + /// when either the TSR or the THR contain valid data. + TEMT: u1, + /// Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing + /// error, parity error or break interrupt, is loaded into the RBR. This bit is + /// cleared when the LSR register is read and there are no subsequent errors in the + /// UART1 FIFO. + RXFE: u1, + /// Reserved, the value read from a reserved bit is not defined. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40010018 + /// Modem Status Register. Contains handshake signal status flags. + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. + DCTS: u1, + /// Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. + DDSR: u1, + /// Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR + /// read. + TERI: u1, + /// Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. + DDCD: u1, + /// Clear To Send State. Complement of input signal CTS. This bit is connected to + /// MCR[1] in modem loopback mode. + CTS: u1, + /// Data Set Ready State. Complement of input signal DSR. This bit is connected to + /// MCR[0] in modem loopback mode. + DSR: u1, + /// Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in + /// modem loopback mode. + RI: u1, + /// Data Carrier Detect State. Complement of input DCD. This bit is connected to + /// MCR[3] in modem loopback mode. + DCD: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x4001001c + /// Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + /// A readable, writable byte. + Pad: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x1c); + + /// address: 0x40010020 + /// Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Auto-baud start bit. This bit is automatically cleared after auto-baud + /// completion. + START: u1, + /// Auto-baud mode select bit. + MODE: u1, + /// Auto-baud restart bit. + AUTORESTART: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u5, + /// End of auto-baud interrupt clear bit (write-only). + ABEOINTCLR: u1, + /// Auto-baud time-out interrupt clear bit (write-only). + ABTOINTCLR: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x20); + + /// address: 0x40010028 + /// Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud rate generation pre-scaler divisor value. If this field is 0, fractional + /// baud rate generator will not impact the UART1 baud rate. + DIVADDVAL: u4, + /// Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for + /// UART1 to operate properly, regardless of whether the fractional baud rate + /// generator is used or not. + MULVAL: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x40010030 + /// Transmit Enable Register. Turns off UART transmitter for use with software flow + /// control. + pub const TER = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u7, + /// When this bit is 1, as it is after a Reset, data written to the THR is output on + /// the TXD pin as soon as any preceding data has been sent. If this bit cleared to + /// 0 while a character is being sent, the transmission of that character is + /// completed, but no further characters are sent until this bit is set again. In + /// other words, a 0 in this bit blocks the transfer of characters from the THR or + /// TX FIFO into the transmit shift register. Software can clear this bit when it + /// detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, + /// or with software handshaking, when it receives an XOFF character (DC3). Software + /// can set this bit again when it detects that the TX-permit signal has gone true, + /// or when it receives an XON (DC1) character. + TXEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x30); + + /// address: 0x4001004c + /// RS-485/EIA-485 Control. Contains controls to configure various aspects of + /// RS-485/EIA-485 modes. + pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select. + NMMEN: u1, + /// Receive enable. + RXDIS: u1, + /// Auto Address Detect (AAD) enable. + AADEN: u1, + /// Direction control. + SEL: u1, + /// Direction control enable. + DCTRL: u1, + /// Polarity. This bit reverses the polarity of the direction control signal on the + /// RTS (or DTR) pin. + OINV: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x4c); + + /// address: 0x40010050 + /// RS-485/EIA-485 address match. Contains the address match value for + /// RS-485/EIA-485 mode. + pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the address match value. + ADRMATCH: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x50); + + /// address: 0x40010054 + /// RS-485/EIA-485 direction control delay. + pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the direction control (RTS or DTR) delay value. This register works in + /// conjunction with an 8-bit counter. + DLY: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x54); + }; + /// Pulse Width Modulators (PWM1) + pub const PWM1 = struct { + pub const base_address = 0x40018000; + + /// address: 0x40018000 + /// Interrupt Register. The IR can be written to clear interrupts, or read to + /// identify which PWM interrupt sources are pending. + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag for PWM match channel 0. + PWMMR0INT: u1, + /// Interrupt flag for PWM match channel 1. + PWMMR1INT: u1, + /// Interrupt flag for PWM match channel 2. + PWMMR2INT: u1, + /// Interrupt flag for PWM match channel 3. + PWMMR3INT: u1, + /// Interrupt flag for capture input 0 + PWMCAP0INT: u1, + /// Interrupt flag for capture input 1 (available in PWM1IR only; this bit is + /// reserved in PWM0IR). + PWMCAP1INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// Interrupt flag for PWM match channel 4. + PWMMR4INT: u1, + /// Interrupt flag for PWM match channel 5. + PWMMR5INT: u1, + /// Interrupt flag for PWM match channel 6. + PWMMR6INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x0); + + /// address: 0x40018004 + /// Timer Control Register. The TCR is used to control the Timer Counter functions. + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter Enable + CE: u1, + /// Counter Reset + CR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// PWM Enable + PWMEN: u1, + /// Master Disable (PWM0 only). The two PWMs may be synchronized using the Master + /// Disable control bit. The Master disable bit of the Master PWM (PWM0 module) + /// controls a secondary enable input to both PWMs, as shown in Figure 141. This bit + /// has no function in the Slave PWM (PWM1). + MDIS: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0x4); + + /// address: 0x40018008 + /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is + /// controlled through the TCR. + pub const TC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4001800c + /// Prescale Register. Determines how often the PWM counter is incremented. + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescale counter maximum value. + PM: u32, + }), base_address + 0xc); + + /// address: 0x40018010 + /// Prescale Counter. Prescaler for the main PWM counter. + pub const PC = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40018014 + /// Match Control Register. The MCR is used to control whether an interrupt is + /// generated and if the PWM counter is reset when a Match occurs. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt PWM0 + PWMMR0I: u1, + /// Reset PWM0 + PWMMR0R: u1, + /// Stop PWM0 + PWMMR0S: u1, + /// Interrupt PWM1 + PWMMR1I: u1, + /// Reset PWM1 + PWMMR1R: u1, + /// Stop PWM1 + PWMMR1S: u1, + /// Interrupt PWM0 + PWMMR2I: u1, + /// Reset PWM0 + PWMMR2R: u1, + /// Stop PWM0 + PWMMR2S: u1, + /// Interrupt PWM3 + PWMMR3I: u1, + /// Reset PWM3 + PWMMR3R: u1, + /// Stop PWM0 + PWMMR3S: u1, + /// Interrupt PWM4 + PWMMR4I: u1, + /// Reset PWM4 + PWMMR4R: u1, + /// Stop PWM4 + PWMMR4S: u1, + /// Interrupt PWM5 + PWMMR5I: u1, + /// Reset PWM5 + PWMMR5R: u1, + /// Stop PWM5 + PWMMR5S: u1, + /// Interrupt PWM6 + PWMMR6I: u1, + /// Reset PWM6 + PWMMR6R: u1, + /// Stop PWM6 + PWMMR6S: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u11, + }), base_address + 0x14); + + /// address: 0x40018018 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x18); + + /// address: 0x4001801c + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x1c); + + /// address: 0x40018020 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x20); + + /// address: 0x40018024 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x24); + + /// address: 0x40018028 + /// Capture Control Register. The CCR controls which edges of the capture inputs are + /// used to load the Capture Registers and whether or not an interrupt is generated + /// for a capture event. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture on PWMn_CAP0 rising edge + CAP0_R: u1, + /// Capture on PWMn_CAP0 falling edge + CAP0_F: u1, + /// Interrupt on PWMn_CAP0 event + CAP0_I: u1, + /// Capture on PWMn_CAP1 rising edge. Reserved for PWM0. + CAP1_R: u1, + /// Capture on PWMn_CAP1 falling edge. Reserved for PWM0. + CAP1_F: u1, + /// Interrupt on PWMn_CAP1 event. Reserved for PWM0. + CAP1_I: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x4001802c + /// PWM Control Register. Enables PWM outputs and selects either single edge or + /// double edge controlled PWM outputs. + pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Reserved. + RESERVED: u2, + /// PWM[2] output single/double edge mode control. + PWMSEL2: u1, + /// PWM[3] output edge control. + PWMSEL3: u1, + /// PWM[4] output edge control. + PWMSEL4: u1, + /// PWM[5] output edge control. + PWMSEL5: u1, + /// PWM[6] output edge control. + PWMSEL6: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// PWM[1] output enable control. + PWMENA1: u1, + /// PWM[2] output enable control. + PWMENA2: u1, + /// PWM[3] output enable control. + PWMENA3: u1, + /// PWM[4] output enable control. + PWMENA4: u1, + /// PWM[5] output enable control. + PWMENA5: u1, + /// PWM[6] output enable control. See PWMENA1 for details. + PWMENA6: u1, + /// Unused, always zero. + RESERVED: u17, + }), base_address + 0x2c); + + /// address: 0x40018040 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x40); + + /// address: 0x40018044 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x44); + + /// address: 0x40018048 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x48); + + /// address: 0x4001804c + /// PWM Control Register. Enables PWM outputs and selects either single edge or + /// double edge controlled PWM outputs. + pub const PCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u2, + /// PWM[2] output single/double edge mode control. + PWMSEL2: u1, + /// PWM[3] output edge control. + PWMSEL3: u1, + /// PWM[4] output edge control. + PWMSEL4: u1, + /// PWM[5] output edge control. + PWMSEL5: u1, + /// PWM[6] output edge control. + PWMSEL6: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// PWM[1] output enable control. + PWMENA1: u1, + /// PWM[2] output enable control. + PWMENA2: u1, + /// PWM[3] output enable control. + PWMENA3: u1, + /// PWM[4] output enable control. + PWMENA4: u1, + /// PWM[5] output enable control. + PWMENA5: u1, + /// PWM[6] output enable control. See PWMENA1 for details. + PWMENA6: u1, + /// Unused, always zero. + RESERVED: u17, + }), base_address + 0x4c); + + /// address: 0x40018050 + /// Load Enable Register. Enables use of updated PWM match values. + pub const LER = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this + /// bit allows the last value written to the PWM Match Register 0 to be become + /// effective when the timer is next reset by a PWM Match event. See Section 27.6.7. + MAT0LATCHEN: u1, + /// Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for + /// details. + MAT1LATCHEN: u1, + /// Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for + /// details. + MAT2LATCHEN: u1, + /// Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for + /// details. + MAT3LATCHEN: u1, + /// Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for + /// details. + MAT4LATCHEN: u1, + /// Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for + /// details. + MAT5LATCHEN: u1, + /// Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for + /// details. + MAT6LATCHEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u25, + }), base_address + 0x50); + + /// address: 0x40018070 + /// Count Control Register. The CTCR selects between Timer and Counter mode, and in + /// Counter mode selects the signal and edge(s) for counting. + pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter/ Timer Mode + MOD: u2, + /// Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP + /// pin carries the signal used to increment the TC. Other combinations are + /// reserved. + CIS: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x70); + }; + /// I2C bus interface + pub const I2C0 = struct { + pub const base_address = 0x4001c000; + + /// address: 0x4001c000 + /// I2C Control Set Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is set. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge flag. + AA: u1, + /// I2C interrupt flag. + SI: u1, + /// STOP flag. + STO: u1, + /// START flag. + STA: u1, + /// I2C interface enable. + I2EN: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u25, + }), base_address + 0x0); + + /// address: 0x4001c004 + /// I2C Status Register. During I2C operation, this register provides detailed + /// status codes that allow software to determine the next action needed. + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits are unused and are always 0. + RESERVED: u3, + /// These bits give the actual status information about the I 2C interface. + Status: u5, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x4001c008 + /// I2C Data Register. During master or slave transmit mode, data to be transmitted + /// is written to this register. During master or slave receive mode, data that has + /// been received may be read from this register. + pub const DAT = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds data values that have been received or are to be + /// transmitted. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4001c00c + /// I2C Slave Address Register 0. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x4001c010 + /// SCH Duty Cycle Register High Half Word. Determines the high time of the I2C + /// clock. + pub const SCLH = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL HIGH time period selection. + SCLH: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x10); + + /// address: 0x4001c014 + /// SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. + /// SCLL and SCLH together determine the clock frequency generated by an I2C master + /// and certain times used in slave mode. + pub const SCLL = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL low time period selection. + SCLL: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x14); + + /// address: 0x4001c018 + /// I2C Control Clear Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is cleared. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge Clear bit. + AAC: u1, + /// I2C interrupt Clear bit. + SIC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// START flag Clear bit. + STAC: u1, + /// I2C interface Disable bit. + I2ENC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x4001c01c + /// Monitor mode control register. + pub const MMCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Monitor mode enable. + MM_ENA: u1, + /// SCL output enable. + ENA_SCL: u1, + /// Select interrupt register match. + MATCH_ALL: u1, + /// Reserved. The value read from reserved bits is not defined. + RESERVED: u29, + }), base_address + 0x1c); + + /// address: 0x4001c020 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x20); + + /// address: 0x4001c024 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x24); + + /// address: 0x4001c028 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x4001c02c + /// Data buffer register. The contents of the 8 MSBs of the DAT shift register will + /// be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of + /// data plus ACK or NACK) has been received on the bus. + pub const DATA_BUFFER = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds contents of the 8 MSBs of the DAT shift register. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x2c); + + /// address: 0x4001c030 + /// I2C Slave address mask register + pub const MASK = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. This bit reads + /// always back as 0. + RESERVED: u1, + /// Mask bits. + MASK: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x30); + }; + /// SPI + pub const SPI = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020000 + /// SPI Control Register. This register controls the operation of the SPI. + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// The SPI controller sends and receives 8 bits of data per transfer. + BITENABLE: u1, + /// Clock phase control determines the relationship between the data and the clock + /// on SPI transfers, and controls when a slave transfer is defined as starting and + /// ending. + CPHA: u1, + /// Clock polarity control. + CPOL: u1, + /// Master mode select. + MSTR: u1, + /// LSB First controls which direction each byte is shifted when transferred. + LSBF: u1, + /// Serial peripheral interrupt enable. + SPIE: u1, + /// When bit 2 of this register is 1, this field controls the number of bits per + /// transfer: + BITS: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x0); + + /// address: 0x40020004 + /// SPI Status Register. This register shows the status of the SPI. + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u3, + /// Slave abort. When 1, this bit indicates that a slave abort has occurred. This + /// bit is cleared by reading this register. + ABRT: u1, + /// Mode fault. when 1, this bit indicates that a Mode fault error has occurred. + /// This bit is cleared by reading this register, then writing the SPI0 control + /// register. + MODF: u1, + /// Read overrun. When 1, this bit indicates that a read overrun has occurred. This + /// bit is cleared by reading this register. + ROVR: u1, + /// Write collision. When 1, this bit indicates that a write collision has occurred. + /// This bit is cleared by reading this register, then accessing the SPI Data + /// Register. + WCOL: u1, + /// SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer + /// is complete. When a master, this bit is set at the end of the last cycle of the + /// transfer. When a slave, this bit is set on the last data sampling edge of the + /// SCK. This bit is cleared by first reading this register, then accessing the SPI + /// Data Register. Note: this is not the SPI interrupt flag. This flag is found in + /// the SPINT register. + SPIF: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x40020008 + /// SPI Data Register. This bi-directional register provides the transmit and + /// receive data for the SPI. Transmit data is provided to the SPI0 by writing to + /// this register. Data received by the SPI0 can be read from this register. + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// SPI Bi-directional data port. + DATALOW: u8, + /// If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of + /// these bits contain the additional transmit and receive bits. When less than 16 + /// bits are selected, the more significant among these bits read as zeroes. + DATAHIGH: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x8); + + /// address: 0x4002000c + /// SPI Clock Counter Register. This register controls the frequency of a master's + /// SCK0. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// SPI0 Clock counter setting. + COUNTER: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x4002001c + /// SPI Interrupt Flag. This register contains the interrupt flag for the SPI + /// interface. + pub const INT = @intToPtr(*volatile Mmio(32, packed struct { + /// SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared + /// by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at + /// least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit + /// is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be + /// processed by interrupt handling software. + SPIF: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u7, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x1c); + }; + /// Real Time Clock (RTC) + pub const RTC = struct { + pub const base_address = 0x40024000; + + /// address: 0x40024000 + /// Interrupt Location Register + pub const ILR = @intToPtr(*volatile Mmio(32, packed struct { + /// When one, the Counter Increment Interrupt block generated an interrupt. Writing + /// a one to this bit location clears the counter increment interrupt. + RTCCIF: u1, + /// When one, the alarm registers generated an interrupt. Writing a one to this bit + /// location clears the alarm interrupt. + RTCALF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u11, + }), base_address + 0x0); + + /// address: 0x40024008 + /// Clock Control Register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock Enable. + CLKEN: u1, + /// CTC Reset. + CTCRST: u1, + /// Internal test mode controls. These bits must be 0 for normal RTC operation. + RESERVED: u2, + /// Calibration counter enable. + CCALEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0x8); + + /// address: 0x4002400c + /// Counter Increment Interrupt Register + pub const CIIR = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, an increment of the Second value generates an interrupt. + IMSEC: u1, + /// When 1, an increment of the Minute value generates an interrupt. + IMMIN: u1, + /// When 1, an increment of the Hour value generates an interrupt. + IMHOUR: u1, + /// When 1, an increment of the Day of Month value generates an interrupt. + IMDOM: u1, + /// When 1, an increment of the Day of Week value generates an interrupt. + IMDOW: u1, + /// When 1, an increment of the Day of Year value generates an interrupt. + IMDOY: u1, + /// When 1, an increment of the Month value generates an interrupt. + IMMON: u1, + /// When 1, an increment of the Year value generates an interrupt. + IMYEAR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x40024010 + /// Alarm Mask Register + pub const AMR = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, the Second value is not compared for the alarm. + AMRSEC: u1, + /// When 1, the Minutes value is not compared for the alarm. + AMRMIN: u1, + /// When 1, the Hour value is not compared for the alarm. + AMRHOUR: u1, + /// When 1, the Day of Month value is not compared for the alarm. + AMRDOM: u1, + /// When 1, the Day of Week value is not compared for the alarm. + AMRDOW: u1, + /// When 1, the Day of Year value is not compared for the alarm. + AMRDOY: u1, + /// When 1, the Month value is not compared for the alarm. + AMRMON: u1, + /// When 1, the Year value is not compared for the alarm. + AMRYEAR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x10); + + /// address: 0x40024014 + /// Consolidated Time Register 0 + pub const CTIME0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Seconds value in the range of 0 to 59 + SECONDS: u6, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u2, + /// Minutes value in the range of 0 to 59 + MINUTES: u6, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u2, + /// Hours value in the range of 0 to 23 + HOURS: u5, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u3, + /// Day of week value in the range of 0 to 6 + DOW: u3, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u5, + }), base_address + 0x14); + + /// address: 0x40024018 + /// Consolidated Time Register 1 + pub const CTIME1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the + /// month and whether it is a leap year). + DOM: u5, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u3, + /// Month value in the range of 1 to 12. + MONTH: u4, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u4, + /// Year value in the range of 0 to 4095. + YEAR: u12, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u4, + }), base_address + 0x18); + + /// address: 0x4002401c + /// Consolidated Time Register 2 + pub const CTIME2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of year value in the range of 1 to 365 (366 for leap years). + DOY: u12, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x1c); + + /// address: 0x40024020 + /// Seconds Counter + pub const SEC = @intToPtr(*volatile Mmio(32, packed struct { + /// Seconds value in the range of 0 to 59 + SECONDS: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x20); + + /// address: 0x40024024 + /// Minutes Register + pub const MIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Minutes value in the range of 0 to 59 + MINUTES: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x24); + + /// address: 0x40024028 + /// Hours Register + pub const HRS = @intToPtr(*volatile Mmio(32, packed struct { + /// Hours value in the range of 0 to 23 + HOURS: u5, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0x28); + + /// address: 0x4002402c + /// Day of Month Register + pub const DOM = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the + /// month and whether it is a leap year). + DOM: u5, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0x2c); + + /// address: 0x40024030 + /// Day of Week Register + pub const DOW = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of week value in the range of 0 to 6. + DOW: u3, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u29, + }), base_address + 0x30); + + /// address: 0x40024034 + /// Day of Year Register + pub const DOY = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of year value in the range of 1 to 365 (366 for leap years). + DOY: u9, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u23, + }), base_address + 0x34); + + /// address: 0x40024038 + /// Months Register + pub const MONTH = @intToPtr(*volatile Mmio(32, packed struct { + /// Month value in the range of 1 to 12. + MONTH: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x38); + + /// address: 0x4002403c + /// Years Register + pub const YEAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Year value in the range of 0 to 4095. + YEAR: u12, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x3c); + + /// address: 0x40024040 + /// Calibration Value Register + pub const CALIBRATION = @intToPtr(*volatile Mmio(32, packed struct { + /// If enabled, the calibration counter counts up to this value. The maximum value + /// is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL + /// = 0. + CALVAL: u17, + /// Calibration direction + CALDIR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x40); + + /// address: 0x40024044 + /// General Purpose Register 0 + pub const GPREG0 = @intToPtr(*volatile Mmio(32, packed struct { + /// General purpose storage. + GP: u32, + }), base_address + 0x44); + + /// address: 0x40024048 + /// General Purpose Register 0 + pub const GPREG1 = @intToPtr(*volatile Mmio(32, packed struct { + /// General purpose storage. + GP: u32, + }), base_address + 0x48); + + /// address: 0x4002404c + /// General Purpose Register 0 + pub const GPREG2 = @intToPtr(*volatile Mmio(32, packed struct { + /// General purpose storage. + GP: u32, + }), base_address + 0x4c); + + /// address: 0x40024050 + /// General Purpose Register 0 + pub const GPREG3 = @intToPtr(*volatile Mmio(32, packed struct { + /// General purpose storage. + GP: u32, + }), base_address + 0x50); + + /// address: 0x40024054 + /// General Purpose Register 0 + pub const GPREG4 = @intToPtr(*volatile Mmio(32, packed struct { + /// General purpose storage. + GP: u32, + }), base_address + 0x54); + + /// address: 0x4002405c + /// RTC Auxiliary control register + pub const RTC_AUX = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator + /// stops, and when RTC power is first turned on. An interrupt will occur when this + /// bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is + /// enabled in the NVIC. Write: writing a 1 to this bit clears the flag. + RTC_OSCF: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM + /// pin indicates Deep Power-down mode. + RTC_PDOUT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u25, + }), base_address + 0x5c); + + /// address: 0x40024058 + /// RTC Auxiliary Enable register + pub const RTC_AUXEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect + /// interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is + /// enabled. See Section 30.6.2.5. + RTC_OSCFEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0x58); + + /// address: 0x40024060 + /// Alarm value for Seconds + pub const ASEC = @intToPtr(*volatile Mmio(32, packed struct { + /// Seconds value in the range of 0 to 59 + SECONDS: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x60); + + /// address: 0x40024064 + /// Alarm value for Minutes + pub const AMIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Minutes value in the range of 0 to 59 + MINUTES: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x64); + + /// address: 0x40024068 + /// Alarm value for Hours + pub const AHRS = @intToPtr(*volatile Mmio(32, packed struct { + /// Hours value in the range of 0 to 23 + HOURS: u5, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0x68); + + /// address: 0x4002406c + /// Alarm value for Day of Month + pub const ADOM = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the + /// month and whether it is a leap year). + DOM: u5, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0x6c); + + /// address: 0x40024070 + /// Alarm value for Day of Week + pub const ADOW = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of week value in the range of 0 to 6. + DOW: u3, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u29, + }), base_address + 0x70); + + /// address: 0x40024074 + /// Alarm value for Day of Year + pub const ADOY = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of year value in the range of 1 to 365 (366 for leap years). + DOY: u9, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u23, + }), base_address + 0x74); + + /// address: 0x40024078 + /// Alarm value for Months + pub const AMON = @intToPtr(*volatile Mmio(32, packed struct { + /// Month value in the range of 1 to 12. + MONTH: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x78); + + /// address: 0x4002407c + /// Alarm value for Year + pub const AYRS = @intToPtr(*volatile Mmio(32, packed struct { + /// Year value in the range of 0 to 4095. + YEAR: u12, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x7c); + }; + /// GPIO + pub const GPIOINT = struct { + pub const base_address = 0x40028080; + + /// address: 0x40028080 + /// GPIO overall Interrupt Status. + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 GPIO interrupt pending. + P0INT: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u1, + /// Port 2 GPIO interrupt pending. + P2INT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x40028084 + /// GPIO Interrupt Status for Rising edge for Port 0. + pub const STATR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_0REI: u1, + /// Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_1REI: u1, + /// Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_2REI: u1, + /// Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_3REI: u1, + /// Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_4REI: u1, + /// Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_5REI: u1, + /// Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_6REI: u1, + /// Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_7REI: u1, + /// Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_8REI: u1, + /// Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_9REI: u1, + /// Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_10REI: u1, + /// Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_11REI: u1, + /// Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_12REI: u1, + /// Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_13REI: u1, + /// Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_14REI: u1, + /// Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_15REI: u1, + /// Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_16REI: u1, + /// Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_17REI: u1, + /// Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_18REI: u1, + /// Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_19REI: u1, + /// Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_20REI: u1, + /// Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_21REI: u1, + /// Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_22REI: u1, + /// Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_23REI: u1, + /// Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_24REI: u1, + /// Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_25REI: u1, + /// Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_26REI: u1, + /// Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_27REI: u1, + /// Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_28REI: u1, + /// Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_29REI: u1, + /// Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_30REI: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0x4); + + /// address: 0x40028088 + /// GPIO Interrupt Status for Falling edge for Port 0. + pub const STATF0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_0FEI: u1, + /// Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_1FEI: u1, + /// Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_2FEI: u1, + /// Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_3FEI: u1, + /// Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_4FEI: u1, + /// Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_5FEI: u1, + /// Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_6FEI: u1, + /// Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_7FEI: u1, + /// Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_8FEI: u1, + /// Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_9FEI: u1, + /// Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_10FEI: u1, + /// Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_11FEI: u1, + /// Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_12FEI: u1, + /// Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_13FEI: u1, + /// Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_14FEI: u1, + /// Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_15FEI: u1, + /// Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_16FEI: u1, + /// Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_17FEI: u1, + /// Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_18FEI: u1, + /// Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_19FEI: u1, + /// Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_20FEI: u1, + /// Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_21FEI: u1, + /// Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_22FEI: u1, + /// Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_23FEI: u1, + /// Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_24FEI: u1, + /// Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_25FEI: u1, + /// Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_26FEI: u1, + /// Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_27FEI: u1, + /// Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_28FEI: u1, + /// Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_29FEI: u1, + /// Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_30FEI: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0x8); + + /// address: 0x4002808c + /// GPIO Interrupt Clear. + pub const CLR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_0CI: u1, + /// Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_1CI: u1, + /// Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_2CI: u1, + /// Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_3CI: u1, + /// Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_4CI: u1, + /// Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_5CI: u1, + /// Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_6CI: u1, + /// Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_7CI: u1, + /// Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_8CI: u1, + /// Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_9CI: u1, + /// Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_10CI: u1, + /// Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_11CI: u1, + /// Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_12CI: u1, + /// Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_13CI: u1, + /// Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_14CI: u1, + /// Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_15CI: u1, + /// Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_16CI: u1, + /// Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_17CI: u1, + /// Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_18CI: u1, + /// Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_19CI: u1, + /// Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_20CI: u1, + /// Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_21CI: u1, + /// Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_22CI: u1, + /// Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_23CI: u1, + /// Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_24CI: u1, + /// Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_25CI: u1, + /// Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_26CI: u1, + /// Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_27CI: u1, + /// Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_28CI: u1, + /// Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_29CI: u1, + /// Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_30CI: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0xc); + + /// address: 0x40028090 + /// GPIO Interrupt Enable for Rising edge for Port 0. + pub const ENR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_0ER: u1, + /// Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_1ER: u1, + /// Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_2ER: u1, + /// Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_3ER: u1, + /// Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_4ER: u1, + /// Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_5ER: u1, + /// Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_6ER: u1, + /// Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_7ER: u1, + /// Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_8ER: u1, + /// Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_9ER: u1, + /// Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_10ER: u1, + /// Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_11ER: u1, + /// Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_12ER: u1, + /// Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_13ER: u1, + /// Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_14ER: u1, + /// Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_15ER: u1, + /// Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_16ER: u1, + /// Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_17ER: u1, + /// Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_18ER: u1, + /// Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_19ER: u1, + /// Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_20ER: u1, + /// Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_21ER: u1, + /// Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_22ER: u1, + /// Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_23ER: u1, + /// Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_24ER: u1, + /// Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_25ER: u1, + /// Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_26ER: u1, + /// Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_27ER: u1, + /// Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_28ER: u1, + /// Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_29ER: u1, + /// Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_30ER: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0x10); + + /// address: 0x40028094 + /// GPIO Interrupt Enable for Falling edge for Port 0. + pub const ENF0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_0EF: u1, + /// Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_1EF: u1, + /// Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_2EF: u1, + /// Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_3EF: u1, + /// Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_4EF: u1, + /// Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_5EF: u1, + /// Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_6EF: u1, + /// Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_7EF: u1, + /// Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_8EF: u1, + /// Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_9EF: u1, + /// Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_10EF: u1, + /// Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_11EF: u1, + /// Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_12EF: u1, + /// Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_13EF: u1, + /// Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_14EF: u1, + /// Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_15EF: u1, + /// Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_16EF: u1, + /// Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_17EF: u1, + /// Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_18EF: u1, + /// Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_19EF: u1, + /// Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_20EF: u1, + /// Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_21EF: u1, + /// Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_22EF: u1, + /// Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_23EF: u1, + /// Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_24EF: u1, + /// Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_25EF: u1, + /// Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_26EF: u1, + /// Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_27EF: u1, + /// Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_28EF: u1, + /// Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_29EF: u1, + /// Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_30EF: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0x14); + + /// address: 0x400280a4 + /// GPIO Interrupt Status for Rising edge for Port 0. + pub const STATR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_0REI: u1, + /// Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_1REI: u1, + /// Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_2REI: u1, + /// Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_3REI: u1, + /// Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_4REI: u1, + /// Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_5REI: u1, + /// Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_6REI: u1, + /// Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_7REI: u1, + /// Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_8REI: u1, + /// Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_9REI: u1, + /// Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_10REI: u1, + /// Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_11REI: u1, + /// Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_12REI: u1, + /// Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_13REI: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x24); + + /// address: 0x400280a8 + /// GPIO Interrupt Status for Falling edge for Port 0. + pub const STATF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_0FEI: u1, + /// Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_1FEI: u1, + /// Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_2FEI: u1, + /// Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_3FEI: u1, + /// Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_4FEI: u1, + /// Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_5FEI: u1, + /// Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_6FEI: u1, + /// Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_7FEI: u1, + /// Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_8FEI: u1, + /// Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_9FEI: u1, + /// Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_10FEI: u1, + /// Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_11FEI: u1, + /// Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_12FEI: u1, + /// Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_13FEI: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x28); + + /// address: 0x400280ac + /// GPIO Interrupt Clear. + pub const CLR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_0CI: u1, + /// Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_1CI: u1, + /// Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_2CI: u1, + /// Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_3CI: u1, + /// Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_4CI: u1, + /// Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_5CI: u1, + /// Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_6CI: u1, + /// Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_7CI: u1, + /// Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_8CI: u1, + /// Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_9CI: u1, + /// Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_10CI: u1, + /// Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_11CI: u1, + /// Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_12CI: u1, + /// Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_13CI: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x2c); + + /// address: 0x400280b0 + /// GPIO Interrupt Enable for Rising edge for Port 0. + pub const ENR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_0ER: u1, + /// Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_1ER: u1, + /// Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_2ER: u1, + /// Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_3ER: u1, + /// Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_4ER: u1, + /// Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_5ER: u1, + /// Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_6ER: u1, + /// Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_7ER: u1, + /// Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_8ER: u1, + /// Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_9ER: u1, + /// Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_10ER: u1, + /// Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_11ER: u1, + /// Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_12ER: u1, + /// Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_13ER: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x30); + + /// address: 0x400280b4 + /// GPIO Interrupt Enable for Falling edge for Port 0. + pub const ENF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_0EF: u1, + /// Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_1EF: u1, + /// Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_2EF: u1, + /// Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_3EF: u1, + /// Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_4EF: u1, + /// Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_5EF: u1, + /// Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_6EF: u1, + /// Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_7EF: u1, + /// Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_8EF: u1, + /// Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_9EF: u1, + /// Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P2_10EF: u1, + /// Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P2_11EF: u1, + /// Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P2_12EF: u1, + /// Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P2_13EF: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x34); + }; + /// Pin connect block + pub const PINCONNECT = struct { + pub const base_address = 0x4002c000; + + /// address: 0x4002c000 + /// Pin function select register 0. + pub const PINSEL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pin function select P0.0. + P0_0: u2, + /// Pin function select P0.1. + P0_1: u2, + /// Pin function select P0.2. + P0_2: u2, + /// Pin function select P0.3. + P0_3: u2, + /// Pin function select P0.4. + P0_4: u2, + /// Pin function select P0.5. + P0_5: u2, + /// Pin function select P0.6. + P0_6: u2, + /// Pin function select P0.7. + P0_7: u2, + /// Pin function select P0.8. + P0_8: u2, + /// Pin function select P0.9. + P0_9: u2, + /// Pin function select P0.10. + P0_10: u2, + /// Pin function select P0.11. + P0_11: u2, + /// Reserved. + RESERVED: u6, + /// Pin function select P0.15. + P0_15: u2, + }), base_address + 0x0); + + /// address: 0x4002c004 + /// Pin function select register 1. + pub const PINSEL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pin function select P0.16. + P0_16: u2, + /// Pin function select P0.17. + P0_17: u2, + /// Pin function select P0.18. + P0_18: u2, + /// Pin function select P019. + P0_19: u2, + /// Pin function select P0.20. + P0_20: u2, + /// Pin function select P0.21. + P0_21: u2, + /// Pin function select P022 + P0_22: u2, + /// Pin function select P023. + P0_23: u2, + /// Pin function select P0.24. + P0_24: u2, + /// Pin function select P0.25. + P0_25: u2, + /// Pin function select P0.26. + P0_26: u2, + /// Pin function select P0.27. + P0_27: u2, + /// Pin function select P0.28. + P0_28: u2, + /// Pin function select P0.29 + P0_29: u2, + /// Pin function select P0.30. + P0_30: u2, + /// Reserved + RESERVED: u2, + }), base_address + 0x4); + + /// address: 0x4002c008 + /// Pin function select register 2. + pub const PINSEL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pin function select P1.0. + P1_0: u2, + /// Pin function select P1.1. + P1_1: u2, + /// Reserved. + RESERVED: u4, + /// Pin function select P1.4. + P1_4: u2, + /// Reserved. + RESERVED: u6, + /// Pin function select P1.8. + P1_8: u2, + /// Pin function select P1.9. + P1_9: u2, + /// Pin function select P1.10. + P1_10: u2, + /// Pin function select P1.14. + P1_14: u2, + /// Reserved. + RESERVED: u6, + /// Pin function select P1.15. + P1_15: u2, + }), base_address + 0x8); + + /// address: 0x4002c00c + /// Pin function select register 3. + pub const PINSEL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pin function select P1.16. + P1_16: u2, + /// Pin function select P1.17. + P1_17: u2, + /// Pin function select P1.18. + P1_18: u2, + /// Pin function select P1.19. + P1_19: u2, + /// Pin function select P1.20. + P1_20: u2, + /// Pin function select P1.21. + P1_21: u2, + /// Pin function select P1.22 + P1_22: u2, + /// Pin function select P1.23. + P1_23: u2, + /// Pin function select P1.24. + P1_24: u2, + /// Pin function select P1.25. + P1_25: u2, + /// Pin function select P1.26. + P1_26: u2, + /// Pin function select P1.27. + P1_27: u2, + /// Pin function select P1.28. + P1_28: u2, + /// Pin function select P1.29 + P1_29: u2, + /// Pin function select P1.30. + P1_30: u2, + /// Pin function select P1.31. + P1_31: u2, + }), base_address + 0xc); + + /// address: 0x4002c010 + /// Pin function select register 4 + pub const PINSEL4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pin function select P2.0. + P2_0: u2, + /// Pin function select P2.1. + P2_1: u2, + /// Pin function select P2.2. + P2_2: u2, + /// Pin function select P2.3. + P2_3: u2, + /// Pin function select P2.4. + P2_4: u2, + /// Pin function select P2.5. + P2_5: u2, + /// Pin function select P2.6. + P2_6: u2, + /// Pin function select P2.7. + P2_7: u2, + /// Pin function select P2.8. + P2_8: u2, + /// Pin function select P2.9. + P2_9: u2, + /// Pin function select P2.10. + P2_10: u2, + /// Pin function select P2.11. + P2_11: u2, + /// Pin function select P2.12. + P2_12: u2, + /// Pin function select P2.13. + P2_13: u2, + /// Reserved. + RESERVED: u4, + }), base_address + 0x10); + + /// address: 0x4002c01c + /// Pin function select register 7 + pub const PINSEL7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u18, + /// Pin function select P3.25. + P3_25: u2, + /// Pin function select P3.26. + P3_26: u2, + /// Reserved. + RESERVED: u10, + }), base_address + 0x1c); + + /// address: 0x4002c024 + /// Pin function select register 9 + pub const PINSEL9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u24, + /// Pin function select P4.28. + P4_28: u2, + /// Pin function select P4.29. + P4_29: u2, + /// Reserved. + RESERVED: u4, + }), base_address + 0x24); + + /// address: 0x4002c028 + /// Pin function select register 10 + pub const PINSEL10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Software should not write 1 to these bits. + RESERVED: u3, + /// TPIU interface pins control. + TPIUCTRL: u1, + /// Reserved. Software should not write 1 to these bits. + RESERVED: u28, + }), base_address + 0x28); + + /// address: 0x4002c040 + /// Pin mode select register 0 + pub const PINMODE0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 pin 0 on-chip pull-up/down resistor control. + P0_00MODE: u2, + /// Port 0 pin 1 control. + P0_01MODE: u2, + /// Port 0 pin 2 control. + P0_02MODE: u2, + /// Port 0 pin 3 control. + P0_03MODE: u2, + /// Port 0 pin 4 control. + P0_04MODE: u2, + /// Port 0 pin 5 control. + P0_05MODE: u2, + /// Port 0 pin 6 control. + P0_06MODE: u2, + /// Port 0 pin 7 control. + P0_07MODE: u2, + /// Port 0 pin 8 control. + P0_08MODE: u2, + /// Port 0 pin 9 control. + P0_09MODE: u2, + /// Port 0 pin 10 control. + P0_10MODE: u2, + /// Port 0 pin 11 control. + P0_11MODE: u2, + /// Reserved. + RESERVED: u6, + /// Port 0 pin 15 control. + P0_15MODE: u2, + }), base_address + 0x40); + + /// address: 0x4002c044 + /// Pin mode select register 1 + pub const PINMODE1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 1 pin 16 control. + P0_16MODE: u2, + /// Port 1 pin 17 control. + P0_17MODE: u2, + /// Port 1 pin 18 control. + P0_18MODE: u2, + /// Port 1 pin 19 control. + P0_19MODE: u2, + /// Port 1 pin 20 control. + P0_20MODE: u2, + /// Port 1 pin 21 control. + P0_21MODE: u2, + /// Port 1 pin 22 control. + P0_22MODE: u2, + /// Port 1 pin 23 control. + P0_23MODE: u2, + /// Port 1 pin 24 control. + P0_24MODE: u2, + /// Port 1 pin 25 control. + P0_25MODE: u2, + /// Port 1 pin 26 control. + P0_26MODE: u2, + /// Reserved. + RESERVED: u8, + /// Reserved. + RESERVED: u2, + }), base_address + 0x44); + + /// address: 0x4002c048 + /// Pin mode select register 2 + pub const PINMODE2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 1 pin 0 control. + P1_00MODE: u2, + /// Port 1 pin 1 control. + P1_01MODE: u2, + /// Reserved. + RESERVED: u4, + /// Port 1 pin 4 control. + P1_04MODE: u2, + /// Reserved. + RESERVED: u6, + /// Port 1 pin 8 control. + P1_08MODE: u2, + /// Port 1 pin 9 control. + P1_09MODE: u2, + /// Port 1 pin 10 control. + P1_10MODE: u2, + /// Reserved. + RESERVED: u6, + /// Port 1 pin 14 control. + P1_14MODE: u2, + /// Port 1 pin 15 control. + P1_15MODE: u2, + }), base_address + 0x48); + + /// address: 0x4002c04c + /// Pin mode select register 3. + pub const PINMODE3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 1 pin 16 control. + P1_16MODE: u2, + /// Port 1 pin 17 control. + P1_17MODE: u2, + /// Port 1 pin 18 control. + P1_18MODE: u2, + /// Port 1 pin 19 control. + P1_19MODE: u2, + /// Port 1 pin 20 control. + P1_20MODE: u2, + /// Port 1 pin 21 control. + P1_21MODE: u2, + /// Port 1 pin 22 control. + P1_22MODE: u2, + /// Port 1 pin 23 control. + P1_23MODE: u2, + /// Port 1 pin 24 control. + P1_24MODE: u2, + /// Port 1 pin 25 control. + P1_25MODE: u2, + /// Port 1 pin 26 control. + P1_26MODE: u2, + /// Port 1 pin 27 control. + P1_27MODE: u2, + /// Port 1 pin 28 control. + P1_28MODE: u2, + /// Port 1 pin 29 control. + P1_29MODE: u2, + /// Port 1 pin 30 control. + P1_30MODE: u2, + /// Port 1 pin 31 control. + P1_31MODE: u2, + }), base_address + 0x4c); + + /// address: 0x4002c050 + /// Pin mode select register 4 + pub const PINMODE4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 2 pin 0 control. + P2_00MODE: u2, + /// Port 2 pin 1 control. + P2_01MODE: u2, + /// Port 2 pin 2 control. + P2_02MODE: u2, + /// Port 2 pin 3 control. + P2_03MODE: u2, + /// Port 2 pin 4 control. + P2_04MODE: u2, + /// Port 2 pin 5 control. + P2_05MODE: u2, + /// Port 2 pin 6 control. + P2_06MODE: u2, + /// Port 2 pin 7 control. + P2_07MODE: u2, + /// Port 2 pin 8 control. + P2_08MODE: u2, + /// Port 2 pin 9 control. + P2_09MODE: u2, + /// Port 2 pin 10 control. + P2_10MODE: u2, + /// Port 2 pin 11 control. + P2_11MODE: u2, + /// Port 2 pin 12 control. + P2_12MODE: u2, + /// Port 2 pin 13 control. + P2_13MODE: u2, + /// Reserved. + RESERVED: u4, + }), base_address + 0x50); + + /// address: 0x4002c05c + /// Pin mode select register 7 + pub const PINMODE7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved + RESERVED: u18, + /// Port 3 pin 25 control. + P3_25MODE: u2, + /// Port 3 pin 26 control. + P3_26MODE: u2, + /// Reserved. + RESERVED: u10, + }), base_address + 0x5c); + + /// address: 0x4002c064 + /// Pin mode select register 9 + pub const PINMODE9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u24, + /// Port 4 pin 28 control. + P4_28MODE: u2, + /// Port 4 pin 29 control. + P4_29MODE: u2, + /// Reserved. + RESERVED: u4, + }), base_address + 0x64); + + /// address: 0x4002c068 + /// Open drain mode control register 0 + pub const PINMODE_OD0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses + /// using standard port pins. If so, they should be configured for open drain mode + /// via the related bits in PINMODE_OD0. + P0_00OD: u1, + /// Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses + /// using standard port pins. If so, they should be configured for open drain mode + /// via the related bits in PINMODE_OD0. + P0_01OD: u1, + /// Port 0 pin 2 open drain mode control + P0_02OD: u1, + /// Port 0 pin 3 open drain mode control + P0_03OD: u1, + /// Port 0 pin 4 open drain mode control + P0_04OD: u1, + /// Port 0 pin 5 open drain mode control + P0_05OD: u1, + /// Port 0 pin 6 open drain mode control + P0_06OD: u1, + /// Port 0 pin 7 open drain mode control + P0_07OD: u1, + /// Port 0 pin 8 open drain mode control + P0_08OD: u1, + /// Port 0 pin 9 open drain mode control + P0_09OD: u1, + /// Port 0 pin 10 open drain mode control. Pins may potentially be used for + /// I2C-buses using standard port pins. If so, they should be configured for open + /// drain mode via the related bits in PINMODE_OD0. + P0_10OD: u1, + /// Port 0 pin 11 open drain mode control. Pins may potentially be used for + /// I2C-buses using standard port pins. If so, they should be configured for open + /// drain mode via the related bits in PINMODE_OD0. + P0_11OD: u1, + /// Reserved. + RESERVED: u3, + /// Port 0 pin 15 open drain mode control + P0_15OD: u1, + /// Port 0 pin 16 open drain mode control + P0_16OD: u1, + /// Port 0 pin 17 open drain mode control + P0_17OD: u1, + /// Port 0 pin 18 open drain mode control + P0_18OD: u1, + /// Port 0 pin 19 open drain mode control. Pins may potentially be used for + /// I2C-buses using standard port pins. If so, they should be configured for open + /// drain mode via the related bits in PINMODE_OD0. + P0_19OD: u1, + /// Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses + /// using standard port pins. If so, they should be configured for open drain mode + /// via the related bits in PINMODE_OD0. + P0_20OD: u1, + /// Port 0 pin 21 open drain mode control + P0_21OD: u1, + /// Port 0 pin 22 open drain mode control + P0_22OD: u1, + /// Port 0 pin 23 open drain mode control + P0_23OD: u1, + /// Port 0 pin 24open drain mode control + P0_24OD: u1, + /// Port 0 pin 25 open drain mode control + P0_25OD: u1, + /// Port 0 pin 26 open drain mode control + P0_26OD: u1, + /// Reserved. + RESERVED: u2, + /// Port 0 pin 29 open drain mode control + P0_29OD: u1, + /// Port 0 pin 30 open drain mode control + P0_30OD: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0x68); + + /// address: 0x4002c06c + /// Open drain mode control register 1 + pub const PINMODE_OD1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 1 pin 0 open drain mode control. + P1_00OD: u1, + /// Port 1 pin 1 open drain mode control, see P1.00OD + P1_01OD: u1, + /// Reserved. + RESERVED: u2, + /// Port 1 pin 4 open drain mode control, see P1.00OD + P1_04OD: u1, + /// Reserved. + RESERVED: u3, + /// Port 1 pin 8 open drain mode control, see P1.00OD + P1_08OD: u1, + /// Port 1 pin 9 open drain mode control, see P1.00OD + P1_09OD: u1, + /// Port 1 pin 10 open drain mode control, see P1.00OD + P1_10OD: u1, + /// Reserved. + RESERVED: u3, + /// Port 1 pin 14 open drain mode control, see P1.00OD + P1_14OD: u1, + /// Port 1 pin 15 open drain mode control, see P1.00OD + P1_15OD: u1, + /// Port 1 pin 16 open drain mode control, see P1.00OD + P1_16OD: u1, + /// Port 1 pin 17 open drain mode control, see P1.00OD + P1_17OD: u1, + /// Port 1 pin 18 open drain mode control, see P1.00OD + P1_18OD: u1, + /// Port 1 pin 19 open drain mode control, see P1.00OD + P1_19OD: u1, + /// Port 1 pin 20open drain mode control, see P1.00OD + P1_20OD: u1, + /// Port 1 pin 21 open drain mode control, see P1.00OD + P1_21OD: u1, + /// Port 1 pin 22 open drain mode control, see P1.00OD + P1_22OD: u1, + /// Port 1 pin 23 open drain mode control, see P1.00OD + P1_23OD: u1, + /// Port 1 pin 24open drain mode control, see P1.00OD + P1_24OD: u1, + /// Port 1 pin 25 open drain mode control, see P1.00OD + P1_25OD: u1, + /// Port 1 pin 26 open drain mode control, see P1.00OD + P1_26OD: u1, + /// Port 1 pin 27 open drain mode control, see P1.00OD + P1_27OD: u1, + /// Port 1 pin 28 open drain mode control, see P1.00OD + P1_28OD: u1, + /// Port 1 pin 29 open drain mode control, see P1.00OD + P1_29OD: u1, + /// Port 1 pin 30 open drain mode control, see P1.00OD + P1_30OD: u1, + /// Port 1 pin 31 open drain mode control. + P1_31OD: u1, + }), base_address + 0x6c); + + /// address: 0x4002c070 + /// Open drain mode control register 2 + pub const PINMODE_OD2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 2 pin 0 open drain mode control. + P2_00OD: u1, + /// Port 2 pin 1 open drain mode control, see P2.00OD + P2_01OD: u1, + /// Port 2 pin 2 open drain mode control, see P2.00OD + P2_02OD: u1, + /// Port 2 pin 3 open drain mode control, see P2.00OD + P2_03OD: u1, + /// Port 2 pin 4 open drain mode control, see P2.00OD + P2_04OD: u1, + /// Port 2 pin 5 open drain mode control, see P2.00OD + P2_05OD: u1, + /// Port 2 pin 6 open drain mode control, see P2.00OD + P2_06OD: u1, + /// Port 2 pin 7 open drain mode control, see P2.00OD + P2_07OD: u1, + /// Port 2 pin 8 open drain mode control, see P2.00OD + P2_08OD: u1, + /// Port 2 pin 9 open drain mode control, see P2.00OD + P2_09OD: u1, + /// Port 2 pin 10 open drain mode control, see P2.00OD + P2_10OD: u1, + /// Port 2 pin 11 open drain mode control, see P2.00OD + P2_11OD: u1, + /// Port 2 pin 12 open drain mode control, see P2.00OD + P2_12OD: u1, + /// Port 2 pin 13 open drain mode control, see P2.00OD + P2_13OD: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x70); + + /// address: 0x4002c074 + /// Open drain mode control register 3 + pub const PINMODE_OD3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u25, + /// Port 3 pin 25 open drain mode control. + P3_25OD: u1, + /// Port 3 pin 26 open drain mode control, see P3.25OD + P3_26OD: u1, + /// Reserved. + RESERVED: u5, + }), base_address + 0x74); + + /// address: 0x4002c078 + /// Open drain mode control register 4 + pub const PINMODE_OD4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u28, + /// Port 4 pin 28 open drain mode control. + P4_28OD: u1, + /// Port 4 pin 29 open drain mode control, see P4.28OD + P4_29OD: u1, + /// Reserved. + RESERVED: u2, + }), base_address + 0x78); + + /// address: 0x4002c07c + /// I2C Pin Configuration register + pub const I2CPADCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Drive mode control for the SDA0 pin, P0.27. + SDADRV0: u1, + /// I 2C filter mode control for the SDA0 pin, P0.27. + SDAI2C0: u1, + /// Drive mode control for the SCL0 pin, P0.28. + SCLDRV0: u1, + /// I 2C filter mode control for the SCL0 pin, P0.28. + SCLI2C0: u1, + /// Reserved. + RESERVED: u28, + }), base_address + 0x7c); + }; + /// SSP1 controller + pub const SSP1 = struct { + pub const base_address = 0x40030000; + + /// address: 0x40030000 + /// Control Register 0. Selects the serial clock rate, bus type, and data size. + pub const CR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Size Select. This field controls the number of bits transferred in each + /// frame. Values 0000-0010 are not supported and should not be used. + DSS: u4, + /// Frame Format. + FRF: u2, + /// Clock Out Polarity. This bit is only used in SPI mode. + CPOL: u1, + /// Clock Out Phase. This bit is only used in SPI mode. + CPHA: u1, + /// Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, + /// minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK + /// clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). + SCR: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x0); + + /// address: 0x40030004 + /// Control Register 1. Selects master/slave and other modes. + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Loop Back Mode. + LBM: u1, + /// SSP Enable. + SSE: u1, + /// Master/Slave Mode.This bit can only be written when the SSE bit is 0. + MS: u1, + /// Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is + /// 1, this blocks this SSP controller from driving the transmit data line (MISO). + SOD: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x4); + + /// address: 0x40030008 + /// Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Write: software can write data to be sent in a future frame to this register + /// whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is + /// not full. If the Tx FIFO was previously empty and the SSP controller is not busy + /// on the bus, transmission of the data will begin immediately. Otherwise the data + /// written to this register will be sent as soon as all previous data has been sent + /// (and received). If the data length is less than 16 bits, software must + /// right-justify the data written to this register. Read: software can read data + /// from this register whenever the RNE bit in the Status register is 1, indicating + /// that the Rx FIFO is not empty. When software reads this register, the SSP + /// controller returns data from the least recent frame in the Rx FIFO. If the data + /// length is less than 16 bits, the data is right-justified in this field with + /// higher order bits filled with 0s. + DATA: u16, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x8); + + /// address: 0x4003000c + /// Status Register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. + TFE: u1, + /// Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. + TNF: u1, + /// Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. + RNE: u1, + /// Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. + RFF: u1, + /// Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently + /// sending/receiving a frame and/or the Tx FIFO is not empty. + BSY: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0xc); + + /// address: 0x40030010 + /// Clock Prescale Register + pub const CPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// This even value between 2 and 254, by which PCLK is divided to yield the + /// prescaler output clock. Bit 0 always reads as 0. + CPSDVSR: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x10); + + /// address: 0x40030014 + /// Interrupt Mask Set and Clear Register + pub const IMSC = @intToPtr(*volatile Mmio(32, packed struct { + /// Software should set this bit to enable interrupt when a Receive Overrun occurs, + /// that is, when the Rx FIFO is full and another frame is completely received. The + /// ARM spec implies that the preceding frame data is overwritten by the new frame + /// data when this occurs. + RORIM: u1, + /// Software should set this bit to enable interrupt when a Receive Time-out + /// condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and + /// no has not been read for a time-out period. The time-out period is the same for + /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / + /// (CPSDVSR X [SCR+1]). + RTIM: u1, + /// Software should set this bit to enable interrupt when the Rx FIFO is at least + /// half full. + RXIM: u1, + /// Software should set this bit to enable interrupt when the Tx FIFO is at least + /// half empty. + TXIM: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x14); + + /// address: 0x40030018 + /// Raw Interrupt Status Register + pub const RIS = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit is 1 if another frame was completely received while the RxFIFO was + /// full. The ARM spec implies that the preceding frame data is overwritten by the + /// new frame data when this occurs. + RORRIS: u1, + /// This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out + /// period. The time-out period is the same for master and slave modes and is + /// determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RTRIS: u1, + /// This bit is 1 if the Rx FIFO is at least half full. + RXRIS: u1, + /// This bit is 1 if the Tx FIFO is at least half empty. + TXRIS: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x18); + + /// address: 0x4003001c + /// Masked Interrupt Status Register + pub const MIS = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit is 1 if another frame was completely received while the RxFIFO was + /// full, and this interrupt is enabled. + RORMIS: u1, + /// This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out + /// period, and this interrupt is enabled. The time-out period is the same for + /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / + /// (CPSDVSR X [SCR+1]). + RTMIS: u1, + /// This bit is 1 if the Rx FIFO is at least half full, and this interrupt is + /// enabled. + RXMIS: u1, + /// This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is + /// enabled. + TXMIS: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x1c); + + /// address: 0x40030020 + /// SSPICR Interrupt Clear Register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 to this bit clears the frame was received when RxFIFO was full + /// interrupt. + RORIC: u1, + /// Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read + /// for a time-out period interrupt. The time-out period is the same for master and + /// slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / + /// [SCR+1]). + RTIC: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x20); + + /// address: 0x40030024 + /// SSP0 DMA control register + pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is + /// enabled, otherwise receive DMA is disabled. + RXDMAE: u1, + /// Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is + /// enabled, otherwise transmit DMA is disabled + TXDMAE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x24); + }; + /// Analog-to-Digital Converter (ADC) + pub const ADC = struct { + pub const base_address = 0x40034000; + + /// address: 0x40034000 + /// A/D Control Register. The ADCR register must be written to select the operating + /// mode before A/D conversion can occur. + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For + /// AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In + /// software-controlled mode, only one of these bits should be 1. In hardware scan + /// mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to + /// 0x01. + SEL: u8, + /// The APB clock (PCLK) is divided by (this value plus one) to produce the clock + /// for the A/D converter, which should be less than or equal to 12.4 MHz. + /// Typically, software should program the smallest value in this field that yields + /// a clock of 12.4 MHz or slightly less, but in certain cases (such as a + /// high-impedance analog source) a slower clock may be desirable. + CLKDIV: u8, + /// Burst mode + BURST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// Power down mode + PDN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// When the BURST bit is 0, these bits control whether and when an A/D conversion + /// is started: + START: u3, + /// This bit is significant only when the START field contains 010-111. In these + /// cases: + EDGE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + }), base_address + 0x0); + + /// address: 0x40034004 + /// A/D Global Data Register. This register contains the ADC's DONE bit and the + /// result of the most recent A/D conversion. + pub const GDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// When DONE is 1, this field contains a binary fraction representing the voltage + /// on the AD0[n] pin selected by the SEL field, as it falls within the range of + /// VREFP to VSS. Zero in the field indicates that the voltage on the input pin was + /// less than, equal to, or close to that on VSS, while 0xFFF indicates that the + /// voltage on the input was close to, equal to, or greater than that on VREFP. + RESULT: u12, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// These bits contain the channel from which the RESULT bits were converted (e.g. + /// 000 identifies channel 0, 001 channel 1...). + CHN: u3, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u3, + /// This bit is 1 in burst mode if the results of one or more conversions was (were) + /// lost and overwritten before the conversion that produced the result in the + /// RESULT bits. This bit is cleared by reading this register. + OVERRUN: u1, + /// This bit is set to 1 when an A/D conversion completes. It is cleared when this + /// register is read and when the ADCR is written. If the ADCR is written while a + /// conversion is still in progress, this bit is set and a new conversion is + /// started. + DONE: u1, + }), base_address + 0x4); + + /// address: 0x4003400c + /// A/D Interrupt Enable Register. This register contains enable bits that allow the + /// DONE flag of each A/D channel to be included or excluded from contributing to + /// the generation of an A/D interrupt. + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt enable + ADINTEN0: u1, + /// Interrupt enable + ADINTEN1: u1, + /// Interrupt enable + ADINTEN2: u1, + /// Interrupt enable + ADINTEN3: u1, + /// Interrupt enable + ADINTEN4: u1, + /// Interrupt enable + ADINTEN5: u1, + /// Interrupt enable + ADINTEN6: u1, + /// Interrupt enable + ADINTEN7: u1, + /// Interrupt enable + ADGINTEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u23, + }), base_address + 0xc); + + /// address: 0x40034010 + /// A/D Channel 0 Data Register. This register contains the result of the most + /// recent conversion completed on channel 0. + pub const DR = @intToPtr(*volatile [8]Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// When DONE is 1, this field contains a binary fraction representing the voltage + /// on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the + /// field indicates that the voltage on the input pin was less than, equal to, or + /// close to that on VSS, while 0xFFF indicates that the voltage on the input was + /// close to, equal to, or greater than that on VREFP. + RESULT: u12, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u14, + /// This bit is 1 in burst mode if the results of one or more conversions was (were) + /// lost and overwritten before the conversion that produced the result in the + /// RESULT bits.This bit is cleared by reading this register. + OVERRUN: u1, + /// This bit is set to 1 when an A/D conversion completes. It is cleared when this + /// register is read. + DONE: u1, + }), base_address + 0x10); + + /// address: 0x40034030 + /// A/D Status Register. This register contains DONE and OVERRUN flags for all of + /// the A/D channels, as well as the A/D interrupt/DMA flag. + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 0. + DONE0: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 1. + DONE1: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 2. + DONE2: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 3. + DONE3: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 4. + DONE4: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 5. + DONE5: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 6. + DONE6: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 7. + DONE7: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 0. + OVERRUN0: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 1. + OVERRUN1: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 2. + OVERRUN2: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 3. + OVERRUN3: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 4. + OVERRUN4: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 5. + OVERRUN5: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 6. + OVERRUN6: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 7. + OVERRUN7: u1, + /// This bit is the A/D interrupt flag. It is one when any of the individual A/D + /// channel Done flags is asserted and enabled to contribute to the A/D interrupt + /// via the ADINTEN register. + ADINT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u15, + }), base_address + 0x30); + + /// address: 0x40034034 + /// ADC trim register. + pub const TRM = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// Offset trim bits for ADC operation. Initialized by the boot code. Can be + /// overwritten by the user. + ADCOFFS: u4, + /// written-to by boot code. Can not be overwritten by the user. These bits are + /// locked after boot code write. + TRIM: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u20, + }), base_address + 0x34); + }; + /// CAN acceptance filter RAM + pub const CANAFRAM = struct { + pub const base_address = 0x40038000; + + /// address: 0x40038000 + /// CAN AF ram access register + pub const MASK = @intToPtr(*volatile [512]u32, base_address + 0x0); + }; + /// CAN controller acceptance filter + pub const CANAF = struct { + pub const base_address = 0x4003c000; + + /// address: 0x4003c000 + /// Acceptance Filter Register + pub const AFMR = @intToPtr(*volatile Mmio(32, packed struct { + /// if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all + /// CAN buses are ignored. + ACCOFF: u1, + /// All Rx messages are accepted on enabled CAN controllers. Software must set this + /// bit before modifying the contents of any of the registers described below, and + /// before modifying the contents of Lookup Table RAM in any way other than setting + /// or clearing Disable bits in Standard Identifier entries. When both this bit and + /// AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers. + ACCBP: u1, + /// FullCAN mode + EFCAN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u29, + }), base_address + 0x0); + + /// address: 0x4003c004 + /// Standard Frame Individual Start Address Register + pub const SFF_SA = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// The start address of the table of individual Standard Identifiers in AF Lookup + /// RAM. If the table is empty, write the same value in this register and the + /// SFF_GRP_sa register described below. For compatibility with possible future + /// devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit + /// in the AFMR is 1, this value also indicates the size of the table of Standard + /// IDs which the Acceptance Filter will search and (if found) automatically store + /// received messages in Acceptance Filter RAM. + SFF_SA: u9, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x4); + + /// address: 0x4003c008 + /// Standard Frame Group Start Address Register + pub const SFF_GRP_SA = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// The start address of the table of grouped Standard Identifiers in AF Lookup RAM. + /// If the table is empty, write the same value in this register and the EFF_sa + /// register described below. The largest value that should be written to this + /// register is 0x800, when only the Standard Individual table is used, and the last + /// word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with + /// possible future devices, please write zeroes in bits 31:12 and 1:0 of this + /// register. + SFF_GRP_SA: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u20, + }), base_address + 0x8); + + /// address: 0x4003c00c + /// Extended Frame Start Address Register + pub const EFF_SA = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// The start address of the table of individual Extended Identifiers in AF Lookup + /// RAM. If the table is empty, write the same value in this register and the + /// EFF_GRP_sa register described below. The largest value that should be written to + /// this register is 0x800, when both Extended Tables are empty and the last word + /// (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible + /// future devices, please write zeroes in bits 31:11 and 1:0 of this register. + EFF_SA: u9, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0xc); + + /// address: 0x4003c010 + /// Extended Frame Group Start Address Register + pub const EFF_GRP_SA = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// The start address of the table of grouped Extended Identifiers in AF Lookup RAM. + /// If the table is empty, write the same value in this register and the ENDofTable + /// register described below. The largest value that should be written to this + /// register is 0x800, when this table is empty and the last word (address 0x7FC) in + /// AF Lookup Table RAM is used. For compatibility with possible future devices, + /// please write zeroes in bits 31:12 and 1:0 of this register. + EFF_GRP_SA: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u20, + }), base_address + 0x10); + + /// address: 0x4003c014 + /// End of AF Tables register + pub const ENDOFTABLE = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// The address above the last active address in the last active AF table. For + /// compatibility with possible future devices, please write zeroes in bits 31:12 + /// and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value + /// that should be written to this register is 0x800, which allows the last word + /// (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR + /// is 1, this value marks the start of the area of Acceptance Filter RAM, into + /// which the Acceptance Filter will automatically receive messages for selected IDs + /// on selected CAN buses. In this case, the maximum value that should be written to + /// this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes + /// of message storage between this address and the end of Acceptance Filter RAM, + /// for each Standard ID that is specified between the start of Acceptance Filter + /// RAM, and the next active AF table. + ENDOFTABLE: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u20, + }), base_address + 0x14); + + /// address: 0x4003c018 + /// LUT Error Address register + pub const LUTERRAD = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// It the LUT Error bit (below) is 1, this read-only field contains the address in + /// AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the + /// content of the tables. + LUTERRAD: u9, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x18); + + /// address: 0x4003c01c + /// LUT Error Register + pub const LUTERR = @intToPtr(*volatile Mmio(32, packed struct { + /// This read-only bit is set to 1 if the Acceptance Filter encounters an error in + /// the content of the tables in AF RAM. It is cleared when software reads the + /// LUTerrAd register. This condition is ORed with the other CAN interrupts from the + /// CAN controllers, to produce the request that is connected to the NVIC. + LUTERR: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u31, + }), base_address + 0x1c); + + /// address: 0x4003c020 + /// FullCAN interrupt enable register + pub const FCANIE = @intToPtr(*volatile Mmio(32, packed struct { + /// Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. + FCANIE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u31, + }), base_address + 0x20); + + /// address: 0x4003c024 + /// FullCAN interrupt and capture register0 + pub const FCANIC0 = @intToPtr(*volatile Mmio(32, packed struct { + /// FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan + /// Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31. + INTPND: u32, + }), base_address + 0x24); + + /// address: 0x4003c028 + /// FullCAN interrupt and capture register1 + pub const FCANIC1 = @intToPtr(*volatile Mmio(32, packed struct { + /// FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = + /// FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63. + IntPnd32: u32, + }), base_address + 0x28); + }; + /// Central CAN controller + pub const CCAN = struct { + pub const base_address = 0x40040000; + + /// address: 0x40040000 + /// CAN Central Transmit Status Register + pub const TXSR = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). + TS1: u1, + /// When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) + TS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u6, + /// When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same + /// as TBS in CAN1GSR). + TBS1: u1, + /// When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same + /// as TBS in CAN2GSR). + TBS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u6, + /// When 1, all requested transmissions have been completed successfully by the CAN1 + /// controller (same as TCS in CAN1GSR). + TCS1: u1, + /// When 1, all requested transmissions have been completed successfully by the CAN2 + /// controller (same as TCS in CAN2GSR). + TCS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u14, + }), base_address + 0x0); + + /// address: 0x40040004 + /// CAN Central Receive Status Register + pub const RXSR = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, CAN1 is receiving a message (same as RS in CAN1GSR). + RS1: u1, + /// When 1, CAN2 is receiving a message (same as RS in CAN2GSR). + RS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u6, + /// When 1, a received message is available in the CAN1 controller (same as RBS in + /// CAN1GSR). + RB1: u1, + /// When 1, a received message is available in the CAN2 controller (same as RBS in + /// CAN2GSR). + RB2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u6, + /// When 1, a message was lost because the preceding message to CAN1 controller was + /// not read out quickly enough (same as DOS in CAN1GSR). + DOS1: u1, + /// When 1, a message was lost because the preceding message to CAN2 controller was + /// not read out quickly enough (same as DOS in CAN2GSR). + DOS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u14, + }), base_address + 0x4); + + /// address: 0x40040008 + /// CAN Central Miscellaneous Register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit + /// set in the CAN1EWL register (same as ES in CAN1GSR) + E1: u1, + /// When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit + /// set in the CAN2EWL register (same as ES in CAN2GSR) + E2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u6, + /// When 1, the CAN1 controller is currently involved in bus activities (same as BS + /// in CAN1GSR). + BS1: u1, + /// When 1, the CAN2 controller is currently involved in bus activities (same as BS + /// in CAN2GSR). + BS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x8); + }; + /// CAN1 controller + pub const CAN1 = struct { + pub const base_address = 0x40044000; + + /// address: 0x40044000 + /// Controls the operating mode of the CAN Controller. + pub const MOD = @intToPtr(*volatile Mmio(32, packed struct { + /// Reset Mode. + RM: u1, + /// Listen Only Mode. + LOM: u1, + /// Self Test Mode. + STM: u1, + /// Transmit Priority Mode. + TPM: u1, + /// Sleep Mode. + SM: u1, + /// Receive Polarity Mode. + RPM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Test Mode. + TM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x40044004 + /// Command bits that affect the state of the CAN Controller + pub const CMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Request. + TR: u1, + /// Abort Transmission. + AT: u1, + /// Release Receive Buffer. + RRB: u1, + /// Clear Data Overrun. + CDO: u1, + /// Self Reception Request. + SRR: u1, + /// Select Tx Buffer 1. + STB1: u1, + /// Select Tx Buffer 2. + STB2: u1, + /// Select Tx Buffer 3. + STB3: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x40044008 + /// Global Controller Status and Error Counters. The error counters can only be + /// written when RM in CANMOD is 1. + pub const GSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Buffer Status. After reading all messages and releasing their memory + /// space with the command 'Release Receive Buffer,' this bit is cleared. + RBS: u1, + /// Data Overrun Status. If there is not enough space to store the message within + /// the Receive Buffer, that message is dropped and the Data Overrun condition is + /// signalled to the CPU in the moment this message becomes valid. If this message + /// is not completed successfully (e.g. because of an error), no overrun condition + /// is signalled. + DOS: u1, + /// Transmit Buffer Status. + TBS: u1, + /// Transmit Complete Status. The Transmission Complete Status bit is set '0' + /// (incomplete) whenever the Transmission Request bit or the Self Reception Request + /// bit is set '1' at least for one of the three Transmit Buffers. The Transmission + /// Complete Status bit will remain '0' until all messages are transmitted + /// successfully. + TCS: u1, + /// Receive Status. If both the Receive Status and the Transmit Status bits are '0' + /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to + /// become idle again. After hardware reset 11 consecutive recessive bits have to be + /// detected until idle status is reached. After Bus-off this will take 128 times of + /// 11 consecutive recessive bits. + RS: u1, + /// Transmit Status. If both the Receive Status and the Transmit Status bits are '0' + /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to + /// become idle again. After hardware reset 11 consecutive recessive bits have to be + /// detected until idle status is reached. After Bus-off this will take 128 times of + /// 11 consecutive recessive bits. + TS: u1, + /// Error Status. Errors detected during reception or transmission will effect the + /// error counters according to the CAN specification. The Error Status bit is set + /// when at least one of the error counters has reached or exceeded the Error + /// Warning Limit. An Error Warning Interrupt is generated, if enabled. The default + /// value of the Error Warning Limit after hardware reset is 96 decimal, see also + /// Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL + /// - 0x4004 8018). + ES: u1, + /// Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, + /// if enabled. Afterwards the Transmit Error Counter is set to '127', and the + /// Receive Error Counter is cleared. It will stay in this mode until the CPU clears + /// the Reset Mode bit. Once this is completed the CAN Controller will wait the + /// minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting + /// down the Transmit Error Counter. After that, the Bus Status bit is cleared + /// (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, + /// and an Error Warning Interrupt is generated, if enabled. Reading the TX Error + /// Counter during this time gives information about the status of the Bus-Off + /// recovery. + BS: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// The current value of the Rx Error Counter (an 8-bit value). + RXERR: u8, + /// The current value of the Tx Error Counter (an 8-bit value). + TXERR: u8, + }), base_address + 0x8); + + /// address: 0x4004400c + /// Interrupt status, Arbitration Lost Capture, Error Code Capture + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE + /// bit in CANxIER are both 1, indicating that a new message was received and stored + /// in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read + /// access to the Interrupt Register. Giving the Command Release Receive Buffer will + /// clear RI temporarily. If there is another message available within the Receive + /// Buffer after the release command, RI is set again. Otherwise RI remains cleared. + RI: u1, + /// Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB1 was successfully transmitted or aborted), + /// indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is + /// 1. + TI1: u1, + /// Error Warning Interrupt. This bit is set on every change (set or clear) of + /// either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set + /// within the Interrupt Enable Register at the time of the change. + EI: u1, + /// Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 + /// to 1 and the DOIE bit in CANxIER is 1. + DOI: u1, + /// Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus + /// activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is + /// also generated if the CPU tries to set the Sleep bit while the CAN controller is + /// involved in bus activities or a CAN Interrupt is pending. The WUI flag can also + /// get asserted when the according enable bit WUIE is not set. In this case a + /// Wake-Up Interrupt does not get asserted. + WUI: u1, + /// Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and + /// the CAN controller switches between Error Passive and Error Active mode in + /// either direction. This is the case when the CAN Controller has reached the Error + /// Passive Status (at least one error counter exceeds the CAN protocol defined + /// level of 127) or if the CAN Controller is in Error Passive Status and enters the + /// Error Active Status again. + EPI: u1, + /// Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and + /// the CAN controller loses arbitration while attempting to transmit. In this case + /// the CAN node becomes a receiver. + ALI: u1, + /// Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the + /// CAN controller detects an error on the bus. + BEI: u1, + /// ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN + /// Identifier has been received (a message was successfully transmitted or + /// aborted). This bit is set whenever a message was successfully transmitted or + /// aborted and the IDIE bit is set in the IER register. + IDI: u1, + /// Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB2 was successfully transmitted or aborted), + /// indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is + /// 1. + TI2: u1, + /// Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB3 was successfully transmitted or aborted), + /// indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is + /// 1. + TI3: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u5, + /// Error Code Capture: when the CAN controller detects a bus error, the location of + /// the error within the frame is captured in this field. The value reflects an + /// internal state variable, and as a result is not very linear: 00011 = Start of + /// Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE + /// bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit + /// 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = + /// Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot + /// 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever + /// a bus error occurs, the corresponding bus error interrupt is forced, if enabled. + /// At the same time, the current position of the Bit Stream Processor is captured + /// into the Error Code Capture Register. The content within this register is fixed + /// until the user software has read out its content once. From now on, the capture + /// mechanism is activated again, i.e. reading the CANxICR enables another Bus Error + /// Interrupt. + ERRBIT4_0: u5, + /// When the CAN controller detects a bus error, the direction of the current bit is + /// captured in this bit. + ERRDIR: u1, + /// When the CAN controller detects a bus error, the type of error is captured in + /// this field: + ERRC1_0: u2, + /// Each time arbitration is lost while trying to send on the CAN, the bit number + /// within the frame is captured into this field. After the content of ALCBIT is + /// read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 + /// = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost + /// in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE + /// bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 + /// = arbitration lost in last bit of identifier (extended frame only) 31 = + /// arbitration lost in RTR bit (extended frame only) On arbitration lost, the + /// corresponding arbitration lost interrupt is forced, if enabled. At that time, + /// the current bit position of the Bit Stream Processor is captured into the + /// Arbitration Lost Capture Register. The content within this register is fixed + /// until the user application has read out its contents once. From now on, the + /// capture mechanism is activated again. + ALCBIT: u8, + }), base_address + 0xc); + + /// address: 0x40044010 + /// Interrupt Enable + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN + /// Controller requests the respective interrupt. + RIE: u1, + /// Transmit Interrupt Enable for Buffer1. When a message has been successfully + /// transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE1: u1, + /// Error Warning Interrupt Enable. If the Error or Bus Status change (see Status + /// Register), the CAN Controller requests the respective interrupt. + EIE: u1, + /// Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status + /// Register), the CAN Controller requests the respective interrupt. + DOIE: u1, + /// Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the + /// respective interrupt is requested. + WUIE: u1, + /// Error Passive Interrupt Enable. If the error status of the CAN Controller + /// changes from error active to error passive or vice versa, the respective + /// interrupt is requested. + EPIE: u1, + /// Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, + /// the respective interrupt is requested. + ALIE: u1, + /// Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller + /// requests the respective interrupt. + BEIE: u1, + /// ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN + /// Controller requests the respective interrupt. + IDIE: u1, + /// Transmit Interrupt Enable for Buffer2. When a message has been successfully + /// transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE2: u1, + /// Transmit Interrupt Enable for Buffer3. When a message has been successfully + /// transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE3: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x10); + + /// address: 0x40044014 + /// Bus Timing. Can only be written when RM in CANMOD is 1. + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud Rate Prescaler. The APB clock is divided by (this value plus one) to + /// produce the CAN clock. + BRP: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// The Synchronization Jump Width is (this value plus one) CAN clocks. + SJW: u2, + /// The delay from the nominal Sync point to the sample point is (this value plus + /// one) CAN clocks. + TESG1: u4, + /// The delay from the sample point to the next nominal sync point is (this value + /// plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in + /// TSEG1 plus 3) CAN clocks. + TESG2: u3, + /// Sampling + SAM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + }), base_address + 0x14); + + /// address: 0x40044018 + /// Error Warning Limit. Can only be written when RM in CANMOD is 1. + pub const EWL = @intToPtr(*volatile Mmio(32, packed struct { + /// During CAN operation, this value is compared to both the Tx and Rx Error + /// Counters. If either of these counter matches this value, the Error Status (ES) + /// bit in CANSR is set. + EWL: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x4004401c + /// Status Register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_1: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_1: u1, + /// Transmit Buffer Status 1. + TBS1_1: u1, + /// Transmission Complete Status. + TCS1_1: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_1: u1, + /// Transmit Status 1. + TS1_1: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_1: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_1: u1, + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_2: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_2: u1, + /// Transmit Buffer Status 2. + TBS2_2: u1, + /// Transmission Complete Status. + TCS2_2: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_2: u1, + /// Transmit Status 2. + TS2_2: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_2: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_2: u1, + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_3: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_3: u1, + /// Transmit Buffer Status 3. + TBS3_3: u1, + /// Transmission Complete Status. + TCS3_3: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_3: u1, + /// Transmit Status 3. + TS3_3: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_3: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_3: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u8, + }), base_address + 0x1c); + + /// address: 0x40044020 + /// Receive frame status. Can only be written when RM in CANMOD is 1. + pub const RFS = @intToPtr(*volatile Mmio(32, packed struct { + /// ID Index. If the BP bit (below) is 0, this value is the zero-based number of the + /// Lookup Table RAM entry at which the Acceptance Filter matched the received + /// Identifier. Disabled entries in the Standard tables are included in this + /// numbering, but will not be matched. See Section 21.17 Examples of acceptance + /// filter tables and ID index values on page 587 for examples of ID Index values. + IDINDEX: u10, + /// If this bit is 1, the current message was received in AF Bypass mode, and the ID + /// Index field (above) is meaningless. + BP: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u5, + /// The field contains the Data Length Code (DLC) field of the current received + /// message. When RTR = 0, this is related to the number of data bytes available in + /// the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = + /// 8 bytes With RTR = 1, this value indicates the number of data bytes requested to + /// be sent back, with the same encoding. + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This bit contains the Remote Transmission Request bit of the current received + /// message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be + /// read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote + /// frame, in which case the DLC value identifies the number of data bytes requested + /// to be sent using the same Identifier. + RTR: u1, + /// A 0 in this bit indicates that the current received message included an 11-bit + /// Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents + /// of the CANid register described below. + FF: u1, + }), base_address + 0x20); + + /// address: 0x40044024 + /// Received Identifier. Can only be written when RM in CANMOD is 1. + pub const RID = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier field of the current received message. In CAN 2.0A, these + /// bits are called ID10-0, while in CAN 2.0B they're called ID29-18. + ID: u11, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u21, + }), base_address + 0x24); + + /// address: 0x40044028 + /// Received data bytes 1-4. Can only be written when RM in CANMOD is 1. + pub const RDA = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of + /// the current received message. + DATA1: u8, + /// Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of + /// the current received message. + DATA2: u8, + /// Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of + /// the current received message. + DATA3: u8, + /// Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of + /// the current received message. + DATA4: u8, + }), base_address + 0x28); + + /// address: 0x4004402c + /// Received data bytes 5-8. Can only be written when RM in CANMOD is 1. + pub const RDB = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of + /// the current received message. + DATA5: u8, + /// Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of + /// the current received message. + DATA6: u8, + /// Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of + /// the current received message. + DATA7: u8, + /// Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of + /// the current received message. + DATA8: u8, + }), base_address + 0x2c); + + /// address: 0x40044030 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI1 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x30); + + /// address: 0x40044040 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI2 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x40); + + /// address: 0x40044050 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI3 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x50); + + /// address: 0x40044034 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x34); + + /// address: 0x40044044 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x44); + + /// address: 0x40044054 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x54); + + /// address: 0x40044038 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x38); + + /// address: 0x40044048 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x48); + + /// address: 0x40044058 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x58); + + /// address: 0x4004403c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x3c); + + /// address: 0x4004404c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x4c); + + /// address: 0x4004405c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x5c); + }; + pub const CAN2 = struct { + pub const base_address = 0x40048000; + + /// address: 0x40048000 + /// Controls the operating mode of the CAN Controller. + pub const MOD = @intToPtr(*volatile Mmio(32, packed struct { + /// Reset Mode. + RM: u1, + /// Listen Only Mode. + LOM: u1, + /// Self Test Mode. + STM: u1, + /// Transmit Priority Mode. + TPM: u1, + /// Sleep Mode. + SM: u1, + /// Receive Polarity Mode. + RPM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Test Mode. + TM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x40048004 + /// Command bits that affect the state of the CAN Controller + pub const CMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Request. + TR: u1, + /// Abort Transmission. + AT: u1, + /// Release Receive Buffer. + RRB: u1, + /// Clear Data Overrun. + CDO: u1, + /// Self Reception Request. + SRR: u1, + /// Select Tx Buffer 1. + STB1: u1, + /// Select Tx Buffer 2. + STB2: u1, + /// Select Tx Buffer 3. + STB3: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x40048008 + /// Global Controller Status and Error Counters. The error counters can only be + /// written when RM in CANMOD is 1. + pub const GSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Buffer Status. After reading all messages and releasing their memory + /// space with the command 'Release Receive Buffer,' this bit is cleared. + RBS: u1, + /// Data Overrun Status. If there is not enough space to store the message within + /// the Receive Buffer, that message is dropped and the Data Overrun condition is + /// signalled to the CPU in the moment this message becomes valid. If this message + /// is not completed successfully (e.g. because of an error), no overrun condition + /// is signalled. + DOS: u1, + /// Transmit Buffer Status. + TBS: u1, + /// Transmit Complete Status. The Transmission Complete Status bit is set '0' + /// (incomplete) whenever the Transmission Request bit or the Self Reception Request + /// bit is set '1' at least for one of the three Transmit Buffers. The Transmission + /// Complete Status bit will remain '0' until all messages are transmitted + /// successfully. + TCS: u1, + /// Receive Status. If both the Receive Status and the Transmit Status bits are '0' + /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to + /// become idle again. After hardware reset 11 consecutive recessive bits have to be + /// detected until idle status is reached. After Bus-off this will take 128 times of + /// 11 consecutive recessive bits. + RS: u1, + /// Transmit Status. If both the Receive Status and the Transmit Status bits are '0' + /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to + /// become idle again. After hardware reset 11 consecutive recessive bits have to be + /// detected until idle status is reached. After Bus-off this will take 128 times of + /// 11 consecutive recessive bits. + TS: u1, + /// Error Status. Errors detected during reception or transmission will effect the + /// error counters according to the CAN specification. The Error Status bit is set + /// when at least one of the error counters has reached or exceeded the Error + /// Warning Limit. An Error Warning Interrupt is generated, if enabled. The default + /// value of the Error Warning Limit after hardware reset is 96 decimal, see also + /// Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL + /// - 0x4004 8018). + ES: u1, + /// Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, + /// if enabled. Afterwards the Transmit Error Counter is set to '127', and the + /// Receive Error Counter is cleared. It will stay in this mode until the CPU clears + /// the Reset Mode bit. Once this is completed the CAN Controller will wait the + /// minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting + /// down the Transmit Error Counter. After that, the Bus Status bit is cleared + /// (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, + /// and an Error Warning Interrupt is generated, if enabled. Reading the TX Error + /// Counter during this time gives information about the status of the Bus-Off + /// recovery. + BS: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// The current value of the Rx Error Counter (an 8-bit value). + RXERR: u8, + /// The current value of the Tx Error Counter (an 8-bit value). + TXERR: u8, + }), base_address + 0x8); + + /// address: 0x4004800c + /// Interrupt status, Arbitration Lost Capture, Error Code Capture + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE + /// bit in CANxIER are both 1, indicating that a new message was received and stored + /// in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read + /// access to the Interrupt Register. Giving the Command Release Receive Buffer will + /// clear RI temporarily. If there is another message available within the Receive + /// Buffer after the release command, RI is set again. Otherwise RI remains cleared. + RI: u1, + /// Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB1 was successfully transmitted or aborted), + /// indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is + /// 1. + TI1: u1, + /// Error Warning Interrupt. This bit is set on every change (set or clear) of + /// either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set + /// within the Interrupt Enable Register at the time of the change. + EI: u1, + /// Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 + /// to 1 and the DOIE bit in CANxIER is 1. + DOI: u1, + /// Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus + /// activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is + /// also generated if the CPU tries to set the Sleep bit while the CAN controller is + /// involved in bus activities or a CAN Interrupt is pending. The WUI flag can also + /// get asserted when the according enable bit WUIE is not set. In this case a + /// Wake-Up Interrupt does not get asserted. + WUI: u1, + /// Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and + /// the CAN controller switches between Error Passive and Error Active mode in + /// either direction. This is the case when the CAN Controller has reached the Error + /// Passive Status (at least one error counter exceeds the CAN protocol defined + /// level of 127) or if the CAN Controller is in Error Passive Status and enters the + /// Error Active Status again. + EPI: u1, + /// Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and + /// the CAN controller loses arbitration while attempting to transmit. In this case + /// the CAN node becomes a receiver. + ALI: u1, + /// Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the + /// CAN controller detects an error on the bus. + BEI: u1, + /// ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN + /// Identifier has been received (a message was successfully transmitted or + /// aborted). This bit is set whenever a message was successfully transmitted or + /// aborted and the IDIE bit is set in the IER register. + IDI: u1, + /// Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB2 was successfully transmitted or aborted), + /// indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is + /// 1. + TI2: u1, + /// Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB3 was successfully transmitted or aborted), + /// indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is + /// 1. + TI3: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u5, + /// Error Code Capture: when the CAN controller detects a bus error, the location of + /// the error within the frame is captured in this field. The value reflects an + /// internal state variable, and as a result is not very linear: 00011 = Start of + /// Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE + /// bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit + /// 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = + /// Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot + /// 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever + /// a bus error occurs, the corresponding bus error interrupt is forced, if enabled. + /// At the same time, the current position of the Bit Stream Processor is captured + /// into the Error Code Capture Register. The content within this register is fixed + /// until the user software has read out its content once. From now on, the capture + /// mechanism is activated again, i.e. reading the CANxICR enables another Bus Error + /// Interrupt. + ERRBIT4_0: u5, + /// When the CAN controller detects a bus error, the direction of the current bit is + /// captured in this bit. + ERRDIR: u1, + /// When the CAN controller detects a bus error, the type of error is captured in + /// this field: + ERRC1_0: u2, + /// Each time arbitration is lost while trying to send on the CAN, the bit number + /// within the frame is captured into this field. After the content of ALCBIT is + /// read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 + /// = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost + /// in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE + /// bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 + /// = arbitration lost in last bit of identifier (extended frame only) 31 = + /// arbitration lost in RTR bit (extended frame only) On arbitration lost, the + /// corresponding arbitration lost interrupt is forced, if enabled. At that time, + /// the current bit position of the Bit Stream Processor is captured into the + /// Arbitration Lost Capture Register. The content within this register is fixed + /// until the user application has read out its contents once. From now on, the + /// capture mechanism is activated again. + ALCBIT: u8, + }), base_address + 0xc); + + /// address: 0x40048010 + /// Interrupt Enable + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN + /// Controller requests the respective interrupt. + RIE: u1, + /// Transmit Interrupt Enable for Buffer1. When a message has been successfully + /// transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE1: u1, + /// Error Warning Interrupt Enable. If the Error or Bus Status change (see Status + /// Register), the CAN Controller requests the respective interrupt. + EIE: u1, + /// Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status + /// Register), the CAN Controller requests the respective interrupt. + DOIE: u1, + /// Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the + /// respective interrupt is requested. + WUIE: u1, + /// Error Passive Interrupt Enable. If the error status of the CAN Controller + /// changes from error active to error passive or vice versa, the respective + /// interrupt is requested. + EPIE: u1, + /// Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, + /// the respective interrupt is requested. + ALIE: u1, + /// Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller + /// requests the respective interrupt. + BEIE: u1, + /// ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN + /// Controller requests the respective interrupt. + IDIE: u1, + /// Transmit Interrupt Enable for Buffer2. When a message has been successfully + /// transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE2: u1, + /// Transmit Interrupt Enable for Buffer3. When a message has been successfully + /// transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE3: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x10); + + /// address: 0x40048014 + /// Bus Timing. Can only be written when RM in CANMOD is 1. + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud Rate Prescaler. The APB clock is divided by (this value plus one) to + /// produce the CAN clock. + BRP: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// The Synchronization Jump Width is (this value plus one) CAN clocks. + SJW: u2, + /// The delay from the nominal Sync point to the sample point is (this value plus + /// one) CAN clocks. + TESG1: u4, + /// The delay from the sample point to the next nominal sync point is (this value + /// plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in + /// TSEG1 plus 3) CAN clocks. + TESG2: u3, + /// Sampling + SAM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + }), base_address + 0x14); + + /// address: 0x40048018 + /// Error Warning Limit. Can only be written when RM in CANMOD is 1. + pub const EWL = @intToPtr(*volatile Mmio(32, packed struct { + /// During CAN operation, this value is compared to both the Tx and Rx Error + /// Counters. If either of these counter matches this value, the Error Status (ES) + /// bit in CANSR is set. + EWL: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x4004801c + /// Status Register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_1: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_1: u1, + /// Transmit Buffer Status 1. + TBS1_1: u1, + /// Transmission Complete Status. + TCS1_1: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_1: u1, + /// Transmit Status 1. + TS1_1: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_1: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_1: u1, + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_2: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_2: u1, + /// Transmit Buffer Status 2. + TBS2_2: u1, + /// Transmission Complete Status. + TCS2_2: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_2: u1, + /// Transmit Status 2. + TS2_2: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_2: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_2: u1, + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_3: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_3: u1, + /// Transmit Buffer Status 3. + TBS3_3: u1, + /// Transmission Complete Status. + TCS3_3: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_3: u1, + /// Transmit Status 3. + TS3_3: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_3: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_3: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u8, + }), base_address + 0x1c); + + /// address: 0x40048020 + /// Receive frame status. Can only be written when RM in CANMOD is 1. + pub const RFS = @intToPtr(*volatile Mmio(32, packed struct { + /// ID Index. If the BP bit (below) is 0, this value is the zero-based number of the + /// Lookup Table RAM entry at which the Acceptance Filter matched the received + /// Identifier. Disabled entries in the Standard tables are included in this + /// numbering, but will not be matched. See Section 21.17 Examples of acceptance + /// filter tables and ID index values on page 587 for examples of ID Index values. + IDINDEX: u10, + /// If this bit is 1, the current message was received in AF Bypass mode, and the ID + /// Index field (above) is meaningless. + BP: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u5, + /// The field contains the Data Length Code (DLC) field of the current received + /// message. When RTR = 0, this is related to the number of data bytes available in + /// the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = + /// 8 bytes With RTR = 1, this value indicates the number of data bytes requested to + /// be sent back, with the same encoding. + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This bit contains the Remote Transmission Request bit of the current received + /// message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be + /// read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote + /// frame, in which case the DLC value identifies the number of data bytes requested + /// to be sent using the same Identifier. + RTR: u1, + /// A 0 in this bit indicates that the current received message included an 11-bit + /// Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents + /// of the CANid register described below. + FF: u1, + }), base_address + 0x20); + + /// address: 0x40048024 + /// Received Identifier. Can only be written when RM in CANMOD is 1. + pub const RID = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier field of the current received message. In CAN 2.0A, these + /// bits are called ID10-0, while in CAN 2.0B they're called ID29-18. + ID: u11, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u21, + }), base_address + 0x24); + + /// address: 0x40048028 + /// Received data bytes 1-4. Can only be written when RM in CANMOD is 1. + pub const RDA = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of + /// the current received message. + DATA1: u8, + /// Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of + /// the current received message. + DATA2: u8, + /// Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of + /// the current received message. + DATA3: u8, + /// Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of + /// the current received message. + DATA4: u8, + }), base_address + 0x28); + + /// address: 0x4004802c + /// Received data bytes 5-8. Can only be written when RM in CANMOD is 1. + pub const RDB = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of + /// the current received message. + DATA5: u8, + /// Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of + /// the current received message. + DATA6: u8, + /// Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of + /// the current received message. + DATA7: u8, + /// Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of + /// the current received message. + DATA8: u8, + }), base_address + 0x2c); + + /// address: 0x40048030 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI1 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x30); + + /// address: 0x40048040 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI2 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x40); + + /// address: 0x40048050 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI3 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x50); + + /// address: 0x40048034 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x34); + + /// address: 0x40048044 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x44); + + /// address: 0x40048054 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x54); + + /// address: 0x40048038 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x38); + + /// address: 0x40048048 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x48); + + /// address: 0x40048058 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x58); + + /// address: 0x4004803c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x3c); + + /// address: 0x4004804c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x4c); + + /// address: 0x4004805c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x5c); + }; + pub const I2C1 = struct { + pub const base_address = 0x4005c000; + + /// address: 0x4005c000 + /// I2C Control Set Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is set. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge flag. + AA: u1, + /// I2C interrupt flag. + SI: u1, + /// STOP flag. + STO: u1, + /// START flag. + STA: u1, + /// I2C interface enable. + I2EN: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u25, + }), base_address + 0x0); + + /// address: 0x4005c004 + /// I2C Status Register. During I2C operation, this register provides detailed + /// status codes that allow software to determine the next action needed. + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits are unused and are always 0. + RESERVED: u3, + /// These bits give the actual status information about the I 2C interface. + Status: u5, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x4005c008 + /// I2C Data Register. During master or slave transmit mode, data to be transmitted + /// is written to this register. During master or slave receive mode, data that has + /// been received may be read from this register. + pub const DAT = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds data values that have been received or are to be + /// transmitted. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4005c00c + /// I2C Slave Address Register 0. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x4005c010 + /// SCH Duty Cycle Register High Half Word. Determines the high time of the I2C + /// clock. + pub const SCLH = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL HIGH time period selection. + SCLH: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x10); + + /// address: 0x4005c014 + /// SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. + /// SCLL and SCLH together determine the clock frequency generated by an I2C master + /// and certain times used in slave mode. + pub const SCLL = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL low time period selection. + SCLL: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x14); + + /// address: 0x4005c018 + /// I2C Control Clear Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is cleared. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge Clear bit. + AAC: u1, + /// I2C interrupt Clear bit. + SIC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// START flag Clear bit. + STAC: u1, + /// I2C interface Disable bit. + I2ENC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x4005c01c + /// Monitor mode control register. + pub const MMCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Monitor mode enable. + MM_ENA: u1, + /// SCL output enable. + ENA_SCL: u1, + /// Select interrupt register match. + MATCH_ALL: u1, + /// Reserved. The value read from reserved bits is not defined. + RESERVED: u29, + }), base_address + 0x1c); + + /// address: 0x4005c020 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x20); + + /// address: 0x4005c024 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x24); + + /// address: 0x4005c028 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x4005c02c + /// Data buffer register. The contents of the 8 MSBs of the DAT shift register will + /// be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of + /// data plus ACK or NACK) has been received on the bus. + pub const DATA_BUFFER = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds contents of the 8 MSBs of the DAT shift register. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x2c); + + /// address: 0x4005c030 + /// I2C Slave address mask register + pub const MASK = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. This bit reads + /// always back as 0. + RESERVED: u1, + /// Mask bits. + MASK: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x30); + }; + /// SSP controller + pub const SSP0 = struct { + pub const base_address = 0x40088000; + + /// address: 0x40088000 + /// Control Register 0. Selects the serial clock rate, bus type, and data size. + pub const CR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Size Select. This field controls the number of bits transferred in each + /// frame. Values 0000-0010 are not supported and should not be used. + DSS: u4, + /// Frame Format. + FRF: u2, + /// Clock Out Polarity. This bit is only used in SPI mode. + CPOL: u1, + /// Clock Out Phase. This bit is only used in SPI mode. + CPHA: u1, + /// Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, + /// minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK + /// clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). + SCR: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x0); + + /// address: 0x40088004 + /// Control Register 1. Selects master/slave and other modes. + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Loop Back Mode. + LBM: u1, + /// SSP Enable. + SSE: u1, + /// Master/Slave Mode.This bit can only be written when the SSE bit is 0. + MS: u1, + /// Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is + /// 1, this blocks this SSP controller from driving the transmit data line (MISO). + SOD: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x4); + + /// address: 0x40088008 + /// Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Write: software can write data to be sent in a future frame to this register + /// whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is + /// not full. If the Tx FIFO was previously empty and the SSP controller is not busy + /// on the bus, transmission of the data will begin immediately. Otherwise the data + /// written to this register will be sent as soon as all previous data has been sent + /// (and received). If the data length is less than 16 bits, software must + /// right-justify the data written to this register. Read: software can read data + /// from this register whenever the RNE bit in the Status register is 1, indicating + /// that the Rx FIFO is not empty. When software reads this register, the SSP + /// controller returns data from the least recent frame in the Rx FIFO. If the data + /// length is less than 16 bits, the data is right-justified in this field with + /// higher order bits filled with 0s. + DATA: u16, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x8); + + /// address: 0x4008800c + /// Status Register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. + TFE: u1, + /// Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. + TNF: u1, + /// Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. + RNE: u1, + /// Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. + RFF: u1, + /// Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently + /// sending/receiving a frame and/or the Tx FIFO is not empty. + BSY: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0xc); + + /// address: 0x40088010 + /// Clock Prescale Register + pub const CPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// This even value between 2 and 254, by which PCLK is divided to yield the + /// prescaler output clock. Bit 0 always reads as 0. + CPSDVSR: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x10); + + /// address: 0x40088014 + /// Interrupt Mask Set and Clear Register + pub const IMSC = @intToPtr(*volatile Mmio(32, packed struct { + /// Software should set this bit to enable interrupt when a Receive Overrun occurs, + /// that is, when the Rx FIFO is full and another frame is completely received. The + /// ARM spec implies that the preceding frame data is overwritten by the new frame + /// data when this occurs. + RORIM: u1, + /// Software should set this bit to enable interrupt when a Receive Time-out + /// condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and + /// no has not been read for a time-out period. The time-out period is the same for + /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / + /// (CPSDVSR X [SCR+1]). + RTIM: u1, + /// Software should set this bit to enable interrupt when the Rx FIFO is at least + /// half full. + RXIM: u1, + /// Software should set this bit to enable interrupt when the Tx FIFO is at least + /// half empty. + TXIM: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x14); + + /// address: 0x40088018 + /// Raw Interrupt Status Register + pub const RIS = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit is 1 if another frame was completely received while the RxFIFO was + /// full. The ARM spec implies that the preceding frame data is overwritten by the + /// new frame data when this occurs. + RORRIS: u1, + /// This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out + /// period. The time-out period is the same for master and slave modes and is + /// determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RTRIS: u1, + /// This bit is 1 if the Rx FIFO is at least half full. + RXRIS: u1, + /// This bit is 1 if the Tx FIFO is at least half empty. + TXRIS: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x18); + + /// address: 0x4008801c + /// Masked Interrupt Status Register + pub const MIS = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit is 1 if another frame was completely received while the RxFIFO was + /// full, and this interrupt is enabled. + RORMIS: u1, + /// This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out + /// period, and this interrupt is enabled. The time-out period is the same for + /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / + /// (CPSDVSR X [SCR+1]). + RTMIS: u1, + /// This bit is 1 if the Rx FIFO is at least half full, and this interrupt is + /// enabled. + RXMIS: u1, + /// This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is + /// enabled. + TXMIS: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x1c); + + /// address: 0x40088020 + /// SSPICR Interrupt Clear Register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 to this bit clears the frame was received when RxFIFO was full + /// interrupt. + RORIC: u1, + /// Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read + /// for a time-out period interrupt. The time-out period is the same for master and + /// slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / + /// [SCR+1]). + RTIC: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x20); + + /// address: 0x40088024 + /// SSP0 DMA control register + pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is + /// enabled, otherwise receive DMA is disabled. + RXDMAE: u1, + /// Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is + /// enabled, otherwise transmit DMA is disabled + TXDMAE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x24); + }; + /// Digital-to-Analog Converter (DAC) + pub const DAC = struct { + pub const base_address = 0x4008c000; + + /// address: 0x4008c000 + /// D/A Converter Register. This register contains the digital value to be converted + /// to analog and a power control bit. + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u6, + /// After the selected settling time after this field is written with a new VALUE, + /// the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V + /// REFN)/1024) + VREFN. + VALUE: u10, + /// Settling time The settling times noted in the description of the BIAS bit are + /// valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load + /// impedance value greater than that value will cause settling time longer than the + /// specified time. One or more graphs of load impedance vs. settling time will be + /// included in the final data sheet. + BIAS: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u15, + }), base_address + 0x0); + + /// address: 0x4008c004 + /// DAC Control register. This register controls DMA and timer operation. + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA interrupt request + INT_DMA_REQ: u1, + /// Double buffering + DBLBUF_ENA: u1, + /// Time-out counter operation + CNT_ENA: u1, + /// DMA access + DMA_ENA: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x4); + + /// address: 0x4008c008 + /// DAC Counter Value register. This register contains the reload value for the DAC + /// DMA/Interrupt timer. + pub const CNTVAL = @intToPtr(*volatile Mmio(32, packed struct { + /// 16-bit reload value for the DAC interrupt/DMA timer. + VALUE: u16, + /// Reserved + RESERVED: u16, + }), base_address + 0x8); + }; + pub const TIMER2 = struct { + pub const base_address = 0x40090000; + + /// address: 0x40090000 + /// Interrupt Register. The IR can be written to clear interrupts. The IR can be + /// read to identify which of eight possible interrupt sources are pending. + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag for match channel 0. + MR0INT: u1, + /// Interrupt flag for match channel 1. + MR1INT: u1, + /// Interrupt flag for match channel 2. + MR2INT: u1, + /// Interrupt flag for match channel 3. + MR3INT: u1, + /// Interrupt flag for capture channel 0 event. + CR0INT: u1, + /// Interrupt flag for capture channel 1 event. + CR1INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x0); + + /// address: 0x40090004 + /// Timer Control Register. The TCR is used to control the Timer Counter functions. + /// The Timer Counter can be disabled or reset through the TCR. + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + /// When one, the Timer Counter and Prescale Counter are enabled for counting. When + /// zero, the counters are disabled. + CEN: u1, + /// When one, the Timer Counter and the Prescale Counter are synchronously reset on + /// the next positive edge of PCLK. The counters remain reset until TCR[1] is + /// returned to zero. + CRST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x4); + + /// address: 0x40090008 + /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is + /// controlled through the TCR. + pub const TC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4009000c + /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the + /// next clock increments the TC and clears the PC. + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescale counter maximum value. + PM: u32, + }), base_address + 0xc); + + /// address: 0x40090010 + /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value + /// stored in PR. When the value in PR is reached, the TC is incremented and the PC + /// is cleared. The PC is observable and controllable through the bus interface. + pub const PC = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40090014 + /// Match Control Register. The MCR is used to control if an interrupt is generated + /// and if the TC is reset when a Match occurs. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt on MR0 + MR0I: u1, + /// Reset on MR0 + MR0R: u1, + /// Stop on MR0 + MR0S: u1, + /// Interrupt on MR1 + MR1I: u1, + /// Reset on MR1 + MR1R: u1, + /// Stop on MR1 + MR1S: u1, + /// Interrupt on MR2 + MR2I: u1, + /// Reset on MR2 + MR2R: u1, + /// Stop on MR2. + MR2S: u1, + /// Interrupt on MR3 + MR3I: u1, + /// Reset on MR3 + MR3R: u1, + /// Stop on MR3 + MR3S: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x14); + + /// address: 0x40090018 + /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both + /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x18); + + /// address: 0x40090028 + /// Capture Control Register. The CCR controls which edges of the capture inputs are + /// used to load the Capture Registers and whether or not an interrupt is generated + /// when a capture takes place. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture on CAPn.0 rising edge + CAP0RE: u1, + /// Capture on CAPn.0 falling edge + CAP0FE: u1, + /// Interrupt on CAPn.0 event + CAP0I: u1, + /// Capture on CAPn.1 rising edge + CAP1RE: u1, + /// Capture on CAPn.1 falling edge + CAP1FE: u1, + /// Interrupt on CAPn.1 event + CAP1I: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x4009002c + /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on + /// the CAPn.0 input. + pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Timer counter capture value. + CAP: u32, + }), base_address + 0x2c); + + /// address: 0x4009003c + /// External Match Register. The EMR controls the external match pins. + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { + /// External Match 0. When a match occurs between the TC and MR0, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM0: u1, + /// External Match 1. When a match occurs between the TC and MR1, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this + /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM1: u1, + /// External Match 2. When a match occurs between the TC and MR2, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM2: u1, + /// External Match 3. When a match occurs between the TC and MR3, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM3: u1, + /// External Match Control 0. Determines the functionality of External Match 0. + EMC0: u2, + /// External Match Control 1. Determines the functionality of External Match 1. + EMC1: u2, + /// External Match Control 2. Determines the functionality of External Match 2. + EMC2: u2, + /// External Match Control 3. Determines the functionality of External Match 3. + EMC3: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x3c); + + /// address: 0x40090070 + /// Count Control Register. The CTCR selects between Timer and Counter mode, and in + /// Counter mode selects the signal and edge(s) for counting. + pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter/Timer Mode This field selects which rising PCLK edges can increment + /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). + /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale + /// Register. + CTMODE: u2, + /// Count Input Select When bits 1:0 in this register are not 00, these bits select + /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a + /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture + /// Control Register (TnCCR) must be programmed as 000. However, capture and/or + /// interrupt can be selected for the other 3 CAPn inputs in the same timer. + CINSEL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x70); + }; + pub const TIMER3 = struct { + pub const base_address = 0x40094000; + + /// address: 0x40094000 + /// Interrupt Register. The IR can be written to clear interrupts. The IR can be + /// read to identify which of eight possible interrupt sources are pending. + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag for match channel 0. + MR0INT: u1, + /// Interrupt flag for match channel 1. + MR1INT: u1, + /// Interrupt flag for match channel 2. + MR2INT: u1, + /// Interrupt flag for match channel 3. + MR3INT: u1, + /// Interrupt flag for capture channel 0 event. + CR0INT: u1, + /// Interrupt flag for capture channel 1 event. + CR1INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x0); + + /// address: 0x40094004 + /// Timer Control Register. The TCR is used to control the Timer Counter functions. + /// The Timer Counter can be disabled or reset through the TCR. + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + /// When one, the Timer Counter and Prescale Counter are enabled for counting. When + /// zero, the counters are disabled. + CEN: u1, + /// When one, the Timer Counter and the Prescale Counter are synchronously reset on + /// the next positive edge of PCLK. The counters remain reset until TCR[1] is + /// returned to zero. + CRST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x4); + + /// address: 0x40094008 + /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is + /// controlled through the TCR. + pub const TC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4009400c + /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the + /// next clock increments the TC and clears the PC. + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescale counter maximum value. + PM: u32, + }), base_address + 0xc); + + /// address: 0x40094010 + /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value + /// stored in PR. When the value in PR is reached, the TC is incremented and the PC + /// is cleared. The PC is observable and controllable through the bus interface. + pub const PC = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40094014 + /// Match Control Register. The MCR is used to control if an interrupt is generated + /// and if the TC is reset when a Match occurs. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt on MR0 + MR0I: u1, + /// Reset on MR0 + MR0R: u1, + /// Stop on MR0 + MR0S: u1, + /// Interrupt on MR1 + MR1I: u1, + /// Reset on MR1 + MR1R: u1, + /// Stop on MR1 + MR1S: u1, + /// Interrupt on MR2 + MR2I: u1, + /// Reset on MR2 + MR2R: u1, + /// Stop on MR2. + MR2S: u1, + /// Interrupt on MR3 + MR3I: u1, + /// Reset on MR3 + MR3R: u1, + /// Stop on MR3 + MR3S: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x14); + + /// address: 0x40094018 + /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both + /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x18); + + /// address: 0x40094028 + /// Capture Control Register. The CCR controls which edges of the capture inputs are + /// used to load the Capture Registers and whether or not an interrupt is generated + /// when a capture takes place. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture on CAPn.0 rising edge + CAP0RE: u1, + /// Capture on CAPn.0 falling edge + CAP0FE: u1, + /// Interrupt on CAPn.0 event + CAP0I: u1, + /// Capture on CAPn.1 rising edge + CAP1RE: u1, + /// Capture on CAPn.1 falling edge + CAP1FE: u1, + /// Interrupt on CAPn.1 event + CAP1I: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x4009402c + /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on + /// the CAPn.0 input. + pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Timer counter capture value. + CAP: u32, + }), base_address + 0x2c); + + /// address: 0x4009403c + /// External Match Register. The EMR controls the external match pins. + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { + /// External Match 0. When a match occurs between the TC and MR0, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM0: u1, + /// External Match 1. When a match occurs between the TC and MR1, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this + /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM1: u1, + /// External Match 2. When a match occurs between the TC and MR2, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM2: u1, + /// External Match 3. When a match occurs between the TC and MR3, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM3: u1, + /// External Match Control 0. Determines the functionality of External Match 0. + EMC0: u2, + /// External Match Control 1. Determines the functionality of External Match 1. + EMC1: u2, + /// External Match Control 2. Determines the functionality of External Match 2. + EMC2: u2, + /// External Match Control 3. Determines the functionality of External Match 3. + EMC3: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x3c); + + /// address: 0x40094070 + /// Count Control Register. The CTCR selects between Timer and Counter mode, and in + /// Counter mode selects the signal and edge(s) for counting. + pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter/Timer Mode This field selects which rising PCLK edges can increment + /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). + /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale + /// Register. + CTMODE: u2, + /// Count Input Select When bits 1:0 in this register are not 00, these bits select + /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a + /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture + /// Control Register (TnCCR) must be programmed as 000. However, capture and/or + /// interrupt can be selected for the other 3 CAPn inputs in the same timer. + CINSEL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x70); + }; + pub const UART2 = struct { + pub const base_address = 0x40098000; + + /// address: 0x40098000 + /// Receiver Buffer Register. Contains the next received character to be read (DLAB + /// =0). + pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Receiver Buffer Register contains the oldest received byte in the + /// UARTn Rx FIFO. + RBR: u8, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x40098000 + /// Transmit Holding Regiter. The next character to be transmitted is written here + /// (DLAB =0). + pub const THR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing to the UARTn Transmit Holding Register causes the data to be stored in + /// the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the + /// FIFO and the transmitter is available. + THR: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x40098000 + /// Divisor Latch LSB. Least significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines + /// the baud rate of the UARTn. + DLLSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x40098004 + /// Divisor Latch MSB. Most significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines + /// the baud rate of the UARTn. + DLMSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x40098004 + /// Interrupt Enable Register. Contains individual interrupt enable bits for the 7 + /// potential UART interrupts (DLAB =0). + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It + /// also controls the Character Receive Time-out interrupt. + RBRIE: u1, + /// THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this + /// can be read from UnLSR[5]. + THREIE: u1, + /// RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. + /// The status of this interrupt can be read from UnLSR[4:1]. + RXIE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// Enables the end of auto-baud interrupt. + ABEOINTEN: u1, + /// Enables the auto-baud time-out interrupt. + ABTOINTEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x4); + + /// address: 0x40098008 + /// Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be + /// determined by evaluating UnIIR[3:1]. + INTSTATUS: u1, + /// Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to + /// the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below + /// are reserved (000,100,101,111). + INTID: u3, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// Copies of UnFCR[0]. + FIFOENABLE: u2, + /// End of auto-baud interrupt. True if auto-baud has finished successfully and + /// interrupt is enabled. + ABEOINT: u1, + /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is + /// enabled. + ABTOINT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x8); + + /// address: 0x40098008 + /// FIFO Control Register. Controls UART FIFO usage and modes. + pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO Enable. + FIFOEN: u1, + /// RX FIFO Reset. + RXFIFORES: u1, + /// TX FIFO Reset. + TXFIFORES: u1, + /// DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit + /// selects the DMA mode. See Section 18.6.6.1. + DMAMODE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// RX Trigger Level. These two bits determine how many receiver UARTn FIFO + /// characters must be written before an interrupt or DMA request is activated. + RXTRIGLVL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4009800c + /// Line Control Register. Contains controls for frame formatting and break + /// generation. + pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Word Length Select. + WLS: u2, + /// Stop Bit Select + SBS: u1, + /// Parity Enable. + PE: u1, + /// Parity Select + PS: u2, + /// Break Control + BC: u1, + /// Divisor Latch Access Bit + DLAB: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x40098014 + /// Line Status Register. Contains flags for transmit and receive status, including + /// line errors. + pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character + /// and is cleared when the UARTn RBR FIFO is empty. + RDR: u1, + /// Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR + /// read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character + /// assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will + /// not be overwritten and the character in the UARTn RSR will be lost. + OE: u1, + /// Parity Error. When the parity bit of a received character is in the wrong state, + /// a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error + /// detection is dependent on UnFCR[0]. Note: A parity error is associated with the + /// character at the top of the UARTn RBR FIFO. + PE: u1, + /// Framing Error. When the stop bit of a received character is a logic 0, a framing + /// error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error + /// detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx + /// will attempt to resynchronize to the data and assume that the bad stop bit is + /// actually an early start bit. However, it cannot be assumed that the next + /// received byte will be correct even if there is no Framing Error. Note: A framing + /// error is associated with the character at the top of the UARTn RBR FIFO. + FE: u1, + /// Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one + /// full character transmission (start, data, parity, stop), a break interrupt + /// occurs. Once the break condition has been detected, the receiver goes idle until + /// RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The + /// time of break detection is dependent on UnFCR[0]. Note: The break interrupt is + /// associated with the character at the top of the UARTn RBR FIFO. + BI: u1, + /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an + /// empty UARTn THR and is cleared on a UnTHR write. + THRE: u1, + /// Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is + /// cleared when either the UnTSR or the UnTHR contain valid data. + TEMT: u1, + /// Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as + /// framing error, parity error or break interrupt, is loaded into the UnRBR. This + /// bit is cleared when the UnLSR register is read and there are no subsequent + /// errors in the UARTn FIFO. + RXFE: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x14); + + /// address: 0x4009801c + /// Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + /// A readable, writable byte. + PAD: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x1c); + + /// address: 0x40098020 + /// Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit. This bit is automatically cleared after auto-baud completion. + START: u1, + /// Auto-baud mode select bit. + MODE: u1, + /// Restart bit. + AUTORESTART: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABEOINTCLR: u1, + /// Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABTOINTCLR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x20); + + /// address: 0x40098028 + /// Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud-rate generation pre-scaler divisor value. If this field is 0, fractional + /// baud-rate generator will not impact the UARTn baudrate. + DIVADDVAL: u4, + /// Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for + /// UARTn to operate properly, regardless of whether the fractional baud-rate + /// generator is used or not. + MULVAL: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x40098030 + /// Transmit Enable Register. Turns off UART transmitter for use with software flow + /// control. + pub const TER = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u7, + /// When this bit is 1, as it is after a Reset, data written to the THR is output on + /// the TXD pin as soon as any preceding data has been sent. If this bit is cleared + /// to 0 while a character is being sent, the transmission of that character is + /// completed, but no further characters are sent until this bit is set again. In + /// other words, a 0 in this bit blocks the transfer of characters from the THR or + /// TX FIFO into the transmit shift register. Software implementing + /// software-handshaking can clear this bit when it receives an XOFF character + /// (DC3). Software can set this bit again when it receives an XON (DC1) character. + TXEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x30); + + /// address: 0x4009804c + /// RS-485/EIA-485 Control. Contains controls to configure various aspects of + /// RS-485/EIA-485 modes. + pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// NMM enable. + NMMEN: u1, + /// Receiver enable. + RXDIS: u1, + /// AAD enable. + AADEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Direction control enable. + DCTRL: u1, + /// Direction control pin polarity. This bit reverses the polarity of the direction + /// control signal on the Un_OE pin. + OINV: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x4c); + + /// address: 0x40098050 + /// RS-485/EIA-485 address match. Contains the address match value for + /// RS-485/EIA-485 mode. + pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the address match value. + ADRMATCH: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x50); + + /// address: 0x40098054 + /// RS-485/EIA-485 direction control delay. + pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the direction control (UnOE) delay value. This register works in + /// conjunction with an 8-bit counter. + DLY: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x54); + }; + pub const UART3 = struct { + pub const base_address = 0x4009c000; + + /// address: 0x4009c000 + /// Receiver Buffer Register. Contains the next received character to be read (DLAB + /// =0). + pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Receiver Buffer Register contains the oldest received byte in the + /// UARTn Rx FIFO. + RBR: u8, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4009c000 + /// Transmit Holding Regiter. The next character to be transmitted is written here + /// (DLAB =0). + pub const THR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing to the UARTn Transmit Holding Register causes the data to be stored in + /// the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the + /// FIFO and the transmitter is available. + THR: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4009c000 + /// Divisor Latch LSB. Least significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines + /// the baud rate of the UARTn. + DLLSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4009c004 + /// Divisor Latch MSB. Most significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines + /// the baud rate of the UARTn. + DLMSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x4009c004 + /// Interrupt Enable Register. Contains individual interrupt enable bits for the 7 + /// potential UART interrupts (DLAB =0). + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It + /// also controls the Character Receive Time-out interrupt. + RBRIE: u1, + /// THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this + /// can be read from UnLSR[5]. + THREIE: u1, + /// RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. + /// The status of this interrupt can be read from UnLSR[4:1]. + RXIE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// Enables the end of auto-baud interrupt. + ABEOINTEN: u1, + /// Enables the auto-baud time-out interrupt. + ABTOINTEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x4); + + /// address: 0x4009c008 + /// Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be + /// determined by evaluating UnIIR[3:1]. + INTSTATUS: u1, + /// Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to + /// the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below + /// are reserved (000,100,101,111). + INTID: u3, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// Copies of UnFCR[0]. + FIFOENABLE: u2, + /// End of auto-baud interrupt. True if auto-baud has finished successfully and + /// interrupt is enabled. + ABEOINT: u1, + /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is + /// enabled. + ABTOINT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x8); + + /// address: 0x4009c008 + /// FIFO Control Register. Controls UART FIFO usage and modes. + pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO Enable. + FIFOEN: u1, + /// RX FIFO Reset. + RXFIFORES: u1, + /// TX FIFO Reset. + TXFIFORES: u1, + /// DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit + /// selects the DMA mode. See Section 18.6.6.1. + DMAMODE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// RX Trigger Level. These two bits determine how many receiver UARTn FIFO + /// characters must be written before an interrupt or DMA request is activated. + RXTRIGLVL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4009c00c + /// Line Control Register. Contains controls for frame formatting and break + /// generation. + pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Word Length Select. + WLS: u2, + /// Stop Bit Select + SBS: u1, + /// Parity Enable. + PE: u1, + /// Parity Select + PS: u2, + /// Break Control + BC: u1, + /// Divisor Latch Access Bit + DLAB: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x4009c014 + /// Line Status Register. Contains flags for transmit and receive status, including + /// line errors. + pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character + /// and is cleared when the UARTn RBR FIFO is empty. + RDR: u1, + /// Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR + /// read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character + /// assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will + /// not be overwritten and the character in the UARTn RSR will be lost. + OE: u1, + /// Parity Error. When the parity bit of a received character is in the wrong state, + /// a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error + /// detection is dependent on UnFCR[0]. Note: A parity error is associated with the + /// character at the top of the UARTn RBR FIFO. + PE: u1, + /// Framing Error. When the stop bit of a received character is a logic 0, a framing + /// error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error + /// detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx + /// will attempt to resynchronize to the data and assume that the bad stop bit is + /// actually an early start bit. However, it cannot be assumed that the next + /// received byte will be correct even if there is no Framing Error. Note: A framing + /// error is associated with the character at the top of the UARTn RBR FIFO. + FE: u1, + /// Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one + /// full character transmission (start, data, parity, stop), a break interrupt + /// occurs. Once the break condition has been detected, the receiver goes idle until + /// RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The + /// time of break detection is dependent on UnFCR[0]. Note: The break interrupt is + /// associated with the character at the top of the UARTn RBR FIFO. + BI: u1, + /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an + /// empty UARTn THR and is cleared on a UnTHR write. + THRE: u1, + /// Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is + /// cleared when either the UnTSR or the UnTHR contain valid data. + TEMT: u1, + /// Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as + /// framing error, parity error or break interrupt, is loaded into the UnRBR. This + /// bit is cleared when the UnLSR register is read and there are no subsequent + /// errors in the UARTn FIFO. + RXFE: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x14); + + /// address: 0x4009c01c + /// Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + /// A readable, writable byte. + PAD: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x1c); + + /// address: 0x4009c020 + /// Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit. This bit is automatically cleared after auto-baud completion. + START: u1, + /// Auto-baud mode select bit. + MODE: u1, + /// Restart bit. + AUTORESTART: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABEOINTCLR: u1, + /// Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABTOINTCLR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x20); + + /// address: 0x4009c028 + /// Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud-rate generation pre-scaler divisor value. If this field is 0, fractional + /// baud-rate generator will not impact the UARTn baudrate. + DIVADDVAL: u4, + /// Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for + /// UARTn to operate properly, regardless of whether the fractional baud-rate + /// generator is used or not. + MULVAL: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x4009c030 + /// Transmit Enable Register. Turns off UART transmitter for use with software flow + /// control. + pub const TER = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u7, + /// When this bit is 1, as it is after a Reset, data written to the THR is output on + /// the TXD pin as soon as any preceding data has been sent. If this bit is cleared + /// to 0 while a character is being sent, the transmission of that character is + /// completed, but no further characters are sent until this bit is set again. In + /// other words, a 0 in this bit blocks the transfer of characters from the THR or + /// TX FIFO into the transmit shift register. Software implementing + /// software-handshaking can clear this bit when it receives an XOFF character + /// (DC3). Software can set this bit again when it receives an XON (DC1) character. + TXEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x30); + + /// address: 0x4009c04c + /// RS-485/EIA-485 Control. Contains controls to configure various aspects of + /// RS-485/EIA-485 modes. + pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// NMM enable. + NMMEN: u1, + /// Receiver enable. + RXDIS: u1, + /// AAD enable. + AADEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Direction control enable. + DCTRL: u1, + /// Direction control pin polarity. This bit reverses the polarity of the direction + /// control signal on the Un_OE pin. + OINV: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x4c); + + /// address: 0x4009c050 + /// RS-485/EIA-485 address match. Contains the address match value for + /// RS-485/EIA-485 mode. + pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the address match value. + ADRMATCH: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x50); + + /// address: 0x4009c054 + /// RS-485/EIA-485 direction control delay. + pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the direction control (UnOE) delay value. This register works in + /// conjunction with an 8-bit counter. + DLY: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x54); + }; + pub const I2C2 = struct { + pub const base_address = 0x400a0000; + + /// address: 0x400a0000 + /// I2C Control Set Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is set. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge flag. + AA: u1, + /// I2C interrupt flag. + SI: u1, + /// STOP flag. + STO: u1, + /// START flag. + STA: u1, + /// I2C interface enable. + I2EN: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u25, + }), base_address + 0x0); + + /// address: 0x400a0004 + /// I2C Status Register. During I2C operation, this register provides detailed + /// status codes that allow software to determine the next action needed. + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits are unused and are always 0. + RESERVED: u3, + /// These bits give the actual status information about the I 2C interface. + Status: u5, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x400a0008 + /// I2C Data Register. During master or slave transmit mode, data to be transmitted + /// is written to this register. During master or slave receive mode, data that has + /// been received may be read from this register. + pub const DAT = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds data values that have been received or are to be + /// transmitted. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x400a000c + /// I2C Slave Address Register 0. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x400a0010 + /// SCH Duty Cycle Register High Half Word. Determines the high time of the I2C + /// clock. + pub const SCLH = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL HIGH time period selection. + SCLH: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x10); + + /// address: 0x400a0014 + /// SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. + /// SCLL and SCLH together determine the clock frequency generated by an I2C master + /// and certain times used in slave mode. + pub const SCLL = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL low time period selection. + SCLL: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x14); + + /// address: 0x400a0018 + /// I2C Control Clear Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is cleared. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge Clear bit. + AAC: u1, + /// I2C interrupt Clear bit. + SIC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// START flag Clear bit. + STAC: u1, + /// I2C interface Disable bit. + I2ENC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x400a001c + /// Monitor mode control register. + pub const MMCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Monitor mode enable. + MM_ENA: u1, + /// SCL output enable. + ENA_SCL: u1, + /// Select interrupt register match. + MATCH_ALL: u1, + /// Reserved. The value read from reserved bits is not defined. + RESERVED: u29, + }), base_address + 0x1c); + + /// address: 0x400a0020 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x20); + + /// address: 0x400a0024 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x24); + + /// address: 0x400a0028 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x400a002c + /// Data buffer register. The contents of the 8 MSBs of the DAT shift register will + /// be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of + /// data plus ACK or NACK) has been received on the bus. + pub const DATA_BUFFER = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds contents of the 8 MSBs of the DAT shift register. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x2c); + + /// address: 0x400a0030 + /// I2C Slave address mask register + pub const MASK = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. This bit reads + /// always back as 0. + RESERVED: u1, + /// Mask bits. + MASK: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x30); + }; + /// I2S interface + pub const I2S = struct { + pub const base_address = 0x400a8000; + + /// address: 0x400a8000 + /// I2S Digital Audio Output Register. Contains control bits for the I2S transmit + /// channel. + pub const DAO = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the number of bytes in data as follows: + WORDWIDTH: u2, + /// When 1, data is of monaural format. When 0, the data is in stereo format. + MONO: u1, + /// When 1, disables accesses on FIFOs, places the transmit channel in mute mode. + STOP: u1, + /// When 1, asynchronously resets the transmit channel and FIFO. + RESET: u1, + /// When 0, the interface is in master mode. When 1, the interface is in slave mode. + /// See Section 34.7.2 for a summary of useful combinations for this bit with + /// TXMODE. + WS_SEL: u1, + /// Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. + WS_HALFPERIOD: u9, + /// When 1, the transmit channel sends only zeroes. + MUTE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x0); + + /// address: 0x400a8004 + /// I2S Digital Audio Input Register. Contains control bits for the I2S receive + /// channel. + pub const DAI = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the number of bytes in data as follows: + WORDWIDTH: u2, + /// When 1, data is of monaural format. When 0, the data is in stereo format. + MONO: u1, + /// When 1, disables accesses on FIFOs, places the transmit channel in mute mode. + STOP: u1, + /// When 1, asynchronously reset the transmit channel and FIFO. + RESET: u1, + /// When 0, the interface is in master mode. When 1, the interface is in slave mode. + /// See Section 34.7.2 for a summary of useful combinations for this bit with + /// RXMODE. + WS_SEL: u1, + /// Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. + WS_HALFPERIOD: u9, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u17, + }), base_address + 0x4); + + /// address: 0x400a8008 + /// I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. + pub const TXFIFO = @intToPtr(*volatile Mmio(32, packed struct { + /// 8 x 32-bit transmit FIFO. + I2STXFIFO: u32, + }), base_address + 0x8); + + /// address: 0x400a800c + /// I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. + pub const RXFIFO = @intToPtr(*volatile Mmio(32, packed struct { + /// 8 x 32-bit transmit FIFO. + I2SRXFIFO: u32, + }), base_address + 0xc); + + /// address: 0x400a8010 + /// I2S Status Feedback Register. Contains status information about the I2S + /// interface. + pub const STATE = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This + /// is determined by comparing the current FIFO levels to the rx_depth_irq and + /// tx_depth_irq fields in the IRQ register. + IRQ: u1, + /// This bit reflects the presence of Receive or Transmit DMA Request 1. This is + /// determined by comparing the current FIFO levels to the rx_depth_dma1 and + /// tx_depth_dma1 fields in the DMA1 register. + DMAREQ1: u1, + /// This bit reflects the presence of Receive or Transmit DMA Request 2. This is + /// determined by comparing the current FIFO levels to the rx_depth_dma2 and + /// tx_depth_dma2 fields in the DMA2 register. + DMAREQ2: u1, + /// Reserved. + RESERVED: u5, + /// Reflects the current level of the Receive FIFO. + RX_LEVEL: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u4, + /// Reflects the current level of the Transmit FIFO. + TX_LEVEL: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u12, + }), base_address + 0x10); + + /// address: 0x400a8014 + /// I2S DMA Configuration Register 1. Contains control information for DMA request + /// 1. + pub const DMA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, enables DMA1 for I2S receive. + RX_DMA1_ENABLE: u1, + /// When 1, enables DMA1 for I2S transmit. + TX_DMA1_ENABLE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u6, + /// Set the FIFO level that triggers a receive DMA request on DMA1. + RX_DEPTH_DMA1: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u4, + /// Set the FIFO level that triggers a transmit DMA request on DMA1. + TX_DEPTH_DMA1: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u12, + }), base_address + 0x14); + + /// address: 0x400a8018 + /// I2S DMA Configuration Register 2. Contains control information for DMA request + /// 2. + pub const DMA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, enables DMA1 for I2S receive. + RX_DMA2_ENABLE: u1, + /// When 1, enables DMA1 for I2S transmit. + TX_DMA2_ENABLE: u1, + /// Reserved. + RESERVED: u6, + /// Set the FIFO level that triggers a receive DMA request on DMA2. + RX_DEPTH_DMA2: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u4, + /// Set the FIFO level that triggers a transmit DMA request on DMA2. + TX_DEPTH_DMA2: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u12, + }), base_address + 0x18); + + /// address: 0x400a801c + /// I2S Interrupt Request Control Register. Contains bits that control how the I2S + /// interrupt request is generated. + pub const IRQ = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, enables I2S receive interrupt. + RX_IRQ_ENABLE: u1, + /// When 1, enables I2S transmit interrupt. + TX_IRQ_ENABLE: u1, + /// Reserved. + RESERVED: u6, + /// Set the FIFO level on which to create an irq request. + RX_DEPTH_IRQ: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u4, + /// Set the FIFO level on which to create an irq request. + TX_DEPTH_IRQ: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u12, + }), base_address + 0x1c); + + /// address: 0x400a8020 + /// I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by + /// specifying the value to divide PCLK by in order to produce MCLK. + pub const TXRATE = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce + /// the transmit MCLK. Eight bits of fractional divide supports a wide range of + /// possibilities. A value of 0 stops the clock. + Y_DIVIDER: u8, + /// I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to + /// produce the transmit MCLK. A value of 0 stops the clock. Eight bits of + /// fractional divide supports a wide range of possibilities. Note: the resulting + /// ratio X/Y is divided by 2. + X_DIVIDER: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x20); + + /// address: 0x400a8024 + /// I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by + /// specifying the value to divide PCLK by in order to produce MCLK. + pub const RXRATE = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S receive MCLK rate denominator. This value is used to divide PCLK to produce + /// the receive MCLK. Eight bits of fractional divide supports a wide range of + /// possibilities. A value of 0 stops the clock. + Y_DIVIDER: u8, + /// I2S receive MCLK rate numerator. This value is used to multiply PCLK by to + /// produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional + /// divide supports a wide range of possibilities. Note: the resulting ratio X/Y is + /// divided by 2. + X_DIVIDER: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x24); + + /// address: 0x400a8028 + /// I2S Transmit bit rate divider. This register determines the I2S transmit bit + /// rate by specifying the value to divide TX_MCLK by in order to produce the + /// transmit bit clock. + pub const TXBITRATE = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce + /// the transmit bit clock. + TX_BITRATE: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x400a802c + /// I2S Receive bit rate divider. This register determines the I2S receive bit rate + /// by specifying the value to divide RX_MCLK by in order to produce the receive bit + /// clock. + pub const RXBITRATE = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce + /// the receive bit clock. + RX_BITRATE: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x2c); + + /// address: 0x400a8030 + /// I2S Transmit mode control. + pub const TXMODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock source selection for the transmit bit clock divider. + TXCLKSEL: u2, + /// Transmit 4-pin mode selection. When 1, enables 4-pin mode. + TX4PIN: u1, + /// Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, + /// output of TX_MCLK is enabled. + TXMCENA: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x30); + + /// address: 0x400a8034 + /// I2S Receive mode control. + pub const RXMODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock source selection for the receive bit clock divider. + RXCLKSEL: u2, + /// Receive 4-pin mode selection. When 1, enables 4-pin mode. + RX4PIN: u1, + /// Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, + /// output of RX_MCLK is enabled. + RXMCENA: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x34); + }; + /// Repetitive Interrupt Timer (RIT) + pub const RITIMER = struct { + pub const base_address = 0x400b0000; + + /// address: 0x400b0000 + /// Compare register + pub const COMPVAL = @intToPtr(*volatile Mmio(32, packed struct { + /// Compare register. Holds the compare value which is compared to the counter. + RICOMP: u32, + }), base_address + 0x0); + + /// address: 0x400b0004 + /// Mask register. This register holds the 32-bit mask value. A 1 written to any bit + /// will force a compare on the corresponding bit of the counter and compare + /// register. + pub const MASK = @intToPtr(*volatile Mmio(32, packed struct { + /// Mask register. This register holds the 32-bit mask value. A one written to any + /// bit overrides the result of the comparison for the corresponding bit of the + /// counter and compare register (causes the comparison of the register bits to be + /// always true). + RIMASK: u32, + }), base_address + 0x4); + + /// address: 0x400b0008 + /// Control register. + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag + RITINT: u1, + /// Timer enable clear + RITENCLR: u1, + /// Timer enable for debug + RITENBR: u1, + /// Timer enable. + RITEN: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x8); + + /// address: 0x400b000c + /// 32-bit counter + pub const COUNTER = @intToPtr(*volatile Mmio(32, packed struct { + /// 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is + /// cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can + /// be loaded to any value in software. + RICOUNTER: u32, + }), base_address + 0xc); + }; + /// Motor Control PWM + pub const MCPWM = struct { + pub const base_address = 0x400b8000; + + /// address: 0x400b8000 + /// PWM Control read address + pub const CON = @intToPtr(*volatile Mmio(32, packed struct { + /// Stops/starts timer channel 0. + RUN0: u1, + /// Edge/center aligned operation for channel 0. + CENTER0: u1, + /// Selects polarity of the MCOA0 and MCOB0 pins. + POLA0: u1, + /// Controls the dead-time feature for channel 0. + DTE0: u1, + /// Enable/disable updates of functional registers for channel 0 (see Section + /// 24.8.2). + DISUP0: u1, + /// Reserved. + RESERVED: u3, + /// Stops/starts timer channel 1. + RUN1: u1, + /// Edge/center aligned operation for channel 1. + CENTER1: u1, + /// Selects polarity of the MCOA1 and MCOB1 pins. + POLA1: u1, + /// Controls the dead-time feature for channel 1. + DTE1: u1, + /// Enable/disable updates of functional registers for channel 1 (see Section + /// 24.8.2). + DISUP1: u1, + /// Reserved. + RESERVED: u3, + /// Stops/starts timer channel 2. + RUN2: u1, + /// Edge/center aligned operation for channel 2. + CENTER2: u1, + /// Selects polarity of the MCOA2 and MCOB2 pins. + POLA2: u1, + /// Controls the dead-time feature for channel 1. + DTE2: u1, + /// Enable/disable updates of functional registers for channel 2 (see Section + /// 24.8.2). + DISUP2: u1, + /// Reserved. + RESERVED: u8, + /// Controls the polarity of the MCOB outputs for all 3 channels. This bit is + /// typically set to 1 only in 3-phase DC mode. + INVBDC: u1, + /// 3-phase AC mode select (see Section 24.8.7). + ACMODE: u1, + /// 3-phase DC mode select (see Section 24.8.6). + DCMODE: u1, + }), base_address + 0x0); + + /// address: 0x400b8004 + /// PWM Control set address + pub const CON_SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one sets the corresponding bit in the CON register. + RUN0_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + CENTER0_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + POLA0_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DTE0_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DISUP0_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + RESERVED: u3, + /// Writing a one sets the corresponding bit in the CON register. + RUN1_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + CENTER1_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + POLA1_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DTE1_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DISUP1_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + RESERVED: u3, + /// Writing a one sets the corresponding bit in the CON register. + RUN2_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + CENTER2_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + POLA2_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DTE2_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DISUP2_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + RESERVED: u8, + /// Writing a one sets the corresponding bit in the CON register. + INVBDC_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + ACMODE_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DCMODE_SET: u1, + }), base_address + 0x4); + + /// address: 0x400b8008 + /// PWM Control clear address + pub const CON_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one clears the corresponding bit in the CON register. + RUN0_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + CENTER0_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + POLA0_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DTE0_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DISUP0_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + RESERVED: u3, + /// Writing a one clears the corresponding bit in the CON register. + RUN1_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + CENTER1_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + POLA1_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DTE1_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DISUP1_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + RESERVED: u3, + /// Writing a one clears the corresponding bit in the CON register. + RUN2_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + CENTER2_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + POLA2_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DTE2_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DISUP2_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + RESERVED: u8, + /// Writing a one clears the corresponding bit in the CON register. + INVBDC_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + ACMOD_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DCMODE_CLR: u1, + }), base_address + 0x8); + + /// address: 0x400b800c + /// Capture Control read address + pub const CAPCON = @intToPtr(*volatile Mmio(32, packed struct { + /// A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. + CAP0MCI0_RE: u1, + /// A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. + CAP0MCI0_FE: u1, + /// A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. + CAP0MCI1_RE: u1, + /// A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. + CAP0MCI1_FE: u1, + /// A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. + CAP0MCI2_RE: u1, + /// A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. + CAP0MCI2_FE: u1, + /// A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. + CAP1MCI0_RE: u1, + /// A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. + CAP1MCI0_FE: u1, + /// A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. + CAP1MCI1_RE: u1, + /// A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. + CAP1MCI1_FE: u1, + /// A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. + CAP1MCI2_RE: u1, + /// A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. + CAP1MCI2_FE: u1, + /// A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. + CAP2MCI0_RE: u1, + /// A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. + CAP2MCI0_FE: u1, + /// A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. + CAP2MCI1_RE: u1, + /// A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. + CAP2MCI1_FE: u1, + /// A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. + CAP2MCI2_RE: u1, + /// A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. + CAP2MCI2_FE: u1, + /// If this bit is 1, TC0 is reset by a channel 0 capture event. + RT0: u1, + /// If this bit is 1, TC1 is reset by a channel 1 capture event. + RT1: u1, + /// If this bit is 1, TC2 is reset by a channel 2 capture event. + RT2: u1, + /// Reserved. + RESERVED: u11, + }), base_address + 0xc); + + /// address: 0x400b8010 + /// Capture Control set address + pub const CAPCON_SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI2_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI2_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI2_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + RT0_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + RT1_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + RT2_SET: u1, + /// Reserved. + RESERVED: u11, + }), base_address + 0x10); + + /// address: 0x400b8014 + /// Event Control clear address + pub const CAPCON_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI2_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI2_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI2_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI2_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI2_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI2_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + RT0_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + RT1_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + RT2_CLR: u1, + /// Reserved. + RESERVED: u11, + }), base_address + 0x14); + + /// address: 0x400b8018 + /// Timer Counter register + pub const TC = @intToPtr(*volatile [3]Mmio(32, packed struct { + /// Timer/Counter value. + MCTC: u32, + }), base_address + 0x18); + + /// address: 0x400b8024 + /// Limit register + pub const LIM = @intToPtr(*volatile [3]Mmio(32, packed struct { + /// Limit value. + MCLIM: u32, + }), base_address + 0x24); + + /// address: 0x400b8030 + /// Match register + pub const MAT = @intToPtr(*volatile [3]Mmio(32, packed struct { + /// Match value. + MCMAT: u32, + }), base_address + 0x30); + + /// address: 0x400b803c + /// Dead time register + pub const DT = @intToPtr(*volatile Mmio(32, packed struct { + /// Dead time for channel 0.[1] + DT0: u10, + /// Dead time for channel 1.[2] + DT1: u10, + /// Dead time for channel 2.[2] + DT2: u10, + /// reserved + RESERVED: u2, + }), base_address + 0x3c); + + /// address: 0x400b8040 + /// Communication Pattern register + pub const CP = @intToPtr(*volatile Mmio(32, packed struct { + /// Communication pattern output A, channel 0. + CCPA0: u1, + /// Communication pattern output B, channel 0. + CCPB0: u1, + /// Communication pattern output A, channel 1. + CCPA1: u1, + /// Communication pattern output B, channel 1. + CCPB1: u1, + /// Communication pattern output A, channel 2. + CCPA2: u1, + /// Communication pattern output B, channel 2. + CCPB2: u1, + /// Reserved. + RESERVED: u26, + }), base_address + 0x40); + + /// address: 0x400b8044 + /// Capture register + pub const CAP = @intToPtr(*volatile [3]u32, base_address + 0x44); + + /// address: 0x400b8050 + /// Interrupt Enable read address + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Limit interrupt for channel 0. + ILIM0: u1, + /// Match interrupt for channel 0. + IMAT0: u1, + /// Capture interrupt for channel 0. + ICAP0: u1, + /// Reserved. + RESERVED: u1, + /// Limit interrupt for channel 1. + ILIM1: u1, + /// Match interrupt for channel 1. + IMAT1: u1, + /// Capture interrupt for channel 1. + ICAP1: u1, + /// Reserved. + RESERVED: u1, + /// Limit interrupt for channel 2. + ILIM2: u1, + /// Match interrupt for channel 2. + IMAT2: u1, + /// Capture interrupt for channel 2. + ICAP2: u1, + /// Reserved. + RESERVED: u4, + /// Fast abort interrupt. + ABORT: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x50); + + /// address: 0x400b8054 + /// Interrupt Enable set address + pub const INTEN_SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ILIM0_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT0_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP0_SET: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ILIM1_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT1_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP1_SET: u1, + /// Reserved. + RESERVED: u1, + reserved0: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ILIM2_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT2_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP2_SET: u1, + /// Reserved. + RESERVED: u3, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ABORT_SET: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x54); + + /// address: 0x400b8058 + /// Interrupt Enable clear address + pub const INTEN_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ILIM0_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT0_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP0_CLR: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ILIM1_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT1_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP1_CLR: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ILIM2_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT2_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP2_CLR: u1, + /// Reserved. + RESERVED: u4, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ABORT_CLR: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x58); + + /// address: 0x400b8068 + /// Interrupt flags read address + pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Limit interrupt flag for channel 0. + ILIM0_F: u1, + /// Match interrupt flag for channel 0. + IMAT0_F: u1, + /// Capture interrupt flag for channel 0. + ICAP0_F: u1, + /// Reserved. + RESERVED: u1, + /// Limit interrupt flag for channel 1. + ILIM1_F: u1, + /// Match interrupt flag for channel 1. + IMAT1_F: u1, + /// Capture interrupt flag for channel 1. + ICAP1_F: u1, + /// Reserved. + RESERVED: u1, + /// Limit interrupt flag for channel 2. + ILIM2_F: u1, + /// Match interrupt flag for channel 2. + IMAT2_F: u1, + /// Capture interrupt flag for channel 2. + ICAP2_F: u1, + /// Reserved. + RESERVED: u4, + /// Fast abort interrupt flag. + ABORT_F: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x68); + + /// address: 0x400b806c + /// Interrupt flags set address + pub const INTF_SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ILIM0_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + IMAT0_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ICAP0_F_SET: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ILIM1_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + IMAT1_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ICAP1_F_SET: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ILIM2_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + IMAT2_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ICAP2_F_SET: u1, + /// Reserved. + RESERVED: u4, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ABORT_F_SET: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x6c); + + /// address: 0x400b8070 + /// Interrupt flags clear address + pub const INTF_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one clears the corresponding bit in the INTF register, thus clearing + /// the corresponding interrupt request. + ILIM0_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT0_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP0_F_CLR: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ILIM1_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT1_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP1_F_CLR: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ILIM2_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT2_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP2_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + RESERVED: u4, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ABORT_F_CLR: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x70); + + /// address: 0x400b805c + /// Count Control read address + pub const CNTCON = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter 0 rising edge mode, channel 0. + TC0MCI0_RE: u1, + /// Counter 0 falling edge mode, channel 0. + TC0MCI0_FE: u1, + /// Counter 0 rising edge mode, channel 1. + TC0MCI1_RE: u1, + /// Counter 0 falling edge mode, channel 1. + TC0MCI1_FE: u1, + /// Counter 0 rising edge mode, channel 2. + TC0MCI2_RE: u1, + /// Counter 0 falling edge mode, channel 2. + TC0MCI2_FE: u1, + /// Counter 1 rising edge mode, channel 0. + TC1MCI0_RE: u1, + /// Counter 1 falling edge mode, channel 0. + TC1MCI0_FE: u1, + /// Counter 1 rising edge mode, channel 1. + TC1MCI1_RE: u1, + /// Counter 1 falling edge mode, channel 1. + TC1MCI1_FE: u1, + /// Counter 1 rising edge mode, channel 2. + TC1MCI2_RE: u1, + /// Counter 1 falling edge mode, channel 2. + TC1MCI2_FE: u1, + /// Counter 2 rising edge mode, channel 0. + TC2MCI0_RE: u1, + /// Counter 2 falling edge mode, channel 0. + TC2MCI0_FE: u1, + /// Counter 2 rising edge mode, channel 1. + TC2MCI1_RE: u1, + /// Counter 2 falling edge mode, channel 1. + TC2MCI1_FE: u1, + /// Counter 2 rising edge mode, channel 2. + TC2MCI2_RE: u1, + /// Counter 2 falling edge mode, channel 2. + TC2MCI2_FE: u1, + /// Reserved. + RESERVED: u11, + /// Channel 0 counter/timer mode. + CNTR0: u1, + /// Channel 1 counter/timer mode. + CNTR1: u1, + /// Channel 2 counter/timer mode. + CNTR2: u1, + }), base_address + 0x5c); + + /// address: 0x400b8060 + /// Count Control set address + pub const CNTCON_SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI2_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI2_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI2_FE_SET: u1, + /// Reserved. + RESERVED: u11, + /// Writing a one sets the corresponding bit in the CNTCON register. + CNTR0_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + CNTR1_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + CNTR2_SET: u1, + }), base_address + 0x60); + + /// address: 0x400b8064 + /// Count Control clear address + pub const CNTCON_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI2_RE: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI2_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI2_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI2_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI2_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI2_FE_CLR: u1, + /// Reserved. + RESERVED: u11, + /// Writing a one clears the corresponding bit in the CNTCON register. + CNTR0_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + CNTR1_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + CNTR2_CLR: u1, + }), base_address + 0x64); + + /// address: 0x400b8074 + /// Capture clear address + pub const CAP_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 to this bit clears the CAP0 register. + CAP_CLR0: u1, + /// Writing a 1 to this bit clears the CAP1 register. + CAP_CLR1: u1, + /// Writing a 1 to this bit clears the CAP2 register. + CAP_CLR2: u1, + /// Reserved + RESERVED: u29, + }), base_address + 0x74); + }; + /// Quadrature Encoder Interface (QEI) + pub const QEI = struct { + pub const base_address = 0x400bc000; + + /// address: 0x400bc000 + /// Control register + pub const CON = @intToPtr(*volatile Mmio(32, packed struct { + /// Reset position counter. When set = 1, resets the position counter to all zeros. + /// Autoclears when the position counter is cleared. + RESP: u1, + /// Reset position counter on index. When set = 1, resets the position counter to + /// all zeros once only the first time an index pulse occurs. Autoclears when the + /// position counter is cleared. + RESPI: u1, + /// Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads + /// the velocity timer, and presets the velocity compare register. Autoclears when + /// the velocity counter is cleared. + RESV: u1, + /// Reset index counter. When set = 1, resets the index counter to all zeros. + /// Autoclears when the index counter is cleared. + RESI: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x0); + + /// address: 0x400bc008 + /// Configuration register + pub const CONF = @intToPtr(*volatile Mmio(32, packed struct { + /// Direction invert. When 1, complements the DIR bit. + DIRINV: u1, + /// Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, + /// PhA functions as the direction signal and PhB functions as the clock signal. + SIGMODE: u1, + /// Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB + /// edges are counted (4X), increasing resolution but decreasing range. + CAPMODE: u1, + /// Invert Index. When 1, inverts the sense of the index input. + INVINX: u1, + /// Continuously reset the position counter on index. When 1, resets the position + /// counter to all zeros whenever an index pulse occurs after the next position + /// increase (recalibration). + CRESPI: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u11, + /// Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 + /// and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when + /// PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index + /// when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the + /// index when PHA = 0 and PHB = 0, otherwise block index. + INXGATE: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u12, + }), base_address + 0x8); + + /// address: 0x400bc004 + /// Status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Direction bit. In combination with DIRINV bit indicates forward or reverse + /// direction. See Table 597. + DIR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u31, + }), base_address + 0x4); + + /// address: 0x400bc00c + /// Position register + pub const POS = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x400bc010 + /// Maximum position register + pub const MAXPOS = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x400bc014 + /// Position compare register 0 + pub const CMPOS0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Position compare value 0. + PCMP0: u32, + }), base_address + 0x14); + + /// address: 0x400bc018 + /// Position compare register 1 + pub const CMPOS1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Position compare value 1. + PCMP1: u32, + }), base_address + 0x18); + + /// address: 0x400bc01c + /// Position compare register 2 + pub const CMPOS2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Position compare value 2. + PCMP2: u32, + }), base_address + 0x1c); + + /// address: 0x400bc020 + /// Index count register 0 + pub const INXCNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Current index counter value. + ENCPOS: u32, + }), base_address + 0x20); + + /// address: 0x400bc024 + /// Index compare register 0 + pub const INXCMP0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Index compare value 0. + ICMP0: u32, + }), base_address + 0x24); + + /// address: 0x400bc028 + /// Velocity timer reload register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { + /// Current velocity timer load value. + VELLOAD: u32, + }), base_address + 0x28); + + /// address: 0x400bc02c + /// Velocity timer register + pub const TIME = @intToPtr(*volatile Mmio(32, packed struct { + /// Current velocity timer value. + VELVAL: u32, + }), base_address + 0x2c); + + /// address: 0x400bc030 + /// Velocity counter register + pub const VEL = @intToPtr(*volatile Mmio(32, packed struct { + /// Current velocity pulse count. + VELPC: u32, + }), base_address + 0x30); + + /// address: 0x400bc034 + /// Velocity capture register + pub const CAP = @intToPtr(*volatile Mmio(32, packed struct { + /// Last velocity capture. + VELCAP: u32, + }), base_address + 0x34); + + /// address: 0x400bc038 + /// Velocity compare register + pub const VELCOMP = @intToPtr(*volatile Mmio(32, packed struct { + /// Compare velocity pulse count. + VELPC: u32, + }), base_address + 0x38); + + /// address: 0x400bc03c + /// Digital filter register + pub const FILTER = @intToPtr(*volatile Mmio(32, packed struct { + /// Digital filter sampling delay. + FILTA: u32, + }), base_address + 0x3c); + + /// address: 0x400bcfe0 + /// Interrupt status register + pub const INTSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Indicates that an index pulse was detected. + INX_INT: u1, + /// Indicates that a velocity timer overflow occurred + TIM_INT: u1, + /// Indicates that captured velocity is less than compare velocity. + VELC_INT: u1, + /// Indicates that a change of direction was detected. + DIR_INT: u1, + /// Indicates that an encoder phase error was detected. + ERR_INT: u1, + /// Indicates that and encoder clock pulse was detected. + ENCLK_INT: u1, + /// Indicates that the position 0 compare value is equal to the current position. + POS0_INT: u1, + /// Indicates that the position 1compare value is equal to the current position. + POS1_INT: u1, + /// Indicates that the position 2 compare value is equal to the current position. + POS2_INT: u1, + /// Indicates that the index compare 0 value is equal to the current index count. + REV0_INT: u1, + /// Combined position 0 and revolution count interrupt. Set when both the POS0_Int + /// bit is set and the REV0_Int is set. + POS0REV_INT: u1, + /// Combined position 1 and revolution count interrupt. Set when both the POS1_Int + /// bit is set and the REV1_Int is set. + POS1REV_INT: u1, + /// Combined position 2 and revolution count interrupt. Set when both the POS2_Int + /// bit is set and the REV2_Int is set. + POS2REV_INT: u1, + /// Indicates that the index compare 1value is equal to the current index count. + REV1_INT: u1, + /// Indicates that the index compare 2 value is equal to the current index count. + REV2_INT: u1, + /// Indicates that the current position count goes through the MAXPOS value to zero + /// in the forward direction, or through zero to MAXPOS in the reverse direction. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfe0); + + /// address: 0x400bcfec + /// Interrupt status set register + pub const SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 sets the INX_Int bit in QEIINTSTAT. + INX_INT: u1, + /// Writing a 1 sets the TIN_Int bit in QEIINTSTAT. + TIM_INT: u1, + /// Writing a 1 sets the VELC_Int bit in QEIINTSTAT. + VELC_INT: u1, + /// Writing a 1 sets the DIR_Int bit in QEIINTSTAT. + DIR_INT: u1, + /// Writing a 1 sets the ERR_Int bit in QEIINTSTAT. + ERR_INT: u1, + /// Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT. + ENCLK_INT: u1, + /// Writing a 1 sets the POS0_Int bit in QEIINTSTAT. + POS0_INT: u1, + /// Writing a 1 sets the POS1_Int bit in QEIINTSTAT. + POS1_INT: u1, + /// Writing a 1 sets the POS2_Int bit in QEIINTSTAT. + POS2_INT: u1, + /// Writing a 1 sets the REV0_Int bit in QEIINTSTAT. + REV0_INT: u1, + /// Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT. + POS0REV_INT: u1, + /// Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT. + POS1REV_INT: u1, + /// Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT. + POS2REV_INT: u1, + /// Writing a 1 sets the REV1_Int bit in QEIINTSTAT. + REV1_INT: u1, + /// Writing a 1 sets the REV2_Int bit in QEIINTSTAT. + REV2_INT: u1, + /// Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfec); + + /// address: 0x400bcfe8 + /// Interrupt status clear register + pub const CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 clears the INX_Int bit in QEIINTSTAT. + INX_INT: u1, + /// Writing a 1 clears the TIN_Int bit in QEIINTSTAT. + TIM_INT: u1, + /// Writing a 1 clears the VELC_Int bit in QEIINTSTAT. + VELC_INT: u1, + /// Writing a 1 clears the DIR_Int bit in QEIINTSTAT. + DIR_INT: u1, + /// Writing a 1 clears the ERR_Int bit in QEIINTSTAT. + ERR_INT: u1, + /// Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT. + ENCLK_INT: u1, + /// Writing a 1 clears the POS0_Int bit in QEIINTSTAT. + POS0_INT: u1, + /// Writing a 1 clears the POS1_Int bit in QEIINTSTAT. + POS1_INT: u1, + /// Writing a 1 clears the POS2_Int bit in QEIINTSTAT. + POS2_INT: u1, + /// Writing a 1 clears the REV0_Int bit in QEIINTSTAT. + REV0_INT: u1, + /// Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT. + POS0REV_INT: u1, + /// Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT. + POS1REV_INT: u1, + /// Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT. + POS2REV_INT: u1, + /// Writing a 1 clears the REV1_Int bit in QEIINTSTAT. + REV1_INT: u1, + /// Writing a 1 clears the REV2_Int bit in QEIINTSTAT. + REV2_INT: u1, + /// Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfe8); + + /// address: 0x400bcfe4 + /// Interrupt enable register + pub const IE = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, the INX_Int interrupt is enabled. + INX_INT: u1, + /// When 1, the TIN_Int interrupt is enabled. + TIM_INT: u1, + /// When 1, the VELC_Int interrupt is enabled. + VELC_INT: u1, + /// When 1, the DIR_Int interrupt is enabled. + DIR_INT: u1, + /// When 1, the ERR_Int interrupt is enabled. + ERR_INT: u1, + /// When 1, the ENCLK_Int interrupt is enabled. + ENCLK_INT: u1, + /// When 1, the POS0_Int interrupt is enabled. + POS0_INT: u1, + /// When 1, the POS1_Int interrupt is enabled. + POS1_INT: u1, + /// When 1, the POS2_Int interrupt is enabled. + POS2_INT: u1, + /// When 1, the REV0_Int interrupt is enabled. + REV0_INT: u1, + /// When 1, the POS0REV_Int interrupt is enabled. + POS0REV_INT: u1, + /// When 1, the POS1REV_Int interrupt is enabled. + POS1REV_INT: u1, + /// When 1, the POS2REV_Int interrupt is enabled. + POS2REV_INT: u1, + /// When 1, the REV1_Int interrupt is enabled. + REV1_INT: u1, + /// When 1, the REV2_Int interrupt is enabled. + REV2_INT: u1, + /// When 1, the MAXPOS_Int interrupt is enabled. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfe4); + + /// address: 0x400bcfdc + /// Interrupt enable set register + pub const IES = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 enables the INX_Int interrupt in the QEIIE register. + INX_INT: u1, + /// Writing a 1 enables the TIN_Int interrupt in the QEIIE register. + TIM_INT: u1, + /// Writing a 1 enables the VELC_Int interrupt in the QEIIE register. + VELC_INT: u1, + /// Writing a 1 enables the DIR_Int interrupt in the QEIIE register. + DIR_INT: u1, + /// Writing a 1 enables the ERR_Int interrupt in the QEIIE register. + ERR_INT: u1, + /// Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register. + ENCLK_INT: u1, + /// Writing a 1 enables the POS0_Int interrupt in the QEIIE register. + POS0_INT: u1, + /// Writing a 1 enables the POS1_Int interrupt in the QEIIE register. + POS1_INT: u1, + /// Writing a 1 enables the POS2_Int interrupt in the QEIIE register. + POS2_INT: u1, + /// Writing a 1 enables the REV0_Int interrupt in the QEIIE register. + REV0_INT: u1, + /// Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register. + POS0REV_INT: u1, + /// Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register. + POS1REV_INT: u1, + /// Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register. + POS2REV_INT: u1, + /// Writing a 1 enables the REV1_Int interrupt in the QEIIE register. + REV1_INT: u1, + /// Writing a 1 enables the REV2_Int interrupt in the QEIIE register. + REV2_INT: u1, + /// Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfdc); + + /// address: 0x400bcfd8 + /// Interrupt enable clear register + pub const IEC = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 disables the INX_Int interrupt in the QEIIE register. + INX_INT: u1, + /// Writing a 1 disables the TIN_Int interrupt in the QEIIE register. + TIM_INT: u1, + /// Writing a 1 disables the VELC_Int interrupt in the QEIIE register. + VELC_INT: u1, + /// Writing a 1 disables the DIR_Int interrupt in the QEIIE register. + DIR_INT: u1, + /// Writing a 1 disables the ERR_Int interrupt in the QEIIE register. + ERR_INT: u1, + /// Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register. + ENCLK_INT: u1, + /// Writing a 1 disables the POS0_Int interrupt in the QEIIE register. + POS0_INT: u1, + /// Writing a 1 disables the POS1_Int interrupt in the QEIIE register. + POS1_INT: u1, + /// Writing a 1 disables the POS2_Int interrupt in the QEIIE register. + POS2_INT: u1, + /// Writing a 1 disables the REV0_Int interrupt in the QEIIE register. + REV0_INT: u1, + /// Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register. + POS0REV_INT: u1, + /// Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register. + POS1REV_INT: u1, + /// Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register. + POS2REV_INT: u1, + /// Writing a 1 disables the REV1_Int interrupt in the QEIIE register. + REV1_INT: u1, + /// Writing a 1 disables the REV2_Int interrupt in the QEIIE register. + REV2_INT: u1, + /// Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfd8); + }; + /// System and clock control + pub const SYSCON = struct { + pub const base_address = 0x400fc000; + + /// address: 0x400fc000 + /// Flash Accelerator Configuration Register. Controls flash access timing. + pub const FLASHCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, user software should not change these bits from the reset value. + reserved0: u12, + /// Flash access time. The value of this field plus 1 gives the number of CPU clocks + /// used for a flash access. Warning: improper setting of this value may result in + /// incorrect operation of the device. Other values are reserved. + FLASHTIM: u4, + /// Reserved. The value read from a reserved bit is not defined. + reserved1: u16, + }), base_address + 0x0); + + /// address: 0x400fc080 + /// PLL0 Control Register + pub const PLL0CON = @intToPtr(*volatile Mmio(32, packed struct { + /// PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 + /// and allow it to lock to the requested frequency. See PLL0STAT register. + PLLE0: u1, + /// PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then + /// followed by a valid PLL0 feed sequence causes PLL0 to become the clock source + /// for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. + /// The PLL0 output may potentially be used to clock the USB subsystem if the + /// frequency is 48 MHz. See PLL0STAT register. + PLLC0: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x80); + + /// address: 0x400fc084 + /// PLL0 Configuration Register + pub const PLL0CFG = @intToPtr(*volatile Mmio(32, packed struct { + /// PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The + /// value stored here is M - 1. Note: Not all values of M are needed, and therefore + /// some are not supported by hardware. + MSEL0: u15, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + reserved0: u1, + /// PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The + /// value stored here is N - 1. Supported values for N are 1 through 32. + NSEL0: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + reserved1: u8, + }), base_address + 0x84); + + /// address: 0x400fc088 + /// PLL0 Status Register + pub const PLL0STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Read-back for the PLL0 Multiplier value. This is the value currently used by + /// PLL0, and is one less than the actual multiplier. + MSEL0: u15, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// Read-back for the PLL0 Pre-Divider value. This is the value currently used by + /// PLL0, and is one less than the actual divider. + NSEL0: u8, + /// Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit + /// in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When + /// zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode + /// is entered. + PLLE0_STAT: u1, + /// Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit + /// in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is + /// connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, + /// PLL0 is bypassed. This bit is automatically cleared when Power-down mode is + /// entered. + PLLC0_STAT: u1, + /// Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is + /// locked onto the requested frequency. See text for details. + PLOCK0: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u5, + }), base_address + 0x88); + + /// address: 0x400fc08c + /// PLL0 Feed Register + pub const PLL0FEED = @intToPtr(*volatile Mmio(32, packed struct { + /// The PLL0 feed sequence must be written to this register in order for PLL0 + /// configuration and control register changes to take effect. + PLL0FEED: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8c); + + /// address: 0x400fc0a0 + /// PLL1 Control Register + pub const PLL1CON = @intToPtr(*volatile Mmio(32, packed struct { + /// PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 + /// and allow it to lock to the requested frequency. + PLLE1: u1, + /// PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then + /// followed by a valid PLL1 feed sequence causes PLL1 to become the clock source + /// for the USB subsystem via the USB clock divider. See PLL1STAT register. + PLLC1: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0xa0); + + /// address: 0x400fc0a4 + /// PLL1 Configuration Register + pub const PLL1CFG = @intToPtr(*volatile Mmio(32, packed struct { + /// PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations. + MSEL1: u5, + /// PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations. + PSEL1: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u25, + }), base_address + 0xa4); + + /// address: 0x400fc0a8 + /// PLL1 Status Register + pub const PLL1STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Read-back for the PLL1 Multiplier value. This is the value currently used by + /// PLL1. + MSEL1: u5, + /// Read-back for the PLL1 Divider value. This is the value currently used by PLL1. + PSEL1: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When + /// zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode + /// is activated. + PLLE1_STAT: u1, + /// Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is + /// connected as the clock source for the microcontroller. When either PLLC or PLLE + /// is zero, PLL1 is bypassed and the oscillator clock is used directly by the + /// microcontroller. This bit is automatically cleared when Power-down mode is + /// activated. + PLLC1_STAT: u1, + /// Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is + /// locked onto the requested frequency. + PLOCK1: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u21, + }), base_address + 0xa8); + + /// address: 0x400fc0ac + /// PLL1 Feed Register + pub const PLL1FEED = @intToPtr(*volatile Mmio(32, packed struct { + /// The PLL1 feed sequence must be written to this register in order for PLL1 + /// configuration and control register changes to take effect. + PLL1FEED: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xac); + + /// address: 0x400fc0c0 + /// Power Control Register + pub const PCON = @intToPtr(*volatile Mmio(32, packed struct { + /// Power mode control bit 0. This bit controls entry to the Power-down mode. + PM0: u1, + /// Power mode control bit 1. This bit controls entry to the Deep Power-down mode. + PM1: u1, + /// Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry + /// will be turned off when chip Power-down mode or Deep Sleep mode is entered, + /// resulting in a further reduction in power usage. However, the possibility of + /// using Brown-Out Detect as a wake-up source from the reduced power mode will be + /// lost. When 0, the Brown-Out Detect function remains active during Power-down and + /// Deep Sleep modes. See the System Control Block chapter for details of Brown-Out + /// detection. + BODRPM: u1, + /// Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is + /// fully disabled at all times, and does not consume power. When 0, the Brown-Out + /// Detect circuitry is enabled. See the System Control Block chapter for details of + /// Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) + /// and the Brown-Out Interrupt (xx) must be disabled when software changes the + /// value of this bit. + BOGD: u1, + /// Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when + /// the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The + /// Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. + BORD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared + /// by software writing a one to this bit. + SMFLAG: u1, + /// Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. + /// Cleared by software writing a one to this bit. + DSFLAG: u1, + /// Power-down entry flag. Set when the Power-down mode is successfully entered. + /// Cleared by software writing a one to this bit. + PDFLAG: u1, + /// Deep Power-down entry flag. Set when the Deep Power-down mode is successfully + /// entered. Cleared by software writing a one to this bit. + DPDFLAG: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0xc0); + + /// address: 0x400fc0c4 + /// Power Control for Peripherals Register + pub const PCONP = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + reserved0: u1, + /// Timer/Counter 0 power/clock control bit. + PCTIM0: u1, + /// Timer/Counter 1 power/clock control bit. + PCTIM1: u1, + /// UART0 power/clock control bit. + PCUART0: u1, + /// UART1 power/clock control bit. + PCUART1: u1, + /// Reserved. + reserved1: u1, + /// PWM1 power/clock control bit. + PCPWM1: u1, + /// The I2C0 interface power/clock control bit. + PCI2C0: u1, + /// The SPI interface power/clock control bit. + PCSPI: u1, + /// The RTC power/clock control bit. + PCRTC: u1, + /// The SSP 1 interface power/clock control bit. + PCSSP1: u1, + /// Reserved. + reserved2: u1, + /// A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the + /// AD0CR before clearing this bit, and set this bit before setting PDN. + PCADC: u1, + /// CAN Controller 1 power/clock control bit. + PCCAN1: u1, + /// CAN Controller 2 power/clock control bit. + PCCAN2: u1, + /// Power/clock control bit for IOCON, GPIO, and GPIO interrupts. + PCGPIO: u1, + /// Repetitive Interrupt Timer power/clock control bit. + PCRIT: u1, + /// Motor Control PWM + PCMCPWM: u1, + /// Quadrature Encoder Interface power/clock control bit. + PCQEI: u1, + /// The I2C1 interface power/clock control bit. + PCI2C1: u1, + /// Reserved. + reserved3: u1, + /// The SSP0 interface power/clock control bit. + PCSSP0: u1, + /// Timer 2 power/clock control bit. + PCTIM2: u1, + /// Timer 3 power/clock control bit. + PCTIM3: u1, + /// UART 2 power/clock control bit. + PCUART2: u1, + /// UART 3 power/clock control bit. + PCUART3: u1, + /// I2C interface 2 power/clock control bit. + PCI2C2: u1, + /// I2S interface power/clock control bit. + PCI2S: u1, + /// Reserved. + reserved4: u1, + /// GPDMA function power/clock control bit. + PCGPDMA: u1, + /// Ethernet block power/clock control bit. + PCENET: u1, + /// USB interface power/clock control bit. + PCUSB: u1, + }), base_address + 0xc4); + + /// address: 0x400fc104 + /// CPU Clock Configuration Register + pub const CCLKCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. + /// 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed + /// when the PLL0 is connected, because the rate would always be greater than the + /// maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. + /// This setting is not allowed when the PLL0 is connected, because the rate would + /// always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 + /// to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. + /// ... 255 = pllclk is divided by 256 to produce the CPU clock. + CCLKSEL: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x104); + + /// address: 0x400fc108 + /// USB Clock Configuration Register + pub const USBCLKCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the divide value for creating the USB clock from the PLL0 output. Only + /// the values shown below can produce even number multiples of 48 MHz from the PLL0 + /// output. Warning: Improper setting of this value will result in incorrect + /// operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output + /// must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 + /// = PLL0 output is divided by 10. PLL0 output must be 480 MHz. + USBSEL: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x108); + + /// address: 0x400fc10c + /// Clock Source Select Register + pub const CLKSRCSEL = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the clock source for PLL0 as follows. Warning: Improper setting of this + /// value, or an incorrect sequence of changing this value may result in incorrect + /// operation of the device. + CLKSRC: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x10c); + + /// address: 0x400fc110 + /// Allows clearing the current CAN channel sleep state as well as reading that + /// state. + pub const CANSLEEPCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN + /// channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored + /// to CAN channel 1. + CAN1SLEEP: u1, + /// Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN + /// channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored + /// to CAN channel 2. + CAN2SLEEP: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u29, + }), base_address + 0x110); + + /// address: 0x400fc114 + /// Allows reading the wake-up state of the CAN channels. + pub const CANWAKEFLAGS = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge + /// has occurred on the receive data line of CAN channel 1. Write: writing a 1 + /// clears this bit. + CAN1WAKE: u1, + /// Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge + /// has occurred on the receive data line of CAN channel 2. Write: writing a 1 + /// clears this bit. + CAN2WAKE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u29, + }), base_address + 0x114); + + /// address: 0x400fc140 + /// External Interrupt Flag Register + pub const EXTINT = @intToPtr(*volatile Mmio(32, packed struct { + /// In level-sensitive mode, this bit is set if the EINT0 function is selected for + /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is + /// set if the EINT0 function is selected for its pin, and the selected edge occurs + /// on the pin. This bit is cleared by writing a one to it, except in level + /// sensitive mode when the pin is in its active state. + EINT0: u1, + /// In level-sensitive mode, this bit is set if the EINT1 function is selected for + /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is + /// set if the EINT1 function is selected for its pin, and the selected edge occurs + /// on the pin. This bit is cleared by writing a one to it, except in level + /// sensitive mode when the pin is in its active state. + EINT1: u1, + /// In level-sensitive mode, this bit is set if the EINT2 function is selected for + /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is + /// set if the EINT2 function is selected for its pin, and the selected edge occurs + /// on the pin. This bit is cleared by writing a one to it, except in level + /// sensitive mode when the pin is in its active state. + EINT2: u1, + /// In level-sensitive mode, this bit is set if the EINT3 function is selected for + /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is + /// set if the EINT3 function is selected for its pin, and the selected edge occurs + /// on the pin. This bit is cleared by writing a one to it, except in level + /// sensitive mode when the pin is in its active state. + EINT3: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x140); + + /// address: 0x400fc148 + /// External Interrupt Mode register + pub const EXTMODE = @intToPtr(*volatile Mmio(32, packed struct { + /// External interrupt 0 EINT0 mode. + EXTMODE0: u1, + /// External interrupt 1 EINT1 mode. + EXTMODE1: u1, + /// External interrupt 2 EINT2 mode. + EXTMODE2: u1, + /// External interrupt 3 EINT3 mode. + EXTMODE3: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x148); + + /// address: 0x400fc14c + /// External Interrupt Polarity Register + pub const EXTPOLAR = @intToPtr(*volatile Mmio(32, packed struct { + /// External interrupt 0 EINT0 polarity. + EXTPOLAR0: u1, + /// External interrupt 1 EINT1 polarity. + EXTPOLAR1: u1, + /// External interrupt 2 EINT2 polarity. + EXTPOLAR2: u1, + /// External interrupt 3 EINT3 polarity. + EXTPOLAR3: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x14c); + + /// address: 0x400fc180 + /// Reset Source Identification Register + pub const RSID = @intToPtr(*volatile Mmio(32, packed struct { + /// Assertion of the POR signal sets this bit, and clears all of the other bits in + /// this register. But if another Reset signal (e.g., External Reset) remains + /// asserted after the POR signal is negated, then its bit is set. This bit is not + /// affected by any of the other sources of Reset. + POR: u1, + /// Assertion of the RESET signal sets this bit. This bit is cleared only by + /// software or POR. + EXTR: u1, + /// This bit is set when the Watchdog Timer times out and the WDTRESET bit in the + /// Watchdog Mode Register is 1. This bit is cleared only by software or POR. + WDTR: u1, + /// This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD + /// reset trip level (typically 1.85 V under nominal room temperature conditions). + /// If the VDD(REG)(3V3) voltage dips from the normal operating range to below the + /// BOD reset trip level and recovers, the BODR bit will be set to 1. If the + /// VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD + /// reset trip level and continues to decline to the level at which POR is asserted + /// (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises + /// continuously from below 1 V to a level above the BOD reset trip level, the BODR + /// will be set to 1. This bit is cleared only by software or POR. Note: Only in the + /// case where a reset occurs and the POR = 0, the BODR bit indicates if the + /// VDD(REG)(3V3) voltage was below the BOD reset trip level or not. + BODR: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x180); + + /// address: 0x400fc1a0 + /// System control and status + pub const SCS = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u4, + /// Main oscillator range select. + OSCRANGE: u1, + /// Main oscillator enable. + OSCEN: u1, + /// Main oscillator status. + OSCSTAT: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u25, + }), base_address + 0x1a0); + + /// address: 0x400fc1a8 + /// Peripheral Clock Selection register 0. + pub const PCLKSEL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock selection for WDT. + PCLK_WDT: u2, + /// Peripheral clock selection for TIMER0. + PCLK_TIMER0: u2, + /// Peripheral clock selection for TIMER1. + PCLK_TIMER1: u2, + /// Peripheral clock selection for UART0. + PCLK_UART0: u2, + /// Peripheral clock selection for UART1. + PCLK_UART1: u2, + /// Reserved. + reserved0: u2, + /// Peripheral clock selection for PWM1. + PCLK_PWM1: u2, + /// Peripheral clock selection for I2C0. + PCLK_I2C0: u2, + /// Peripheral clock selection for SPI. + PCLK_SPI: u2, + /// Reserved. + reserved1: u2, + /// Peripheral clock selection for SSP1. + PCLK_SSP1: u2, + /// Peripheral clock selection for DAC. + PCLK_DAC: u2, + /// Peripheral clock selection for ADC. + PCLK_ADC: u2, + /// Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same + /// PCLK divide value when the CAN function is used. + PCLK_CAN1: u2, + /// Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same + /// PCLK divide value when the CAN function is used. + PCLK_CAN2: u2, + /// Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 + /// must have the same PCLK divide value when the CAN function is used. + PCLK_ACF: u2, + }), base_address + 0x1a8); + + /// address: 0x400fc1ac + /// Peripheral Clock Selection register 1. + pub const PCLKSEL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock selection for the Quadrature Encoder Interface. + PCLK_QEI: u2, + /// Peripheral clock selection for GPIO interrupts. + PCLK_GPIOINT: u2, + /// Peripheral clock selection for the Pin Connect block. + PCLK_PCB: u2, + /// Peripheral clock selection for I2C1. + PCLK_I2C1: u2, + /// Reserved. + RESERVED: u2, + /// Peripheral clock selection for SSP0. + PCLK_SSP0: u2, + /// Peripheral clock selection for TIMER2. + PCLK_TIMER2: u2, + /// Peripheral clock selection for TIMER3. + PCLK_TIMER3: u2, + /// Peripheral clock selection for UART2. + PCLK_UART2: u2, + /// Peripheral clock selection for UART3. + PCLK_UART3: u2, + /// Peripheral clock selection for I2C2. + PCLK_I2C2: u2, + /// Peripheral clock selection for I2S. + PCLK_I2S: u2, + /// Reserved. + RESERVED: u2, + /// Peripheral clock selection for Repetitive Interrupt Timer. + PCLK_RIT: u2, + /// Peripheral clock selection for the System Control block. + PCLK_SYSCON: u2, + /// Peripheral clock selection for the Motor Control PWM. + PCLK_MC: u2, + }), base_address + 0x1ac); + + /// address: 0x400fc1c0 + /// USB Interrupt Status + pub const USBINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// Low priority interrupt line status. This bit is read-only. + USB_INT_REQ_LP: u1, + /// High priority interrupt line status. This bit is read-only. + USB_INT_REQ_HP: u1, + /// DMA interrupt line status. This bit is read-only. + USB_INT_REQ_DMA: u1, + /// USB host interrupt line status. This bit is read-only. + USB_HOST_INT: u1, + /// External ATX interrupt line status. This bit is read-only. + USB_ATX_INT: u1, + /// OTG interrupt line status. This bit is read-only. + USB_OTG_INT: u1, + /// I2C module interrupt line status. This bit is read-only. + USB_I2C_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// USB need clock indicator. This bit is read-only. This bit is set to 1 when USB + /// activity or a change of state on the USB data pins is detected, and it indicates + /// that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it + /// resets to zero 5 ms after the last packet has been received/sent, or 2 ms after + /// the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 + /// to 1 can wake up the microcontroller if activity on the USB bus is selected to + /// wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from + /// Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down + /// mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F + /// C0C4) for considerations about the PLL and invoking the Power-down mode. This + /// bit is read-only. + USB_NEED_CLK: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + /// Enable all USB interrupts. When this bit is cleared, the NVIC does not see the + /// ORed output of the USB interrupt lines. + EN_USB_INTS: u1, + }), base_address + 0x1c0); + + /// address: 0x400fc1c4 + /// Selects between alternative requests on DMA channels 0 through 7 and 10 through + /// 15 + pub const DMACREQSEL = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is + /// selected. + DMASEL08: u1, + /// Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is + /// selected. + DMASEL09: u1, + /// Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer + /// 1 match 0 is selected. + DMASEL10: u1, + /// Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer + /// 1 match 1 is selected. + DMASEL11: u1, + /// Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer + /// 2 match 0 is selected. + DMASEL12: u1, + /// Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer + /// 2 match 1 is selected. + DMASEL13: u1, + /// Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S + /// channel 0 is selected. + DMASEL14: u1, + /// Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S + /// channel 1 is selected. + DMASEL15: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x1c4); + + /// address: 0x400fc1c8 + /// Clock Output Configuration Register + pub const CLKOUTCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the clock source for the CLKOUT function. Other values are reserved. Do + /// not use. + CLKOUTSEL: u4, + /// Integer value to divide the output clock by, minus one. 0 = Clock is divided by + /// 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is + /// divided by 16. + CLKOUTDIV: u4, + /// CLKOUT enable control, allows switching the CLKOUT source without glitches. + /// Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. + CLKOUT_EN: u1, + /// CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when + /// CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being + /// stopped. + CLKOUT_ACT: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x1c8); + }; + /// Ethernet + pub const EMAC = struct { + pub const base_address = 0x50000000; + + /// address: 0x50000000 + /// MAC configuration register 1. + pub const MAC1 = @intToPtr(*volatile Mmio(32, packed struct { + /// RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the + /// MAC synchronizes this control bit to the incoming receive stream. + RXENABLE: u1, + /// PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames + /// regardless of type (normal vs. Control). When disabled, the MAC does not pass + /// valid Control frames. + PARF: u1, + /// RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow + /// Control frames. When disabled, received PAUSE Flow Control frames are ignored. + RXFLOWCTRL: u1, + /// TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed + /// to be transmitted. When disabled, Flow Control frames are blocked. + TXFLOWCTRL: u1, + /// Setting this bit will cause the MAC Transmit interface to be looped back to the + /// MAC Receive interface. Clearing this bit results in normal operation. + LOOPBACK: u1, + /// Unused + RESERVED: u3, + /// Setting this bit will put the Transmit Function logic in reset. + RESETTX: u1, + /// Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic + /// implements flow control. + RESETMCSTX: u1, + /// Setting this bit will put the Ethernet receive logic in reset. + RESETRX: u1, + /// Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic + /// implements flow control. + RESETMCSRX: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// SIMULATION RESET. Setting this bit will cause a reset to the random number + /// generator within the Transmit Function. + SIMRESET: u1, + /// SOFT RESET. Setting this bit will put all modules within the MAC in reset except + /// the Host Interface. + SOFTRESET: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x0); + + /// address: 0x50000004 + /// MAC configuration register 2. + pub const MAC2 = @intToPtr(*volatile Mmio(32, packed struct { + /// When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, + /// the MAC operates in Half-Duplex mode. + FULLDUPLEX: u1, + /// FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame + /// lengths are compared to the Length/Type field. If the Length/Type field + /// represents a length then the check is performed. Mismatches are reported in the + /// StatusInfo word for each received frame. + FLC: u1, + /// HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted + /// and received. + HFEN: u1, + /// DELAYED CRC. This bit determines the number of bytes, if any, of proprietary + /// header information that exist on the front of IEEE 802.3 frames. When 1, four + /// bytes of header (ignored by the CRC function) are added. When 0, there is no + /// proprietary header. + DELAYEDCRC: u1, + /// CRC ENABLESet this bit to append a CRC to every frame whether padding was + /// required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames + /// presented to the MAC contain a CRC. + CRCEN: u1, + /// PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this + /// bit if frames presented to the MAC have a valid length. This bit is used in + /// conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad + /// Operation for details on the pad function. + PADCRCEN: u1, + /// VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 + /// bytes and append a valid CRC. Consult Table 153 - Pad Operation for more + /// information on the various padding features. Note: This bit is ignored if PAD / + /// CRC ENABLE is cleared. + VLANPADEN: u1, + /// AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the + /// type of frame, either tagged or un-tagged, by comparing the two octets following + /// the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 + /// - Pad Operation provides a description of the pad function based on the + /// configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is + /// cleared. + AUTODETPADEN: u1, + /// PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the + /// content of the preamble to ensure it contains 0x55 and is error-free. A packet + /// with an incorrect preamble is discarded. When disabled, no preamble checking is + /// performed. + PPENF: u1, + /// LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive + /// packets which contain preamble fields less than 12 bytes in length. When + /// disabled, the MAC allows any length preamble as per the Standard. + LPENF: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// When enabled (set to 1), the MAC will immediately retransmit following a + /// collision rather than using the Binary Exponential Backoff algorithm as + /// specified in the Standard. + NOBACKOFF: u1, + /// BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally + /// causes a collision during back pressure, it will immediately retransmit without + /// backoff, reducing the chance of further collisions and ensuring transmit packets + /// get sent. + BP_NOBACKOFF: u1, + /// When enabled (set to 1) the MAC will defer to carrier indefinitely as per the + /// Standard. When disabled, the MAC will abort when the excessive deferral limit is + /// reached. + EXCESSDEFER: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u17, + }), base_address + 0x4); + + /// address: 0x50000008 + /// Back-to-Back Inter-Packet-Gap register. + pub const IPGT = @intToPtr(*volatile Mmio(32, packed struct { + /// BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the + /// nibble time offset of the minimum possible period between the end of any + /// transmitted packet to the beginning of the next. In Full-Duplex mode, the + /// register value should be the desired period in nibble times minus 3. In + /// Half-Duplex mode, the register value should be the desired period in nibble + /// times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which + /// represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps + /// mode). In Half-Duplex the recommended setting is 0x12 (18d), which also + /// represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps + /// mode). + BTOBINTEGAP: u7, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u25, + }), base_address + 0x8); + + /// address: 0x5000000c + /// Non Back-to-Back Inter-Packet-Gap register. + pub const IPGR = @intToPtr(*volatile Mmio(32, packed struct { + /// NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field + /// representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is + /// 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 + /// us (in 10 Mbps mode). + NBTOBINTEGAP2: u7, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field + /// representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 + /// 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC + /// defers to carrier. If, however, carrier becomes active after IPGR1, the MAC + /// continues timing IPGR2 and transmits, knowingly causing a collision, thus + /// ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The + /// recommended value is 0xC (12d) + NBTOBINTEGAP1: u7, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u17, + }), base_address + 0xc); + + /// address: 0x50000010 + /// Collision window / Retry register. + pub const CLRT = @intToPtr(*volatile Mmio(32, packed struct { + /// RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of + /// retransmission attempts following a collision before aborting the packet due to + /// excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). + /// See IEEE 802.3/4.2.3.2.5. + RETRANSMAX: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// COLLISION WINDOW. This is a programmable field representing the slot time or + /// collision window during which collisions occur in properly configured networks. + /// The default value of 0x37 (55d) represents a 56 byte window following the + /// preamble and SFD. + COLLWIN: u6, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u18, + }), base_address + 0x10); + + /// address: 0x50000014 + /// Maximum Frame register. + pub const MAXF = @intToPtr(*volatile Mmio(32, packed struct { + /// MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a + /// maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is + /// 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a + /// shorter maximum length restriction is desired, program this 16-bit field. + MAXFLEN: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x14); + + /// address: 0x50000018 + /// PHY Support register. + pub const SUPP = @intToPtr(*volatile Mmio(32, packed struct { + /// Unused + RESERVED: u8, + /// This bit configures the Reduced MII logic for the current operating speed. When + /// set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. + SPEED: u1, + /// Unused + RESERVED: u23, + }), base_address + 0x18); + + /// address: 0x5000001c + /// Test register. + pub const TEST = @intToPtr(*volatile Mmio(32, packed struct { + /// SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 + /// byte-times to 1 byte-time. + SCPQ: u1, + /// This bit causes the MAC Control sublayer to inhibit transmissions, just as if a + /// PAUSE Receive Control frame with a nonzero pause time parameter was received. + TESTPAUSE: u1, + /// TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on + /// the link. Backpressure causes preamble to be transmitted, raising carrier sense. + /// A transmit packet from the system will be sent during backpressure. + TESTBP: u1, + /// Unused + RESERVED: u29, + }), base_address + 0x1c); + + /// address: 0x50000020 + /// MII Mgmt Configuration register. + pub const MCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform + /// read cycles across a range of PHYs. When set, the MII Management hardware will + /// perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. + /// Clear this bit to allow continuous reads of the same PHY. + SCANINC: u1, + /// SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform + /// read/write cycles without the 32-bit preamble field. Clear this bit to cause + /// normal cycles to be performed. Some PHYs support suppressed preamble. + SUPPPREAMBLE: u1, + /// CLOCK SELECT. This field is used by the clock divide logic in creating the MII + /// Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. + /// Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) + /// is divided by the specified amount. Refer to Table 160 below for the definition + /// of values for this field. + CLOCKSEL: u4, + /// Unused + reserved0: u9, + /// RESET MII MGMT. This bit resets the MII Management hardware. + RESETMIIMGMT: u1, + /// Unused + reserved1: u16, + }), base_address + 0x20); + + /// address: 0x50000024 + /// MII Mgmt Command register. + pub const MCMD = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit causes the MII Management hardware to perform a single Read cycle. The + /// Read data is returned in Register MRDD (MII Mgmt Read Data). + READ: u1, + /// This bit causes the MII Management hardware to perform Read cycles continuously. + /// This is useful for monitoring Link Fail for example. + SCAN: u1, + /// Unused + RESERVED: u30, + }), base_address + 0x24); + + /// address: 0x50000028 + /// MII Mgmt Address register. + pub const MADR = @intToPtr(*volatile Mmio(32, packed struct { + /// REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt + /// cycles. Up to 32 registers can be accessed. + REGADDR: u5, + /// Unused + RESERVED: u3, + /// PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. + /// Up to 31 PHYs can be addressed (0 is reserved). + PHYADDR: u5, + /// Unused + RESERVED: u19, + }), base_address + 0x28); + + /// address: 0x5000002c + /// MII Mgmt Write Data register. + pub const MWTD = @intToPtr(*volatile Mmio(32, packed struct { + /// WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit + /// data and the pre-configured PHY and Register addresses from the MII Mgmt Address + /// register (MADR). + WRITEDATA: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x2c); + + /// address: 0x50000030 + /// MII Mgmt Read Data register. + pub const MRDD = @intToPtr(*volatile Mmio(32, packed struct { + /// READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from + /// this location. + READDATA: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x30); + + /// address: 0x50000034 + /// MII Mgmt Indicators register. + pub const MIND = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read + /// or Write cycle. + BUSY: u1, + /// When 1 is returned - indicates a scan operation (continuous MII Mgmt Read + /// cycles) is in progress. + SCANNING: u1, + /// When 1 is returned - indicates MII Mgmt Read cycle has not completed and the + /// Read Data is not yet valid. + NOTVALID: u1, + /// When 1 is returned - indicates that an MII Mgmt link fail has occurred. + MIILINKFAIL: u1, + /// Unused + RESERVED: u28, + }), base_address + 0x34); + + /// address: 0x50000040 + /// Station Address 0 register. + pub const SA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// STATION ADDRESS, 2nd octet. This field holds the second octet of the station + /// address. + SADDR2: u8, + /// STATION ADDRESS, 1st octet. This field holds the first octet of the station + /// address. + SADDR1: u8, + /// Unused + RESERVED: u16, + }), base_address + 0x40); + + /// address: 0x50000044 + /// Station Address 1 register. + pub const SA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// STATION ADDRESS, 4th octet. This field holds the fourth octet of the station + /// address. + SADDR4: u8, + /// STATION ADDRESS, 3rd octet. This field holds the third octet of the station + /// address. + SADDR3: u8, + /// Unused + RESERVED: u16, + }), base_address + 0x44); + + /// address: 0x50000048 + /// Station Address 2 register. + pub const SA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// STATION ADDRESS, 6th octet. This field holds the sixth octet of the station + /// address. + SADDR6: u8, + /// STATION ADDRESS, 5th octet. This field holds the fifth octet of the station + /// address. + SADDR5: u8, + /// Unused + RESERVED: u16, + }), base_address + 0x48); + + /// address: 0x50000100 + /// Command register. + pub const COMMAND = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable receive. + RXENABLE: u1, + /// Enable transmit. + TXENABLE: u1, + /// Unused + RESERVED: u1, + /// When a 1 is written, all datapaths and the host registers are reset. The MAC + /// needs to be reset separately. + REGRESET: u1, + /// When a 1 is written, the transmit datapath is reset. + TXRESET: u1, + /// When a 1 is written, the receive datapath is reset. + RXRESET: u1, + /// When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they + /// have a CRC error. If 0 runt frames are filtered out. + PASSRUNTFRAME: u1, + /// When set to 1 , disables receive filtering i.e. all frames received are written + /// to memory. + PASSRXFILTER: u1, + /// Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex + /// and continuous preamble in half duplex. + TXFLOWCONTROL: u1, + /// When set to 1 , RMII mode is selected; if 0, MII mode is selected. + RMII: u1, + /// When set to 1 , indicates full duplex operation. + FULLDUPLEX: u1, + /// Unused + RESERVED: u21, + }), base_address + 0x100); + + /// address: 0x50000104 + /// Status register. + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// If 1, the receive channel is active. If 0, the receive channel is inactive. + RXSTATUS: u1, + /// If 1, the transmit channel is active. If 0, the transmit channel is inactive. + TXSTATUS: u1, + /// Unused + RESERVED: u30, + }), base_address + 0x104); + + /// address: 0x50000108 + /// Receive descriptor base address register. + pub const RXDESCRIPTOR = @intToPtr(*volatile Mmio(32, packed struct { + /// Fixed to 00 + RESERVED: u2, + /// MSBs of receive descriptor base address. + RXDESCRIPTOR: u30, + }), base_address + 0x108); + + /// address: 0x5000010c + /// Receive status base address register. + pub const RXSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Fixed to 000 + RESERVED: u3, + /// MSBs of receive status base address. + RXSTATUS: u29, + }), base_address + 0x10c); + + /// address: 0x50000110 + /// Receive number of descriptors register. + pub const RXDESCRIPTORNUMBER = @intToPtr(*volatile Mmio(32, packed struct { + /// RxDescriptorNumber. Number of descriptors in the descriptor array for which + /// RxDescriptor is the base address. The number of descriptors is minus one + /// encoded. + RXDESCRIPTORN: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x110); + + /// address: 0x50000114 + /// Receive produce index register. + pub const RXPRODUCEINDEX = @intToPtr(*volatile Mmio(32, packed struct { + /// Index of the descriptor that is going to be filled next by the receive datapath. + RXPRODUCEIX: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x114); + + /// address: 0x50000118 + /// Receive consume index register. + pub const RXCONSUMEINDEX = @intToPtr(*volatile Mmio(32, packed struct { + /// Index of the descriptor that is going to be processed next by the receive + RXCONSUMEIX: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x118); + + /// address: 0x5000011c + /// Transmit descriptor base address register. + pub const TXDESCRIPTOR = @intToPtr(*volatile Mmio(32, packed struct { + /// Fixed to 00 + RESERVED: u2, + /// TxDescriptor. MSBs of transmit descriptor base address. + TXD: u30, + }), base_address + 0x11c); + + /// address: 0x50000120 + /// Transmit status base address register. + pub const TXSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Fixed to 00 + RESERVED: u2, + /// TxStatus. MSBs of transmit status base address. + TXSTAT: u30, + }), base_address + 0x120); + + /// address: 0x50000124 + /// Transmit number of descriptors register. + pub const TXDESCRIPTORNUMBER = @intToPtr(*volatile Mmio(32, packed struct { + /// TxDescriptorNumber. Number of descriptors in the descriptor array for which + /// TxDescriptor is the base address. The register is minus one encoded. + TXDN: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x124); + + /// address: 0x50000128 + /// Transmit produce index register. + pub const TXPRODUCEINDEX = @intToPtr(*volatile Mmio(32, packed struct { + /// TxProduceIndex. Index of the descriptor that is going to be filled next by the + /// transmit software driver. + TXPI: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x128); + + /// address: 0x5000012c + /// Transmit consume index register. + pub const TXCONSUMEINDEX = @intToPtr(*volatile Mmio(32, packed struct { + /// TxConsumeIndex. Index of the descriptor that is going to be transmitted next by + /// the transmit datapath. + TXCI: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x12c); + + /// address: 0x50000158 + /// Transmit status vector 0 register. + pub const TSV0 = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC error. The attached CRC in the packet did not match the internally generated + /// CRC. + CRCERR: u1, + /// Length check error. Indicates the frame length field does not match the actual + /// number of data items and is not a type field. + LCE: u1, + /// Length out of range. Indicates that frame type/length field was larger than 1500 + /// bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. + /// when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame + /// type with the max length and gives the "Length out of range" error. In fact, + /// this bit is not an error indication, but simply a statement by the chip + /// regarding the status of the received frame. + LOR: u1, + /// Transmission of packet was completed. + DONE: u1, + /// Packet's destination was a multicast address. + MULTICAST: u1, + /// Packet's destination was a broadcast address. + BROADCAST: u1, + /// Packet was deferred for at least one attempt, but less than an excessive defer. + PACKETDEFER: u1, + /// Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps + /// or 24287 bit times in 10 Mbps mode. + EXDF: u1, + /// Excessive Collision. Packet was aborted due to exceeding of maximum allowed + /// number of collisions. + EXCOL: u1, + /// Late Collision. Collision occurred beyond collision window, 512 bit times. + LCOL: u1, + /// Byte count in frame was greater than can be represented in the transmit byte + /// count field in TSV1. + GIANT: u1, + /// Host side caused buffer underrun. + UNDERRUN: u1, + /// The total number of bytes transferred including collided attempts. + TOTALBYTES: u16, + /// The frame was a control frame. + CONTROLFRAME: u1, + /// The frame was a control frame with a valid PAUSE opcode. + PAUSE: u1, + /// Carrier-sense method backpressure was previously applied. + BACKPRESSURE: u1, + /// Frame's length/type field contained 0x8100 which is the VLAN protocol + /// identifier. + VLAN: u1, + }), base_address + 0x158); + + /// address: 0x5000015c + /// Transmit status vector 1 register. + pub const TSV1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit byte count. The total number of bytes in the frame, not counting the + /// collided bytes. + TBC: u16, + /// Transmit collision count. Number of collisions the current packet incurred + /// during transmission attempts. The maximum number of collisions (16) cannot be + /// represented. + TCC: u4, + /// Unused + RESERVED: u12, + }), base_address + 0x15c); + + /// address: 0x50000160 + /// Receive status vector register. + pub const RSV = @intToPtr(*volatile Mmio(32, packed struct { + /// Received byte count. Indicates length of received frame. + RBC: u16, + /// Packet previously ignored. Indicates that a packet was dropped. + PPI: u1, + /// RXDV event previously seen. Indicates that the last receive event seen was not + /// long enough to be a valid packet. + RXDVSEEN: u1, + /// Carrier event previously seen. Indicates that at some time since the last + /// receive statistics, a carrier event was detected. + CESEEN: u1, + /// Receive code violation. Indicates that received PHY data does not represent a + /// valid receive code. + RCV: u1, + /// CRC error. The attached CRC in the packet did not match the internally generated + /// CRC. + CRCERR: u1, + /// Length check error. Indicates the frame length field does not match the actual + /// number of data items and is not a type field. + LCERR: u1, + /// Length out of range. Indicates that frame type/length field was larger than 1518 + /// bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. + /// when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame + /// type with the max length and gives the "Length out of range" error. In fact, + /// this bit is not an error indication, but simply a statement by the chip + /// regarding the status of the received frame. + LOR: u1, + /// Receive OK. The packet had valid CRC and no symbol errors. + ROK: u1, + /// The packet destination was a multicast address. + MULTICAST: u1, + /// The packet destination was a broadcast address. + BROADCAST: u1, + /// Indicates that after the end of packet another 1-7 bits were received. A single + /// nibble, called dribble nibble, is formed but not sent out. + DRIBBLENIBBLE: u1, + /// The frame was a control frame. + CONTROLFRAME: u1, + /// The frame was a control frame with a valid PAUSE opcode. + PAUSE: u1, + /// Unsupported Opcode. The current frame was recognized as a Control Frame but + /// contains an unknown opcode. + UO: u1, + /// Frame's length/type field contained 0x8100 which is the VLAN protocol + /// identifier. + VLAN: u1, + /// Unused + RESERVED: u1, + }), base_address + 0x160); + + /// address: 0x50000170 + /// Flow control counter register. + pub const FLOWCONTROLCOUNTER = @intToPtr(*volatile Mmio(32, packed struct { + /// MirrorCounter. In full duplex mode the MirrorCounter specifies the number of + /// cycles before re-issuing the Pause control frame. + MC: u16, + /// PauseTimer. In full-duplex mode the PauseTimer specifies the value that is + /// inserted into the pause timer field of a pause flow control frame. In half + /// duplex mode the PauseTimer specifies the number of backpressure cycles. + PT: u16, + }), base_address + 0x170); + + /// address: 0x50000174 + /// Flow control status register. + pub const FLOWCONTROLSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// MirrorCounterCurrent. In full duplex mode this register represents the current + /// value of the datapath's mirror counter which counts up to the value specified by + /// the MirrorCounter field in the FlowControlCounter register. In half duplex mode + /// the register counts until it reaches the value of the PauseTimer bits in the + /// FlowControlCounter register. + MCC: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x174); + + /// address: 0x50000200 + /// Receive filter control register. + pub const RXFILTERCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// AcceptUnicastEn. When set to 1, all unicast frames are accepted. + AUE: u1, + /// AcceptBroadcastEn. When set to 1, all broadcast frames are accepted. + ABE: u1, + /// AcceptMulticastEn. When set to 1, all multicast frames are accepted. + AME: u1, + /// AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash + /// filter are accepted. + AUHE: u1, + /// AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect + /// hash filter are accepted. + AMHE: u1, + /// AcceptPerfectEn. When set to 1, the frames with a destination address identical + /// to the station address are accepted. + APE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u6, + /// MagicPacketEnWoL. When set to 1, the result of the magic packet filter will + /// generate a WoL interrupt when there is a match. + MPEW: u1, + /// RxFilterEnWoL. When set to 1, the result of the perfect address matching filter + /// and the imperfect hash filter will generate a WoL interrupt when there is a + /// match. + RFEW: u1, + /// Unused + RESERVED: u18, + }), base_address + 0x200); + + /// address: 0x50000204 + /// Receive filter WoL status register. + pub const RXFILTERWOLSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL. + AUW: u1, + /// AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL. + ABW: u1, + /// AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL. + AMW: u1, + /// AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the + /// imperfect hash filter caused WoL. + AUHW: u1, + /// AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the + /// imperfect hash filter caused WoL. + AMHW: u1, + /// AcceptPerfectWoL. When the value is 1, the perfect address matching filter + /// caused WoL. + APW: u1, + /// Unused + RESERVED: u1, + /// RxFilterWoL. When the value is 1, the receive filter caused WoL. + RFW: u1, + /// MagicPacketWoL. When the value is 1, the magic packet filter caused WoL. + MPW: u1, + /// Unused + RESERVED: u23, + }), base_address + 0x204); + + /// address: 0x50000208 + /// Receive filter WoL clear register. + pub const RXFILTERWOLCLEAR = @intToPtr(*volatile Mmio(32, packed struct { + /// AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + AUWCLR: u1, + /// AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + ABWCLR: u1, + /// AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + AMWCLR: u1, + /// AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in + /// the RxFilterWoLStatus register is cleared. + AUHWCLR: u1, + /// AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in + /// the RxFilterWoLStatus register is cleared. + AMHWCLR: u1, + /// AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + APWCLR: u1, + /// Unused + RESERVED: u1, + /// RxFilterWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + RFWCLR: u1, + /// MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + MPWCLR: u1, + /// Unused + RESERVED: u23, + }), base_address + 0x208); + + /// address: 0x50000210 + /// Hash filter table LSBs register. + pub const HASHFILTERL = @intToPtr(*volatile Mmio(32, packed struct { + /// HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering. + HFL: u32, + }), base_address + 0x210); + + /// address: 0x50000214 + /// Hash filter table MSBs register. + pub const HASHFILTERH = @intToPtr(*volatile Mmio(32, packed struct { + /// Bits 63:32 of the imperfect filter hash table for receive filtering. + HFH: u32, + }), base_address + 0x214); + + /// address: 0x50000fe0 + /// Interrupt status register. + pub const INTSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt + /// should be resolved by a Rx soft-reset. The bit is not set when there is a + /// nonfatal overrun error. + RXOVERRUNINT: u1, + /// Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, + /// SymbolError, CRCError or NoDescriptor or Overrun. + RXERRORINT: u1, + /// Interrupt triggered when all receive descriptors have been processed i.e. on the + /// transition to the situation where ProduceIndex == ConsumeIndex. + RXFINISHEDINT: u1, + /// Interrupt triggered when a receive descriptor has been processed while the + /// Interrupt bit in the Control field of the descriptor was set. + RXDONEINT: u1, + /// Interrupt set on a fatal underrun error in the transmit queue. The fatal + /// interrupt should be resolved by a Tx soft-reset. The bit is not set when there + /// is a nonfatal underrun error. + TXUNDERRUNINT: u1, + /// Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and + /// ExcessiveDefer, NoDescriptor or Underrun. + TXERRORINT: u1, + /// Interrupt triggered when all transmit descriptors have been processed i.e. on + /// the transition to the situation where ProduceIndex == ConsumeIndex. + TXFINISHEDINT: u1, + /// Interrupt triggered when a descriptor has been transmitted while the Interrupt + /// bit in the Control field of the descriptor was set. + TXDONEINT: u1, + /// Unused + RESERVED: u4, + /// Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet + /// register. + SOFTINT: u1, + /// Interrupt triggered by a Wake-up event detected by the receive filter. + WAKEUPINT: u1, + /// Unused + RESERVED: u18, + }), base_address + 0xfe0); + + /// address: 0x50000fe4 + /// Interrupt enable register. + pub const INTENABLE = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable for interrupt trigger on receive buffer overrun or descriptor underrun + /// situations. + RXOVERRUNINTEN: u1, + /// Enable for interrupt trigger on receive errors. + RXERRORINTEN: u1, + /// Enable for interrupt triggered when all receive descriptors have been processed + /// i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + RXFINISHEDINTEN: u1, + /// Enable for interrupt triggered when a receive descriptor has been processed + /// while the Interrupt bit in the Control field of the descriptor was set. + RXDONEINTEN: u1, + /// Enable for interrupt trigger on transmit buffer or descriptor underrun + /// situations. + TXUNDERRUNINTEN: u1, + /// Enable for interrupt trigger on transmit errors. + TXERRORINTEN: u1, + /// Enable for interrupt triggered when all transmit descriptors have been processed + /// i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + TXFINISHEDINTEN: u1, + /// Enable for interrupt triggered when a descriptor has been transmitted while the + /// Interrupt bit in the Control field of the descriptor was set. + TXDONEINTEN: u1, + /// Unused + RESERVED: u4, + /// Enable for interrupt triggered by the SoftInt bit in the IntStatus register, + /// caused by software writing a 1 to the SoftIntSet bit in the IntSet register. + SOFTINTEN: u1, + /// Enable for interrupt triggered by a Wake-up event detected by the receive + /// filter. + WAKEUPINTEN: u1, + /// Unused + RESERVED: u18, + }), base_address + 0xfe4); + + /// address: 0x50000fe8 + /// Interrupt clear register. + pub const INTCLEAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + RXOVERRUNINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + RXERRORINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + RXFINISHEDINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + RXDONEINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + TXUNDERRUNINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + TXERRORINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + TXFINISHEDINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + TXDONEINTCLR: u1, + /// Unused + RESERVED: u4, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + SOFTINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + WAKEUPINTCLR: u1, + /// Unused + RESERVED: u18, + }), base_address + 0xfe8); + + /// address: 0x50000fec + /// Interrupt set register. + pub const INTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + RXOVERRUNINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + RXERRORINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + RXFINISHEDINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + RXDONEINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + TXUNDERRUNINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + TXERRORINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + TXFINISHEDINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + TXDONEINTSET: u1, + /// Unused + RESERVED: u4, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + SOFTINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + WAKEUPINTSET: u1, + /// Unused + RESERVED: u18, + }), base_address + 0xfec); + + /// address: 0x50000ff4 + /// Power-down register. + pub const POWERDOWN = @intToPtr(*volatile Mmio(32, packed struct { + /// Unused + RESERVED: u31, + /// PowerDownMACAHB. If true, all AHB accesses will return a read/write error, + /// except accesses to the Power-Down register. + PD: u1, + }), base_address + 0xff4); + }; + /// General purpose DMA controller + pub const GPDMA = struct { + pub const base_address = 0x50004000; + + /// address: 0x50004000 + /// DMA Interrupt Status Register + pub const INTSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT0: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT1: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT2: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT3: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT4: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT5: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT6: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x50004004 + /// DMA Interrupt Terminal Count Request Status Register + pub const INTTCSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT0: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT1: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT2: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT3: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT4: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT5: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT6: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x50004008 + /// DMA Interrupt Terminal Count Request Clear Register + pub const INTTCCLEAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR0: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR1: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR2: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR3: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR4: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR5: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR6: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR7: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x5000400c + /// DMA Interrupt Error Status Register + pub const INTERRSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT0: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT1: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT2: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT3: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT4: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT5: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT6: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x50004010 + /// DMA Interrupt Error Clear Register + pub const INTERRCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR0: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR1: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR2: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR3: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR4: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR5: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR6: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR7: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x10); + + /// address: 0x50004014 + /// DMA Raw Interrupt Terminal Count Status Register + pub const RAWINTTCSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT0: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT1: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT2: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT3: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT4: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT5: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT6: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x14); + + /// address: 0x50004018 + /// DMA Raw Error Interrupt Status Register + pub const RAWINTERRSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT0: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT1: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT2: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT3: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT4: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT5: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT6: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x5000401c + /// DMA Enabled Channel Register + pub const ENBLDCHNS = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS0: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS1: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS2: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS3: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS4: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS5: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS6: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x1c); + + /// address: 0x50004020 + /// DMA Software Burst Request Register + pub const SOFTBREQ = @intToPtr(*volatile Mmio(32, packed struct { + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ0: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ1: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ2: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ3: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ4: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ5: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ6: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ7: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ8: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ9: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ10: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ11: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ12: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ13: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ14: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ15: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x20); + + /// address: 0x50004024 + /// DMA Software Single Request Register + pub const SOFTSREQ = @intToPtr(*volatile Mmio(32, packed struct { + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ0: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ1: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ2: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ3: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ4: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ5: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ6: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ7: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ8: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ9: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ10: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ11: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ12: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ13: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ14: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ15: u1, + /// Reserved. Read undefined. Write reserved bits as zero. + RESERVED: u16, + }), base_address + 0x24); + + /// address: 0x50004028 + /// DMA Software Last Burst Request Register + pub const SOFTLBREQ = @intToPtr(*volatile Mmio(32, packed struct { + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ0: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ1: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ2: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ3: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ4: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ5: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ6: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ7: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ8: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ9: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ10: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ11: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ12: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ13: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ14: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ15: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x28); + + /// address: 0x5000402c + /// DMA Software Last Single Request Register + pub const SOFTLSREQ = @intToPtr(*volatile Mmio(32, packed struct { + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ0: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ1: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ2: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ3: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ4: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ5: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ6: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ7: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ8: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ9: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ10: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ11: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ12: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ13: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ14: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ15: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x2c); + + /// address: 0x50004030 + /// DMA Configuration Register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller + /// reduces power consumption. 1 = enabled. + E: u1, + /// AHB Master endianness configuration: 0 = little-endian mode (default). 1 = + /// big-endian mode. + M: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x30); + + /// address: 0x50004034 + /// DMA Synchronization Register + pub const SYNC = @intToPtr(*volatile Mmio(32, packed struct { + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC0: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC1: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC2: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC3: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC4: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC5: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC6: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC7: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC8: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC9: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC10: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC11: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC12: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC13: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC14: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC15: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x34); + + /// address: 0x50004100 + /// DMA Channel 0 Source Address Register + pub const SRCADDR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x100); + + /// address: 0x50004120 + /// DMA Channel 0 Source Address Register + pub const SRCADDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x120); + + /// address: 0x50004140 + /// DMA Channel 0 Source Address Register + pub const SRCADDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x140); + + /// address: 0x50004160 + /// DMA Channel 0 Source Address Register + pub const SRCADDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x160); + + /// address: 0x50004180 + /// DMA Channel 0 Source Address Register + pub const SRCADDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x180); + + /// address: 0x500041a0 + /// DMA Channel 0 Source Address Register + pub const SRCADDR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x1a0); + + /// address: 0x500041c0 + /// DMA Channel 0 Source Address Register + pub const SRCADDR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x1c0); + + /// address: 0x500041e0 + /// DMA Channel 0 Source Address Register + pub const SRCADDR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x1e0); + + /// address: 0x50004104 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x104); + + /// address: 0x50004124 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x124); + + /// address: 0x50004144 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x144); + + /// address: 0x50004164 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x164); + + /// address: 0x50004184 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x184); + + /// address: 0x500041a4 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x1a4); + + /// address: 0x500041c4 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x1c4); + + /// address: 0x500041e4 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x1e4); + + /// address: 0x50004108 + /// DMA Channel 0 Linked List Item Register + pub const LLI0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x108); + + /// address: 0x50004128 + /// DMA Channel 0 Linked List Item Register + pub const LLI1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x128); + + /// address: 0x50004148 + /// DMA Channel 0 Linked List Item Register + pub const LLI2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x148); + + /// address: 0x50004168 + /// DMA Channel 0 Linked List Item Register + pub const LLI3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x168); + + /// address: 0x50004188 + /// DMA Channel 0 Linked List Item Register + pub const LLI4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x188); + + /// address: 0x500041a8 + /// DMA Channel 0 Linked List Item Register + pub const LLI5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x1a8); + + /// address: 0x500041c8 + /// DMA Channel 0 Linked List Item Register + pub const LLI6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x1c8); + + /// address: 0x500041e8 + /// DMA Channel 0 Linked List Item Register + pub const LLI7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x1e8); + + /// address: 0x5000410c + /// DMA Channel 0 Control Register + pub const CONTROL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x10c); + + /// address: 0x5000412c + /// DMA Channel 0 Control Register + pub const CONTROL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x12c); + + /// address: 0x5000414c + /// DMA Channel 0 Control Register + pub const CONTROL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x14c); + + /// address: 0x5000416c + /// DMA Channel 0 Control Register + pub const CONTROL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x16c); + + /// address: 0x5000418c + /// DMA Channel 0 Control Register + pub const CONTROL4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x18c); + + /// address: 0x500041ac + /// DMA Channel 0 Control Register + pub const CONTROL5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x1ac); + + /// address: 0x500041cc + /// DMA Channel 0 Control Register + pub const CONTROL6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x1cc); + + /// address: 0x500041ec + /// DMA Channel 0 Control Register + pub const CONTROL7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x1ec); + + /// address: 0x50004110 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x110); + + /// address: 0x50004130 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x130); + + /// address: 0x50004150 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x150); + + /// address: 0x50004170 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x170); + + /// address: 0x50004190 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x190); + + /// address: 0x500041b0 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x1b0); + + /// address: 0x500041d0 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x1d0); + + /// address: 0x500041f0 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x1f0); + }; + /// USB device/host/OTG controller + pub const USB = struct { + pub const base_address = 0x50008000; + + /// address: 0x50008100 + /// OTG Interrupt Status + pub const INTST = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer time-out. + TMR: u1, + /// Remove pull-up. This bit is set by hardware to indicate that software needs to + /// disable the D+ pull-up resistor. + REMOVE_PU: u1, + /// HNP failed. This bit is set by hardware to indicate that the HNP switching has + /// failed. + HNP_FAILURE: u1, + /// HNP succeeded. This bit is set by hardware to indicate that the HNP switching + /// has succeeded. + HNP_SUCCESS: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x100); + + /// address: 0x50008104 + /// OTG Interrupt Enable + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// 1 = enable the corresponding bit in the IntSt register. + TMR_EN: u1, + /// 1 = enable the corresponding bit in the IntSt register. + REMOVE_PU_EN: u1, + /// 1 = enable the corresponding bit in the IntSt register. + HNP_FAILURE_EN: u1, + /// 1 = enable the corresponding bit in the IntSt register. + HNP_SUCCES_EN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x104); + + /// address: 0x50008108 + /// OTG Interrupt Set + pub const INTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. + TMR_SET: u1, + /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. + REMOVE_PU_SET: u1, + /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. + HNP_FAILURE_SET: u1, + /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. + HNP_SUCCES_SET: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x108); + + /// address: 0x5000810c + /// OTG Interrupt Clear + pub const INTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + TMR_CLR: u1, + /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + REMOVE_PU_CLR: u1, + /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + HNP_FAILURE_CLR: u1, + /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + HNP_SUCCES_CLR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x10c); + + /// address: 0x50008110 + /// OTG Status and Control and USB port select + pub const STCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by + /// hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section + /// 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: + /// Reserved 11: U1 = host, U2 = device In a device-only configuration, the + /// following values are allowed: 00: U1 = device. The USB device controller signals + /// are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = + /// device. The USB device controller signals are mapped to the U2 port: + /// USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2. + PORT_FUNC: u2, + /// Timer scale selection. This field determines the duration of each timer count. + /// 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved + TMR_SCALE: u2, + /// Timer mode selection. 0: monoshot 1: free running + TMR_MODE: u1, + /// Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0. + TMR_EN: u1, + /// Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single + /// bit control for the software to restart the timer when the timer is enabled. + TMR_RST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears + /// this bit when HNP_SUCCESS or HNP_FAILURE is set. + B_HNP_TRACK: u1, + /// Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this + /// bit when HNP_SUCCESS or HNP_FAILURE is set. + A_HNP_TRACK: u1, + /// When the B-device changes its role from peripheral to host, software sets this + /// bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit + /// when HNP_SUCCESS or HNP_FAILURE is set. + PU_REMOVED: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// Current timer count value. + TMR_CNT: u16, + }), base_address + 0x110); + + /// address: 0x50008114 + /// OTG Timer + pub const TMR = @intToPtr(*volatile Mmio(32, packed struct { + /// The TMR interrupt is set when TMR_CNT reaches this value. + TIMEOUT_CNT: u16, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x114); + + /// address: 0x50008200 + /// USB Device Interrupt Status + pub const DEVINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// The frame interrupt occurs every 1 ms. This is used in isochronous packet + /// transfers. + FRAME: u1, + /// Fast endpoint interrupt. If an Endpoint Interrupt Priority register + /// (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to + /// this bit. + EP_FAST: u1, + /// Slow endpoints interrupt. If an Endpoint Interrupt Priority Register + /// (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be + /// routed to this bit. + EP_SLOW: u1, + /// Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer + /// to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page + /// 366. + DEV_STAT: u1, + /// The command code register (USBCmdCode) is empty (New command can be written). + CCEMPTY: u1, + /// Command data register (USBCmdData) is full (Data can be read now). + CDFULL: u1, + /// The current packet in the endpoint buffer is transferred to the CPU. + RxENDPKT: u1, + /// The number of data bytes transferred to the endpoint buffer equals the number of + /// bytes programmed in the TxPacket length register (USBTxPLen). + TxENDPKT: u1, + /// Endpoints realized. Set when Realize Endpoint register (USBReEp) or + /// MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation + /// is completed. + EP_RLZED: u1, + /// Error Interrupt. Any bus error interrupt from the USB device. Refer to Section + /// 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368 + ERR_INT: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x200); + + /// address: 0x50008204 + /// USB Device Interrupt Enable + pub const DEVINTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + FRAMEEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_FASTEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_SLOWEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + DEV_STATEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + CCEMPTYEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + CDFULLEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + RxENDPKTEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + TxENDPKTEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_RLZEDEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + ERR_INTEN: u1, + /// Reserved + RESERVED: u22, + }), base_address + 0x204); + + /// address: 0x50008208 + /// USB Device Interrupt Clear + pub const DEVINTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + FRAMECLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + EP_FASTCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + EP_SLOWCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + DEV_STATCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + CCEMPTYCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + CDFULLCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + RxENDPKTCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + TxENDPKTCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + EP_RLZEDCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + ERR_INTCLR: u1, + /// Reserved + RESERVED: u22, + }), base_address + 0x208); + + /// address: 0x5000820c + /// USB Device Interrupt Set + pub const DEVINTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + FRAMESET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + EP_FASTSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + EP_SLOWSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + DEV_STATSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + CCEMPTYSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + CDFULLSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + RxENDPKTSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + TxENDPKTSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + EP_RLZEDSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + ERR_INTSET: u1, + /// Reserved + RESERVED: u22, + }), base_address + 0x20c); + + /// address: 0x50008210 + /// USB Command Code + pub const CMDCODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// The command phase: + CMD_PHASE: u8, + /// This is a multi-purpose field. When CMD_PHASE is Command or Read, this field + /// contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this + /// field contains the command write data (CMD_WDATA). + CMD_CODE_WDATA: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + }), base_address + 0x210); + + /// address: 0x50008214 + /// USB Command Data + pub const CMDDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Command Read Data. + CMD_RDATA: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x214); + + /// address: 0x50008218 + /// USB Receive Data + pub const RXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Data received. + RX_DATA: u32, + }), base_address + 0x218); + + /// address: 0x5000821c + /// USB Transmit Data + pub const TXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Data. + TX_DATA: u32, + }), base_address + 0x21c); + + /// address: 0x500080dc + /// USB Receive Packet Length + pub const RXPLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// The remaining number of bytes to be read from the currently selected endpoint's + /// buffer. When this field decrements to 0, the RxENDPKT bit will be set in + /// USBDevIntSt. + PKT_LNGTH: u10, + /// Data valid. This bit is useful for isochronous endpoints. Non-isochronous + /// endpoints do not raise an interrupt when an erroneous data packet is received. + /// But invalid data packet can be produced with a bus reset. For isochronous + /// endpoints, data transfer will happen even if an erroneous packet is received. In + /// this case DV bit will not be set for the packet. + DV: u1, + /// The PKT_LNGTH field is valid and the packet is ready for reading. + PKT_RDY: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0xdc); + + /// address: 0x50008224 + /// USB Transmit Packet Length + pub const TXPLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// The remaining number of bytes to be written to the selected endpoint buffer. + /// This field is decremented by 4 by hardware after each write to USBTxData. When + /// this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt. + PKT_LNGTH: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x224); + + /// address: 0x50008228 + /// USB Control + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Read mode control. Enables reading data from the OUT endpoint buffer for the + /// endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This + /// bit is cleared by hardware when the last word of the current packet is read from + /// USBRxData. + RD_EN: u1, + /// Write mode control. Enables writing data to the IN endpoint buffer for the + /// endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This + /// bit is cleared by hardware when the number of bytes in USBTxLen have been sent. + WR_EN: u1, + /// Logical Endpoint number. + LOG_ENDPOINT: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x228); + + /// address: 0x5000822c + /// USB Device Interrupt Priority + pub const DEVINTPRI = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame interrupt routing + FRAME: u1, + /// Fast endpoint interrupt routing + EP_FAST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x22c); + + /// address: 0x50008230 + /// USB Endpoint Interrupt Status + pub const EPINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST0: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST1: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST2: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST3: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST4: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST5: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST6: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST7: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST8: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST9: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST10: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST11: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST12: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST13: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST14: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST15: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST16: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST17: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST18: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST19: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST20: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST21: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST22: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST23: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST24: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST25: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST26: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST27: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST28: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST29: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST30: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST31: u1, + }), base_address + 0x230); + + /// address: 0x50008234 + /// USB Endpoint Interrupt Enable + pub const EPINTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN0: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN1: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN2: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN3: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN4: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN5: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN6: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN7: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN8: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN9: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN10: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN11: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN12: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN13: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN14: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN15: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN16: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN17: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN18: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN19: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN20: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN21: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN22: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN23: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN24: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN25: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN26: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN27: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN28: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN29: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN30: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN31: u1, + }), base_address + 0x234); + + /// address: 0x50008238 + /// USB Endpoint Interrupt Clear + pub const EPINTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR0: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR1: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR2: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR3: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR4: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR5: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR6: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR7: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR8: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR9: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR10: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR11: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR12: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR13: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR14: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR15: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR16: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR17: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR18: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR19: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR20: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR21: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR22: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR23: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR24: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR25: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR26: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR27: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR28: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR29: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR30: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR31: u1, + }), base_address + 0x238); + + /// address: 0x5000823c + /// USB Endpoint Interrupt Set + pub const EPINTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET0: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET1: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET2: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET3: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET4: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET5: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET6: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET7: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET8: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET9: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET10: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET11: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET12: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET13: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET14: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET15: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET16: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET17: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET18: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET19: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET20: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET21: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET22: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET23: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET24: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET25: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET26: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET27: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET28: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET29: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET30: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET31: u1, + }), base_address + 0x23c); + + /// address: 0x50008240 + /// USB Endpoint Priority + pub const EPINTPRI = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI0: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI1: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI2: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI3: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI4: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI5: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI6: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI7: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI8: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI9: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI10: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI11: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI12: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI13: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI14: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI15: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI16: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI17: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI18: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI19: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI20: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI21: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI22: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI23: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI24: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI25: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI26: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI27: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI28: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI29: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI30: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI31: u1, + }), base_address + 0x240); + + /// address: 0x50008244 + /// USB Realize Endpoint + pub const REEP = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR0: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR1: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR2: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR3: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR4: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR5: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR6: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR7: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR8: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR9: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR10: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR11: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR12: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR13: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR14: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR15: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR16: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR17: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR18: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR19: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR20: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR21: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR22: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR23: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR24: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR25: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR26: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR27: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR28: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR29: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR30: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR31: u1, + }), base_address + 0x244); + + /// address: 0x50008248 + /// USB Endpoint Index + pub const EPIND = @intToPtr(*volatile Mmio(32, packed struct { + /// Physical endpoint number (0-31) + PHY_EP: u5, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0x248); + + /// address: 0x5000824c + /// USB MaxPacketSize + pub const MAXPSIZE = @intToPtr(*volatile Mmio(32, packed struct { + /// The maximum packet size value. + MPS: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x24c); + + /// address: 0x50008250 + /// USB DMA Request Status + pub const DMARST = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must + /// be 0). + EPRST0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be + /// 0). + EPRST1: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST2: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST3: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST4: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST5: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST6: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST7: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST8: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST9: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST10: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST11: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST12: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST13: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST14: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST15: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST16: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST17: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST18: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST19: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST20: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST21: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST22: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST23: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST24: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST25: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST26: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST27: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST28: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST29: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST30: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST31: u1, + }), base_address + 0x250); + + /// address: 0x50008254 + /// USB DMA Request Clear + pub const DMARCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit + /// must be 0). + EPRCLR0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit + /// must be 0). + EPRCLR1: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR2: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR3: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR4: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR5: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR6: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR7: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR8: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR9: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR10: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR11: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR12: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR13: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR14: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR15: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR16: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR17: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR18: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR19: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR20: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR21: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR22: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR23: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR24: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR25: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR26: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR27: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR28: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR29: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR30: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR31: u1, + }), base_address + 0x254); + + /// address: 0x50008258 + /// USB DMA Request Set + pub const DMARSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit + /// must be 0). + EPRSET0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit + /// must be 0). + EPRSET1: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET2: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET3: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET4: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET5: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET6: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET7: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET8: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET9: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET10: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET11: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET12: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET13: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET14: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET15: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET16: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET17: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET18: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET19: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET20: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET21: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET22: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET23: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET24: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET25: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET26: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET27: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET28: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET29: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET30: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET31: u1, + }), base_address + 0x258); + + /// address: 0x50008280 + /// USB UDCA Head + pub const UDCAH = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. The UDCA is + /// aligned to 128-byte boundaries. + RESERVED: u7, + /// Start address of the UDCA. + UDCA_ADDR: u25, + }), base_address + 0x280); + + /// address: 0x50008284 + /// USB Endpoint DMA Status + pub const EPDMAST = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the + /// EP0_DMA_ENABLE bit must be 0). + EP_DMA_ST0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and the + /// EP1_DMA_ENABLE bit must be 0). + EP_DMA_ST1: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST2: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST3: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST4: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST5: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST6: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST7: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST8: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST9: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST10: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST11: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST12: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST13: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST14: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST15: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST16: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST17: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST18: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST19: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST20: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST21: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST22: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST23: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST24: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST25: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST26: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST27: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST28: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST29: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST30: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST31: u1, + }), base_address + 0x284); + + /// address: 0x50008288 + /// USB Endpoint DMA Enable + pub const EPDMAEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the + /// EP0_DMA_ENABLE bit value must be 0). + EP_DMA_EN0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and the + /// EP1_DMA_ENABLE bit must be 0). + EP_DMA_EN1: u1, + /// Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the + /// DMA operation for endpoint EPxx. + EP_DMA_EN: u30, + }), base_address + 0x288); + + /// address: 0x5000828c + /// USB Endpoint DMA Disable + pub const EPDMADIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the + /// EP0_DMA_DISABLE bit value must be 0). + EP_DMA_DIS0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and the + /// EP1_DMA_DISABLE bit value must be 0). + EP_DMA_DIS1: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS2: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS3: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS4: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS5: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS6: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS7: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS8: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS9: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS10: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS11: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS12: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS13: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS14: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS15: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS16: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS17: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS18: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS19: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS20: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS21: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS22: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS23: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS24: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS25: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS26: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS27: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS28: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS29: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS30: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS31: u1, + }), base_address + 0x28c); + + /// address: 0x50008290 + /// USB DMA Interrupt Status + pub const DMAINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// End of Transfer Interrupt bit. + EOT: u1, + /// New DD Request Interrupt bit. + NDDR: u1, + /// System Error Interrupt bit. + ERR: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u29, + }), base_address + 0x290); + + /// address: 0x50008294 + /// USB DMA Interrupt Enable + pub const DMAINTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// End of Transfer Interrupt enable bit. + EOT: u1, + /// New DD Request Interrupt enable bit. + NDDR: u1, + /// System Error Interrupt enable bit. + ERR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u29, + }), base_address + 0x294); + + /// address: 0x500082a0 + /// USB End of Transfer Interrupt Status + pub const EOTINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST0: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST1: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST2: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST3: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST4: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST5: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST6: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST7: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST8: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST9: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST10: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST11: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST12: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST13: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST14: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST15: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST16: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST17: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST18: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST19: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST20: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST21: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST22: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST23: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST24: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST25: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST26: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST27: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST28: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST29: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST30: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST31: u1, + }), base_address + 0x2a0); + + /// address: 0x500082a4 + /// USB End of Transfer Interrupt Clear + pub const EOTINTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR0: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR1: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR2: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR3: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR4: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR5: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR6: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR7: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR8: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR9: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR10: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR11: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR12: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR13: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR14: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR15: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR16: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR17: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR18: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR19: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR20: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR21: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR22: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR23: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR24: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR25: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR26: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR27: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR28: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR29: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR30: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR31: u1, + }), base_address + 0x2a4); + + /// address: 0x500082a8 + /// USB End of Transfer Interrupt Set + pub const EOTINTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET0: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET1: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET2: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET3: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET4: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET5: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET6: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET7: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET8: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET9: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET10: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET11: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET12: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET13: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET14: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET15: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET16: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET17: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET18: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET19: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET20: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET21: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET22: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET23: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET24: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET25: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET26: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET27: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET28: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET29: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET30: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET31: u1, + }), base_address + 0x2a8); + + /// address: 0x500082ac + /// USB New DD Request Interrupt Status + pub const NDDRINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST0: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST1: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST2: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST3: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST4: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST5: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST6: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST7: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST8: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST9: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST10: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST11: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST12: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST13: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST14: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST15: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST16: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST17: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST18: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST19: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST20: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST21: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST22: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST23: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST24: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST25: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST26: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST27: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST28: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST29: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST30: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST31: u1, + }), base_address + 0x2ac); + + /// address: 0x500082b0 + /// USB New DD Request Interrupt Clear + pub const NDDRINTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR0: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR1: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR2: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR3: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR4: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR5: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR6: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR7: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR8: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR9: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR10: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR11: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR12: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR13: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR14: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR15: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR16: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR17: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR18: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR19: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR20: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR21: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR22: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR23: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR24: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR25: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR26: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR27: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR28: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR29: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR30: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR31: u1, + }), base_address + 0x2b0); + + /// address: 0x500082b4 + /// USB New DD Request Interrupt Set + pub const NDDRINTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET0: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET1: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET2: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET3: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET4: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET5: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET6: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET7: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET8: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET9: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET10: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET11: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET12: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET13: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET14: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET15: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET16: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET17: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET18: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET19: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET20: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET21: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET22: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET23: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET24: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET25: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET26: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET27: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET28: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET29: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET30: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET31: u1, + }), base_address + 0x2b4); + + /// address: 0x500082b8 + /// USB System Error Interrupt Status + pub const SYSERRINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST0: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST1: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST2: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST3: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST4: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST5: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST6: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST7: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST8: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST9: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST10: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST11: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST12: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST13: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST14: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST15: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST16: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST17: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST18: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST19: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST20: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST21: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST22: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST23: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST24: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST25: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST26: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST27: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST28: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST29: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST30: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST31: u1, + }), base_address + 0x2b8); + + /// address: 0x500082bc + /// USB System Error Interrupt Clear + pub const SYSERRINTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR0: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR1: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR2: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR3: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR4: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR5: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR6: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR7: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR8: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR9: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR10: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR11: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR12: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR13: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR14: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR15: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR16: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR17: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR18: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR19: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR20: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR21: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR22: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR23: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR24: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR25: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR26: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR27: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR28: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR29: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR30: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR31: u1, + }), base_address + 0x2bc); + + /// address: 0x500082c0 + /// USB System Error Interrupt Set + pub const SYSERRINTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET0: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET1: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET2: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET3: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET4: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET5: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET6: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET7: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET8: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET9: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET10: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET11: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET12: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET13: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET14: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET15: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET16: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET17: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET18: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET19: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET20: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET21: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET22: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET23: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET24: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET25: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET26: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET27: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET28: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET29: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET30: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET31: u1, + }), base_address + 0x2c0); + + /// address: 0x50008300 + /// I2C Receive + pub const I2C_RX = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive data. + RXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x300); + + /// address: 0x50008300 + /// I2C Transmit + pub const I2C_WO = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit data. + TXDATA: u8, + /// When 1, issue a START condition before transmitting this byte. + START: u1, + /// When 1, issue a STOP condition after transmitting this byte. + STOP: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x300); + + /// address: 0x50008304 + /// I2C Status + pub const I2C_STS = @intToPtr(*volatile Mmio(32, packed struct { + /// Transaction Done Interrupt. This flag is set if a transaction completes + /// successfully. It is cleared by writing a one to bit 0 of the status register. It + /// is unaffected by slave transactions. + TDI: u1, + /// Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT + /// is high, then this I2C has lost the arbitration to another device on the bus. + /// The Arbitration Failure bit is set when this happens. It is cleared by writing a + /// one to bit 1 of the status register. + AFI: u1, + /// No Acknowledge Interrupt. After every byte of data is sent, the transmitter + /// expects an acknowledge from the receiver. This bit is set if the acknowledge is + /// not received. It is cleared when a byte is written to the master TX FIFO. + NAI: u1, + /// Master Data Request Interrupt. Once a transmission is started, the transmitter + /// must have data to transmit as long as it isn't followed by a stop condition or + /// it will hold SCL low until more data is available. The Master Data Request bit + /// is set when the master transmitter is data-starved. If the master TX FIFO is + /// empty and the last byte did not have a STOP condition flag, then SCL is held low + /// until the CPU writes another byte to transmit. This bit is cleared when a byte + /// is written to the master TX FIFO. + DRMI: u1, + /// Slave Data Request Interrupt. Once a transmission is started, the transmitter + /// must have data to transmit as long as it isn't followed by a STOP condition or + /// it will hold SCL low until more data is available. The Slave Data Request bit is + /// set when the slave transmitter is data-starved. If the slave TX FIFO is empty + /// and the last byte transmitted was acknowledged, then SCL is held low until the + /// CPU writes another byte to transmit. This bit is cleared when a byte is written + /// to the slave Tx FIFO. + DRSI: u1, + /// Indicates whether the bus is busy. This bit is set when a START condition has + /// been seen. It is cleared when a STOP condition is seen.. + Active: u1, + /// The current value of the SCL signal. + SCL: u1, + /// The current value of the SDA signal. + SDA: u1, + /// Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot + /// accept any more data. It is cleared when the RX FIFO is not full. If a byte + /// arrives when the Receive FIFO is full, the SCL is held low until the CPU reads + /// the RX FIFO and makes room for it. + RFF: u1, + /// Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the + /// RX FIFO contains valid data. + RFE: u1, + /// Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the + /// TX FIFO is not full. + TFF: u1, + /// Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when + /// the TX FIFO contains valid data. + TFE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u20, + }), base_address + 0x304); + + /// address: 0x50008308 + /// I2C Control + pub const I2C_CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that + /// this I2C issued a STOP condition. + TDIE: u1, + /// Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt + /// which is asserted during transmission when trying to set SDA high, but the bus + /// is driven low by another device. + AFIE: u1, + /// Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt + /// signalling that transmitted byte was not acknowledged. + NAIE: u1, + /// Master Transmitter Data Request Interrupt Enable. This enables the DRMI + /// interrupt which signals that the master transmitter has run out of data, has not + /// issued a STOP, and is holding the SCL line low. + DRMIE: u1, + /// Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt + /// which signals that the slave transmitter has run out of data and the last byte + /// was acknowledged, so the SCL line is being held low. + DRSIE: u1, + /// Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt + /// to indicate that the receive FIFO cannot accept any more data. + REFIE: u1, + /// Receive Data Available Interrupt Enable. This enables the DAI interrupt to + /// indicate that data is available in the receive FIFO (i.e. not empty). + RFDAIE: u1, + /// Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full + /// interrupt to indicate that the more data can be written to the transmit FIFO. + /// Note that this is not full. It is intended help the CPU to write to the I2C + /// block only when there is room in the FIFO and do this without polling the status + /// register. + TFFIE: u1, + /// Soft reset. This is only needed in unusual circumstances. If a device issues a + /// start condition without issuing a stop condition. A system timer may be used to + /// reset the I2C if the bus remains busy longer than the time-out period. On a soft + /// reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all + /// internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and + /// I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset. + SRST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u23, + }), base_address + 0x308); + + /// address: 0x5000830c + /// I2C Clock High + pub const I2C_CLKHI = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock divisor high. This value is the number of 48 MHz clocks the serial clock + /// (SCL) will be high. + CDHI: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x30c); + + /// address: 0x50008310 + /// I2C Clock Low + pub const I2C_CLKLO = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock divisor low. This value is the number of 48 MHz clocks the serial clock + /// (SCL) will be low. + CDLO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x310); + + /// address: 0x50008ff4 + /// USB Clock Control + pub const USBCLKCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Device clock enable. Enables the usbclk input to the device controller + DEV_CLK_EN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Port select register clock enable. + PORTSEL_CLK_EN: u1, + /// AHB clock enable + AHB_CLK_EN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0xff4); + + /// address: 0x50008ff4 + /// OTG clock controller + pub const OTGCLKCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Host clock enable + HOST_CLK_EN: u1, + /// Device clock enable + DEV_CLK_EN: u1, + /// I2C clock enable + I2C_CLK_EN: u1, + /// OTG clock enable. In device-only applications, this bit enables access to the + /// PORTSEL register. + OTG_CLK_EN: u1, + /// AHB master clock enable + AHB_CLK_EN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0xff4); + + /// address: 0x50008ff8 + /// USB Clock Status + pub const USBCLKST = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Device clock on. The usbclk input to the device controller is active . + DEV_CLK_ON: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Port select register clock on. + PORTSEL_CLK_ON: u1, + /// AHB clock on. + AHB_CLK_ON: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0xff8); + + /// address: 0x50008ff8 + /// OTG clock status + pub const OTGCLKST = @intToPtr(*volatile Mmio(32, packed struct { + /// Host clock status. + HOST_CLK_ON: u1, + /// Device clock status. + DEV_CLK_ON: u1, + /// I2C clock status. + I2C_CLK_ON: u1, + /// OTG clock status. + OTG_CLK_ON: u1, + /// AHB master clock status. + AHB_CLK_ON: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0xff8); + }; + /// General Purpose I/O + pub const GPIO = struct { + pub const base_address = 0x2009c000; + + /// address: 0x2009c000 + /// GPIO Port Direction control register. + pub const DIR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR0: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR1: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR2: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR3: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR4: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR5: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR6: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR7: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR8: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR9: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR10: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR11: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR12: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR13: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR14: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR15: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR16: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR17: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR18: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR19: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR20: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR21: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR22: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR23: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR24: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR25: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR26: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR27: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR28: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR29: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR30: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR31: u1, + }), base_address + 0x0); + + /// address: 0x2009c020 + /// GPIO Port Direction control register. + pub const DIR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR0: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR1: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR2: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR3: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR4: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR5: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR6: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR7: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR8: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR9: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR10: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR11: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR12: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR13: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR14: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR15: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR16: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR17: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR18: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR19: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR20: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR21: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR22: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR23: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR24: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR25: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR26: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR27: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR28: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR29: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR30: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR31: u1, + }), base_address + 0x20); + + /// address: 0x2009c040 + /// GPIO Port Direction control register. + pub const DIR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR0: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR1: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR2: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR3: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR4: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR5: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR6: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR7: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR8: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR9: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR10: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR11: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR12: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR13: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR14: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR15: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR16: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR17: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR18: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR19: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR20: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR21: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR22: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR23: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR24: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR25: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR26: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR27: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR28: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR29: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR30: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR31: u1, + }), base_address + 0x40); + + /// address: 0x2009c060 + /// GPIO Port Direction control register. + pub const DIR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR0: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR1: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR2: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR3: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR4: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR5: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR6: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR7: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR8: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR9: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR10: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR11: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR12: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR13: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR14: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR15: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR16: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR17: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR18: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR19: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR20: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR21: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR22: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR23: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR24: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR25: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR26: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR27: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR28: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR29: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR30: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR31: u1, + }), base_address + 0x60); + + /// address: 0x2009c080 + /// GPIO Port Direction control register. + pub const DIR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR0: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR1: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR2: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR3: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR4: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR5: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR6: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR7: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR8: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR9: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR10: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR11: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR12: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR13: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR14: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR15: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR16: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR17: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR18: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR19: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR20: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR21: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR22: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR23: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR24: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR25: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR26: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR27: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR28: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR29: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR30: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR31: u1, + }), base_address + 0x80); + + /// address: 0x2009c010 + /// Mask register for Port. + pub const MASK0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK0: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK1: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK2: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK3: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK4: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK5: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK6: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK7: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK8: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK9: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK10: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK11: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK12: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK13: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK14: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK15: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK16: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK17: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK18: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK19: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK20: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK21: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK22: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK23: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK24: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK25: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK26: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK27: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK28: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK29: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK30: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK31: u1, + }), base_address + 0x10); + + /// address: 0x2009c030 + /// Mask register for Port. + pub const MASK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK0: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK1: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK2: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK3: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK4: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK5: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK6: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK7: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK8: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK9: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK10: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK11: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK12: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK13: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK14: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK15: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK16: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK17: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK18: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK19: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK20: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK21: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK22: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK23: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK24: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK25: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK26: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK27: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK28: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK29: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK30: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK31: u1, + }), base_address + 0x30); + + /// address: 0x2009c050 + /// Mask register for Port. + pub const MASK2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK0: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK1: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK2: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK3: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK4: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK5: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK6: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK7: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK8: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK9: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK10: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK11: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK12: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK13: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK14: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK15: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK16: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK17: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK18: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK19: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK20: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK21: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK22: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK23: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK24: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK25: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK26: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK27: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK28: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK29: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK30: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK31: u1, + }), base_address + 0x50); + + /// address: 0x2009c070 + /// Mask register for Port. + pub const MASK3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK0: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK1: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK2: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK3: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK4: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK5: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK6: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK7: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK8: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK9: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK10: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK11: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK12: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK13: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK14: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK15: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK16: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK17: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK18: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK19: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK20: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK21: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK22: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK23: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK24: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK25: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK26: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK27: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK28: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK29: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK30: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK31: u1, + }), base_address + 0x70); + + /// address: 0x2009c090 + /// Mask register for Port. + pub const MASK4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK0: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK1: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK2: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK3: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK4: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK5: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK6: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK7: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK8: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK9: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK10: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK11: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK12: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK13: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK14: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK15: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK16: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK17: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK18: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK19: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK20: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK21: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK22: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK23: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK24: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK25: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK26: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK27: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK28: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK29: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK30: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK31: u1, + }), base_address + 0x90); + + /// address: 0x2009c014 + /// Port Pin value register using FIOMASK. + pub const PIN0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL0: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL1: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL2: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL3: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL4: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL5: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL6: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL7: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL8: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL9: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL10: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL11: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL12: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL13: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL14: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL15: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL16: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL17: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL18: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL19: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL20: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL21: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL22: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL23: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL24: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL25: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL26: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL27: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL28: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL29: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL30: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL31: u1, + }), base_address + 0x14); + + /// address: 0x2009c034 + /// Port Pin value register using FIOMASK. + pub const PIN1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL0: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL1: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL2: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL3: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL4: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL5: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL6: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL7: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL8: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL9: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL10: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL11: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL12: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL13: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL14: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL15: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL16: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL17: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL18: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL19: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL20: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL21: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL22: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL23: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL24: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL25: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL26: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL27: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL28: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL29: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL30: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL31: u1, + }), base_address + 0x34); + + /// address: 0x2009c054 + /// Port Pin value register using FIOMASK. + pub const PIN2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL0: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL1: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL2: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL3: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL4: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL5: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL6: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL7: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL8: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL9: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL10: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL11: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL12: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL13: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL14: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL15: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL16: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL17: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL18: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL19: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL20: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL21: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL22: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL23: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL24: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL25: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL26: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL27: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL28: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL29: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL30: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL31: u1, + }), base_address + 0x54); + + /// address: 0x2009c074 + /// Port Pin value register using FIOMASK. + pub const PIN3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL0: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL1: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL2: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL3: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL4: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL5: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL6: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL7: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL8: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL9: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL10: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL11: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL12: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL13: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL14: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL15: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL16: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL17: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL18: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL19: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL20: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL21: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL22: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL23: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL24: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL25: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL26: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL27: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL28: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL29: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL30: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL31: u1, + }), base_address + 0x74); + + /// address: 0x2009c094 + /// Port Pin value register using FIOMASK. + pub const PIN4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL0: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL1: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL2: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL3: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL4: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL5: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL6: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL7: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL8: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL9: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL10: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL11: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL12: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL13: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL14: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL15: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL16: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL17: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL18: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL19: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL20: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL21: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL22: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL23: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL24: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL25: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL26: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL27: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL28: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL29: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL30: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL31: u1, + }), base_address + 0x94); + + /// address: 0x2009c018 + /// Port Output Set register using FIOMASK. + pub const SET0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET0: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET1: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET2: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET3: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET4: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET5: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET6: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET7: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET8: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET9: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET10: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET11: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET12: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET13: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET14: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET15: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET16: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET17: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET18: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET19: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET20: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET21: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET22: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET23: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET24: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET25: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET26: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET27: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET28: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET29: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET30: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET31: u1, + }), base_address + 0x18); + + /// address: 0x2009c038 + /// Port Output Set register using FIOMASK. + pub const SET1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET0: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET1: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET2: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET3: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET4: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET5: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET6: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET7: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET8: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET9: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET10: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET11: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET12: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET13: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET14: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET15: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET16: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET17: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET18: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET19: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET20: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET21: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET22: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET23: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET24: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET25: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET26: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET27: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET28: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET29: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET30: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET31: u1, + }), base_address + 0x38); + + /// address: 0x2009c058 + /// Port Output Set register using FIOMASK. + pub const SET2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET0: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET1: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET2: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET3: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET4: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET5: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET6: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET7: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET8: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET9: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET10: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET11: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET12: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET13: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET14: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET15: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET16: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET17: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET18: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET19: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET20: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET21: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET22: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET23: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET24: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET25: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET26: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET27: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET28: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET29: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET30: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET31: u1, + }), base_address + 0x58); + + /// address: 0x2009c078 + /// Port Output Set register using FIOMASK. + pub const SET3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET0: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET1: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET2: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET3: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET4: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET5: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET6: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET7: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET8: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET9: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET10: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET11: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET12: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET13: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET14: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET15: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET16: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET17: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET18: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET19: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET20: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET21: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET22: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET23: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET24: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET25: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET26: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET27: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET28: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET29: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET30: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET31: u1, + }), base_address + 0x78); + + /// address: 0x2009c098 + /// Port Output Set register using FIOMASK. + pub const SET4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET0: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET1: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET2: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET3: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET4: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET5: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET6: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET7: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET8: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET9: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET10: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET11: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET12: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET13: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET14: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET15: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET16: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET17: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET18: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET19: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET20: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET21: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET22: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET23: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET24: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET25: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET26: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET27: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET28: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET29: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET30: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET31: u1, + }), base_address + 0x98); + + /// address: 0x2009c01c + /// Port Output Clear register using FIOMASK. + pub const CLR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR0: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR1: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR2: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR3: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR4: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR5: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR6: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR7: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR8: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR9: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR10: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR11: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR12: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR13: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR14: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR15: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR16: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR17: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR18: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR19: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR20: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR21: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR22: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR23: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR24: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR25: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR26: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR27: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR28: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR29: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR30: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR31: u1, + }), base_address + 0x1c); + + /// address: 0x2009c03c + /// Port Output Clear register using FIOMASK. + pub const CLR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR0: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR1: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR2: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR3: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR4: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR5: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR6: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR7: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR8: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR9: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR10: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR11: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR12: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR13: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR14: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR15: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR16: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR17: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR18: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR19: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR20: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR21: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR22: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR23: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR24: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR25: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR26: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR27: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR28: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR29: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR30: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR31: u1, + }), base_address + 0x3c); + + /// address: 0x2009c05c + /// Port Output Clear register using FIOMASK. + pub const CLR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR0: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR1: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR2: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR3: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR4: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR5: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR6: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR7: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR8: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR9: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR10: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR11: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR12: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR13: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR14: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR15: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR16: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR17: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR18: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR19: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR20: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR21: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR22: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR23: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR24: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR25: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR26: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR27: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR28: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR29: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR30: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR31: u1, + }), base_address + 0x5c); + + /// address: 0x2009c07c + /// Port Output Clear register using FIOMASK. + pub const CLR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR0: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR1: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR2: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR3: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR4: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR5: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR6: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR7: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR8: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR9: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR10: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR11: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR12: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR13: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR14: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR15: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR16: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR17: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR18: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR19: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR20: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR21: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR22: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR23: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR24: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR25: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR26: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR27: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR28: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR29: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR30: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR31: u1, + }), base_address + 0x7c); + + /// address: 0x2009c09c + /// Port Output Clear register using FIOMASK. + pub const CLR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR0: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR1: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR2: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR3: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR4: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR5: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR6: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR7: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR8: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR9: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR10: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR11: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR12: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR13: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR14: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR15: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR16: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR17: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR18: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR19: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR20: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR21: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR22: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR23: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR24: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR25: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR26: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR27: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR28: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR29: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR30: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR31: u1, + }), base_address + 0x9c); + }; }; const std = @import("std"); -const root = @import("root"); -const cpu = @import("cpu"); -const config = @import("microzig-config"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} + +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm }; -fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { - return InterruptVector{ - .C = struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt: " ++ str); - } - }.unhandledInterrupt, - }; -} - -pub const VectorTable = extern struct { - initial_stack_pointer: u32 = config.end_of_stack, - Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, - NMI: InterruptVector = makeUnhandledHandler("NMI"), - HardFault: InterruptVector = makeUnhandledHandler("HardFault"), - MemManage: InterruptVector = makeUnhandledHandler("MemManage"), - BusFault: InterruptVector = makeUnhandledHandler("BusFault"), - UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), - - reserved: [4]u32 = .{ 0, 0, 0, 0 }, - SVCall: InterruptVector = makeUnhandledHandler("SVCall"), - DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), - reserved1: u32 = 0, - - PendSV: InterruptVector = makeUnhandledHandler("PendSV"), - SysTick: InterruptVector = makeUnhandledHandler("SysTick"), - - WDT: InterruptVector = makeUnhandledHandler("WDT"), - TIMER0: InterruptVector = makeUnhandledHandler("TIMER0"), - TIMER1: InterruptVector = makeUnhandledHandler("TIMER1"), - TIMER2: InterruptVector = makeUnhandledHandler("TIMER2"), - TIMER3: InterruptVector = makeUnhandledHandler("TIMER3"), - UART0: InterruptVector = makeUnhandledHandler("UART0"), - UART1: InterruptVector = makeUnhandledHandler("UART1"), - UART2: InterruptVector = makeUnhandledHandler("UART2"), - UART3: InterruptVector = makeUnhandledHandler("UART3"), - PWM1: InterruptVector = makeUnhandledHandler("PWM1"), - I2C0: InterruptVector = makeUnhandledHandler("I2C0"), - I2C1: InterruptVector = makeUnhandledHandler("I2C1"), - I2C2: InterruptVector = makeUnhandledHandler("I2C2"), - SPI: InterruptVector = makeUnhandledHandler("SPI"), - SSP0: InterruptVector = makeUnhandledHandler("SSP0"), - SSP1: InterruptVector = makeUnhandledHandler("SSP1"), - PLL0: InterruptVector = makeUnhandledHandler("PLL0"), - RTC: InterruptVector = makeUnhandledHandler("RTC"), - EINT0: InterruptVector = makeUnhandledHandler("EINT0"), - EINT1: InterruptVector = makeUnhandledHandler("EINT1"), - EINT2: InterruptVector = makeUnhandledHandler("EINT2"), - EINT3: InterruptVector = makeUnhandledHandler("EINT3"), - ADC: InterruptVector = makeUnhandledHandler("ADC"), - BOD: InterruptVector = makeUnhandledHandler("BOD"), - USB: InterruptVector = makeUnhandledHandler("USB"), - CAN: InterruptVector = makeUnhandledHandler("CAN"), - DMA: InterruptVector = makeUnhandledHandler("DMA"), - I2S: InterruptVector = makeUnhandledHandler("I2S"), - ENET: InterruptVector = makeUnhandledHandler("ENET"), - RIT: InterruptVector = makeUnhandledHandler("RIT"), - MCPWM: InterruptVector = makeUnhandledHandler("MCPWM"), - QEI: InterruptVector = makeUnhandledHandler("QEI"), - PLL1: InterruptVector = makeUnhandledHandler("PLL1"), - USBActivity: InterruptVector = makeUnhandledHandler("USBActivity"), - CANActivity: InterruptVector = makeUnhandledHandler("CANActivity"), +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + }.tmp, }; diff --git a/src/modules/chips/nrf52/registers.zig b/src/modules/chips/nrf52/registers.zig index 97e4fec..ccde288 100644 --- a/src/modules/chips/nrf52/registers.zig +++ b/src/modules/chips/nrf52/registers.zig @@ -1,21145 +1,16848 @@ -// generated using svd2zig.py -// DO NOT EDIT -// based on nrf52 version 1 -const microzig_mmio = @import("microzig-mmio"); -const mmio = microzig_mmio.mmio; -const MMIO = microzig_mmio.MMIO; -const Name = "nrf52"; - -/// Factory Information Configuration Registers -pub const FICR = extern struct { - pub const Address: u32 = 0x10000000; - - /// Code memory page size - pub const CODEPAGESIZE = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Code memory size - pub const CODESIZE = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Device address type - pub const DEVICEADDRTYPE = mmio(Address + 0x000000a0, 32, packed struct { - /// Device address type - DEVICEADDRTYPE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Device identifier - pub const DEVICEID = @intToPtr(*volatile [2]u32, Address + 0x00000060); - /// Description collection[0]: Encryption Root, word 0 - pub const ER = @intToPtr(*volatile [4]u32, Address + 0x00000080); - /// Description collection[0]: Identity Root, word 0 - pub const IR = @intToPtr(*volatile [4]u32, Address + 0x00000090); - /// Description collection[0]: Device address 0 - pub const DEVICEADDR = @intToPtr(*volatile [2]u32, Address + 0x000000a4); - - pub const INFO = struct { - - /// Part code - pub const PART = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Part Variant, Hardware version and Production configuration - pub const VARIANT = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Package option - pub const PACKAGE = @intToPtr(*volatile u32, Address + 0x00000008); - - /// RAM variant - pub const RAM = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Flash variant - pub const FLASH = @intToPtr(*volatile u32, Address + 0x00000010); - /// Description collection[0]: Unspecified - pub const UNUSED0 = @intToPtr(*volatile [3]u32, Address + 0x00000014); - }; +// this file is generated by regz +// +// vendor: Nordic Semiconductor +// device: nrf52 +// cpu: CM4 + +pub const VectorTable = struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + POWER_CLOCK: InterruptVector = unhandled, + RADIO: InterruptVector = unhandled, + UARTE0_UART0: InterruptVector = unhandled, + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: InterruptVector = unhandled, + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: InterruptVector = unhandled, + NFCT: InterruptVector = unhandled, + GPIOTE: InterruptVector = unhandled, + SAADC: InterruptVector = unhandled, + TIMER0: InterruptVector = unhandled, + TIMER1: InterruptVector = unhandled, + TIMER2: InterruptVector = unhandled, + RTC0: InterruptVector = unhandled, + TEMP: InterruptVector = unhandled, + RNG: InterruptVector = unhandled, + ECB: InterruptVector = unhandled, + CCM_AAR: InterruptVector = unhandled, + WDT: InterruptVector = unhandled, + RTC1: InterruptVector = unhandled, + QDEC: InterruptVector = unhandled, + COMP_LPCOMP: InterruptVector = unhandled, + SWI0_EGU0: InterruptVector = unhandled, + SWI1_EGU1: InterruptVector = unhandled, + SWI2_EGU2: InterruptVector = unhandled, + SWI3_EGU3: InterruptVector = unhandled, + SWI4_EGU4: InterruptVector = unhandled, + SWI5_EGU5: InterruptVector = unhandled, + TIMER3: InterruptVector = unhandled, + TIMER4: InterruptVector = unhandled, + PWM0: InterruptVector = unhandled, + PDM: InterruptVector = unhandled, + reserved2: u32 = undefined, + reserved3: u32 = undefined, + MWU: InterruptVector = unhandled, + PWM1: InterruptVector = unhandled, + PWM2: InterruptVector = unhandled, + SPIM2_SPIS2_SPI2: InterruptVector = unhandled, + RTC2: InterruptVector = unhandled, + I2S: InterruptVector = unhandled, + FPU: InterruptVector = unhandled, +}; - pub const TEMP = struct { +pub const registers = struct { + /// Factory Information Configuration Registers + pub const FICR = struct { + pub const base_address = 0x10000000; - /// Slope definition A0. - pub const A0 = mmio(Address + 0x00000000, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope definition A1. - pub const A1 = mmio(Address + 0x00000004, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope definition A2. - pub const A2 = mmio(Address + 0x00000008, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope definition A3. - pub const A3 = mmio(Address + 0x0000000c, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope definition A4. - pub const A4 = mmio(Address + 0x00000010, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope definition A5. - pub const A5 = mmio(Address + 0x00000014, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B0. - pub const B0 = mmio(Address + 0x00000018, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B1. - pub const B1 = mmio(Address + 0x0000001c, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B2. - pub const B2 = mmio(Address + 0x00000020, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B3. - pub const B3 = mmio(Address + 0x00000024, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B4. - pub const B4 = mmio(Address + 0x00000028, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B5. - pub const B5 = mmio(Address + 0x0000002c, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Segment end T0. - pub const T0 = mmio(Address + 0x00000030, 32, packed struct { - /// T (segment end)register. - T: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Segment end T1. - pub const T1 = mmio(Address + 0x00000034, 32, packed struct { - /// T (segment end)register. - T: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Segment end T2. - pub const T2 = mmio(Address + 0x00000038, 32, packed struct { - /// T (segment end)register. - T: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Segment end T3. - pub const T3 = mmio(Address + 0x0000003c, 32, packed struct { - /// T (segment end)register. - T: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Segment end T4. - pub const T4 = mmio(Address + 0x00000040, 32, packed struct { - /// T (segment end)register. - T: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + /// address: 0x10000010 + /// Code memory page size + pub const CODEPAGESIZE = @intToPtr(*volatile u32, base_address + 0x10); - pub const NFC = struct { - - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER0 = mmio(Address + 0x00000000, 32, packed struct { - /// Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F - MFGID: u8 = 0, - /// Unique identifier byte 1 - UD1: u8 = 0, - /// Unique identifier byte 2 - UD2: u8 = 0, - /// Unique identifier byte 3 - UD3: u8 = 0, - }); - - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER1 = mmio(Address + 0x00000004, 32, packed struct { - /// Unique identifier byte 4 - UD4: u8 = 0, - /// Unique identifier byte 5 - UD5: u8 = 0, - /// Unique identifier byte 6 - UD6: u8 = 0, - /// Unique identifier byte 7 - UD7: u8 = 0, - }); - - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER2 = mmio(Address + 0x00000008, 32, packed struct { - /// Unique identifier byte 8 - UD8: u8 = 0, - /// Unique identifier byte 9 - UD9: u8 = 0, - /// Unique identifier byte 10 - UD10: u8 = 0, - /// Unique identifier byte 11 - UD11: u8 = 0, - }); - - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER3 = mmio(Address + 0x0000000c, 32, packed struct { - /// Unique identifier byte 12 - UD12: u8 = 0, - /// Unique identifier byte 13 - UD13: u8 = 0, - /// Unique identifier byte 14 - UD14: u8 = 0, - /// Unique identifier byte 15 - UD15: u8 = 0, - }); - }; -}; + /// address: 0x10000014 + /// Code memory size + pub const CODESIZE = @intToPtr(*volatile u32, base_address + 0x14); -/// User Information Configuration Registers -pub const UICR = extern struct { - pub const Address: u32 = 0x10001000; - - /// Unspecified - pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Unspecified - pub const UNUSED1 = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Unspecified - pub const UNUSED2 = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Unspecified - pub const UNUSED3 = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Access Port protection - pub const APPROTECT = mmio(Address + 0x00000208, 32, packed struct { - /// Enable or disable Access Port protection. Any other value than 0xFF being - /// written to this field will enable protection. - PALL: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO - pub const NFCPINS = mmio(Address + 0x0000020c, 32, packed struct { - /// Setting of pins dedicated to NFC functionality - PROTECT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Reserved for Nordic firmware design - pub const NRFFW = @intToPtr(*volatile [15]u32, Address + 0x00000014); - /// Description collection[0]: Reserved for Nordic hardware design - pub const NRFHW = @intToPtr(*volatile [12]u32, Address + 0x00000050); - /// Description collection[0]: Reserved for customer - pub const CUSTOMER = @intToPtr(*volatile [32]u32, Address + 0x00000080); - /// Description collection[0]: Mapping of the nRESET function (see POWER chapter - /// for details) - pub const PSELRESET = @intToPtr(*volatile [2]MMIO(32, packed struct { - /// GPIO number P0.n onto which Reset is exposed - PIN: u6 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }), Address + 0x00000200); -}; + /// address: 0x10000060 + /// Description collection[0]: Device identifier + pub const DEVICEID = @intToPtr(*volatile [2]u32, base_address + 0x60); -/// Block Protect -pub const BPROT = extern struct { - pub const Address: u32 = 0x40000000; - - /// Block protect configuration register 0 - pub const CONFIG0 = mmio(Address + 0x00000600, 32, packed struct { - /// Enable protection for region 0. Write '0' has no effect. - REGION0: u1 = 0, - /// Enable protection for region 1. Write '0' has no effect. - REGION1: u1 = 0, - /// Enable protection for region 2. Write '0' has no effect. - REGION2: u1 = 0, - /// Enable protection for region 3. Write '0' has no effect. - REGION3: u1 = 0, - /// Enable protection for region 4. Write '0' has no effect. - REGION4: u1 = 0, - /// Enable protection for region 5. Write '0' has no effect. - REGION5: u1 = 0, - /// Enable protection for region 6. Write '0' has no effect. - REGION6: u1 = 0, - /// Enable protection for region 7. Write '0' has no effect. - REGION7: u1 = 0, - /// Enable protection for region 8. Write '0' has no effect. - REGION8: u1 = 0, - /// Enable protection for region 9. Write '0' has no effect. - REGION9: u1 = 0, - /// Enable protection for region 10. Write '0' has no effect. - REGION10: u1 = 0, - /// Enable protection for region 11. Write '0' has no effect. - REGION11: u1 = 0, - /// Enable protection for region 12. Write '0' has no effect. - REGION12: u1 = 0, - /// Enable protection for region 13. Write '0' has no effect. - REGION13: u1 = 0, - /// Enable protection for region 14. Write '0' has no effect. - REGION14: u1 = 0, - /// Enable protection for region 15. Write '0' has no effect. - REGION15: u1 = 0, - /// Enable protection for region 16. Write '0' has no effect. - REGION16: u1 = 0, - /// Enable protection for region 17. Write '0' has no effect. - REGION17: u1 = 0, - /// Enable protection for region 18. Write '0' has no effect. - REGION18: u1 = 0, - /// Enable protection for region 19. Write '0' has no effect. - REGION19: u1 = 0, - /// Enable protection for region 20. Write '0' has no effect. - REGION20: u1 = 0, - /// Enable protection for region 21. Write '0' has no effect. - REGION21: u1 = 0, - /// Enable protection for region 22. Write '0' has no effect. - REGION22: u1 = 0, - /// Enable protection for region 23. Write '0' has no effect. - REGION23: u1 = 0, - /// Enable protection for region 24. Write '0' has no effect. - REGION24: u1 = 0, - /// Enable protection for region 25. Write '0' has no effect. - REGION25: u1 = 0, - /// Enable protection for region 26. Write '0' has no effect. - REGION26: u1 = 0, - /// Enable protection for region 27. Write '0' has no effect. - REGION27: u1 = 0, - /// Enable protection for region 28. Write '0' has no effect. - REGION28: u1 = 0, - /// Enable protection for region 29. Write '0' has no effect. - REGION29: u1 = 0, - /// Enable protection for region 30. Write '0' has no effect. - REGION30: u1 = 0, - /// Enable protection for region 31. Write '0' has no effect. - REGION31: u1 = 0, - }); - - /// Block protect configuration register 1 - pub const CONFIG1 = mmio(Address + 0x00000604, 32, packed struct { - /// Enable protection for region 32. Write '0' has no effect. - REGION32: u1 = 0, - /// Enable protection for region 33. Write '0' has no effect. - REGION33: u1 = 0, - /// Enable protection for region 34. Write '0' has no effect. - REGION34: u1 = 0, - /// Enable protection for region 35. Write '0' has no effect. - REGION35: u1 = 0, - /// Enable protection for region 36. Write '0' has no effect. - REGION36: u1 = 0, - /// Enable protection for region 37. Write '0' has no effect. - REGION37: u1 = 0, - /// Enable protection for region 38. Write '0' has no effect. - REGION38: u1 = 0, - /// Enable protection for region 39. Write '0' has no effect. - REGION39: u1 = 0, - /// Enable protection for region 40. Write '0' has no effect. - REGION40: u1 = 0, - /// Enable protection for region 41. Write '0' has no effect. - REGION41: u1 = 0, - /// Enable protection for region 42. Write '0' has no effect. - REGION42: u1 = 0, - /// Enable protection for region 43. Write '0' has no effect. - REGION43: u1 = 0, - /// Enable protection for region 44. Write '0' has no effect. - REGION44: u1 = 0, - /// Enable protection for region 45. Write '0' has no effect. - REGION45: u1 = 0, - /// Enable protection for region 46. Write '0' has no effect. - REGION46: u1 = 0, - /// Enable protection for region 47. Write '0' has no effect. - REGION47: u1 = 0, - /// Enable protection for region 48. Write '0' has no effect. - REGION48: u1 = 0, - /// Enable protection for region 49. Write '0' has no effect. - REGION49: u1 = 0, - /// Enable protection for region 50. Write '0' has no effect. - REGION50: u1 = 0, - /// Enable protection for region 51. Write '0' has no effect. - REGION51: u1 = 0, - /// Enable protection for region 52. Write '0' has no effect. - REGION52: u1 = 0, - /// Enable protection for region 53. Write '0' has no effect. - REGION53: u1 = 0, - /// Enable protection for region 54. Write '0' has no effect. - REGION54: u1 = 0, - /// Enable protection for region 55. Write '0' has no effect. - REGION55: u1 = 0, - /// Enable protection for region 56. Write '0' has no effect. - REGION56: u1 = 0, - /// Enable protection for region 57. Write '0' has no effect. - REGION57: u1 = 0, - /// Enable protection for region 58. Write '0' has no effect. - REGION58: u1 = 0, - /// Enable protection for region 59. Write '0' has no effect. - REGION59: u1 = 0, - /// Enable protection for region 60. Write '0' has no effect. - REGION60: u1 = 0, - /// Enable protection for region 61. Write '0' has no effect. - REGION61: u1 = 0, - /// Enable protection for region 62. Write '0' has no effect. - REGION62: u1 = 0, - /// Enable protection for region 63. Write '0' has no effect. - REGION63: u1 = 0, - }); - - /// Disable protection mechanism in debug interface mode - pub const DISABLEINDEBUG = mmio(Address + 0x00000608, 32, packed struct { - /// Disable the protection mechanism for NVM regions while in debug interface - /// mode. This register will only disable the protection mechanism if the device - /// is in debug interface mode. - DISABLEINDEBUG: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Unspecified - pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x0000060c); - - /// Block protect configuration register 2 - pub const CONFIG2 = mmio(Address + 0x00000610, 32, packed struct { - /// Enable protection for region 64. Write '0' has no effect. - REGION64: u1 = 0, - /// Enable protection for region 65. Write '0' has no effect. - REGION65: u1 = 0, - /// Enable protection for region 66. Write '0' has no effect. - REGION66: u1 = 0, - /// Enable protection for region 67. Write '0' has no effect. - REGION67: u1 = 0, - /// Enable protection for region 68. Write '0' has no effect. - REGION68: u1 = 0, - /// Enable protection for region 69. Write '0' has no effect. - REGION69: u1 = 0, - /// Enable protection for region 70. Write '0' has no effect. - REGION70: u1 = 0, - /// Enable protection for region 71. Write '0' has no effect. - REGION71: u1 = 0, - /// Enable protection for region 72. Write '0' has no effect. - REGION72: u1 = 0, - /// Enable protection for region 73. Write '0' has no effect. - REGION73: u1 = 0, - /// Enable protection for region 74. Write '0' has no effect. - REGION74: u1 = 0, - /// Enable protection for region 75. Write '0' has no effect. - REGION75: u1 = 0, - /// Enable protection for region 76. Write '0' has no effect. - REGION76: u1 = 0, - /// Enable protection for region 77. Write '0' has no effect. - REGION77: u1 = 0, - /// Enable protection for region 78. Write '0' has no effect. - REGION78: u1 = 0, - /// Enable protection for region 79. Write '0' has no effect. - REGION79: u1 = 0, - /// Enable protection for region 80. Write '0' has no effect. - REGION80: u1 = 0, - /// Enable protection for region 81. Write '0' has no effect. - REGION81: u1 = 0, - /// Enable protection for region 82. Write '0' has no effect. - REGION82: u1 = 0, - /// Enable protection for region 83. Write '0' has no effect. - REGION83: u1 = 0, - /// Enable protection for region 84. Write '0' has no effect. - REGION84: u1 = 0, - /// Enable protection for region 85. Write '0' has no effect. - REGION85: u1 = 0, - /// Enable protection for region 86. Write '0' has no effect. - REGION86: u1 = 0, - /// Enable protection for region 87. Write '0' has no effect. - REGION87: u1 = 0, - /// Enable protection for region 88. Write '0' has no effect. - REGION88: u1 = 0, - /// Enable protection for region 89. Write '0' has no effect. - REGION89: u1 = 0, - /// Enable protection for region 90. Write '0' has no effect. - REGION90: u1 = 0, - /// Enable protection for region 91. Write '0' has no effect. - REGION91: u1 = 0, - /// Enable protection for region 92. Write '0' has no effect. - REGION92: u1 = 0, - /// Enable protection for region 93. Write '0' has no effect. - REGION93: u1 = 0, - /// Enable protection for region 94. Write '0' has no effect. - REGION94: u1 = 0, - /// Enable protection for region 95. Write '0' has no effect. - REGION95: u1 = 0, - }); - - /// Block protect configuration register 3 - pub const CONFIG3 = mmio(Address + 0x00000614, 32, packed struct { - /// Enable protection for region 96. Write '0' has no effect. - REGION96: u1 = 0, - /// Enable protection for region 97. Write '0' has no effect. - REGION97: u1 = 0, - /// Enable protection for region 98. Write '0' has no effect. - REGION98: u1 = 0, - /// Enable protection for region 99. Write '0' has no effect. - REGION99: u1 = 0, - /// Enable protection for region 100. Write '0' has no effect. - REGION100: u1 = 0, - /// Enable protection for region 101. Write '0' has no effect. - REGION101: u1 = 0, - /// Enable protection for region 102. Write '0' has no effect. - REGION102: u1 = 0, - /// Enable protection for region 103. Write '0' has no effect. - REGION103: u1 = 0, - /// Enable protection for region 104. Write '0' has no effect. - REGION104: u1 = 0, - /// Enable protection for region 105. Write '0' has no effect. - REGION105: u1 = 0, - /// Enable protection for region 106. Write '0' has no effect. - REGION106: u1 = 0, - /// Enable protection for region 107. Write '0' has no effect. - REGION107: u1 = 0, - /// Enable protection for region 108. Write '0' has no effect. - REGION108: u1 = 0, - /// Enable protection for region 109. Write '0' has no effect. - REGION109: u1 = 0, - /// Enable protection for region 110. Write '0' has no effect. - REGION110: u1 = 0, - /// Enable protection for region 111. Write '0' has no effect. - REGION111: u1 = 0, - /// Enable protection for region 112. Write '0' has no effect. - REGION112: u1 = 0, - /// Enable protection for region 113. Write '0' has no effect. - REGION113: u1 = 0, - /// Enable protection for region 114. Write '0' has no effect. - REGION114: u1 = 0, - /// Enable protection for region 115. Write '0' has no effect. - REGION115: u1 = 0, - /// Enable protection for region 116. Write '0' has no effect. - REGION116: u1 = 0, - /// Enable protection for region 117. Write '0' has no effect. - REGION117: u1 = 0, - /// Enable protection for region 118. Write '0' has no effect. - REGION118: u1 = 0, - /// Enable protection for region 119. Write '0' has no effect. - REGION119: u1 = 0, - /// Enable protection for region 120. Write '0' has no effect. - REGION120: u1 = 0, - /// Enable protection for region 121. Write '0' has no effect. - REGION121: u1 = 0, - /// Enable protection for region 122. Write '0' has no effect. - REGION122: u1 = 0, - /// Enable protection for region 123. Write '0' has no effect. - REGION123: u1 = 0, - /// Enable protection for region 124. Write '0' has no effect. - REGION124: u1 = 0, - /// Enable protection for region 125. Write '0' has no effect. - REGION125: u1 = 0, - /// Enable protection for region 126. Write '0' has no effect. - REGION126: u1 = 0, - /// Enable protection for region 127. Write '0' has no effect. - REGION127: u1 = 0, - }); -}; + /// address: 0x10000080 + /// Description collection[0]: Encryption Root, word 0 + pub const ER = @intToPtr(*volatile [4]u32, base_address + 0x80); -/// Power control -pub const POWER = extern struct { - pub const Address: u32 = 0x40000000; - - /// Enable constant latency mode - pub const TASKS_CONSTLAT = @intToPtr(*volatile u32, Address + 0x00000078); - - /// Enable low power mode (variable latency) - pub const TASKS_LOWPWR = @intToPtr(*volatile u32, Address + 0x0000007c); - - /// Power failure warning - pub const EVENTS_POFWARN = @intToPtr(*volatile u32, Address + 0x00000108); - - /// CPU entered WFI/WFE sleep - pub const EVENTS_SLEEPENTER = @intToPtr(*volatile u32, Address + 0x00000114); - - /// CPU exited WFI/WFE sleep - pub const EVENTS_SLEEPEXIT = @intToPtr(*volatile u32, Address + 0x00000118); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for POFWARN event - POFWARN: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Enable interrupt for SLEEPENTER event - SLEEPENTER: u1 = 0, - /// Write '1' to Enable interrupt for SLEEPEXIT event - SLEEPEXIT: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for POFWARN event - POFWARN: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Disable interrupt for SLEEPENTER event - SLEEPENTER: u1 = 0, - /// Write '1' to Disable interrupt for SLEEPEXIT event - SLEEPEXIT: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reset reason - pub const RESETREAS = mmio(Address + 0x00000400, 32, packed struct { - /// Reset from pin-reset detected - RESETPIN: u1 = 0, - /// Reset from watchdog detected - DOG: u1 = 0, - /// Reset from soft reset detected - SREQ: u1 = 0, - /// Reset from CPU lock-up detected - LOCKUP: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Reset due to wake up from System OFF mode when wakeup is triggered from - /// DETECT signal from GPIO - OFF: u1 = 0, - /// Reset due to wake up from System OFF mode when wakeup is triggered from - /// ANADETECT signal from LPCOMP - LPCOMP: u1 = 0, - /// Reset due to wake up from System OFF mode when wakeup is triggered from - /// entering into debug interface mode - DIF: u1 = 0, - /// Reset due to wake up from System OFF mode by NFC field detect - NFC: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Deprecated register - RAM status register - pub const RAMSTATUS = mmio(Address + 0x00000428, 32, packed struct { - /// RAM block 0 is on or off/powering up - RAMBLOCK0: u1 = 0, - /// RAM block 1 is on or off/powering up - RAMBLOCK1: u1 = 0, - /// RAM block 2 is on or off/powering up - RAMBLOCK2: u1 = 0, - /// RAM block 3 is on or off/powering up - RAMBLOCK3: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// System OFF register - pub const SYSTEMOFF = mmio(Address + 0x00000500, 32, packed struct { - /// Enable System OFF mode - SYSTEMOFF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Power failure comparator configuration - pub const POFCON = mmio(Address + 0x00000510, 32, packed struct { - /// Enable or disable power failure comparator - POF: u1 = 0, - /// Power failure comparator threshold setting - THRESHOLD: u4 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// General purpose retention register - pub const GPREGRET = mmio(Address + 0x0000051c, 32, packed struct { - /// General purpose retention register - GPREGRET: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// General purpose retention register - pub const GPREGRET2 = mmio(Address + 0x00000520, 32, packed struct { - /// General purpose retention register - GPREGRET: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Deprecated register - RAM on/off register (this register is retained) - pub const RAMON = mmio(Address + 0x00000524, 32, packed struct { - /// Keep RAM block 0 on or off in system ON Mode - ONRAM0: u1 = 0, - /// Keep RAM block 1 on or off in system ON Mode - ONRAM1: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Keep retention on RAM block 0 when RAM block is switched off - OFFRAM0: u1 = 0, - /// Keep retention on RAM block 1 when RAM block is switched off - OFFRAM1: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Deprecated register - RAM on/off register (this register is retained) - pub const RAMONB = mmio(Address + 0x00000554, 32, packed struct { - /// Keep RAM block 2 on or off in system ON Mode - ONRAM2: u1 = 0, - /// Keep RAM block 3 on or off in system ON Mode - ONRAM3: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Keep retention on RAM block 2 when RAM block is switched off - OFFRAM2: u1 = 0, - /// Keep retention on RAM block 3 when RAM block is switched off - OFFRAM3: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DC/DC enable register - pub const DCDCEN = mmio(Address + 0x00000578, 32, packed struct { - /// Enable or disable DC/DC converter - DCDCEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + /// address: 0x10000090 + /// Description collection[0]: Identity Root, word 0 + pub const IR = @intToPtr(*volatile [4]u32, base_address + 0x90); -/// Clock control -pub const CLOCK = extern struct { - pub const Address: u32 = 0x40000000; - - /// Start HFCLK crystal oscillator - pub const TASKS_HFCLKSTART = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop HFCLK crystal oscillator - pub const TASKS_HFCLKSTOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Start LFCLK source - pub const TASKS_LFCLKSTART = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop LFCLK source - pub const TASKS_LFCLKSTOP = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Start calibration of LFRC oscillator - pub const TASKS_CAL = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Start calibration timer - pub const TASKS_CTSTART = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Stop calibration timer - pub const TASKS_CTSTOP = @intToPtr(*volatile u32, Address + 0x00000018); - - /// HFCLK oscillator started - pub const EVENTS_HFCLKSTARTED = @intToPtr(*volatile u32, Address + 0x00000100); - - /// LFCLK started - pub const EVENTS_LFCLKSTARTED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Calibration of LFCLK RC oscillator complete event - pub const EVENTS_DONE = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// Calibration timer timeout - pub const EVENTS_CTTO = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for HFCLKSTARTED event - HFCLKSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for LFCLKSTARTED event - LFCLKSTARTED: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for DONE event - DONE: u1 = 0, - /// Write '1' to Enable interrupt for CTTO event - CTTO: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for HFCLKSTARTED event - HFCLKSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for LFCLKSTARTED event - LFCLKSTARTED: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for DONE event - DONE: u1 = 0, - /// Write '1' to Disable interrupt for CTTO event - CTTO: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status indicating that HFCLKSTART task has been triggered - pub const HFCLKRUN = mmio(Address + 0x00000408, 32, packed struct { - /// HFCLKSTART task triggered or not - STATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// HFCLK status - pub const HFCLKSTAT = mmio(Address + 0x0000040c, 32, packed struct { - /// Source of HFCLK - SRC: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// HFCLK state - STATE: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status indicating that LFCLKSTART task has been triggered - pub const LFCLKRUN = mmio(Address + 0x00000414, 32, packed struct { - /// LFCLKSTART task triggered or not - STATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// LFCLK status - pub const LFCLKSTAT = mmio(Address + 0x00000418, 32, packed struct { - /// Source of LFCLK - SRC: u2 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// LFCLK state - STATE: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered - pub const LFCLKSRCCOPY = mmio(Address + 0x0000041c, 32, packed struct { - /// Clock source - SRC: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock source for the LFCLK - pub const LFCLKSRC = mmio(Address + 0x00000518, 32, packed struct { - /// Clock source - SRC: u2 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable bypass of LFCLK crystal oscillator with external clock - /// source - BYPASS: u1 = 0, - /// Enable or disable external source for LFCLK - EXTERNAL: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Calibration timer interval - pub const CTIV = mmio(Address + 0x00000538, 32, packed struct { - /// Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds - /// to 31.75 seconds. - CTIV: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clocking options for the Trace Port debug interface - pub const TRACECONFIG = mmio(Address + 0x0000055c, 32, packed struct { - /// Speed of Trace Port clock. Note that the TRACECLK pin will output this clock - /// divided by two. - TRACEPORTSPEED: u2 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Pin multiplexing of trace signals. - TRACEMUX: u2 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + /// address: 0x100000a0 + /// Device address type + pub const DEVICEADDRTYPE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xa0); + + /// address: 0x100000a4 + /// Description collection[0]: Device address 0 + pub const DEVICEADDR = @intToPtr(*volatile [2]u32, base_address + 0xa4); + + /// Device info + pub const INFO = struct { + + /// address: 0x10000000 + /// Part code + pub const PART = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x10000004 + /// Part Variant, Hardware version and Production configuration + pub const VARIANT = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x10000008 + /// Package option + pub const PACKAGE = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x1000000c + /// RAM variant + pub const RAM = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x10000010 + /// Flash variant + pub const FLASH = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x10000014 + /// Description collection[0]: Unspecified + pub const UNUSED0 = @intToPtr(*volatile [3]u32, base_address + 0x14); + }; + + /// Registers storing factory TEMP module linearization coefficients + pub const TEMP = struct { + + /// address: 0x10000000 + /// Slope definition A0. + pub const A0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x10000004 + /// Slope definition A1. + pub const A1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x10000008 + /// Slope definition A2. + pub const A2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x1000000c + /// Slope definition A3. + pub const A3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0xc); + + /// address: 0x10000010 + /// Slope definition A4. + pub const A4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x10); + + /// address: 0x10000014 + /// Slope definition A5. + pub const A5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x10000018 + /// y-intercept B0. + pub const B0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x18); + + /// address: 0x1000001c + /// y-intercept B1. + pub const B1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1c); + + /// address: 0x10000020 + /// y-intercept B2. + pub const B2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x10000024 + /// y-intercept B3. + pub const B3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x24); + + /// address: 0x10000028 + /// y-intercept B4. + pub const B4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x28); + + /// address: 0x1000002c + /// y-intercept B5. + pub const B5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x2c); + + /// address: 0x10000030 + /// Segment end T0. + pub const T0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// T (segment end)register. + T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x10000034 + /// Segment end T1. + pub const T1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// T (segment end)register. + T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x34); + + /// address: 0x10000038 + /// Segment end T2. + pub const T2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// T (segment end)register. + T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x38); + + /// address: 0x1000003c + /// Segment end T3. + pub const T3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// T (segment end)register. + T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x3c); + + /// address: 0x10000040 + /// Segment end T4. + pub const T4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// T (segment end)register. + T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x40); + }; + + pub const NFC = struct { + + /// address: 0x10000000 + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + MFGID: u8, + /// Unique identifier byte 1 + UD1: u8, + /// Unique identifier byte 2 + UD2: u8, + /// Unique identifier byte 3 + UD3: u8, + }), base_address + 0x0); + + /// address: 0x10000004 + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Unique identifier byte 4 + UD4: u8, + /// Unique identifier byte 5 + UD5: u8, + /// Unique identifier byte 6 + UD6: u8, + /// Unique identifier byte 7 + UD7: u8, + }), base_address + 0x4); + + /// address: 0x10000008 + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Unique identifier byte 8 + UD8: u8, + /// Unique identifier byte 9 + UD9: u8, + /// Unique identifier byte 10 + UD10: u8, + /// Unique identifier byte 11 + UD11: u8, + }), base_address + 0x8); + + /// address: 0x1000000c + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Unique identifier byte 12 + UD12: u8, + /// Unique identifier byte 13 + UD13: u8, + /// Unique identifier byte 14 + UD14: u8, + /// Unique identifier byte 15 + UD15: u8, + }), base_address + 0xc); + }; + }; + /// User Information Configuration Registers + pub const UICR = struct { + pub const base_address = 0x10001000; + + /// address: 0x10001000 + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x10001004 + /// Unspecified + pub const UNUSED1 = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x10001008 + /// Unspecified + pub const UNUSED2 = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x10001010 + /// Unspecified + pub const UNUSED3 = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x10001014 + /// Description collection[0]: Reserved for Nordic firmware design + pub const NRFFW = @intToPtr(*volatile [15]u32, base_address + 0x14); + + /// address: 0x10001050 + /// Description collection[0]: Reserved for Nordic hardware design + pub const NRFHW = @intToPtr(*volatile [12]u32, base_address + 0x50); + + /// address: 0x10001080 + /// Description collection[0]: Reserved for customer + pub const CUSTOMER = @intToPtr(*volatile [32]u32, base_address + 0x80); + + /// address: 0x10001200 + /// Description collection[0]: Mapping of the nRESET function (see POWER chapter for + /// details) + pub const PSELRESET = @intToPtr(*volatile [2]Mmio(32, packed struct{ + /// GPIO number P0.n onto which Reset is exposed + PIN: u6, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x200); + + /// address: 0x10001208 + /// Access Port protection + pub const APPROTECT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable Access Port protection. Any other value than 0xFF being + /// written to this field will enable protection. + PALL: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x208); + + /// address: 0x1000120c + /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + pub const NFCPINS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Setting of pins dedicated to NFC functionality + PROTECT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x20c); + }; + /// Block Protect + pub const BPROT = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000600 + /// Block protect configuration register 0 + pub const CONFIG0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable protection for region 0. Write '0' has no effect. + REGION0: u1, + /// Enable protection for region 1. Write '0' has no effect. + REGION1: u1, + /// Enable protection for region 2. Write '0' has no effect. + REGION2: u1, + /// Enable protection for region 3. Write '0' has no effect. + REGION3: u1, + /// Enable protection for region 4. Write '0' has no effect. + REGION4: u1, + /// Enable protection for region 5. Write '0' has no effect. + REGION5: u1, + /// Enable protection for region 6. Write '0' has no effect. + REGION6: u1, + /// Enable protection for region 7. Write '0' has no effect. + REGION7: u1, + /// Enable protection for region 8. Write '0' has no effect. + REGION8: u1, + /// Enable protection for region 9. Write '0' has no effect. + REGION9: u1, + /// Enable protection for region 10. Write '0' has no effect. + REGION10: u1, + /// Enable protection for region 11. Write '0' has no effect. + REGION11: u1, + /// Enable protection for region 12. Write '0' has no effect. + REGION12: u1, + /// Enable protection for region 13. Write '0' has no effect. + REGION13: u1, + /// Enable protection for region 14. Write '0' has no effect. + REGION14: u1, + /// Enable protection for region 15. Write '0' has no effect. + REGION15: u1, + /// Enable protection for region 16. Write '0' has no effect. + REGION16: u1, + /// Enable protection for region 17. Write '0' has no effect. + REGION17: u1, + /// Enable protection for region 18. Write '0' has no effect. + REGION18: u1, + /// Enable protection for region 19. Write '0' has no effect. + REGION19: u1, + /// Enable protection for region 20. Write '0' has no effect. + REGION20: u1, + /// Enable protection for region 21. Write '0' has no effect. + REGION21: u1, + /// Enable protection for region 22. Write '0' has no effect. + REGION22: u1, + /// Enable protection for region 23. Write '0' has no effect. + REGION23: u1, + /// Enable protection for region 24. Write '0' has no effect. + REGION24: u1, + /// Enable protection for region 25. Write '0' has no effect. + REGION25: u1, + /// Enable protection for region 26. Write '0' has no effect. + REGION26: u1, + /// Enable protection for region 27. Write '0' has no effect. + REGION27: u1, + /// Enable protection for region 28. Write '0' has no effect. + REGION28: u1, + /// Enable protection for region 29. Write '0' has no effect. + REGION29: u1, + /// Enable protection for region 30. Write '0' has no effect. + REGION30: u1, + /// Enable protection for region 31. Write '0' has no effect. + REGION31: u1, + }), base_address + 0x600); + + /// address: 0x40000604 + /// Block protect configuration register 1 + pub const CONFIG1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable protection for region 32. Write '0' has no effect. + REGION32: u1, + /// Enable protection for region 33. Write '0' has no effect. + REGION33: u1, + /// Enable protection for region 34. Write '0' has no effect. + REGION34: u1, + /// Enable protection for region 35. Write '0' has no effect. + REGION35: u1, + /// Enable protection for region 36. Write '0' has no effect. + REGION36: u1, + /// Enable protection for region 37. Write '0' has no effect. + REGION37: u1, + /// Enable protection for region 38. Write '0' has no effect. + REGION38: u1, + /// Enable protection for region 39. Write '0' has no effect. + REGION39: u1, + /// Enable protection for region 40. Write '0' has no effect. + REGION40: u1, + /// Enable protection for region 41. Write '0' has no effect. + REGION41: u1, + /// Enable protection for region 42. Write '0' has no effect. + REGION42: u1, + /// Enable protection for region 43. Write '0' has no effect. + REGION43: u1, + /// Enable protection for region 44. Write '0' has no effect. + REGION44: u1, + /// Enable protection for region 45. Write '0' has no effect. + REGION45: u1, + /// Enable protection for region 46. Write '0' has no effect. + REGION46: u1, + /// Enable protection for region 47. Write '0' has no effect. + REGION47: u1, + /// Enable protection for region 48. Write '0' has no effect. + REGION48: u1, + /// Enable protection for region 49. Write '0' has no effect. + REGION49: u1, + /// Enable protection for region 50. Write '0' has no effect. + REGION50: u1, + /// Enable protection for region 51. Write '0' has no effect. + REGION51: u1, + /// Enable protection for region 52. Write '0' has no effect. + REGION52: u1, + /// Enable protection for region 53. Write '0' has no effect. + REGION53: u1, + /// Enable protection for region 54. Write '0' has no effect. + REGION54: u1, + /// Enable protection for region 55. Write '0' has no effect. + REGION55: u1, + /// Enable protection for region 56. Write '0' has no effect. + REGION56: u1, + /// Enable protection for region 57. Write '0' has no effect. + REGION57: u1, + /// Enable protection for region 58. Write '0' has no effect. + REGION58: u1, + /// Enable protection for region 59. Write '0' has no effect. + REGION59: u1, + /// Enable protection for region 60. Write '0' has no effect. + REGION60: u1, + /// Enable protection for region 61. Write '0' has no effect. + REGION61: u1, + /// Enable protection for region 62. Write '0' has no effect. + REGION62: u1, + /// Enable protection for region 63. Write '0' has no effect. + REGION63: u1, + }), base_address + 0x604); + + /// address: 0x40000608 + /// Disable protection mechanism in debug interface mode + pub const DISABLEINDEBUG = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x608); + + /// address: 0x4000060c + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, base_address + 0x60c); + + /// address: 0x40000610 + /// Block protect configuration register 2 + pub const CONFIG2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable protection for region 64. Write '0' has no effect. + REGION64: u1, + /// Enable protection for region 65. Write '0' has no effect. + REGION65: u1, + /// Enable protection for region 66. Write '0' has no effect. + REGION66: u1, + /// Enable protection for region 67. Write '0' has no effect. + REGION67: u1, + /// Enable protection for region 68. Write '0' has no effect. + REGION68: u1, + /// Enable protection for region 69. Write '0' has no effect. + REGION69: u1, + /// Enable protection for region 70. Write '0' has no effect. + REGION70: u1, + /// Enable protection for region 71. Write '0' has no effect. + REGION71: u1, + /// Enable protection for region 72. Write '0' has no effect. + REGION72: u1, + /// Enable protection for region 73. Write '0' has no effect. + REGION73: u1, + /// Enable protection for region 74. Write '0' has no effect. + REGION74: u1, + /// Enable protection for region 75. Write '0' has no effect. + REGION75: u1, + /// Enable protection for region 76. Write '0' has no effect. + REGION76: u1, + /// Enable protection for region 77. Write '0' has no effect. + REGION77: u1, + /// Enable protection for region 78. Write '0' has no effect. + REGION78: u1, + /// Enable protection for region 79. Write '0' has no effect. + REGION79: u1, + /// Enable protection for region 80. Write '0' has no effect. + REGION80: u1, + /// Enable protection for region 81. Write '0' has no effect. + REGION81: u1, + /// Enable protection for region 82. Write '0' has no effect. + REGION82: u1, + /// Enable protection for region 83. Write '0' has no effect. + REGION83: u1, + /// Enable protection for region 84. Write '0' has no effect. + REGION84: u1, + /// Enable protection for region 85. Write '0' has no effect. + REGION85: u1, + /// Enable protection for region 86. Write '0' has no effect. + REGION86: u1, + /// Enable protection for region 87. Write '0' has no effect. + REGION87: u1, + /// Enable protection for region 88. Write '0' has no effect. + REGION88: u1, + /// Enable protection for region 89. Write '0' has no effect. + REGION89: u1, + /// Enable protection for region 90. Write '0' has no effect. + REGION90: u1, + /// Enable protection for region 91. Write '0' has no effect. + REGION91: u1, + /// Enable protection for region 92. Write '0' has no effect. + REGION92: u1, + /// Enable protection for region 93. Write '0' has no effect. + REGION93: u1, + /// Enable protection for region 94. Write '0' has no effect. + REGION94: u1, + /// Enable protection for region 95. Write '0' has no effect. + REGION95: u1, + }), base_address + 0x610); + + /// address: 0x40000614 + /// Block protect configuration register 3 + pub const CONFIG3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable protection for region 96. Write '0' has no effect. + REGION96: u1, + /// Enable protection for region 97. Write '0' has no effect. + REGION97: u1, + /// Enable protection for region 98. Write '0' has no effect. + REGION98: u1, + /// Enable protection for region 99. Write '0' has no effect. + REGION99: u1, + /// Enable protection for region 100. Write '0' has no effect. + REGION100: u1, + /// Enable protection for region 101. Write '0' has no effect. + REGION101: u1, + /// Enable protection for region 102. Write '0' has no effect. + REGION102: u1, + /// Enable protection for region 103. Write '0' has no effect. + REGION103: u1, + /// Enable protection for region 104. Write '0' has no effect. + REGION104: u1, + /// Enable protection for region 105. Write '0' has no effect. + REGION105: u1, + /// Enable protection for region 106. Write '0' has no effect. + REGION106: u1, + /// Enable protection for region 107. Write '0' has no effect. + REGION107: u1, + /// Enable protection for region 108. Write '0' has no effect. + REGION108: u1, + /// Enable protection for region 109. Write '0' has no effect. + REGION109: u1, + /// Enable protection for region 110. Write '0' has no effect. + REGION110: u1, + /// Enable protection for region 111. Write '0' has no effect. + REGION111: u1, + /// Enable protection for region 112. Write '0' has no effect. + REGION112: u1, + /// Enable protection for region 113. Write '0' has no effect. + REGION113: u1, + /// Enable protection for region 114. Write '0' has no effect. + REGION114: u1, + /// Enable protection for region 115. Write '0' has no effect. + REGION115: u1, + /// Enable protection for region 116. Write '0' has no effect. + REGION116: u1, + /// Enable protection for region 117. Write '0' has no effect. + REGION117: u1, + /// Enable protection for region 118. Write '0' has no effect. + REGION118: u1, + /// Enable protection for region 119. Write '0' has no effect. + REGION119: u1, + /// Enable protection for region 120. Write '0' has no effect. + REGION120: u1, + /// Enable protection for region 121. Write '0' has no effect. + REGION121: u1, + /// Enable protection for region 122. Write '0' has no effect. + REGION122: u1, + /// Enable protection for region 123. Write '0' has no effect. + REGION123: u1, + /// Enable protection for region 124. Write '0' has no effect. + REGION124: u1, + /// Enable protection for region 125. Write '0' has no effect. + REGION125: u1, + /// Enable protection for region 126. Write '0' has no effect. + REGION126: u1, + /// Enable protection for region 127. Write '0' has no effect. + REGION127: u1, + }), base_address + 0x614); + }; + /// Power control + pub const POWER = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000078 + /// Enable constant latency mode + pub const TASKS_CONSTLAT = @intToPtr(*volatile u32, base_address + 0x78); + + /// address: 0x4000007c + /// Enable low power mode (variable latency) + pub const TASKS_LOWPWR = @intToPtr(*volatile u32, base_address + 0x7c); + + /// address: 0x40000108 + /// Power failure warning + pub const EVENTS_POFWARN = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40000114 + /// CPU entered WFI/WFE sleep + pub const EVENTS_SLEEPENTER = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x40000118 + /// CPU exited WFI/WFE sleep + pub const EVENTS_SLEEPEXIT = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x40000304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for POFWARN event + POFWARN: u1, + reserved2: u1, + reserved3: u1, + /// Write '1' to Enable interrupt for SLEEPENTER event + SLEEPENTER: u1, + /// Write '1' to Enable interrupt for SLEEPEXIT event + SLEEPEXIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x304); + + /// address: 0x40000308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for POFWARN event + POFWARN: u1, + reserved2: u1, + reserved3: u1, + /// Write '1' to Disable interrupt for SLEEPENTER event + SLEEPENTER: u1, + /// Write '1' to Disable interrupt for SLEEPEXIT event + SLEEPEXIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x308); + + /// address: 0x40000400 + /// Reset reason + pub const RESETREAS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset from pin-reset detected + RESETPIN: u1, + /// Reset from watchdog detected + DOG: u1, + /// Reset from soft reset detected + SREQ: u1, + /// Reset from CPU lock-up detected + LOCKUP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Reset due to wake up from System OFF mode when wakeup is triggered from DETECT + /// signal from GPIO + OFF: u1, + /// Reset due to wake up from System OFF mode when wakeup is triggered from + /// ANADETECT signal from LPCOMP + LPCOMP: u1, + /// Reset due to wake up from System OFF mode when wakeup is triggered from entering + /// into debug interface mode + DIF: u1, + /// Reset due to wake up from System OFF mode by NFC field detect + NFC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x400); + + /// address: 0x40000428 + /// Deprecated register - RAM status register + pub const RAMSTATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// RAM block 0 is on or off/powering up + RAMBLOCK0: u1, + /// RAM block 1 is on or off/powering up + RAMBLOCK1: u1, + /// RAM block 2 is on or off/powering up + RAMBLOCK2: u1, + /// RAM block 3 is on or off/powering up + RAMBLOCK3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x428); + + /// address: 0x40000500 + /// System OFF register + pub const SYSTEMOFF = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x40000510 + /// Power failure comparator configuration + pub const POFCON = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable power failure comparator + POF: u1, + /// Power failure comparator threshold setting + THRESHOLD: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x510); + + /// address: 0x4000051c + /// General purpose retention register + pub const GPREGRET = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); -/// 2.4 GHz Radio -pub const RADIO = extern struct { - pub const Address: u32 = 0x40001000; - - /// Enable RADIO in TX mode - pub const TASKS_TXEN = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Enable RADIO in RX mode - pub const TASKS_RXEN = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Start RADIO - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop RADIO - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Disable RADIO - pub const TASKS_DISABLE = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Start the RSSI and take one single sample of the receive signal strength. - pub const TASKS_RSSISTART = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Stop the RSSI measurement - pub const TASKS_RSSISTOP = @intToPtr(*volatile u32, Address + 0x00000018); - - /// Start the bit counter - pub const TASKS_BCSTART = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Stop the bit counter - pub const TASKS_BCSTOP = @intToPtr(*volatile u32, Address + 0x00000020); - - /// RADIO has ramped up and is ready to be started - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Address sent or received - pub const EVENTS_ADDRESS = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Packet payload sent or received - pub const EVENTS_PAYLOAD = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Packet sent or received - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// RADIO has been disabled - pub const EVENTS_DISABLED = @intToPtr(*volatile u32, Address + 0x00000110); - - /// A device address match occurred on the last received packet - pub const EVENTS_DEVMATCH = @intToPtr(*volatile u32, Address + 0x00000114); - - /// No device address match occurred on the last received packet - pub const EVENTS_DEVMISS = @intToPtr(*volatile u32, Address + 0x00000118); - - /// Sampling of receive signal strength complete. - pub const EVENTS_RSSIEND = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Bit counter reached bit count value. - pub const EVENTS_BCMATCH = @intToPtr(*volatile u32, Address + 0x00000128); - - /// Packet received with CRC ok - pub const EVENTS_CRCOK = @intToPtr(*volatile u32, Address + 0x00000130); - - /// Packet received with CRC error - pub const EVENTS_CRCERROR = @intToPtr(*volatile u32, Address + 0x00000134); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between READY event and START task - READY_START: u1 = 0, - /// Shortcut between END event and DISABLE task - END_DISABLE: u1 = 0, - /// Shortcut between DISABLED event and TXEN task - DISABLED_TXEN: u1 = 0, - /// Shortcut between DISABLED event and RXEN task - DISABLED_RXEN: u1 = 0, - /// Shortcut between ADDRESS event and RSSISTART task - ADDRESS_RSSISTART: u1 = 0, - /// Shortcut between END event and START task - END_START: u1 = 0, - /// Shortcut between ADDRESS event and BCSTART task - ADDRESS_BCSTART: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between DISABLED event and RSSISTOP task - DISABLED_RSSISTOP: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Enable interrupt for ADDRESS event - ADDRESS: u1 = 0, - /// Write '1' to Enable interrupt for PAYLOAD event - PAYLOAD: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - /// Write '1' to Enable interrupt for DISABLED event - DISABLED: u1 = 0, - /// Write '1' to Enable interrupt for DEVMATCH event - DEVMATCH: u1 = 0, - /// Write '1' to Enable interrupt for DEVMISS event - DEVMISS: u1 = 0, - /// Write '1' to Enable interrupt for RSSIEND event - RSSIEND: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for BCMATCH event - BCMATCH: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Enable interrupt for CRCOK event - CRCOK: u1 = 0, - /// Write '1' to Enable interrupt for CRCERROR event - CRCERROR: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Disable interrupt for ADDRESS event - ADDRESS: u1 = 0, - /// Write '1' to Disable interrupt for PAYLOAD event - PAYLOAD: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - /// Write '1' to Disable interrupt for DISABLED event - DISABLED: u1 = 0, - /// Write '1' to Disable interrupt for DEVMATCH event - DEVMATCH: u1 = 0, - /// Write '1' to Disable interrupt for DEVMISS event - DEVMISS: u1 = 0, - /// Write '1' to Disable interrupt for RSSIEND event - RSSIEND: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for BCMATCH event - BCMATCH: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Disable interrupt for CRCOK event - CRCOK: u1 = 0, - /// Write '1' to Disable interrupt for CRCERROR event - CRCERROR: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC status - pub const CRCSTATUS = mmio(Address + 0x00000400, 32, packed struct { - /// CRC status of packet received - CRCSTATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Received address - pub const RXMATCH = mmio(Address + 0x00000408, 32, packed struct { + /// address: 0x40000520 + /// General purpose retention register + pub const GPREGRET2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// General purpose retention register + GPREGRET: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x520); + + /// address: 0x40000524 + /// Deprecated register - RAM on/off register (this register is retained) + pub const RAMON = @intToPtr(*volatile Mmio(32, packed struct{ + /// Keep RAM block 0 on or off in system ON Mode + ONRAM0: u1, + /// Keep RAM block 1 on or off in system ON Mode + ONRAM1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Keep retention on RAM block 0 when RAM block is switched off + OFFRAM0: u1, + /// Keep retention on RAM block 1 when RAM block is switched off + OFFRAM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x524); + + /// address: 0x40000554 + /// Deprecated register - RAM on/off register (this register is retained) + pub const RAMONB = @intToPtr(*volatile Mmio(32, packed struct{ + /// Keep RAM block 2 on or off in system ON Mode + ONRAM2: u1, + /// Keep RAM block 3 on or off in system ON Mode + ONRAM3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Keep retention on RAM block 2 when RAM block is switched off + OFFRAM2: u1, + /// Keep retention on RAM block 3 when RAM block is switched off + OFFRAM3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x554); + + /// address: 0x40000578 + /// DC/DC enable register + pub const DCDCEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x578); + + pub const RAM = @ptrCast(*volatile [8]packed struct { + /// Description cluster[0]: RAM0 power control register + POWER: Mmio(32, packed struct{ + /// Keep RAM section S0 ON or OFF in System ON mode. + S0POWER: u1, + /// Keep RAM section S1 ON or OFF in System ON mode. + S1POWER: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Keep retention on RAM section S0 when RAM section is in OFF + S0RETENTION: u1, + /// Keep retention on RAM section S1 when RAM section is in OFF + S1RETENTION: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), + + /// Description cluster[0]: RAM0 power control set register + POWERSET: Mmio(32, packed struct{ + /// Keep RAM section S0 of RAM0 on or off in System ON mode + S0POWER: u1, + /// Keep RAM section S1 of RAM0 on or off in System ON mode + S1POWER: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Keep retention on RAM section S0 when RAM section is switched off + S0RETENTION: u1, + /// Keep retention on RAM section S1 when RAM section is switched off + S1RETENTION: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), + + /// Description cluster[0]: RAM0 power control clear register + POWERCLR: Mmio(32, packed struct{ + /// Keep RAM section S0 of RAM0 on or off in System ON mode + S0POWER: u1, + /// Keep RAM section S1 of RAM0 on or off in System ON mode + S1POWER: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Keep retention on RAM section S0 when RAM section is switched off + S0RETENTION: u1, + /// Keep retention on RAM section S1 when RAM section is switched off + S1RETENTION: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), + padding0: u32, + }, base_address + 0x900); + }; + /// Clock control + pub const CLOCK = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// Start HFCLK crystal oscillator + pub const TASKS_HFCLKSTART = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40000004 + /// Stop HFCLK crystal oscillator + pub const TASKS_HFCLKSTOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40000008 + /// Start LFCLK source + pub const TASKS_LFCLKSTART = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000000c + /// Stop LFCLK source + pub const TASKS_LFCLKSTOP = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40000010 + /// Start calibration of LFRC oscillator + pub const TASKS_CAL = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40000014 + /// Start calibration timer + pub const TASKS_CTSTART = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x40000018 + /// Stop calibration timer + pub const TASKS_CTSTOP = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x40000100 + /// HFCLK oscillator started + pub const EVENTS_HFCLKSTARTED = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40000104 + /// LFCLK started + pub const EVENTS_LFCLKSTARTED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4000010c + /// Calibration of LFCLK RC oscillator complete event + pub const EVENTS_DONE = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40000110 + /// Calibration timer timeout + pub const EVENTS_CTTO = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40000304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for HFCLKSTARTED event + HFCLKSTARTED: u1, + /// Write '1' to Enable interrupt for LFCLKSTARTED event + LFCLKSTARTED: u1, + reserved0: u1, + /// Write '1' to Enable interrupt for DONE event + DONE: u1, + /// Write '1' to Enable interrupt for CTTO event + CTTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x304); + + /// address: 0x40000308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for HFCLKSTARTED event + HFCLKSTARTED: u1, + /// Write '1' to Disable interrupt for LFCLKSTARTED event + LFCLKSTARTED: u1, + reserved0: u1, + /// Write '1' to Disable interrupt for DONE event + DONE: u1, + /// Write '1' to Disable interrupt for CTTO event + CTTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x308); + + /// address: 0x40000408 + /// Status indicating that HFCLKSTART task has been triggered + pub const HFCLKRUN = @intToPtr(*volatile Mmio(32, packed struct{ + /// HFCLKSTART task triggered or not + STATUS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x408); + + /// address: 0x4000040c + /// HFCLK status + pub const HFCLKSTAT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Source of HFCLK + SRC: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// HFCLK state + STATE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x40c); + + /// address: 0x40000414 + /// Status indicating that LFCLKSTART task has been triggered + pub const LFCLKRUN = @intToPtr(*volatile Mmio(32, packed struct{ + /// LFCLKSTART task triggered or not + STATUS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x414); + + /// address: 0x40000418 + /// LFCLK status + pub const LFCLKSTAT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Source of LFCLK + SRC: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// LFCLK state + STATE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x418); + + /// address: 0x4000041c + /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + pub const LFCLKSRCCOPY = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock source + SRC: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x41c); + + /// address: 0x40000518 + /// Clock source for the LFCLK + pub const LFCLKSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock source + SRC: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Enable or disable bypass of LFCLK crystal oscillator with external clock source + BYPASS: u1, + /// Enable or disable external source for LFCLK + EXTERNAL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x518); + + /// address: 0x40000538 + /// Calibration timer interval + pub const CTIV = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x538); + + /// address: 0x4000055c + /// Clocking options for the Trace Port debug interface + pub const TRACECONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Speed of Trace Port clock. Note that the TRACECLK pin will output this clock + /// divided by two. + TRACEPORTSPEED: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Pin multiplexing of trace signals. + TRACEMUX: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x55c); + }; + /// 2.4 GHz Radio + pub const RADIO = struct { + pub const base_address = 0x40001000; + + /// address: 0x40001000 + /// Enable RADIO in TX mode + pub const TASKS_TXEN = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40001004 + /// Enable RADIO in RX mode + pub const TASKS_RXEN = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40001008 + /// Start RADIO + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000100c + /// Stop RADIO + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40001010 + /// Disable RADIO + pub const TASKS_DISABLE = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40001014 + /// Start the RSSI and take one single sample of the receive signal strength. + pub const TASKS_RSSISTART = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x40001018 + /// Stop the RSSI measurement + pub const TASKS_RSSISTOP = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x4000101c + /// Start the bit counter + pub const TASKS_BCSTART = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40001020 + /// Stop the bit counter + pub const TASKS_BCSTOP = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40001100 + /// RADIO has ramped up and is ready to be started + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40001104 + /// Address sent or received + pub const EVENTS_ADDRESS = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40001108 + /// Packet payload sent or received + pub const EVENTS_PAYLOAD = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000110c + /// Packet sent or received + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40001110 + /// RADIO has been disabled + pub const EVENTS_DISABLED = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40001114 + /// A device address match occurred on the last received packet + pub const EVENTS_DEVMATCH = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x40001118 + /// No device address match occurred on the last received packet + pub const EVENTS_DEVMISS = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x4000111c + /// Sampling of receive signal strength complete. + pub const EVENTS_RSSIEND = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40001128 + /// Bit counter reached bit count value. + pub const EVENTS_BCMATCH = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x40001130 + /// Packet received with CRC ok + pub const EVENTS_CRCOK = @intToPtr(*volatile u32, base_address + 0x130); + + /// address: 0x40001134 + /// Packet received with CRC error + pub const EVENTS_CRCERROR = @intToPtr(*volatile u32, base_address + 0x134); + + /// address: 0x40001200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between READY event and START task + READY_START: u1, + /// Shortcut between END event and DISABLE task + END_DISABLE: u1, + /// Shortcut between DISABLED event and TXEN task + DISABLED_TXEN: u1, + /// Shortcut between DISABLED event and RXEN task + DISABLED_RXEN: u1, + /// Shortcut between ADDRESS event and RSSISTART task + ADDRESS_RSSISTART: u1, + /// Shortcut between END event and START task + END_START: u1, + /// Shortcut between ADDRESS event and BCSTART task + ADDRESS_BCSTART: u1, + reserved0: u1, + /// Shortcut between DISABLED event and RSSISTOP task + DISABLED_RSSISTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x200); + + /// address: 0x40001304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for READY event + READY: u1, + /// Write '1' to Enable interrupt for ADDRESS event + ADDRESS: u1, + /// Write '1' to Enable interrupt for PAYLOAD event + PAYLOAD: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + /// Write '1' to Enable interrupt for DISABLED event + DISABLED: u1, + /// Write '1' to Enable interrupt for DEVMATCH event + DEVMATCH: u1, + /// Write '1' to Enable interrupt for DEVMISS event + DEVMISS: u1, + /// Write '1' to Enable interrupt for RSSIEND event + RSSIEND: u1, + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for BCMATCH event + BCMATCH: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for CRCOK event + CRCOK: u1, + /// Write '1' to Enable interrupt for CRCERROR event + CRCERROR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x304); + + /// address: 0x40001308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for READY event + READY: u1, + /// Write '1' to Disable interrupt for ADDRESS event + ADDRESS: u1, + /// Write '1' to Disable interrupt for PAYLOAD event + PAYLOAD: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + /// Write '1' to Disable interrupt for DISABLED event + DISABLED: u1, + /// Write '1' to Disable interrupt for DEVMATCH event + DEVMATCH: u1, + /// Write '1' to Disable interrupt for DEVMISS event + DEVMISS: u1, + /// Write '1' to Disable interrupt for RSSIEND event + RSSIEND: u1, + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for BCMATCH event + BCMATCH: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for CRCOK event + CRCOK: u1, + /// Write '1' to Disable interrupt for CRCERROR event + CRCERROR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x308); + + /// address: 0x40001400 + /// CRC status + pub const CRCSTATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x40001408 /// Received address - RXMATCH: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC field of previously received packet - pub const RXCRC = mmio(Address + 0x0000040c, 32, packed struct { + pub const RXMATCH = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x408); + + /// address: 0x4000140c /// CRC field of previously received packet - RXCRC: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Device address match index - pub const DAI = mmio(Address + 0x00000410, 32, packed struct { + pub const RXCRC = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40c); + + /// address: 0x40001410 /// Device address match index - DAI: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Packet pointer - pub const PACKETPTR = @intToPtr(*volatile u32, Address + 0x00000504); - - /// Frequency - pub const FREQUENCY = mmio(Address + 0x00000508, 32, packed struct { - /// Radio channel frequency - FREQUENCY: u7 = 0, - reserved1: u1 = 0, - /// Channel map selection. - MAP: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Output power - pub const TXPOWER = mmio(Address + 0x0000050c, 32, packed struct { - /// RADIO output power. - TXPOWER: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data rate and modulation - pub const MODE = mmio(Address + 0x00000510, 32, packed struct { - /// Radio data rate and modulation setting. The radio supports Frequency-shift - /// Keying (FSK) modulation. - MODE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Packet configuration register 0 - pub const PCNF0 = mmio(Address + 0x00000514, 32, packed struct { - /// Length on air of LENGTH field in number of bits. - LFLEN: u4 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Length on air of S0 field in number of bytes. - S0LEN: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Length on air of S1 field in number of bits. - S1LEN: u4 = 0, - /// Include or exclude S1 field in RAM - S1INCL: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - /// Length of preamble on air. Decision point: TASKS_START task - PLEN: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Packet configuration register 1 - pub const PCNF1 = mmio(Address + 0x00000518, 32, packed struct { - /// Maximum length of packet payload. If the packet payload is larger than - /// MAXLEN, the radio will truncate the payload to MAXLEN. - MAXLEN: u8 = 0, - /// Static length in number of bytes - STATLEN: u8 = 0, - /// Base address length in number of bytes - BALEN: u3 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// On air endianness of packet, this applies to the S0, LENGTH, S1 and the - /// PAYLOAD fields. - ENDIAN: u1 = 0, - /// Enable or disable packet whitening - WHITEEN: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Base address 0 - pub const BASE0 = @intToPtr(*volatile u32, Address + 0x0000051c); - - /// Base address 1 - pub const BASE1 = @intToPtr(*volatile u32, Address + 0x00000520); - - /// Prefixes bytes for logical addresses 0-3 - pub const PREFIX0 = mmio(Address + 0x00000524, 32, packed struct { - /// Address prefix 0. - AP0: u8 = 0, - /// Address prefix 1. - AP1: u8 = 0, - /// Address prefix 2. - AP2: u8 = 0, - /// Address prefix 3. - AP3: u8 = 0, - }); - - /// Prefixes bytes for logical addresses 4-7 - pub const PREFIX1 = mmio(Address + 0x00000528, 32, packed struct { - /// Address prefix 4. - AP4: u8 = 0, - /// Address prefix 5. - AP5: u8 = 0, - /// Address prefix 6. - AP6: u8 = 0, - /// Address prefix 7. - AP7: u8 = 0, - }); - - /// Transmit address select - pub const TXADDRESS = mmio(Address + 0x0000052c, 32, packed struct { + pub const DAI = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x410); + + /// address: 0x40001504 + /// Packet pointer + pub const PACKETPTR = @intToPtr(*volatile u32, base_address + 0x504); + + /// address: 0x40001508 + /// Frequency + pub const FREQUENCY = @intToPtr(*volatile Mmio(32, packed struct{ + /// Radio channel frequency + FREQUENCY: u7, + reserved0: u1, + /// Channel map selection. + MAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x508); + + /// address: 0x4000150c + /// Output power + pub const TXPOWER = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x50c); + + /// address: 0x40001510 + /// Data rate and modulation + pub const MODE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x40001514 + /// Packet configuration register 0 + pub const PCNF0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Length on air of LENGTH field in number of bits. + LFLEN: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Length on air of S0 field in number of bytes. + S0LEN: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Length on air of S1 field in number of bits. + S1LEN: u4, + /// Include or exclude S1 field in RAM + S1INCL: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Length of preamble on air. Decision point: TASKS_START task + PLEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x514); + + /// address: 0x40001518 + /// Packet configuration register 1 + pub const PCNF1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Maximum length of packet payload. If the packet payload is larger than MAXLEN, + /// the radio will truncate the payload to MAXLEN. + MAXLEN: u8, + /// Static length in number of bytes + STATLEN: u8, + /// Base address length in number of bytes + BALEN: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD + /// fields. + ENDIAN: u1, + /// Enable or disable packet whitening + WHITEEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x518); + + /// address: 0x4000151c + /// Base address 0 + pub const BASE0 = @intToPtr(*volatile u32, base_address + 0x51c); + + /// address: 0x40001520 + /// Base address 1 + pub const BASE1 = @intToPtr(*volatile u32, base_address + 0x520); + + /// address: 0x40001524 + /// Prefixes bytes for logical addresses 0-3 + pub const PREFIX0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address prefix 0. + AP0: u8, + /// Address prefix 1. + AP1: u8, + /// Address prefix 2. + AP2: u8, + /// Address prefix 3. + AP3: u8, + }), base_address + 0x524); + + /// address: 0x40001528 + /// Prefixes bytes for logical addresses 4-7 + pub const PREFIX1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address prefix 4. + AP4: u8, + /// Address prefix 5. + AP5: u8, + /// Address prefix 6. + AP6: u8, + /// Address prefix 7. + AP7: u8, + }), base_address + 0x528); + + /// address: 0x4000152c /// Transmit address select - TXADDRESS: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive address select - pub const RXADDRESSES = mmio(Address + 0x00000530, 32, packed struct { - /// Enable or disable reception on logical address 0. - ADDR0: u1 = 0, - /// Enable or disable reception on logical address 1. - ADDR1: u1 = 0, - /// Enable or disable reception on logical address 2. - ADDR2: u1 = 0, - /// Enable or disable reception on logical address 3. - ADDR3: u1 = 0, - /// Enable or disable reception on logical address 4. - ADDR4: u1 = 0, - /// Enable or disable reception on logical address 5. - ADDR5: u1 = 0, - /// Enable or disable reception on logical address 6. - ADDR6: u1 = 0, - /// Enable or disable reception on logical address 7. - ADDR7: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC configuration - pub const CRCCNF = mmio(Address + 0x00000534, 32, packed struct { - /// CRC length in number of bytes. - LEN: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Include or exclude packet address field out of CRC calculation. - SKIPADDR: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial - pub const CRCPOLY = mmio(Address + 0x00000538, 32, packed struct { + pub const TXADDRESS = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x52c); + + /// address: 0x40001530 + /// Receive address select + pub const RXADDRESSES = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable reception on logical address 0. + ADDR0: u1, + /// Enable or disable reception on logical address 1. + ADDR1: u1, + /// Enable or disable reception on logical address 2. + ADDR2: u1, + /// Enable or disable reception on logical address 3. + ADDR3: u1, + /// Enable or disable reception on logical address 4. + ADDR4: u1, + /// Enable or disable reception on logical address 5. + ADDR5: u1, + /// Enable or disable reception on logical address 6. + ADDR6: u1, + /// Enable or disable reception on logical address 7. + ADDR7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x530); + + /// address: 0x40001534 + /// CRC configuration + pub const CRCCNF = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC length in number of bytes. + LEN: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Include or exclude packet address field out of CRC calculation. + SKIPADDR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x534); + + /// address: 0x40001538 /// CRC polynomial - CRCPOLY: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC initial value - pub const CRCINIT = mmio(Address + 0x0000053c, 32, packed struct { + pub const CRCPOLY = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x538); + + /// address: 0x4000153c /// CRC initial value - CRCINIT: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Unspecified - pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x00000540); - - /// Inter Frame Spacing in us - pub const TIFS = mmio(Address + 0x00000544, 32, packed struct { - /// Inter Frame Spacing in us - TIFS: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RSSI sample - pub const RSSISAMPLE = mmio(Address + 0x00000548, 32, packed struct { - /// RSSI sample - RSSISAMPLE: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current radio state - pub const STATE = mmio(Address + 0x00000550, 32, packed struct { - /// Current radio state - STATE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data whitening initial value - pub const DATAWHITEIV = mmio(Address + 0x00000554, 32, packed struct { - /// Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it - /// has no effect, and it will always be read back and used by the device as - /// '1'. - DATAWHITEIV: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Bit counter compare - pub const BCC = @intToPtr(*volatile u32, Address + 0x00000560); - - /// Device address match configuration - pub const DACNF = mmio(Address + 0x00000640, 32, packed struct { - /// Enable or disable device address matching using device address 0 - ENA0: u1 = 0, - /// Enable or disable device address matching using device address 1 - ENA1: u1 = 0, - /// Enable or disable device address matching using device address 2 - ENA2: u1 = 0, - /// Enable or disable device address matching using device address 3 - ENA3: u1 = 0, - /// Enable or disable device address matching using device address 4 - ENA4: u1 = 0, - /// Enable or disable device address matching using device address 5 - ENA5: u1 = 0, - /// Enable or disable device address matching using device address 6 - ENA6: u1 = 0, - /// Enable or disable device address matching using device address 7 - ENA7: u1 = 0, - /// TxAdd for device address 0 - TXADD0: u1 = 0, - /// TxAdd for device address 1 - TXADD1: u1 = 0, - /// TxAdd for device address 2 - TXADD2: u1 = 0, - /// TxAdd for device address 3 - TXADD3: u1 = 0, - /// TxAdd for device address 4 - TXADD4: u1 = 0, - /// TxAdd for device address 5 - TXADD5: u1 = 0, - /// TxAdd for device address 6 - TXADD6: u1 = 0, - /// TxAdd for device address 7 - TXADD7: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Radio mode configuration register 0 - pub const MODECNF0 = mmio(Address + 0x00000650, 32, packed struct { - /// Radio ramp-up time - RU: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Default TX value - DTX: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Peripheral power control - pub const POWER = mmio(Address + 0x00000ffc, 32, packed struct { - /// Peripheral power control. The peripheral and its registers will be reset to - /// its initial state by switching the peripheral off and then back on again. - POWER: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Device address base segment 0 - pub const DAB = @intToPtr(*volatile [8]u32, Address + 0x00000600); - /// Description collection[0]: Device address prefix 0 - pub const DAP = @intToPtr(*volatile [8]MMIO(32, packed struct { - /// Device address prefix 0 - DAP: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000620); -}; + pub const CRCINIT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x53c); -/// UART with EasyDMA -pub const UARTE0 = extern struct { - pub const Address: u32 = 0x40002000; - - /// Start UART receiver - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop UART receiver - pub const TASKS_STOPRX = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Start UART transmitter - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop UART transmitter - pub const TASKS_STOPTX = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Flush RX FIFO into RX buffer - pub const TASKS_FLUSHRX = @intToPtr(*volatile u32, Address + 0x0000002c); - - /// CTS is activated (set low). Clear To Send. - pub const EVENTS_CTS = @intToPtr(*volatile u32, Address + 0x00000100); - - /// CTS is deactivated (set high). Not Clear To Send. - pub const EVENTS_NCTS = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Data received in RXD (but potentially not yet transferred to Data RAM) - pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Receive buffer is filled up - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Data sent from TXD - pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Last TX byte transmitted - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); - - /// Error detected - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Receiver timeout - pub const EVENTS_RXTO = @intToPtr(*volatile u32, Address + 0x00000144); - - /// UART receiver has started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// UART transmitter has started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Transmitter stopped - pub const EVENTS_TXSTOPPED = @intToPtr(*volatile u32, Address + 0x00000158); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between ENDRX event and STARTRX task - ENDRX_STARTRX: u1 = 0, - /// Shortcut between ENDRX event and STOPRX task - ENDRX_STOPRX: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for CTS event - CTS: u1 = 0, - /// Enable or disable interrupt for NCTS event - NCTS: u1 = 0, - /// Enable or disable interrupt for RXDRDY event - RXDRDY: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for TXDRDY event - TXDRDY: u1 = 0, - /// Enable or disable interrupt for ENDTX event - ENDTX: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Enable or disable interrupt for RXTO event - RXTO: u1 = 0, - reserved11: u1 = 0, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved12: u1 = 0, - /// Enable or disable interrupt for TXSTOPPED event - TXSTOPPED: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for CTS event - CTS: u1 = 0, - /// Write '1' to Enable interrupt for NCTS event - NCTS: u1 = 0, - /// Write '1' to Enable interrupt for RXDRDY event - RXDRDY: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for TXDRDY event - TXDRDY: u1 = 0, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for RXTO event - RXTO: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved12: u1 = 0, - /// Write '1' to Enable interrupt for TXSTOPPED event - TXSTOPPED: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for CTS event - CTS: u1 = 0, - /// Write '1' to Disable interrupt for NCTS event - NCTS: u1 = 0, - /// Write '1' to Disable interrupt for RXDRDY event - RXDRDY: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for TXDRDY event - TXDRDY: u1 = 0, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for RXTO event - RXTO: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved12: u1 = 0, - /// Write '1' to Disable interrupt for TXSTOPPED event - TXSTOPPED: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x00000480, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// Parity error - PARITY: u1 = 0, - /// Framing error occurred - FRAMING: u1 = 0, - /// Break condition - BREAK: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable UART - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable UARTE - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate. Accuracy depends on the HFCLK source selected. - pub const BAUDRATE = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration of parity and hardware flow control - pub const CONFIG = mmio(Address + 0x0000056c, 32, packed struct { - /// Hardware flow control - HWFC: u1 = 0, - /// Parity - PARITY: u3 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for RTS signal - pub const RTS = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for TXD signal - pub const TXD = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for CTS signal - pub const CTS = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for RXD signal - pub const RXD = mmio(Address + 0x0000000c, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - }; + /// address: 0x40001540 + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, base_address + 0x540); - pub const RXD = struct { + /// address: 0x40001544 + /// Inter Frame Spacing in us + pub const TIFS = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x544); - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x40001548 + /// RSSI sample + pub const RSSISAMPLE = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x548); - /// Maximum number of bytes in receive buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x40001550 + /// Current radio state + pub const STATE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x550); + + /// address: 0x40001554 + /// Data whitening initial value + pub const DATAWHITEIV = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x554); + + /// address: 0x40001560 + /// Bit counter compare + pub const BCC = @intToPtr(*volatile u32, base_address + 0x560); + + /// address: 0x40001600 + /// Description collection[0]: Device address base segment 0 + pub const DAB = @intToPtr(*volatile [8]u32, base_address + 0x600); + + /// address: 0x40001620 + /// Description collection[0]: Device address prefix 0 + pub const DAP = @intToPtr(*volatile [8]MmioInt(32, u16), base_address + 0x620); + + /// address: 0x40001640 + /// Device address match configuration + pub const DACNF = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable device address matching using device address 0 + ENA0: u1, + /// Enable or disable device address matching using device address 1 + ENA1: u1, + /// Enable or disable device address matching using device address 2 + ENA2: u1, + /// Enable or disable device address matching using device address 3 + ENA3: u1, + /// Enable or disable device address matching using device address 4 + ENA4: u1, + /// Enable or disable device address matching using device address 5 + ENA5: u1, + /// Enable or disable device address matching using device address 6 + ENA6: u1, + /// Enable or disable device address matching using device address 7 + ENA7: u1, + /// TxAdd for device address 0 + TXADD0: u1, + /// TxAdd for device address 1 + TXADD1: u1, + /// TxAdd for device address 2 + TXADD2: u1, + /// TxAdd for device address 3 + TXADD3: u1, + /// TxAdd for device address 4 + TXADD4: u1, + /// TxAdd for device address 5 + TXADD5: u1, + /// TxAdd for device address 6 + TXADD6: u1, + /// TxAdd for device address 7 + TXADD7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x640); + + /// address: 0x40001650 + /// Radio mode configuration register 0 + pub const MODECNF0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Radio ramp-up time + RU: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Default TX value + DTX: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x650); + + /// address: 0x40001ffc + /// Peripheral power control + pub const POWER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xffc); + }; + /// UART with EasyDMA + pub const UARTE0 = struct { + pub const base_address = 0x40002000; + + /// address: 0x40002000 + /// Start UART receiver + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40002004 + /// Stop UART receiver + pub const TASKS_STOPRX = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40002008 + /// Start UART transmitter + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000200c + /// Stop UART transmitter + pub const TASKS_STOPTX = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4000202c + /// Flush RX FIFO into RX buffer + pub const TASKS_FLUSHRX = @intToPtr(*volatile u32, base_address + 0x2c); + + /// address: 0x40002100 + /// CTS is activated (set low). Clear To Send. + pub const EVENTS_CTS = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40002104 + /// CTS is deactivated (set high). Not Clear To Send. + pub const EVENTS_NCTS = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40002108 + /// Data received in RXD (but potentially not yet transferred to Data RAM) + pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40002110 + /// Receive buffer is filled up + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x4000211c + /// Data sent from TXD + pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40002120 + /// Last TX byte transmitted + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x40002124 + /// Error detected + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40002144 + /// Receiver timeout + pub const EVENTS_RXTO = @intToPtr(*volatile u32, base_address + 0x144); + + /// address: 0x4000214c + /// UART receiver has started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40002150 + /// UART transmitter has started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x40002158 + /// Transmitter stopped + pub const EVENTS_TXSTOPPED = @intToPtr(*volatile u32, base_address + 0x158); + + /// address: 0x40002200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Shortcut between ENDRX event and STARTRX task + ENDRX_STARTRX: u1, + /// Shortcut between ENDRX event and STOPRX task + ENDRX_STOPRX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x200); + + /// address: 0x40002300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for CTS event + CTS: u1, + /// Enable or disable interrupt for NCTS event + NCTS: u1, + /// Enable or disable interrupt for RXDRDY event + RXDRDY: u1, + reserved0: u1, + /// Enable or disable interrupt for ENDRX event + ENDRX: u1, + reserved1: u1, + reserved2: u1, + /// Enable or disable interrupt for TXDRDY event + TXDRDY: u1, + /// Enable or disable interrupt for ENDTX event + ENDTX: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Enable or disable interrupt for RXTO event + RXTO: u1, + reserved10: u1, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved11: u1, + /// Enable or disable interrupt for TXSTOPPED event + TXSTOPPED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x300); + + /// address: 0x40002304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for CTS event + CTS: u1, + /// Write '1' to Enable interrupt for NCTS event + NCTS: u1, + /// Write '1' to Enable interrupt for RXDRDY event + RXDRDY: u1, + reserved0: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for TXDRDY event + TXDRDY: u1, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Enable interrupt for RXTO event + RXTO: u1, + reserved10: u1, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved11: u1, + /// Write '1' to Enable interrupt for TXSTOPPED event + TXSTOPPED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x304); + + /// address: 0x40002308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for CTS event + CTS: u1, + /// Write '1' to Disable interrupt for NCTS event + NCTS: u1, + /// Write '1' to Disable interrupt for RXDRDY event + RXDRDY: u1, + reserved0: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for TXDRDY event + TXDRDY: u1, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Disable interrupt for RXTO event + RXTO: u1, + reserved10: u1, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved11: u1, + /// Write '1' to Disable interrupt for TXSTOPPED event + TXSTOPPED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x308); + + /// address: 0x40002480 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// Parity error + PARITY: u1, + /// Framing error occurred + FRAMING: u1, + /// Break condition + BREAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x480); + + /// address: 0x40002500 + /// Enable UART + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40002524 + /// Baud rate. Accuracy depends on the HFCLK source selected. + pub const BAUDRATE = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x4000256c + /// Configuration of parity and hardware flow control + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Hardware flow control + HWFC: u1, + /// Parity + PARITY: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x56c); + + pub const PSEL = struct { + + /// address: 0x40002000 + /// Pin select for RTS signal + pub const RTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40002004 + /// Pin select for TXD signal + pub const TXD = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + + /// address: 0x40002008 + /// Pin select for CTS signal + pub const CTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x8); + + /// address: 0x4000200c + /// Pin select for RXD signal + pub const RXD = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0xc); + }; + + /// RXD EasyDMA channel + pub const RXD = struct { + + /// address: 0x40002000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40002004 /// Maximum number of bytes in receive buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40002008 /// Number of bytes transferred in the last transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; - pub const TXD = struct { + /// TXD EasyDMA channel + pub const TXD = struct { - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x40002000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x40002004 /// Maximum number of bytes in transmit buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40002008 /// Number of bytes transferred in the last transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; }; -}; - -/// Universal Asynchronous Receiver/Transmitter -pub const UART0 = extern struct { - pub const Address: u32 = 0x40002000; - - /// Start UART receiver - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop UART receiver - pub const TASKS_STOPRX = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Start UART transmitter - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop UART transmitter - pub const TASKS_STOPTX = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Suspend UART - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// CTS is activated (set low). Clear To Send. - pub const EVENTS_CTS = @intToPtr(*volatile u32, Address + 0x00000100); - - /// CTS is deactivated (set high). Not Clear To Send. - pub const EVENTS_NCTS = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Data received in RXD - pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Data sent from TXD - pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Error detected - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Receiver timeout - pub const EVENTS_RXTO = @intToPtr(*volatile u32, Address + 0x00000144); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between CTS event and STARTRX task - CTS_STARTRX: u1 = 0, - /// Shortcut between NCTS event and STOPRX task - NCTS_STOPRX: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for CTS event - CTS: u1 = 0, - /// Write '1' to Enable interrupt for NCTS event - NCTS: u1 = 0, - /// Write '1' to Enable interrupt for RXDRDY event - RXDRDY: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for TXDRDY event - TXDRDY: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for RXTO event - RXTO: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for CTS event - CTS: u1 = 0, - /// Write '1' to Disable interrupt for NCTS event - NCTS: u1 = 0, - /// Write '1' to Disable interrupt for RXDRDY event - RXDRDY: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for TXDRDY event - TXDRDY: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for RXTO event - RXTO: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x00000480, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// Parity error - PARITY: u1 = 0, - /// Framing error occurred - FRAMING: u1 = 0, - /// Break condition - BREAK: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable UART - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable UART - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pin select for RTS - pub const PSELRTS = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Pin select for TXD - pub const PSELTXD = @intToPtr(*volatile u32, Address + 0x0000050c); - - /// Pin select for CTS - pub const PSELCTS = @intToPtr(*volatile u32, Address + 0x00000510); - - /// Pin select for RXD - pub const PSELRXD = @intToPtr(*volatile u32, Address + 0x00000514); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { - /// RX data received in previous transfers, double buffered - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { - /// TX data to be transferred - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate - pub const BAUDRATE = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration of parity and hardware flow control - pub const CONFIG = mmio(Address + 0x0000056c, 32, packed struct { - /// Hardware flow control - HWFC: u1 = 0, - /// Parity - PARITY: u3 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + /// Universal Asynchronous Receiver/Transmitter + pub const UART0 = struct { + pub const base_address = 0x40002000; + + /// address: 0x40002000 + /// Start UART receiver + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40002004 + /// Stop UART receiver + pub const TASKS_STOPRX = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40002008 + /// Start UART transmitter + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000200c + /// Stop UART transmitter + pub const TASKS_STOPTX = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4000201c + /// Suspend UART + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40002100 + /// CTS is activated (set low). Clear To Send. + pub const EVENTS_CTS = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40002104 + /// CTS is deactivated (set high). Not Clear To Send. + pub const EVENTS_NCTS = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40002108 + /// Data received in RXD + pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000211c + /// Data sent from TXD + pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40002124 + /// Error detected + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40002144 + /// Receiver timeout + pub const EVENTS_RXTO = @intToPtr(*volatile u32, base_address + 0x144); + + /// address: 0x40002200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Shortcut between CTS event and STARTRX task + CTS_STARTRX: u1, + /// Shortcut between NCTS event and STOPRX task + NCTS_STOPRX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x40002304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for CTS event + CTS: u1, + /// Write '1' to Enable interrupt for NCTS event + NCTS: u1, + /// Write '1' to Enable interrupt for RXDRDY event + RXDRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Write '1' to Enable interrupt for TXDRDY event + TXDRDY: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Write '1' to Enable interrupt for RXTO event + RXTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x304); + + /// address: 0x40002308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for CTS event + CTS: u1, + /// Write '1' to Disable interrupt for NCTS event + NCTS: u1, + /// Write '1' to Disable interrupt for RXDRDY event + RXDRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Write '1' to Disable interrupt for TXDRDY event + TXDRDY: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Write '1' to Disable interrupt for RXTO event + RXTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x308); + + /// address: 0x40002480 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// Parity error + PARITY: u1, + /// Framing error occurred + FRAMING: u1, + /// Break condition + BREAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x480); + + /// address: 0x40002500 + /// Enable UART + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40002508 + /// Pin select for RTS + pub const PSELRTS = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000250c + /// Pin select for TXD + pub const PSELTXD = @intToPtr(*volatile u32, base_address + 0x50c); + + /// address: 0x40002510 + /// Pin select for CTS + pub const PSELCTS = @intToPtr(*volatile u32, base_address + 0x510); + + /// address: 0x40002514 + /// Pin select for RXD + pub const PSELRXD = @intToPtr(*volatile u32, base_address + 0x514); + + /// address: 0x40002518 + /// RXD register + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); -/// Serial Peripheral Interface Master with EasyDMA 0 -pub const SPIM0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// Start SPI transaction - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Stop SPI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend SPI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume SPI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// SPI transaction has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// End of RXD buffer and TXD buffer reached - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); - - /// End of TXD buffer reached - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); - - /// Transaction started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and START task - END_START: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPIM - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPIM - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency. Accuracy depends on the HFCLK source selected. - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character. Character clocked out in case and over-read of the TXD - /// buffer. - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// address: 0x4000251c + /// TXD register + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + /// address: 0x40002524 + /// Baud rate + pub const BAUDRATE = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x4000256c + /// Configuration of parity and hardware flow control + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Hardware flow control + HWFC: u1, + /// Parity + PARITY: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x56c); + }; + /// Serial Peripheral Interface Master with EasyDMA 0 + pub const SPIM0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003010 + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40003014 + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000301c + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40003020 + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40003104 + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40003110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40003118 + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x40003120 + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x4000314c + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40003200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Shortcut between END event and START task + END_START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x200); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x40003500 + /// Enable SPIM + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003524 + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40003554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x400035c0 /// Over-read character. Character clocked out in case and over-read of the TXD /// buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for SCK - pub const SCK = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for MOSI signal - pub const MOSI = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for MISO signal - pub const MISO = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - }; - - pub const RXD = struct { - - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Maximum number of bytes in receive buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + + pub const PSEL = struct { + + /// address: 0x40003000 + /// Pin select for SCK + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Pin select for MOSI signal + pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// Pin select for MISO signal + pub const MISO = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x8); + }; + + /// RXD EasyDMA channel + pub const RXD = struct { + + /// address: 0x40003000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003004 /// Maximum number of bytes in receive buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 /// Number of bytes transferred in the last transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// EasyDMA list type - pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { - /// List type - LIST: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - pub const TXD = struct { + /// address: 0x4000300c + /// EasyDMA list type + pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); + }; - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// TXD EasyDMA channel + pub const TXD = struct { - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x40003000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003004 /// Maximum number of bytes in transmit buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 /// Number of bytes transferred in the last transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// EasyDMA list type - pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { - /// List type - LIST: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; -}; + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); -/// SPI Slave 0 -pub const SPIS0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// Acquire SPI semaphore - pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); - - /// Release SPI semaphore, enabling the SPI slave to acquire it - pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); - - /// Granted transaction completed - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Semaphore acquired - pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and ACQUIRE task - END_ACQUIRE: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Semaphore status register - pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { - /// Semaphore status - SEMSTAT: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status from last transaction - pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { - /// TX buffer over-read detected, and prevented - OVERREAD: u1 = 0, - /// RX buffer overflow detected, and prevented - OVERFLOW: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI slave - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI slave - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Default character. Character clocked out in case of an ignored transaction. - pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { - /// Default character. Character clocked out in case of an ignored transaction. - DEF: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character clocked out after an over-read of the - /// transmit buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for SCK - pub const SCK = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for MISO signal - pub const MISO = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for MOSI signal - pub const MOSI = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for CSN signal - pub const CSN = mmio(Address + 0x0000000c, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); + /// address: 0x4000300c + /// EasyDMA list type + pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); + }; }; - - pub const RXD = struct { - - /// RXD data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Maximum number of bytes in receive buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// SPI Slave 0 + pub const SPIS0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003024 + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x40003028 + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003104 + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40003110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40003128 + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x40003200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x200); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x308); + + /// address: 0x40003400 + /// Semaphore status register + pub const SEMSTAT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x400); + + /// address: 0x40003440 + /// Status from last transaction + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// TX buffer over-read detected, and prevented + OVERREAD: u1, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x440); + + /// address: 0x40003500 + /// Enable SPI slave + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x4000355c + /// Default character. Character clocked out in case of an ignored transaction. + pub const DEF = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x55c); + + /// address: 0x400035c0 + /// Over-read character + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + + pub const PSEL = struct { + + /// address: 0x40003000 + /// Pin select for SCK + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Pin select for MISO signal + pub const MISO = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// Pin select for MOSI signal + pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// Pin select for CSN signal + pub const CSN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0xc); + }; + + pub const RXD = struct { + + /// address: 0x40003000 + /// RXD data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003004 /// Maximum number of bytes in receive buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes received in last granted transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { - /// Number of bytes received in the last granted transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 + /// Number of bytes received in last granted transaction + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; - pub const TXD = struct { + pub const TXD = struct { - /// TXD data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x40003000 + /// TXD data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x40003004 /// Maximum number of bytes in transmit buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transmitted in last granted transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 /// Number of bytes transmitted in last granted transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; }; -}; - -/// I2C compatible Two-Wire Master Interface with EasyDMA 0 -pub const TWIM0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop TWI transaction. Must be issued while the TWI master is not suspended. - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Last byte has been sent out after the SUSPEND task has been issued, TWI - /// traffic is now suspended. - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); - - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Byte boundary, starting to receive the last byte - pub const EVENTS_LASTRX = @intToPtr(*volatile u32, Address + 0x0000015c); - - /// Byte boundary, starting to transmit the last byte - pub const EVENTS_LASTTX = @intToPtr(*volatile u32, Address + 0x00000160); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between LASTTX event and STARTRX task - LASTTX_STARTRX: u1 = 0, - /// Shortcut between LASTTX event and SUSPEND task - LASTTX_SUSPEND: u1 = 0, - /// Shortcut between LASTTX event and STOP task - LASTTX_STOP: u1 = 0, - /// Shortcut between LASTRX event and STARTTX task - LASTRX_STARTTX: u1 = 0, - reserved8: u1 = 0, - /// Shortcut between LASTRX event and STOP task - LASTRX_STOP: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Enable or disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Enable or disable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Enable or disable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Write '1' to Enable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Write '1' to Enable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Write '1' to Disable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Write '1' to Disable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1 = 0, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWIM - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWIM - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Address used in the TWI transfer - pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// I2C compatible Two-Wire Master Interface with EasyDMA 0 + pub const TWIM0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003008 + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40003014 + /// Stop TWI transaction. Must be issued while the TWI master is not suspended. + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000301c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40003020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40003104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40003124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40003148 + /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic + /// is now suspended. + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x4000314c + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40003150 + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x4000315c + /// Byte boundary, starting to receive the last byte + pub const EVENTS_LASTRX = @intToPtr(*volatile u32, base_address + 0x15c); + + /// address: 0x40003160 + /// Byte boundary, starting to transmit the last byte + pub const EVENTS_LASTTX = @intToPtr(*volatile u32, base_address + 0x160); + + /// address: 0x40003200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Shortcut between LASTTX event and STARTRX task + LASTTX_STARTRX: u1, + /// Shortcut between LASTTX event and SUSPEND task + LASTTX_SUSPEND: u1, + /// Shortcut between LASTTX event and STOP task + LASTTX_STOP: u1, + /// Shortcut between LASTRX event and STARTTX task + LASTRX_STARTTX: u1, + reserved7: u1, + /// Shortcut between LASTRX event and STOP task + LASTRX_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x200); + + /// address: 0x40003300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable or disable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Enable or disable interrupt for LASTRX event + LASTRX: u1, + /// Enable or disable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x300); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Write '1' to Enable interrupt for LASTRX event + LASTRX: u1, + /// Write '1' to Enable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Write '1' to Disable interrupt for LASTRX event + LASTRX: u1, + /// Write '1' to Disable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x308); + + /// address: 0x400034c4 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4c4); + + /// address: 0x40003500 + /// Enable TWIM + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003524 + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40003588 /// Address used in the TWI transfer - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for SCL signal - pub const SCL = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for SDA signal - pub const SDA = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - }; - - pub const RXD = struct { - - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Maximum number of bytes in receive buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); + + pub const PSEL = struct { + + /// address: 0x40003000 + /// Pin select for SCL signal + pub const SCL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Pin select for SDA signal + pub const SDA = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + }; + + /// RXD EasyDMA channel + pub const RXD = struct { + + /// address: 0x40003000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003004 /// Maximum number of bytes in receive buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { - /// Number of bytes transferred in the last transaction. In case of NACK error, - /// includes the NACK'ed byte. - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// EasyDMA list type - pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { - /// List type - LIST: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - pub const TXD = struct { + /// address: 0x40003008 + /// Number of bytes transferred in the last transaction + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x4000300c + /// EasyDMA list type + pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); + }; - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { - /// Maximum number of bytes in transmit buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { - /// Number of bytes transferred in the last transaction. In case of NACK error, - /// includes the NACK'ed byte. - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// EasyDMA list type - pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { - /// List type - LIST: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; -}; + /// TXD EasyDMA channel + pub const TXD = struct { -/// I2C compatible Two-Wire Slave Interface with EasyDMA 0 -pub const TWIS0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// Prepare the TWI slave to respond to a write command - pub const TASKS_PREPARERX = @intToPtr(*volatile u32, Address + 0x00000030); - - /// Prepare the TWI slave to respond to a read command - pub const TASKS_PREPARETX = @intToPtr(*volatile u32, Address + 0x00000034); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Write command received - pub const EVENTS_WRITE = @intToPtr(*volatile u32, Address + 0x00000164); - - /// Read command received - pub const EVENTS_READ = @intToPtr(*volatile u32, Address + 0x00000168); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between WRITE event and SUSPEND task - WRITE_SUSPEND: u1 = 0, - /// Shortcut between READ event and SUSPEND task - READ_SUSPEND: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Enable or disable interrupt for WRITE event - WRITE: u1 = 0, - /// Enable or disable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Write '1' to Enable interrupt for WRITE event - WRITE: u1 = 0, - /// Write '1' to Enable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Write '1' to Disable interrupt for WRITE event - WRITE: u1 = 0, - /// Write '1' to Disable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004d0, 32, packed struct { - /// RX buffer overflow detected, and prevented - OVERFLOW: u1 = 0, - reserved1: u1 = 0, - /// NACK sent after receiving a data byte - DNACK: u1 = 0, - /// TX buffer over-read detected, and prevented - OVERREAD: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register indicating which address had a match - pub const MATCH = mmio(Address + 0x000004d4, 32, packed struct { - /// Which of the addresses in {ADDRESS} matched the incoming address - MATCH: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWIS - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWIS - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register for the address match mechanism - pub const CONFIG = mmio(Address + 0x00000594, 32, packed struct { - /// Enable or disable address matching on ADDRESS[0] - ADDRESS0: u1 = 0, - /// Enable or disable address matching on ADDRESS[1] - ADDRESS1: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character. Character sent out in case of an over-read of the - /// transmit buffer. - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character sent out in case of an over-read of the - /// transmit buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: TWI slave address 0 - pub const ADDRESS = @intToPtr(*volatile [2]MMIO(32, packed struct { - /// TWI slave address - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000588); - - pub const PSEL = struct { - - /// Pin select for SCL signal - pub const SCL = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for SDA signal - pub const SDA = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - }; + /// address: 0x40003000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - pub const RXD = struct { + /// address: 0x40003004 + /// Maximum number of bytes in transmit buffer + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - /// RXD Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x40003008 + /// Number of bytes transferred in the last transaction + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - /// Maximum number of bytes in RXD buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x4000300c + /// EasyDMA list type + pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); + }; + }; + /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 + pub const TWIS0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003014 + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000301c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40003020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40003030 + /// Prepare the TWI slave to respond to a write command + pub const TASKS_PREPARERX = @intToPtr(*volatile u32, base_address + 0x30); + + /// address: 0x40003034 + /// Prepare the TWI slave to respond to a read command + pub const TASKS_PREPARETX = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0x40003104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40003124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x4000314c + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40003150 + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x40003164 + /// Write command received + pub const EVENTS_WRITE = @intToPtr(*volatile u32, base_address + 0x164); + + /// address: 0x40003168 + /// Read command received + pub const EVENTS_READ = @intToPtr(*volatile u32, base_address + 0x168); + + /// address: 0x40003200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Shortcut between WRITE event and SUSPEND task + WRITE_SUSPEND: u1, + /// Shortcut between READ event and SUSPEND task + READ_SUSPEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x200); + + /// address: 0x40003300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Enable or disable interrupt for WRITE event + WRITE: u1, + /// Enable or disable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x300); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Write '1' to Enable interrupt for WRITE event + WRITE: u1, + /// Write '1' to Enable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Write '1' to Disable interrupt for WRITE event + WRITE: u1, + /// Write '1' to Disable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x308); + + /// address: 0x400034d0 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// RX buffer overflow detected, and prevented + OVERFLOW: u1, + reserved0: u1, + /// NACK sent after receiving a data byte + DNACK: u1, + /// TX buffer over-read detected, and prevented + OVERREAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x4d0); + + /// address: 0x400034d4 + /// Status register indicating which address had a match + pub const MATCH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4d4); + + /// address: 0x40003500 + /// Enable TWIS + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003588 + /// Description collection[0]: TWI slave address 0 + pub const ADDRESS = @intToPtr(*volatile [2]MmioInt(32, u7), base_address + 0x588); + + /// address: 0x40003594 + /// Configuration register for the address match mechanism + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable address matching on ADDRESS[0] + ADDRESS0: u1, + /// Enable or disable address matching on ADDRESS[1] + ADDRESS1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x594); + + /// address: 0x400035c0 + /// Over-read character. Character sent out in case of an over-read of the transmit + /// buffer. + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + + pub const PSEL = struct { + + /// address: 0x40003000 + /// Pin select for SCL signal + pub const SCL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Pin select for SDA signal + pub const SDA = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + }; + + /// RXD EasyDMA channel + pub const RXD = struct { + + /// address: 0x40003000 + /// RXD Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003004 /// Maximum number of bytes in RXD buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last RXD transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 /// Number of bytes transferred in the last RXD transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; - pub const TXD = struct { + /// TXD EasyDMA channel + pub const TXD = struct { - /// TXD Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x40003000 + /// TXD Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - /// Maximum number of bytes in TXD buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x40003004 /// Maximum number of bytes in TXD buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last TXD transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 /// Number of bytes transferred in the last TXD transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; }; -}; + /// Serial Peripheral Interface 0 + pub const SPI0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003108 + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x40003500 + /// Enable SPI + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003518 + /// RXD register + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); -/// Serial Peripheral Interface 0 -pub const SPI0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// TXD byte sent and RXD byte received - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { - /// RX data received. Double buffered - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { - /// TX data to send. Double buffered - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for SCK - pub const SCK = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number configuration for SPI SCK signal - PSELSCK: u32 = 0, - }); - - /// Pin select for MOSI - pub const MOSI = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number configuration for SPI MOSI signal - PSELMOSI: u32 = 0, - }); - - /// Pin select for MISO - pub const MISO = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number configuration for SPI MISO signal - PSELMISO: u32 = 0, - }); + /// address: 0x4000351c + /// TXD register + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + /// address: 0x40003524 + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40003554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + pub const PSEL = struct { + + /// address: 0x40003000 + /// Pin select for SCK + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number configuration for SPI SCK signal + PSELSCK: u32, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Pin select for MOSI + pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number configuration for SPI MOSI signal + PSELMOSI: u32, + }), base_address + 0x4); + + /// address: 0x40003008 + /// Pin select for MISO + pub const MISO = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number configuration for SPI MISO signal + PSELMISO: u32, + }), base_address + 0x8); + }; }; -}; - -/// I2C compatible Two-Wire Interface 0 -pub const TWI0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI RXD byte received - pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// TWI TXD byte sent - pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// TWI byte boundary, generated before each byte that is sent or received - pub const EVENTS_BB = @intToPtr(*volatile u32, Address + 0x00000138); - - /// TWI entered the suspended state - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between BB event and SUSPEND task - BB_SUSPEND: u1 = 0, - /// Shortcut between BB event and STOP task - BB_STOP: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for RXDREADY event - RXDREADY: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for TXDSENT event - TXDSENT: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Write '1' to Enable interrupt for BB event - BB: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for RXDREADY event - RXDREADY: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for TXDSENT event - TXDSENT: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Write '1' to Disable interrupt for BB event - BB: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1 = 0, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWI - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWI - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pin select for SCL - pub const PSELSCL = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Pin select for SDA - pub const PSELSDA = @intToPtr(*volatile u32, Address + 0x0000050c); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// I2C compatible Two-Wire Interface 0 + pub const TWI0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003008 + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40003014 + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000301c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40003020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40003104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40003108 + /// TWI RXD byte received + pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000311c + /// TWI TXD byte sent + pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40003124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40003138 + /// TWI byte boundary, generated before each byte that is sent or received + pub const EVENTS_BB = @intToPtr(*volatile u32, base_address + 0x138); + + /// address: 0x40003148 + /// TWI entered the suspended state + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x40003200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between BB event and SUSPEND task + BB_SUSPEND: u1, + /// Shortcut between BB event and STOP task + BB_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x200); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for RXDREADY event + RXDREADY: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for TXDSENT event + TXDSENT: u1, + reserved5: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Enable interrupt for BB event + BB: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for RXDREADY event + RXDREADY: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for TXDSENT event + TXDSENT: u1, + reserved5: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Disable interrupt for BB event + BB: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x308); + + /// address: 0x400034c4 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4c4); + + /// address: 0x40003500 + /// Enable TWI + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003508 + /// Pin select for SCL + pub const PSELSCL = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000350c + /// Pin select for SDA + pub const PSELSDA = @intToPtr(*volatile u32, base_address + 0x50c); + + /// address: 0x40003518 /// RXD register - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); + + /// address: 0x4000351c /// TXD register - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Address used in the TWI transfer - pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { - /// Address used in the TWI transfer - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + /// address: 0x40003524 + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); -/// Serial Peripheral Interface Master with EasyDMA 1 -pub const SPIM1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// Start SPI transaction - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Stop SPI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend SPI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume SPI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// SPI transaction has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// End of RXD buffer and TXD buffer reached - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); - - /// End of TXD buffer reached - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); - - /// Transaction started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and START task - END_START: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPIM - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPIM - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency. Accuracy depends on the HFCLK source selected. - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character. Character clocked out in case and over-read of the TXD - /// buffer. - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// address: 0x40003588 + /// Address used in the TWI transfer + pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); + }; + /// Serial Peripheral Interface Master with EasyDMA 1 + pub const SPIM1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004010 + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40004014 + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000401c + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40004020 + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40004104 + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40004110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40004118 + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x40004120 + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x4000414c + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40004200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Shortcut between END event and START task + END_START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x200); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x40004500 + /// Enable SPIM + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004524 + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40004554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x400045c0 /// Over-read character. Character clocked out in case and over-read of the TXD /// buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// SPI Slave 1 -pub const SPIS1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// Acquire SPI semaphore - pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); - - /// Release SPI semaphore, enabling the SPI slave to acquire it - pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); - - /// Granted transaction completed - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Semaphore acquired - pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and ACQUIRE task - END_ACQUIRE: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Semaphore status register - pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { - /// Semaphore status - SEMSTAT: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status from last transaction - pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { - /// TX buffer over-read detected, and prevented - OVERREAD: u1 = 0, - /// RX buffer overflow detected, and prevented - OVERFLOW: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI slave - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI slave - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Default character. Character clocked out in case of an ignored transaction. - pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + }; + /// SPI Slave 1 + pub const SPIS1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004024 + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x40004028 + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40004104 + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40004110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40004128 + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x40004200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x200); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x308); + + /// address: 0x40004400 + /// Semaphore status register + pub const SEMSTAT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x400); + + /// address: 0x40004440 + /// Status from last transaction + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// TX buffer over-read detected, and prevented + OVERREAD: u1, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x440); + + /// address: 0x40004500 + /// Enable SPI slave + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x4000455c /// Default character. Character clocked out in case of an ignored transaction. - DEF: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character clocked out after an over-read of the - /// transmit buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const DEF = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x55c); -/// I2C compatible Two-Wire Master Interface with EasyDMA 1 -pub const TWIM1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop TWI transaction. Must be issued while the TWI master is not suspended. - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Last byte has been sent out after the SUSPEND task has been issued, TWI - /// traffic is now suspended. - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); - - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Byte boundary, starting to receive the last byte - pub const EVENTS_LASTRX = @intToPtr(*volatile u32, Address + 0x0000015c); - - /// Byte boundary, starting to transmit the last byte - pub const EVENTS_LASTTX = @intToPtr(*volatile u32, Address + 0x00000160); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between LASTTX event and STARTRX task - LASTTX_STARTRX: u1 = 0, - /// Shortcut between LASTTX event and SUSPEND task - LASTTX_SUSPEND: u1 = 0, - /// Shortcut between LASTTX event and STOP task - LASTTX_STOP: u1 = 0, - /// Shortcut between LASTRX event and STARTTX task - LASTRX_STARTTX: u1 = 0, - reserved8: u1 = 0, - /// Shortcut between LASTRX event and STOP task - LASTRX_STOP: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Enable or disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Enable or disable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Enable or disable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Write '1' to Enable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Write '1' to Enable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Write '1' to Disable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Write '1' to Disable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1 = 0, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWIM - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWIM - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Address used in the TWI transfer - pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// address: 0x400045c0 + /// Over-read character + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + }; + /// I2C compatible Two-Wire Master Interface with EasyDMA 1 + pub const TWIM1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004000 + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40004008 + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40004014 + /// Stop TWI transaction. Must be issued while the TWI master is not suspended. + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000401c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40004020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40004104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40004124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40004148 + /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic + /// is now suspended. + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x4000414c + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40004150 + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x4000415c + /// Byte boundary, starting to receive the last byte + pub const EVENTS_LASTRX = @intToPtr(*volatile u32, base_address + 0x15c); + + /// address: 0x40004160 + /// Byte boundary, starting to transmit the last byte + pub const EVENTS_LASTTX = @intToPtr(*volatile u32, base_address + 0x160); + + /// address: 0x40004200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Shortcut between LASTTX event and STARTRX task + LASTTX_STARTRX: u1, + /// Shortcut between LASTTX event and SUSPEND task + LASTTX_SUSPEND: u1, + /// Shortcut between LASTTX event and STOP task + LASTTX_STOP: u1, + /// Shortcut between LASTRX event and STARTTX task + LASTRX_STARTTX: u1, + reserved7: u1, + /// Shortcut between LASTRX event and STOP task + LASTRX_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x200); + + /// address: 0x40004300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable or disable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Enable or disable interrupt for LASTRX event + LASTRX: u1, + /// Enable or disable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x300); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Write '1' to Enable interrupt for LASTRX event + LASTRX: u1, + /// Write '1' to Enable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Write '1' to Disable interrupt for LASTRX event + LASTRX: u1, + /// Write '1' to Disable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x308); + + /// address: 0x400044c4 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4c4); + + /// address: 0x40004500 + /// Enable TWIM + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004524 + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40004588 /// Address used in the TWI transfer - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// I2C compatible Two-Wire Slave Interface with EasyDMA 1 -pub const TWIS1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// Prepare the TWI slave to respond to a write command - pub const TASKS_PREPARERX = @intToPtr(*volatile u32, Address + 0x00000030); - - /// Prepare the TWI slave to respond to a read command - pub const TASKS_PREPARETX = @intToPtr(*volatile u32, Address + 0x00000034); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Write command received - pub const EVENTS_WRITE = @intToPtr(*volatile u32, Address + 0x00000164); - - /// Read command received - pub const EVENTS_READ = @intToPtr(*volatile u32, Address + 0x00000168); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between WRITE event and SUSPEND task - WRITE_SUSPEND: u1 = 0, - /// Shortcut between READ event and SUSPEND task - READ_SUSPEND: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Enable or disable interrupt for WRITE event - WRITE: u1 = 0, - /// Enable or disable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Write '1' to Enable interrupt for WRITE event - WRITE: u1 = 0, - /// Write '1' to Enable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Write '1' to Disable interrupt for WRITE event - WRITE: u1 = 0, - /// Write '1' to Disable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004d0, 32, packed struct { - /// RX buffer overflow detected, and prevented - OVERFLOW: u1 = 0, - reserved1: u1 = 0, - /// NACK sent after receiving a data byte - DNACK: u1 = 0, - /// TX buffer over-read detected, and prevented - OVERREAD: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register indicating which address had a match - pub const MATCH = mmio(Address + 0x000004d4, 32, packed struct { - /// Which of the addresses in {ADDRESS} matched the incoming address - MATCH: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWIS - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWIS - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register for the address match mechanism - pub const CONFIG = mmio(Address + 0x00000594, 32, packed struct { - /// Enable or disable address matching on ADDRESS[0] - ADDRESS0: u1 = 0, - /// Enable or disable address matching on ADDRESS[1] - ADDRESS1: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character. Character sent out in case of an over-read of the - /// transmit buffer. - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character sent out in case of an over-read of the - /// transmit buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: TWI slave address 0 - pub const ADDRESS = @intToPtr(*volatile [2]MMIO(32, packed struct { - /// TWI slave address - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000588); -}; - -/// Serial Peripheral Interface 1 -pub const SPI1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// TXD byte sent and RXD byte received - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { - /// RX data received. Double buffered - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { - /// TX data to send. Double buffered - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); + }; + /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 + pub const TWIS1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004014 + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000401c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40004020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40004030 + /// Prepare the TWI slave to respond to a write command + pub const TASKS_PREPARERX = @intToPtr(*volatile u32, base_address + 0x30); + + /// address: 0x40004034 + /// Prepare the TWI slave to respond to a read command + pub const TASKS_PREPARETX = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0x40004104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40004124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x4000414c + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40004150 + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x40004164 + /// Write command received + pub const EVENTS_WRITE = @intToPtr(*volatile u32, base_address + 0x164); + + /// address: 0x40004168 + /// Read command received + pub const EVENTS_READ = @intToPtr(*volatile u32, base_address + 0x168); + + /// address: 0x40004200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Shortcut between WRITE event and SUSPEND task + WRITE_SUSPEND: u1, + /// Shortcut between READ event and SUSPEND task + READ_SUSPEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x200); + + /// address: 0x40004300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Enable or disable interrupt for WRITE event + WRITE: u1, + /// Enable or disable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x300); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Write '1' to Enable interrupt for WRITE event + WRITE: u1, + /// Write '1' to Enable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Write '1' to Disable interrupt for WRITE event + WRITE: u1, + /// Write '1' to Disable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x308); + + /// address: 0x400044d0 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// RX buffer overflow detected, and prevented + OVERFLOW: u1, + reserved0: u1, + /// NACK sent after receiving a data byte + DNACK: u1, + /// TX buffer over-read detected, and prevented + OVERREAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x4d0); + + /// address: 0x400044d4 + /// Status register indicating which address had a match + pub const MATCH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4d4); + + /// address: 0x40004500 + /// Enable TWIS + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004588 + /// Description collection[0]: TWI slave address 0 + pub const ADDRESS = @intToPtr(*volatile [2]MmioInt(32, u7), base_address + 0x588); + + /// address: 0x40004594 + /// Configuration register for the address match mechanism + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable address matching on ADDRESS[0] + ADDRESS0: u1, + /// Enable or disable address matching on ADDRESS[1] + ADDRESS1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x594); + + /// address: 0x400045c0 + /// Over-read character. Character sent out in case of an over-read of the transmit + /// buffer. + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + }; + /// Serial Peripheral Interface 1 + pub const SPI1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004108 + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x40004500 + /// Enable SPI + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004518 + /// RXD register + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); -/// I2C compatible Two-Wire Interface 1 -pub const TWI1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI RXD byte received - pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// TWI TXD byte sent - pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// TWI byte boundary, generated before each byte that is sent or received - pub const EVENTS_BB = @intToPtr(*volatile u32, Address + 0x00000138); - - /// TWI entered the suspended state - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between BB event and SUSPEND task - BB_SUSPEND: u1 = 0, - /// Shortcut between BB event and STOP task - BB_STOP: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for RXDREADY event - RXDREADY: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for TXDSENT event - TXDSENT: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Write '1' to Enable interrupt for BB event - BB: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for RXDREADY event - RXDREADY: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for TXDSENT event - TXDSENT: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Write '1' to Disable interrupt for BB event - BB: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1 = 0, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWI - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWI - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pin select for SCL - pub const PSELSCL = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Pin select for SDA - pub const PSELSDA = @intToPtr(*volatile u32, Address + 0x0000050c); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// address: 0x4000451c + /// TXD register + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + /// address: 0x40004524 + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40004554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + }; + /// I2C compatible Two-Wire Interface 1 + pub const TWI1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004000 + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40004008 + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40004014 + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000401c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40004020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40004104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40004108 + /// TWI RXD byte received + pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000411c + /// TWI TXD byte sent + pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40004124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40004138 + /// TWI byte boundary, generated before each byte that is sent or received + pub const EVENTS_BB = @intToPtr(*volatile u32, base_address + 0x138); + + /// address: 0x40004148 + /// TWI entered the suspended state + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x40004200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between BB event and SUSPEND task + BB_SUSPEND: u1, + /// Shortcut between BB event and STOP task + BB_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x200); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for RXDREADY event + RXDREADY: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for TXDSENT event + TXDSENT: u1, + reserved5: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Enable interrupt for BB event + BB: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for RXDREADY event + RXDREADY: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for TXDSENT event + TXDSENT: u1, + reserved5: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Disable interrupt for BB event + BB: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x308); + + /// address: 0x400044c4 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4c4); + + /// address: 0x40004500 + /// Enable TWI + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004508 + /// Pin select for SCL + pub const PSELSCL = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000450c + /// Pin select for SDA + pub const PSELSDA = @intToPtr(*volatile u32, base_address + 0x50c); + + /// address: 0x40004518 /// RXD register - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); + + /// address: 0x4000451c /// TXD register - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Address used in the TWI transfer - pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { - /// Address used in the TWI transfer - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); -/// NFC-A compatible radio -pub const NFCT = extern struct { - pub const Address: u32 = 0x40005000; - - /// Activate NFC peripheral for incoming and outgoing frames, change state to - /// activated - pub const TASKS_ACTIVATE = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Disable NFC peripheral - pub const TASKS_DISABLE = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Enable NFC sense field mode, change state to sense mode - pub const TASKS_SENSE = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Start transmission of a outgoing frame, change state to transmit - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Initializes the EasyDMA for receive. - pub const TASKS_ENABLERXDATA = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Force state machine to IDLE state - pub const TASKS_GOIDLE = @intToPtr(*volatile u32, Address + 0x00000024); - - /// Force state machine to SLEEP_A state - pub const TASKS_GOSLEEP = @intToPtr(*volatile u32, Address + 0x00000028); - - /// The NFC peripheral is ready to receive and send frames - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Remote NFC field detected - pub const EVENTS_FIELDDETECTED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Remote NFC field lost - pub const EVENTS_FIELDLOST = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Marks the start of the first symbol of a transmitted frame - pub const EVENTS_TXFRAMESTART = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// Marks the end of the last transmitted on-air symbol of a frame - pub const EVENTS_TXFRAMEEND = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Marks the end of the first symbol of a received frame - pub const EVENTS_RXFRAMESTART = @intToPtr(*volatile u32, Address + 0x00000114); - - /// Received data have been checked (CRC, parity) and transferred to RAM, and - /// EasyDMA has ended accessing the RX buffer - pub const EVENTS_RXFRAMEEND = @intToPtr(*volatile u32, Address + 0x00000118); - - /// NFC error reported. The ERRORSTATUS register contains details on the source - /// of the error. - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on - /// the source of the error. - pub const EVENTS_RXERROR = @intToPtr(*volatile u32, Address + 0x00000128); - - /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x0000012c); - - /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the - /// TX buffer - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000130); - - /// Auto collision resolution process has started - pub const EVENTS_AUTOCOLRESSTARTED = @intToPtr(*volatile u32, Address + 0x00000138); - - /// NFC Auto collision resolution error reported. - pub const EVENTS_COLLISION = @intToPtr(*volatile u32, Address + 0x00000148); - - /// NFC Auto collision resolution successfully completed - pub const EVENTS_SELECTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// EasyDMA is ready to receive or send frames. - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between FIELDDETECTED event and ACTIVATE task - FIELDDETECTED_ACTIVATE: u1 = 0, - /// Shortcut between FIELDLOST event and SENSE task - FIELDLOST_SENSE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for READY event - READY: u1 = 0, - /// Enable or disable interrupt for FIELDDETECTED event - FIELDDETECTED: u1 = 0, - /// Enable or disable interrupt for FIELDLOST event - FIELDLOST: u1 = 0, - /// Enable or disable interrupt for TXFRAMESTART event - TXFRAMESTART: u1 = 0, - /// Enable or disable interrupt for TXFRAMEEND event - TXFRAMEEND: u1 = 0, - /// Enable or disable interrupt for RXFRAMESTART event - RXFRAMESTART: u1 = 0, - /// Enable or disable interrupt for RXFRAMEEND event - RXFRAMEEND: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable interrupt for RXERROR event - RXERROR: u1 = 0, - /// Enable or disable interrupt for ENDRX event - ENDRX: u1 = 0, - /// Enable or disable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved3: u1 = 0, - /// Enable or disable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Enable or disable interrupt for COLLISION event - COLLISION: u1 = 0, - /// Enable or disable interrupt for SELECTED event - SELECTED: u1 = 0, - /// Enable or disable interrupt for STARTED event - STARTED: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Enable interrupt for FIELDDETECTED event - FIELDDETECTED: u1 = 0, - /// Write '1' to Enable interrupt for FIELDLOST event - FIELDLOST: u1 = 0, - /// Write '1' to Enable interrupt for TXFRAMESTART event - TXFRAMESTART: u1 = 0, - /// Write '1' to Enable interrupt for TXFRAMEEND event - TXFRAMEEND: u1 = 0, - /// Write '1' to Enable interrupt for RXFRAMESTART event - RXFRAMESTART: u1 = 0, - /// Write '1' to Enable interrupt for RXFRAMEEND event - RXFRAMEEND: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for RXERROR event - RXERROR: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Enable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for COLLISION event - COLLISION: u1 = 0, - /// Write '1' to Enable interrupt for SELECTED event - SELECTED: u1 = 0, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Disable interrupt for FIELDDETECTED event - FIELDDETECTED: u1 = 0, - /// Write '1' to Disable interrupt for FIELDLOST event - FIELDLOST: u1 = 0, - /// Write '1' to Disable interrupt for TXFRAMESTART event - TXFRAMESTART: u1 = 0, - /// Write '1' to Disable interrupt for TXFRAMEEND event - TXFRAMEEND: u1 = 0, - /// Write '1' to Disable interrupt for RXFRAMESTART event - RXFRAMESTART: u1 = 0, - /// Write '1' to Disable interrupt for RXFRAMEEND event - RXFRAMEEND: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for RXERROR event - RXERROR: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Disable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for COLLISION event - COLLISION: u1 = 0, - /// Write '1' to Disable interrupt for SELECTED event - SELECTED: u1 = 0, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// NFC Error Status register - pub const ERRORSTATUS = mmio(Address + 0x00000404, 32, packed struct { - /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX - FRAMEDELAYTIMEOUT: u1 = 0, - reserved1: u1 = 0, - /// Field level is too high at max load resistance - NFCFIELDTOOSTRONG: u1 = 0, - /// Field level is too low at min load resistance - NFCFIELDTOOWEAK: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current value driven to the NFC Load Control - pub const CURRENTLOADCTRL = mmio(Address + 0x00000430, 32, packed struct { + /// address: 0x40004524 + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40004588 + /// Address used in the TWI transfer + pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); + }; + /// NFC-A compatible radio + pub const NFCT = struct { + pub const base_address = 0x40005000; + + /// address: 0x40005000 + /// Activate NFC peripheral for incoming and outgoing frames, change state to + /// activated + pub const TASKS_ACTIVATE = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40005004 + /// Disable NFC peripheral + pub const TASKS_DISABLE = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40005008 + /// Enable NFC sense field mode, change state to sense mode + pub const TASKS_SENSE = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000500c + /// Start transmission of a outgoing frame, change state to transmit + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4000501c + /// Initializes the EasyDMA for receive. + pub const TASKS_ENABLERXDATA = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40005024 + /// Force state machine to IDLE state + pub const TASKS_GOIDLE = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x40005028 + /// Force state machine to SLEEP_A state + pub const TASKS_GOSLEEP = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40005100 + /// The NFC peripheral is ready to receive and send frames + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40005104 + /// Remote NFC field detected + pub const EVENTS_FIELDDETECTED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40005108 + /// Remote NFC field lost + pub const EVENTS_FIELDLOST = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000510c + /// Marks the start of the first symbol of a transmitted frame + pub const EVENTS_TXFRAMESTART = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40005110 + /// Marks the end of the last transmitted on-air symbol of a frame + pub const EVENTS_TXFRAMEEND = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40005114 + /// Marks the end of the first symbol of a received frame + pub const EVENTS_RXFRAMESTART = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x40005118 + /// Received data have been checked (CRC, parity) and transferred to RAM, and + /// EasyDMA has ended accessing the RX buffer + pub const EVENTS_RXFRAMEEND = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x4000511c + /// NFC error reported. The ERRORSTATUS register contains details on the source of + /// the error. + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40005128 + /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the + /// source of the error. + pub const EVENTS_RXERROR = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x4000512c + /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x12c); + + /// address: 0x40005130 + /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX + /// buffer + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x130); + + /// address: 0x40005138 + /// Auto collision resolution process has started + pub const EVENTS_AUTOCOLRESSTARTED = @intToPtr(*volatile u32, base_address + 0x138); + + /// address: 0x40005148 + /// NFC Auto collision resolution error reported. + pub const EVENTS_COLLISION = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x4000514c + /// NFC Auto collision resolution successfully completed + pub const EVENTS_SELECTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40005150 + /// EasyDMA is ready to receive or send frames. + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x40005200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between FIELDDETECTED event and ACTIVATE task + FIELDDETECTED_ACTIVATE: u1, + /// Shortcut between FIELDLOST event and SENSE task + FIELDLOST_SENSE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x200); + + /// address: 0x40005300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for READY event + READY: u1, + /// Enable or disable interrupt for FIELDDETECTED event + FIELDDETECTED: u1, + /// Enable or disable interrupt for FIELDLOST event + FIELDLOST: u1, + /// Enable or disable interrupt for TXFRAMESTART event + TXFRAMESTART: u1, + /// Enable or disable interrupt for TXFRAMEEND event + TXFRAMEEND: u1, + /// Enable or disable interrupt for RXFRAMESTART event + RXFRAMESTART: u1, + /// Enable or disable interrupt for RXFRAMEEND event + RXFRAMEEND: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved0: u1, + reserved1: u1, + /// Enable or disable interrupt for RXERROR event + RXERROR: u1, + /// Enable or disable interrupt for ENDRX event + ENDRX: u1, + /// Enable or disable interrupt for ENDTX event + ENDTX: u1, + reserved2: u1, + /// Enable or disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Enable or disable interrupt for COLLISION event + COLLISION: u1, + /// Enable or disable interrupt for SELECTED event + SELECTED: u1, + /// Enable or disable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x300); + + /// address: 0x40005304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for READY event + READY: u1, + /// Write '1' to Enable interrupt for FIELDDETECTED event + FIELDDETECTED: u1, + /// Write '1' to Enable interrupt for FIELDLOST event + FIELDLOST: u1, + /// Write '1' to Enable interrupt for TXFRAMESTART event + TXFRAMESTART: u1, + /// Write '1' to Enable interrupt for TXFRAMEEND event + TXFRAMEEND: u1, + /// Write '1' to Enable interrupt for RXFRAMESTART event + RXFRAMESTART: u1, + /// Write '1' to Enable interrupt for RXFRAMEEND event + RXFRAMEEND: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for RXERROR event + RXERROR: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Write '1' to Enable interrupt for COLLISION event + COLLISION: u1, + /// Write '1' to Enable interrupt for SELECTED event + SELECTED: u1, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x304); + + /// address: 0x40005308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for READY event + READY: u1, + /// Write '1' to Disable interrupt for FIELDDETECTED event + FIELDDETECTED: u1, + /// Write '1' to Disable interrupt for FIELDLOST event + FIELDLOST: u1, + /// Write '1' to Disable interrupt for TXFRAMESTART event + TXFRAMESTART: u1, + /// Write '1' to Disable interrupt for TXFRAMEEND event + TXFRAMEEND: u1, + /// Write '1' to Disable interrupt for RXFRAMESTART event + RXFRAMESTART: u1, + /// Write '1' to Disable interrupt for RXFRAMEEND event + RXFRAMEEND: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for RXERROR event + RXERROR: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Write '1' to Disable interrupt for COLLISION event + COLLISION: u1, + /// Write '1' to Disable interrupt for SELECTED event + SELECTED: u1, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x308); + + /// address: 0x40005404 + /// NFC Error Status register + pub const ERRORSTATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + FRAMEDELAYTIMEOUT: u1, + reserved0: u1, + /// Field level is too high at max load resistance + NFCFIELDTOOSTRONG: u1, + /// Field level is too low at min load resistance + NFCFIELDTOOWEAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x404); + + /// address: 0x40005430 /// Current value driven to the NFC Load Control - CURRENTLOADCTRL: u6 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Indicates the presence or not of a valid field - pub const FIELDPRESENT = mmio(Address + 0x0000043c, 32, packed struct { - /// Indicates the presence or not of a valid field. Available only in the - /// activated state. - FIELDPRESENT: u1 = 0, - /// Indicates if the low level has locked to the field - LOCKDETECT: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Minimum frame delay - pub const FRAMEDELAYMIN = mmio(Address + 0x00000504, 32, packed struct { - /// Minimum frame delay in number of 13.56 MHz clocks - FRAMEDELAYMIN: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Maximum frame delay - pub const FRAMEDELAYMAX = mmio(Address + 0x00000508, 32, packed struct { - /// Maximum frame delay in number of 13.56 MHz clocks - FRAMEDELAYMAX: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register for the Frame Delay Timer - pub const FRAMEDELAYMODE = mmio(Address + 0x0000050c, 32, packed struct { + pub const CURRENTLOADCTRL = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x430); + + /// address: 0x4000543c + /// Indicates the presence or not of a valid field + pub const FIELDPRESENT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Indicates the presence or not of a valid field. Available only in the activated + /// state. + FIELDPRESENT: u1, + /// Indicates if the low level has locked to the field + LOCKDETECT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x43c); + + /// address: 0x40005504 + /// Minimum frame delay + pub const FRAMEDELAYMIN = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x504); + + /// address: 0x40005508 + /// Maximum frame delay + pub const FRAMEDELAYMAX = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x508); + + /// address: 0x4000550c /// Configuration register for the Frame Delay Timer - FRAMEDELAYMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Packet pointer for TXD and RXD data storage in Data RAM - pub const PACKETPTR = mmio(Address + 0x00000510, 32, packed struct { - /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a - /// byte aligned RAM address. - PTR: u32 = 0, - }); - - /// Size of allocated for TXD and RXD data storage buffer in Data RAM - pub const MAXLEN = mmio(Address + 0x00000514, 32, packed struct { - /// Size of allocated for TXD and RXD data storage buffer in Data RAM - MAXLEN: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Last NFCID1 part (4, 7 or 10 bytes ID) - pub const NFCID1_LAST = mmio(Address + 0x00000590, 32, packed struct { - /// NFCID1 byte Z (very last byte sent) - NFCID1_Z: u8 = 0, - /// NFCID1 byte Y - NFCID1_Y: u8 = 0, - /// NFCID1 byte X - NFCID1_X: u8 = 0, - /// NFCID1 byte W - NFCID1_W: u8 = 0, - }); - - /// Second last NFCID1 part (7 or 10 bytes ID) - pub const NFCID1_2ND_LAST = mmio(Address + 0x00000594, 32, packed struct { - /// NFCID1 byte V - NFCID1_V: u8 = 0, - /// NFCID1 byte U - NFCID1_U: u8 = 0, - /// NFCID1 byte T - NFCID1_T: u8 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Third last NFCID1 part (10 bytes ID) - pub const NFCID1_3RD_LAST = mmio(Address + 0x00000598, 32, packed struct { - /// NFCID1 byte S - NFCID1_S: u8 = 0, - /// NFCID1 byte R - NFCID1_R: u8 = 0, - /// NFCID1 byte Q - NFCID1_Q: u8 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// NFC-A SENS_RES auto-response settings - pub const SENSRES = mmio(Address + 0x000005a0, 32, packed struct { - /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the - /// NFC Forum, NFC Digital Protocol Technical Specification - BITFRAMESDD: u5 = 0, - /// Reserved for future use. Shall be 0. - RFU5: u1 = 0, - /// NFCID1 size. This value is used by the Auto collision resolution engine. - NFCIDSIZE: u2 = 0, - /// Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES - /// response in the NFC Forum, NFC Digital Protocol Technical Specification - PLATFCONFIG: u4 = 0, - /// Reserved for future use. Shall be 0. - RFU74: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// NFC-A SEL_RES auto-response settings - pub const SELRES = mmio(Address + 0x000005a4, 32, packed struct { - /// Reserved for future use. Shall be 0. - RFU10: u2 = 0, - /// Cascade bit (controlled by hardware, write has no effect) - CASCADE: u1 = 0, - /// Reserved for future use. Shall be 0. - RFU43: u2 = 0, - /// Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC - /// Digital Protocol Technical Specification - PROTOCOL: u2 = 0, - /// Reserved for future use. Shall be 0. - RFU7: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const FRAMESTATUS = struct { - - /// Result of last incoming frames - pub const RX = mmio(Address + 0x00000000, 32, packed struct { - /// No valid End of Frame detected - CRCERROR: u1 = 0, - reserved1: u1 = 0, - /// Parity status of received frame - PARITYSTATUS: u1 = 0, - /// Overrun detected - OVERRUN: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const FRAMEDELAYMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x50c); - pub const TXD = struct { - - /// Configuration of outgoing frames - pub const FRAMECONFIG = mmio(Address + 0x00000000, 32, packed struct { - /// Adding parity or not in the frame - PARITY: u1 = 0, - /// Discarding unused bits in start or at end of a Frame - DISCARDMODE: u1 = 0, - /// Adding SoF or not in TX frames - SOF: u1 = 0, - reserved1: u1 = 0, - /// CRC mode for outgoing frames - CRCMODETX: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Size of outgoing frame - pub const AMOUNT = mmio(Address + 0x00000004, 32, packed struct { - /// Number of bits in the last or first byte read from RAM that shall be - /// included in the frame (excluding parity bit). - TXDATABITS: u3 = 0, - /// Number of complete bytes that shall be included in the frame, excluding CRC, - /// parity and framing - TXDATABYTES: u9 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + /// address: 0x40005510 + /// Packet pointer for TXD and RXD data storage in Data RAM + pub const PACKETPTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte + /// aligned RAM address. + PTR: u32, + }), base_address + 0x510); - pub const RXD = struct { - - /// Configuration of incoming frames - pub const FRAMECONFIG = mmio(Address + 0x00000000, 32, packed struct { - /// Parity expected or not in RX frame - PARITY: u1 = 0, - reserved1: u1 = 0, - /// SoF expected or not in RX frames - SOF: u1 = 0, - reserved2: u1 = 0, - /// CRC mode for incoming frames - CRCMODERX: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Size of last incoming frame - pub const AMOUNT = mmio(Address + 0x00000004, 32, packed struct { - /// Number of bits in the last byte in the frame, if less than 8 (including CRC, - /// but excluding parity and SoF/EoF framing). - RXDATABITS: u3 = 0, - /// Number of complete bytes received in the frame (including CRC, but excluding - /// parity and SoF/EoF framing) - RXDATABYTES: u9 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + /// address: 0x40005514 + /// Size of allocated for TXD and RXD data storage buffer in Data RAM + pub const MAXLEN = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x514); + + /// address: 0x40005590 + /// Last NFCID1 part (4, 7 or 10 bytes ID) + pub const NFCID1_LAST = @intToPtr(*volatile Mmio(32, packed struct{ + /// NFCID1 byte Z (very last byte sent) + NFCID1_Z: u8, + /// NFCID1 byte Y + NFCID1_Y: u8, + /// NFCID1 byte X + NFCID1_X: u8, + /// NFCID1 byte W + NFCID1_W: u8, + }), base_address + 0x590); + + /// address: 0x40005594 + /// Second last NFCID1 part (7 or 10 bytes ID) + pub const NFCID1_2ND_LAST = @intToPtr(*volatile Mmio(32, packed struct{ + /// NFCID1 byte V + NFCID1_V: u8, + /// NFCID1 byte U + NFCID1_U: u8, + /// NFCID1 byte T + NFCID1_T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x594); + + /// address: 0x40005598 + /// Third last NFCID1 part (10 bytes ID) + pub const NFCID1_3RD_LAST = @intToPtr(*volatile Mmio(32, packed struct{ + /// NFCID1 byte S + NFCID1_S: u8, + /// NFCID1 byte R + NFCID1_R: u8, + /// NFCID1 byte Q + NFCID1_Q: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x598); + + /// address: 0x400055a0 + /// NFC-A SENS_RES auto-response settings + pub const SENSRES = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC + /// Forum, NFC Digital Protocol Technical Specification + BITFRAMESDD: u5, + /// Reserved for future use. Shall be 0. + RFU5: u1, + /// NFCID1 size. This value is used by the Auto collision resolution engine. + NFCIDSIZE: u2, + /// Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES + /// response in the NFC Forum, NFC Digital Protocol Technical Specification + PLATFCONFIG: u4, + /// Reserved for future use. Shall be 0. + RFU74: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5a0); + + /// address: 0x400055a4 + /// NFC-A SEL_RES auto-response settings + pub const SELRES = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reserved for future use. Shall be 0. + RFU10: u2, + /// Cascade bit (controlled by hardware, write has no effect) + CASCADE: u1, + /// Reserved for future use. Shall be 0. + RFU43: u2, + /// Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC + /// Digital Protocol Technical Specification + PROTOCOL: u2, + /// Reserved for future use. Shall be 0. + RFU7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x5a4); + + pub const FRAMESTATUS = struct { + + /// address: 0x40005000 + /// Result of last incoming frames + pub const RX = @intToPtr(*volatile Mmio(32, packed struct{ + /// No valid End of Frame detected + CRCERROR: u1, + reserved0: u1, + /// Parity status of received frame + PARITYSTATUS: u1, + /// Overrun detected + OVERRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x0); + }; + + pub const TXD = struct { + + /// address: 0x40005000 + /// Configuration of outgoing frames + pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Adding parity or not in the frame + PARITY: u1, + /// Discarding unused bits in start or at end of a Frame + DISCARDMODE: u1, + /// Adding SoF or not in TX frames + SOF: u1, + reserved0: u1, + /// CRC mode for outgoing frames + CRCMODETX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// Size of outgoing frame + pub const AMOUNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of bits in the last or first byte read from RAM that shall be included in + /// the frame (excluding parity bit). + TXDATABITS: u3, + /// Number of complete bytes that shall be included in the frame, excluding CRC, + /// parity and framing + TXDATABYTES: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + }; + + pub const RXD = struct { + + /// address: 0x40005000 + /// Configuration of incoming frames + pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity expected or not in RX frame + PARITY: u1, + reserved0: u1, + /// SoF expected or not in RX frames + SOF: u1, + reserved1: u1, + /// CRC mode for incoming frames + CRCMODERX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// Size of last incoming frame + pub const AMOUNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of bits in the last byte in the frame, if less than 8 (including CRC, but + /// excluding parity and SoF/EoF framing). + RXDATABITS: u3, + /// Number of complete bytes received in the frame (including CRC, but excluding + /// parity and SoF/EoF framing) + RXDATABYTES: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + }; }; -}; - -/// GPIO Tasks and Events -pub const GPIOTE = extern struct { - pub const Address: u32 = 0x40006000; - - /// Event generated from multiple input GPIO pins with SENSE mechanism enabled - pub const EVENTS_PORT = @intToPtr(*volatile u32, Address + 0x0000017c); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for IN[0] event - IN0: u1 = 0, - /// Write '1' to Enable interrupt for IN[1] event - IN1: u1 = 0, - /// Write '1' to Enable interrupt for IN[2] event - IN2: u1 = 0, - /// Write '1' to Enable interrupt for IN[3] event - IN3: u1 = 0, - /// Write '1' to Enable interrupt for IN[4] event - IN4: u1 = 0, - /// Write '1' to Enable interrupt for IN[5] event - IN5: u1 = 0, - /// Write '1' to Enable interrupt for IN[6] event - IN6: u1 = 0, - /// Write '1' to Enable interrupt for IN[7] event - IN7: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for PORT event - PORT: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for IN[0] event - IN0: u1 = 0, - /// Write '1' to Disable interrupt for IN[1] event - IN1: u1 = 0, - /// Write '1' to Disable interrupt for IN[2] event - IN2: u1 = 0, - /// Write '1' to Disable interrupt for IN[3] event - IN3: u1 = 0, - /// Write '1' to Disable interrupt for IN[4] event - IN4: u1 = 0, - /// Write '1' to Disable interrupt for IN[5] event - IN5: u1 = 0, - /// Write '1' to Disable interrupt for IN[6] event - IN6: u1 = 0, - /// Write '1' to Disable interrupt for IN[7] event - IN7: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for PORT event - PORT: u1 = 0, - }); - /// Description collection[0]: Task for writing to pin specified in - /// CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. - pub const TASKS_OUT = @intToPtr(*volatile [8]u32, Address + 0x00000000); - /// Description collection[0]: Task for writing to pin specified in - /// CONFIG[0].PSEL. Action on pin is to set it high. - pub const TASKS_SET = @intToPtr(*volatile [8]u32, Address + 0x00000030); - /// Description collection[0]: Task for writing to pin specified in - /// CONFIG[0].PSEL. Action on pin is to set it low. - pub const TASKS_CLR = @intToPtr(*volatile [8]u32, Address + 0x00000060); - /// Description collection[0]: Event generated from pin specified in - /// CONFIG[0].PSEL - pub const EVENTS_IN = @intToPtr(*volatile [8]u32, Address + 0x00000100); - /// Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks - /// and IN[n] event - pub const CONFIG = @intToPtr(*volatile [8]MMIO(32, packed struct { - /// Mode - MODE: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event - PSEL: u5 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// When In task mode: Operation to be performed on output when OUT[n] task is - /// triggered. When In event mode: Operation on input that shall trigger IN[n] - /// event. - POLARITY: u2 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - /// When in task mode: Initial value of the output when the GPIOTE channel is - /// configured. When in event mode: No effect. - OUTINIT: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000510); -}; - -/// Analog to Digital Converter -pub const SAADC = extern struct { - pub const Address: u32 = 0x40007000; - - /// Start the ADC and prepare the result buffer in RAM - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Take one ADC sample, if scan is enabled all channels are sampled - pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Stop the ADC and terminate any on-going conversion - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Starts offset auto-calibration - pub const TASKS_CALIBRATEOFFSET = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// The ADC has started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000100); - - /// The ADC has filled up the Result buffer - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); - - /// A conversion task has been completed. Depending on the mode, multiple - /// conversions might be needed for a result to be transferred to RAM. - pub const EVENTS_DONE = @intToPtr(*volatile u32, Address + 0x00000108); - - /// A result is ready to get transferred to RAM. - pub const EVENTS_RESULTDONE = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// Calibration is complete - pub const EVENTS_CALIBRATEDONE = @intToPtr(*volatile u32, Address + 0x00000110); - - /// The ADC has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000114); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for STARTED event - STARTED: u1 = 0, - /// Enable or disable interrupt for END event - END: u1 = 0, - /// Enable or disable interrupt for DONE event - DONE: u1 = 0, - /// Enable or disable interrupt for RESULTDONE event - RESULTDONE: u1 = 0, - /// Enable or disable interrupt for CALIBRATEDONE event - CALIBRATEDONE: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Enable or disable interrupt for CH[0].LIMITH event - CH0LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[0].LIMITL event - CH0LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[1].LIMITH event - CH1LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[1].LIMITL event - CH1LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[2].LIMITH event - CH2LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[2].LIMITL event - CH2LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[3].LIMITH event - CH3LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[3].LIMITL event - CH3LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[4].LIMITH event - CH4LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[4].LIMITL event - CH4LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[5].LIMITH event - CH5LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[5].LIMITL event - CH5LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[6].LIMITH event - CH6LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[6].LIMITL event - CH6LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[7].LIMITH event - CH7LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[7].LIMITL event - CH7LIMITL: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - /// Write '1' to Enable interrupt for DONE event - DONE: u1 = 0, - /// Write '1' to Enable interrupt for RESULTDONE event - RESULTDONE: u1 = 0, - /// Write '1' to Enable interrupt for CALIBRATEDONE event - CALIBRATEDONE: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for CH[0].LIMITH event - CH0LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[0].LIMITL event - CH0LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[1].LIMITH event - CH1LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[1].LIMITL event - CH1LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[2].LIMITH event - CH2LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[2].LIMITL event - CH2LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[3].LIMITH event - CH3LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[3].LIMITL event - CH3LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[4].LIMITH event - CH4LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[4].LIMITL event - CH4LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[5].LIMITH event - CH5LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[5].LIMITL event - CH5LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[6].LIMITH event - CH6LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[6].LIMITL event - CH6LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[7].LIMITH event - CH7LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[7].LIMITL event - CH7LIMITL: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - /// Write '1' to Disable interrupt for DONE event - DONE: u1 = 0, - /// Write '1' to Disable interrupt for RESULTDONE event - RESULTDONE: u1 = 0, - /// Write '1' to Disable interrupt for CALIBRATEDONE event - CALIBRATEDONE: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for CH[0].LIMITH event - CH0LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[0].LIMITL event - CH0LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[1].LIMITH event - CH1LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[1].LIMITL event - CH1LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[2].LIMITH event - CH2LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[2].LIMITL event - CH2LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[3].LIMITH event - CH3LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[3].LIMITL event - CH3LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[4].LIMITH event - CH4LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[4].LIMITL event - CH4LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[5].LIMITH event - CH5LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[5].LIMITL event - CH5LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[6].LIMITH event - CH6LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[6].LIMITL event - CH6LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[7].LIMITH event - CH7LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[7].LIMITL event - CH7LIMITL: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status - pub const STATUS = mmio(Address + 0x00000400, 32, packed struct { + /// GPIO Tasks and Events + pub const GPIOTE = struct { + pub const base_address = 0x40006000; + + /// address: 0x40006000 + /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. + /// Action on pin is configured in CONFIG[0].POLARITY. + pub const TASKS_OUT = @intToPtr(*volatile [8]u32, base_address + 0x0); + + /// address: 0x40006030 + /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. + /// Action on pin is to set it high. + pub const TASKS_SET = @intToPtr(*volatile [8]u32, base_address + 0x30); + + /// address: 0x40006060 + /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. + /// Action on pin is to set it low. + pub const TASKS_CLR = @intToPtr(*volatile [8]u32, base_address + 0x60); + + /// address: 0x40006100 + /// Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL + pub const EVENTS_IN = @intToPtr(*volatile [8]u32, base_address + 0x100); + + /// address: 0x4000617c + /// Event generated from multiple input GPIO pins with SENSE mechanism enabled + pub const EVENTS_PORT = @intToPtr(*volatile u32, base_address + 0x17c); + + /// address: 0x40006304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for IN[0] event + IN0: u1, + /// Write '1' to Enable interrupt for IN[1] event + IN1: u1, + /// Write '1' to Enable interrupt for IN[2] event + IN2: u1, + /// Write '1' to Enable interrupt for IN[3] event + IN3: u1, + /// Write '1' to Enable interrupt for IN[4] event + IN4: u1, + /// Write '1' to Enable interrupt for IN[5] event + IN5: u1, + /// Write '1' to Enable interrupt for IN[6] event + IN6: u1, + /// Write '1' to Enable interrupt for IN[7] event + IN7: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + /// Write '1' to Enable interrupt for PORT event + PORT: u1, + }), base_address + 0x304); + + /// address: 0x40006308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for IN[0] event + IN0: u1, + /// Write '1' to Disable interrupt for IN[1] event + IN1: u1, + /// Write '1' to Disable interrupt for IN[2] event + IN2: u1, + /// Write '1' to Disable interrupt for IN[3] event + IN3: u1, + /// Write '1' to Disable interrupt for IN[4] event + IN4: u1, + /// Write '1' to Disable interrupt for IN[5] event + IN5: u1, + /// Write '1' to Disable interrupt for IN[6] event + IN6: u1, + /// Write '1' to Disable interrupt for IN[7] event + IN7: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + /// Write '1' to Disable interrupt for PORT event + PORT: u1, + }), base_address + 0x308); + + /// address: 0x40006510 + /// Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and + /// IN[n] event + pub const CONFIG = @intToPtr(*volatile [8]Mmio(32, packed struct{ + /// Mode + MODE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + PSEL: u5, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// When In task mode: Operation to be performed on output when OUT[n] task is + /// triggered. When In event mode: Operation on input that shall trigger IN[n] + /// event. + POLARITY: u2, + reserved9: u1, + reserved10: u1, + /// When in task mode: Initial value of the output when the GPIOTE channel is + /// configured. When in event mode: No effect. + OUTINIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x510); + }; + /// Analog to Digital Converter + pub const SAADC = struct { + pub const base_address = 0x40007000; + + /// address: 0x40007000 + /// Start the ADC and prepare the result buffer in RAM + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40007004 + /// Take one ADC sample, if scan is enabled all channels are sampled + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40007008 + /// Stop the ADC and terminate any on-going conversion + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000700c + /// Starts offset auto-calibration + pub const TASKS_CALIBRATEOFFSET = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40007100 + /// The ADC has started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40007104 + /// The ADC has filled up the Result buffer + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40007108 + /// A conversion task has been completed. Depending on the mode, multiple + /// conversions might be needed for a result to be transferred to RAM. + pub const EVENTS_DONE = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000710c + /// A result is ready to get transferred to RAM. + pub const EVENTS_RESULTDONE = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40007110 + /// Calibration is complete + pub const EVENTS_CALIBRATEDONE = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40007114 + /// The ADC has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x40007300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for STARTED event + STARTED: u1, + /// Enable or disable interrupt for END event + END: u1, + /// Enable or disable interrupt for DONE event + DONE: u1, + /// Enable or disable interrupt for RESULTDONE event + RESULTDONE: u1, + /// Enable or disable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + /// Enable or disable interrupt for CH[0].LIMITH event + CH0LIMITH: u1, + /// Enable or disable interrupt for CH[0].LIMITL event + CH0LIMITL: u1, + /// Enable or disable interrupt for CH[1].LIMITH event + CH1LIMITH: u1, + /// Enable or disable interrupt for CH[1].LIMITL event + CH1LIMITL: u1, + /// Enable or disable interrupt for CH[2].LIMITH event + CH2LIMITH: u1, + /// Enable or disable interrupt for CH[2].LIMITL event + CH2LIMITL: u1, + /// Enable or disable interrupt for CH[3].LIMITH event + CH3LIMITH: u1, + /// Enable or disable interrupt for CH[3].LIMITL event + CH3LIMITL: u1, + /// Enable or disable interrupt for CH[4].LIMITH event + CH4LIMITH: u1, + /// Enable or disable interrupt for CH[4].LIMITL event + CH4LIMITL: u1, + /// Enable or disable interrupt for CH[5].LIMITH event + CH5LIMITH: u1, + /// Enable or disable interrupt for CH[5].LIMITL event + CH5LIMITL: u1, + /// Enable or disable interrupt for CH[6].LIMITH event + CH6LIMITH: u1, + /// Enable or disable interrupt for CH[6].LIMITL event + CH6LIMITL: u1, + /// Enable or disable interrupt for CH[7].LIMITH event + CH7LIMITH: u1, + /// Enable or disable interrupt for CH[7].LIMITL event + CH7LIMITL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x300); + + /// address: 0x40007304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + /// Write '1' to Enable interrupt for DONE event + DONE: u1, + /// Write '1' to Enable interrupt for RESULTDONE event + RESULTDONE: u1, + /// Write '1' to Enable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for CH[0].LIMITH event + CH0LIMITH: u1, + /// Write '1' to Enable interrupt for CH[0].LIMITL event + CH0LIMITL: u1, + /// Write '1' to Enable interrupt for CH[1].LIMITH event + CH1LIMITH: u1, + /// Write '1' to Enable interrupt for CH[1].LIMITL event + CH1LIMITL: u1, + /// Write '1' to Enable interrupt for CH[2].LIMITH event + CH2LIMITH: u1, + /// Write '1' to Enable interrupt for CH[2].LIMITL event + CH2LIMITL: u1, + /// Write '1' to Enable interrupt for CH[3].LIMITH event + CH3LIMITH: u1, + /// Write '1' to Enable interrupt for CH[3].LIMITL event + CH3LIMITL: u1, + /// Write '1' to Enable interrupt for CH[4].LIMITH event + CH4LIMITH: u1, + /// Write '1' to Enable interrupt for CH[4].LIMITL event + CH4LIMITL: u1, + /// Write '1' to Enable interrupt for CH[5].LIMITH event + CH5LIMITH: u1, + /// Write '1' to Enable interrupt for CH[5].LIMITL event + CH5LIMITL: u1, + /// Write '1' to Enable interrupt for CH[6].LIMITH event + CH6LIMITH: u1, + /// Write '1' to Enable interrupt for CH[6].LIMITL event + CH6LIMITL: u1, + /// Write '1' to Enable interrupt for CH[7].LIMITH event + CH7LIMITH: u1, + /// Write '1' to Enable interrupt for CH[7].LIMITL event + CH7LIMITL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x40007308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + /// Write '1' to Disable interrupt for DONE event + DONE: u1, + /// Write '1' to Disable interrupt for RESULTDONE event + RESULTDONE: u1, + /// Write '1' to Disable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for CH[0].LIMITH event + CH0LIMITH: u1, + /// Write '1' to Disable interrupt for CH[0].LIMITL event + CH0LIMITL: u1, + /// Write '1' to Disable interrupt for CH[1].LIMITH event + CH1LIMITH: u1, + /// Write '1' to Disable interrupt for CH[1].LIMITL event + CH1LIMITL: u1, + /// Write '1' to Disable interrupt for CH[2].LIMITH event + CH2LIMITH: u1, + /// Write '1' to Disable interrupt for CH[2].LIMITL event + CH2LIMITL: u1, + /// Write '1' to Disable interrupt for CH[3].LIMITH event + CH3LIMITH: u1, + /// Write '1' to Disable interrupt for CH[3].LIMITL event + CH3LIMITL: u1, + /// Write '1' to Disable interrupt for CH[4].LIMITH event + CH4LIMITH: u1, + /// Write '1' to Disable interrupt for CH[4].LIMITL event + CH4LIMITL: u1, + /// Write '1' to Disable interrupt for CH[5].LIMITH event + CH5LIMITH: u1, + /// Write '1' to Disable interrupt for CH[5].LIMITL event + CH5LIMITL: u1, + /// Write '1' to Disable interrupt for CH[6].LIMITH event + CH6LIMITH: u1, + /// Write '1' to Disable interrupt for CH[6].LIMITL event + CH6LIMITL: u1, + /// Write '1' to Disable interrupt for CH[7].LIMITH event + CH7LIMITH: u1, + /// Write '1' to Disable interrupt for CH[7].LIMITL event + CH7LIMITL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x40007400 /// Status - STATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable ADC - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + pub const STATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x40007500 /// Enable or disable ADC - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Resolution configuration - pub const RESOLUTION = mmio(Address + 0x000005f0, 32, packed struct { - /// Set the resolution - VAL: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The - /// RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher - /// RESOLUTION should be used. - pub const OVERSAMPLE = mmio(Address + 0x000005f4, 32, packed struct { - /// Oversample control - OVERSAMPLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Controls normal or continuous sample rate - pub const SAMPLERATE = mmio(Address + 0x000005f8, 32, packed struct { - /// Capture and compare value. Sample rate is 16 MHz/CC - CC: u11 = 0, - reserved1: u1 = 0, - /// Select mode for sample rate control - MODE: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const RESULT = struct { - - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Maximum number of buffer words to transfer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x400075f0 + /// Resolution configuration + pub const RESOLUTION = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set the resolution + VAL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x5f0); + + /// address: 0x400075f4 + /// Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The + /// RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher + /// RESOLUTION should be used. + pub const OVERSAMPLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x5f4); + + /// address: 0x400075f8 + /// Controls normal or continuous sample rate + pub const SAMPLERATE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture and compare value. Sample rate is 16 MHz/CC + CC: u11, + reserved0: u1, + /// Select mode for sample rate control + MODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x5f8); + + pub const EVENTS_CH = @ptrCast(*volatile [8]packed struct { + /// Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH + LIMITH: u32, + + /// Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW + LIMITL: u32, + }, base_address + 0x118); + + pub const CH = @ptrCast(*volatile [8]packed struct { + /// Description cluster[0]: Input positive pin selection for CH[0] + PSELP: MmioInt(32, u5), + + /// Description cluster[0]: Input negative pin selection for CH[0] + PSELN: MmioInt(32, u5), + + /// Description cluster[0]: Input configuration for CH[0] + CONFIG: Mmio(32, packed struct{ + /// Positive channel resistor control + RESP: u2, + reserved0: u1, + reserved1: u1, + /// Negative channel resistor control + RESN: u2, + reserved2: u1, + reserved3: u1, + /// Gain control + GAIN: u3, + reserved4: u1, + /// Reference control + REFSEL: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Acquisition time, the time the ADC uses to sample the input voltage + TACQ: u3, + reserved8: u1, + /// Enable differential mode + MODE: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Enable burst mode + BURST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), + + /// Description cluster[0]: High/low limits for event monitoring a channel + LIMIT: Mmio(32, packed struct{ + /// Low level limit + LOW: u16, + /// High level limit + HIGH: u16, + }), + }, base_address + 0x510); + + /// RESULT EasyDMA channel + pub const RESULT = struct { + + /// address: 0x40007000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40007004 /// Maximum number of buffer words to transfer - MAXCNT: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of buffer words transferred since last START - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { - /// Number of buffer words transferred since last START. This register can be - /// read after an END or STOPPED event. - AMOUNT: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; -}; - -/// Timer/Counter 0 -pub const TIMER0 = extern struct { - pub const Address: u32 = 0x40008000; - - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1 = 0, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1 = 0, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1 = 0, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1 = 0, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1 = 0, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1 = 0, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1 = 0, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1 = 0, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1 = 0, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1 = 0, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer mode selection - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Timer mode - MODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configure the number of bits used by the TIMER - pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { - /// Timer bit width - BITMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer prescaler register - pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { - /// Prescaler value - PRESCALER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); -}; + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x4); -/// Timer/Counter 1 -pub const TIMER1 = extern struct { - pub const Address: u32 = 0x40009000; - - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1 = 0, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1 = 0, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1 = 0, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1 = 0, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1 = 0, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1 = 0, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1 = 0, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1 = 0, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1 = 0, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1 = 0, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer mode selection - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Timer mode - MODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configure the number of bits used by the TIMER - pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { - /// Timer bit width - BITMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer prescaler register - pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { - /// Prescaler value - PRESCALER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); -}; - -/// Timer/Counter 2 -pub const TIMER2 = extern struct { - pub const Address: u32 = 0x4000a000; - - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1 = 0, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1 = 0, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1 = 0, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1 = 0, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1 = 0, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1 = 0, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1 = 0, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1 = 0, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1 = 0, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1 = 0, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer mode selection - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Timer mode - MODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configure the number of bits used by the TIMER - pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { - /// Timer bit width - BITMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer prescaler register - pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { - /// Prescaler value - PRESCALER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); -}; - -/// Real time counter 0 -pub const RTC0 = extern struct { - pub const Address: u32 = 0x4000b000; - - /// Start RTC COUNTER - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop RTC COUNTER - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Clear RTC COUNTER - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Set COUNTER to 0xFFFFF0 - pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Event on COUNTER increment - pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Event on COUNTER overflow - pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Enable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Disable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable event routing - pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { - /// Enable or disable event routing for TICK event - TICK: u1 = 0, - /// Enable or disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Enable or disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Enable or disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Enable or disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable event routing - pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { - /// Write '1' to Enable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Enable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable event routing - pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { - /// Write '1' to Disable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current COUNTER value - pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { - /// Counter value - COUNTER: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written - /// when RTC is stopped - pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { - /// Prescaler value - PRESCALER: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); - /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { - /// Compare value - COMPARE: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000540); -}; - -/// Temperature Sensor -pub const TEMP = extern struct { - pub const Address: u32 = 0x4000c000; - - /// Start temperature measurement - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop temperature measurement - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Temperature measurement complete, data ready - pub const EVENTS_DATARDY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for DATARDY event - DATARDY: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for DATARDY event - DATARDY: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Temperature in degC (0.25deg steps) - pub const TEMP = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Slope of 1st piece wise linear function - pub const A0 = mmio(Address + 0x00000520, 32, packed struct { + /// address: 0x40007008 + /// Number of buffer words transferred since last START + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x8); + }; + }; + /// Timer/Counter 0 + pub const TIMER0 = struct { + pub const base_address = 0x40008000; + + /// address: 0x40008000 + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40008004 + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40008008 + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000800c + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40008010 + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40008040 + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); + + /// address: 0x40008140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); + + /// address: 0x40008200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1, + reserved0: u1, + reserved1: u1, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40008304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x40008308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x40008504 + /// Timer mode selection + pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); + + /// address: 0x40008508 + /// Configure the number of bits used by the TIMER + pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); + + /// address: 0x40008510 + /// Timer prescaler register + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x40008540 + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); + }; + /// Timer/Counter 1 + pub const TIMER1 = struct { + pub const base_address = 0x40009000; + + /// address: 0x40009000 + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40009004 + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40009008 + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000900c + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40009010 + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40009040 + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); + + /// address: 0x40009140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); + + /// address: 0x40009200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1, + reserved0: u1, + reserved1: u1, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40009304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x40009308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x40009504 + /// Timer mode selection + pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); + + /// address: 0x40009508 + /// Configure the number of bits used by the TIMER + pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); + + /// address: 0x40009510 + /// Timer prescaler register + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x40009540 + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); + }; + /// Timer/Counter 2 + pub const TIMER2 = struct { + pub const base_address = 0x4000a000; + + /// address: 0x4000a000 + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000a004 + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000a008 + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000a00c + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4000a010 + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x4000a040 + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); + + /// address: 0x4000a140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); + + /// address: 0x4000a200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1, + reserved0: u1, + reserved1: u1, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x4000a304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x4000a308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x4000a504 + /// Timer mode selection + pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); + + /// address: 0x4000a508 + /// Configure the number of bits used by the TIMER + pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); + + /// address: 0x4000a510 + /// Timer prescaler register + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x4000a540 + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); + }; + /// Real time counter 0 + pub const RTC0 = struct { + pub const base_address = 0x4000b000; + + /// address: 0x4000b000 + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000b004 + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000b008 + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000b00c + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4000b100 + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000b104 + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4000b140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, base_address + 0x140); + + /// address: 0x4000b304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TICK event + TICK: u1, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x4000b308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TICK event + TICK: u1, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x4000b340 + /// Enable or disable event routing + pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable event routing for TICK event + TICK: u1, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x340); + + /// address: 0x4000b344 + /// Enable event routing + pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable event routing for TICK event + TICK: u1, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x344); + + /// address: 0x4000b348 + /// Disable event routing + pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable event routing for TICK event + TICK: u1, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x348); + + /// address: 0x4000b504 + /// Current COUNTER value + pub const COUNTER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x504); + + /// address: 0x4000b508 + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x508); + + /// address: 0x4000b540 + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct{ + /// Compare value + COMPARE: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x540); + }; + /// Temperature Sensor + pub const TEMP = struct { + pub const base_address = 0x4000c000; + + /// address: 0x4000c000 + /// Start temperature measurement + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000c004 + /// Stop temperature measurement + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000c100 + /// Temperature measurement complete, data ready + pub const EVENTS_DATARDY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000c304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for DATARDY event + DATARDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x304); + + /// address: 0x4000c308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for DATARDY event + DATARDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x308); + + /// address: 0x4000c508 + /// Temperature in degC (0.25deg steps) + pub const TEMP = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000c520 /// Slope of 1st piece wise linear function - A0: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope of 2nd piece wise linear function - pub const A1 = mmio(Address + 0x00000524, 32, packed struct { + pub const A0 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x520); + + /// address: 0x4000c524 /// Slope of 2nd piece wise linear function - A1: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope of 3rd piece wise linear function - pub const A2 = mmio(Address + 0x00000528, 32, packed struct { + pub const A1 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x524); + + /// address: 0x4000c528 /// Slope of 3rd piece wise linear function - A2: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope of 4th piece wise linear function - pub const A3 = mmio(Address + 0x0000052c, 32, packed struct { + pub const A2 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x528); + + /// address: 0x4000c52c /// Slope of 4th piece wise linear function - A3: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope of 5th piece wise linear function - pub const A4 = mmio(Address + 0x00000530, 32, packed struct { + pub const A3 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x52c); + + /// address: 0x4000c530 /// Slope of 5th piece wise linear function - A4: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope of 6th piece wise linear function - pub const A5 = mmio(Address + 0x00000534, 32, packed struct { + pub const A4 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x530); + + /// address: 0x4000c534 /// Slope of 6th piece wise linear function - A5: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 1st piece wise linear function - pub const B0 = mmio(Address + 0x00000540, 32, packed struct { + pub const A5 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x534); + + /// address: 0x4000c540 /// y-intercept of 1st piece wise linear function - B0: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 2nd piece wise linear function - pub const B1 = mmio(Address + 0x00000544, 32, packed struct { + pub const B0 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x540); + + /// address: 0x4000c544 /// y-intercept of 2nd piece wise linear function - B1: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 3rd piece wise linear function - pub const B2 = mmio(Address + 0x00000548, 32, packed struct { + pub const B1 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x544); + + /// address: 0x4000c548 /// y-intercept of 3rd piece wise linear function - B2: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 4th piece wise linear function - pub const B3 = mmio(Address + 0x0000054c, 32, packed struct { + pub const B2 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x548); + + /// address: 0x4000c54c /// y-intercept of 4th piece wise linear function - B3: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 5th piece wise linear function - pub const B4 = mmio(Address + 0x00000550, 32, packed struct { + pub const B3 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x54c); + + /// address: 0x4000c550 /// y-intercept of 5th piece wise linear function - B4: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 6th piece wise linear function - pub const B5 = mmio(Address + 0x00000554, 32, packed struct { + pub const B4 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x550); + + /// address: 0x4000c554 /// y-intercept of 6th piece wise linear function - B5: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// End point of 1st piece wise linear function - pub const T0 = mmio(Address + 0x00000560, 32, packed struct { + pub const B5 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x554); + + /// address: 0x4000c560 /// End point of 1st piece wise linear function - T0: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// End point of 2nd piece wise linear function - pub const T1 = mmio(Address + 0x00000564, 32, packed struct { + pub const T0 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x560); + + /// address: 0x4000c564 /// End point of 2nd piece wise linear function - T1: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// End point of 3rd piece wise linear function - pub const T2 = mmio(Address + 0x00000568, 32, packed struct { + pub const T1 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x564); + + /// address: 0x4000c568 /// End point of 3rd piece wise linear function - T2: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// End point of 4th piece wise linear function - pub const T3 = mmio(Address + 0x0000056c, 32, packed struct { + pub const T2 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x568); + + /// address: 0x4000c56c /// End point of 4th piece wise linear function - T3: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// End point of 5th piece wise linear function - pub const T4 = mmio(Address + 0x00000570, 32, packed struct { + pub const T3 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x56c); + + /// address: 0x4000c570 /// End point of 5th piece wise linear function - T4: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const T4 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x570); + }; + /// Random Number Generator + pub const RNG = struct { + pub const base_address = 0x4000d000; + + /// address: 0x4000d000 + /// Task starting the random number generator + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000d004 + /// Task stopping the random number generator + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000d100 + /// Event being generated for every new random number written to the VALUE register + pub const EVENTS_VALRDY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000d200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between VALRDY event and STOP task + VALRDY_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x200); + + /// address: 0x4000d304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for VALRDY event + VALRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x304); + + /// address: 0x4000d308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for VALRDY event + VALRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x308); + + /// address: 0x4000d504 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bias correction + DERCEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x504); + + /// address: 0x4000d508 + /// Output random number + pub const VALUE = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x508); + }; + /// AES ECB Mode Encryption + pub const ECB = struct { + pub const base_address = 0x4000e000; + + /// address: 0x4000e000 + /// Start ECB block encrypt + pub const TASKS_STARTECB = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000e004 + /// Abort a possible executing ECB operation + pub const TASKS_STOPECB = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000e100 + /// ECB block encrypt complete + pub const EVENTS_ENDECB = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000e104 + /// ECB block encrypt aborted because of a STOPECB task or due to an error + pub const EVENTS_ERRORECB = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4000e304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for ENDECB event + ENDECB: u1, + /// Write '1' to Enable interrupt for ERRORECB event + ERRORECB: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x304); + + /// address: 0x4000e308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for ENDECB event + ENDECB: u1, + /// Write '1' to Disable interrupt for ERRORECB event + ERRORECB: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x308); + + /// address: 0x4000e504 + /// ECB block encrypt memory pointers + pub const ECBDATAPTR = @intToPtr(*volatile u32, base_address + 0x504); + }; + /// AES CCM Mode Encryption + pub const CCM = struct { + pub const base_address = 0x4000f000; + + /// address: 0x4000f000 + /// Start generation of key-stream. This operation will stop by itself when + /// completed. + pub const TASKS_KSGEN = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000f004 + /// Start encryption/decryption. This operation will stop by itself when completed. + pub const TASKS_CRYPT = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000f008 + /// Stop encryption/decryption + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000f100 + /// Key-stream generation complete + pub const EVENTS_ENDKSGEN = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000f104 + /// Encrypt/decrypt complete + pub const EVENTS_ENDCRYPT = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4000f108 + /// CCM error event + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000f200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between ENDKSGEN event and CRYPT task + ENDKSGEN_CRYPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x200); + + /// address: 0x4000f304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for ENDKSGEN event + ENDKSGEN: u1, + /// Write '1' to Enable interrupt for ENDCRYPT event + ENDCRYPT: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x4000f308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for ENDKSGEN event + ENDKSGEN: u1, + /// Write '1' to Disable interrupt for ENDCRYPT event + ENDCRYPT: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x4000f400 + /// MIC check result + pub const MICSTATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x4000f500 + /// Enable + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); + + /// address: 0x4000f504 + /// Operation mode + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// The mode of operation to be used + MODE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Data rate that the CCM shall run in synch with + DATARATE: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Packet length configuration + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x504); + + /// address: 0x4000f508 + /// Pointer to data structure holding AES key and NONCE vector + pub const CNFPTR = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000f50c + /// Input pointer + pub const INPTR = @intToPtr(*volatile u32, base_address + 0x50c); + + /// address: 0x4000f510 + /// Output pointer + pub const OUTPTR = @intToPtr(*volatile u32, base_address + 0x510); + + /// address: 0x4000f514 + /// Pointer to data area used for temporary storage + pub const SCRATCHPTR = @intToPtr(*volatile u32, base_address + 0x514); + }; + /// Accelerated Address Resolver + pub const AAR = struct { + pub const base_address = 0x4000f000; + + /// address: 0x4000f000 + /// Start resolving addresses based on IRKs specified in the IRK data structure + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000f008 + /// Stop resolving addresses + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000f100 + /// Address resolution procedure complete + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000f104 + /// Address resolved + pub const EVENTS_RESOLVED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4000f108 + /// Address not resolved + pub const EVENTS_NOTRESOLVED = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000f304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for END event + END: u1, + /// Write '1' to Enable interrupt for RESOLVED event + RESOLVED: u1, + /// Write '1' to Enable interrupt for NOTRESOLVED event + NOTRESOLVED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x4000f308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for END event + END: u1, + /// Write '1' to Disable interrupt for RESOLVED event + RESOLVED: u1, + /// Write '1' to Disable interrupt for NOTRESOLVED event + NOTRESOLVED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x4000f400 + /// Resolution status + pub const STATUS = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x400); + + /// address: 0x4000f500 + /// Enable AAR + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); + + /// address: 0x4000f504 + /// Number of IRKs + pub const NIRK = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x504); + + /// address: 0x4000f508 + /// Pointer to IRK data structure + pub const IRKPTR = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000f510 + /// Pointer to the resolvable address + pub const ADDRPTR = @intToPtr(*volatile u32, base_address + 0x510); + + /// address: 0x4000f514 + /// Pointer to data area used for temporary storage + pub const SCRATCHPTR = @intToPtr(*volatile u32, base_address + 0x514); + }; + /// Watchdog Timer + pub const WDT = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// Start the watchdog + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40010100 + /// Watchdog timeout + pub const EVENTS_TIMEOUT = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40010304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TIMEOUT event + TIMEOUT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x304); + + /// address: 0x40010308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TIMEOUT event + TIMEOUT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x308); + + /// address: 0x40010400 + /// Run status + pub const RUNSTATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x40010404 + /// Request status + pub const REQSTATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Request status for RR[0] register + RR0: u1, + /// Request status for RR[1] register + RR1: u1, + /// Request status for RR[2] register + RR2: u1, + /// Request status for RR[3] register + RR3: u1, + /// Request status for RR[4] register + RR4: u1, + /// Request status for RR[5] register + RR5: u1, + /// Request status for RR[6] register + RR6: u1, + /// Request status for RR[7] register + RR7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x404); + + /// address: 0x40010504 + /// Counter reload value + pub const CRV = @intToPtr(*volatile u32, base_address + 0x504); + + /// address: 0x40010508 + /// Enable register for reload request registers + pub const RREN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable RR[0] register + RR0: u1, + /// Enable or disable RR[1] register + RR1: u1, + /// Enable or disable RR[2] register + RR2: u1, + /// Enable or disable RR[3] register + RR3: u1, + /// Enable or disable RR[4] register + RR4: u1, + /// Enable or disable RR[5] register + RR5: u1, + /// Enable or disable RR[6] register + RR6: u1, + /// Enable or disable RR[7] register + RR7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x508); + + /// address: 0x4001050c + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Configure the watchdog to either be paused, or kept running, while the CPU is + /// sleeping + SLEEP: u1, + reserved0: u1, + reserved1: u1, + /// Configure the watchdog to either be paused, or kept running, while the CPU is + /// halted by the debugger + HALT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x50c); + + /// address: 0x40010600 + /// Description collection[0]: Reload request 0 + pub const RR = @intToPtr(*volatile [8]u32, base_address + 0x600); + }; + /// Real time counter 1 + pub const RTC1 = struct { + pub const base_address = 0x40011000; + + /// address: 0x40011000 + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40011004 + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40011008 + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4001100c + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40011100 + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40011104 + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40011140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, base_address + 0x140); + + /// address: 0x40011304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TICK event + TICK: u1, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x40011308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TICK event + TICK: u1, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x40011340 + /// Enable or disable event routing + pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable event routing for TICK event + TICK: u1, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x340); + + /// address: 0x40011344 + /// Enable event routing + pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable event routing for TICK event + TICK: u1, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x344); + + /// address: 0x40011348 + /// Disable event routing + pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable event routing for TICK event + TICK: u1, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x348); + + /// address: 0x40011504 + /// Current COUNTER value + pub const COUNTER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x504); + + /// address: 0x40011508 + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x508); + + /// address: 0x40011540 + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct{ + /// Compare value + COMPARE: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x540); + }; + /// Quadrature Decoder + pub const QDEC = struct { + pub const base_address = 0x40012000; + + /// address: 0x40012000 + /// Task starting the quadrature decoder + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40012004 + /// Task stopping the quadrature decoder + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40012008 + /// Read and clear ACC and ACCDBL + pub const TASKS_READCLRACC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4001200c + /// Read and clear ACC + pub const TASKS_RDCLRACC = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40012010 + /// Read and clear ACCDBL + pub const TASKS_RDCLRDBL = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40012100 + /// Event being generated for every new sample value written to the SAMPLE register + pub const EVENTS_SAMPLERDY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40012104 + /// Non-null report ready + pub const EVENTS_REPORTRDY = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40012108 + /// ACC or ACCDBL register overflow + pub const EVENTS_ACCOF = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4001210c + /// Double displacement(s) detected + pub const EVENTS_DBLRDY = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40012110 + /// QDEC has been stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40012200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between REPORTRDY event and READCLRACC task + REPORTRDY_READCLRACC: u1, + /// Shortcut between SAMPLERDY event and STOP task + SAMPLERDY_STOP: u1, + /// Shortcut between REPORTRDY event and RDCLRACC task + REPORTRDY_RDCLRACC: u1, + /// Shortcut between REPORTRDY event and STOP task + REPORTRDY_STOP: u1, + /// Shortcut between DBLRDY event and RDCLRDBL task + DBLRDY_RDCLRDBL: u1, + /// Shortcut between DBLRDY event and STOP task + DBLRDY_STOP: u1, + /// Shortcut between SAMPLERDY event and READCLRACC task + SAMPLERDY_READCLRACC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x200); + + /// address: 0x40012304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for SAMPLERDY event + SAMPLERDY: u1, + /// Write '1' to Enable interrupt for REPORTRDY event + REPORTRDY: u1, + /// Write '1' to Enable interrupt for ACCOF event + ACCOF: u1, + /// Write '1' to Enable interrupt for DBLRDY event + DBLRDY: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x304); + + /// address: 0x40012308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for SAMPLERDY event + SAMPLERDY: u1, + /// Write '1' to Disable interrupt for REPORTRDY event + REPORTRDY: u1, + /// Write '1' to Disable interrupt for ACCOF event + ACCOF: u1, + /// Write '1' to Disable interrupt for DBLRDY event + DBLRDY: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x308); + + /// address: 0x40012500 + /// Enable the quadrature decoder + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x40012504 + /// LED output pin polarity + pub const LEDPOL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x504); -/// Random Number Generator -pub const RNG = extern struct { - pub const Address: u32 = 0x4000d000; - - /// Task starting the random number generator - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Task stopping the random number generator - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Event being generated for every new random number written to the VALUE - /// register - pub const EVENTS_VALRDY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between VALRDY event and STOP task - VALRDY_STOP: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for VALRDY event - VALRDY: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for VALRDY event - VALRDY: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000504, 32, packed struct { - /// Bias correction - DERCEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Output random number - pub const VALUE = mmio(Address + 0x00000508, 32, packed struct { - /// Generated random number - VALUE: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + /// address: 0x40012508 + /// Sample period + pub const SAMPLEPER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x508); -/// AES ECB Mode Encryption -pub const ECB = extern struct { - pub const Address: u32 = 0x4000e000; - - /// Start ECB block encrypt - pub const TASKS_STARTECB = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Abort a possible executing ECB operation - pub const TASKS_STOPECB = @intToPtr(*volatile u32, Address + 0x00000004); - - /// ECB block encrypt complete - pub const EVENTS_ENDECB = @intToPtr(*volatile u32, Address + 0x00000100); - - /// ECB block encrypt aborted because of a STOPECB task or due to an error - pub const EVENTS_ERRORECB = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for ENDECB event - ENDECB: u1 = 0, - /// Write '1' to Enable interrupt for ERRORECB event - ERRORECB: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for ENDECB event - ENDECB: u1 = 0, - /// Write '1' to Disable interrupt for ERRORECB event - ERRORECB: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// ECB block encrypt memory pointers - pub const ECBDATAPTR = @intToPtr(*volatile u32, Address + 0x00000504); -}; + /// address: 0x4001250c + /// Motion sample value + pub const SAMPLE = @intToPtr(*volatile u32, base_address + 0x50c); -/// AES CCM Mode Encryption -pub const CCM = extern struct { - pub const Address: u32 = 0x4000f000; - - /// Start generation of key-stream. This operation will stop by itself when - /// completed. - pub const TASKS_KSGEN = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Start encryption/decryption. This operation will stop by itself when - /// completed. - pub const TASKS_CRYPT = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Stop encryption/decryption - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Key-stream generation complete - pub const EVENTS_ENDKSGEN = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Encrypt/decrypt complete - pub const EVENTS_ENDCRYPT = @intToPtr(*volatile u32, Address + 0x00000104); - - /// CCM error event - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between ENDKSGEN event and CRYPT task - ENDKSGEN_CRYPT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for ENDKSGEN event - ENDKSGEN: u1 = 0, - /// Write '1' to Enable interrupt for ENDCRYPT event - ENDCRYPT: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for ENDKSGEN event - ENDKSGEN: u1 = 0, - /// Write '1' to Disable interrupt for ENDCRYPT event - ENDCRYPT: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// MIC check result - pub const MICSTATUS = mmio(Address + 0x00000400, 32, packed struct { - /// The result of the MIC check performed during the previous decryption - /// operation - MICSTATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable CCM - ENABLE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Operation mode - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// The mode of operation to be used - MODE: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Data rate that the CCM shall run in synch with - DATARATE: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - /// Packet length configuration - LENGTH: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pointer to data structure holding AES key and NONCE vector - pub const CNFPTR = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Input pointer - pub const INPTR = @intToPtr(*volatile u32, Address + 0x0000050c); - - /// Output pointer - pub const OUTPTR = @intToPtr(*volatile u32, Address + 0x00000510); - - /// Pointer to data area used for temporary storage - pub const SCRATCHPTR = @intToPtr(*volatile u32, Address + 0x00000514); -}; + /// address: 0x40012510 + /// Number of samples to be taken before REPORTRDY and DBLRDY events can be + /// generated + pub const REPORTPER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); -/// Accelerated Address Resolver -pub const AAR = extern struct { - pub const Address: u32 = 0x4000f000; - - /// Start resolving addresses based on IRKs specified in the IRK data structure - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop resolving addresses - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Address resolution procedure complete - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Address resolved - pub const EVENTS_RESOLVED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Address not resolved - pub const EVENTS_NOTRESOLVED = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - /// Write '1' to Enable interrupt for RESOLVED event - RESOLVED: u1 = 0, - /// Write '1' to Enable interrupt for NOTRESOLVED event - NOTRESOLVED: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - /// Write '1' to Disable interrupt for RESOLVED event - RESOLVED: u1 = 0, - /// Write '1' to Disable interrupt for NOTRESOLVED event - NOTRESOLVED: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Resolution status - pub const STATUS = mmio(Address + 0x00000400, 32, packed struct { - /// The IRK that was used last time an address was resolved - STATUS: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable AAR - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable AAR - ENABLE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of IRKs - pub const NIRK = mmio(Address + 0x00000504, 32, packed struct { - /// Number of Identity root keys available in the IRK data structure - NIRK: u5 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pointer to IRK data structure - pub const IRKPTR = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Pointer to the resolvable address - pub const ADDRPTR = @intToPtr(*volatile u32, Address + 0x00000510); - - /// Pointer to data area used for temporary storage - pub const SCRATCHPTR = @intToPtr(*volatile u32, Address + 0x00000514); -}; + /// address: 0x40012514 + /// Register accumulating the valid transitions + pub const ACC = @intToPtr(*volatile u32, base_address + 0x514); -/// Watchdog Timer -pub const WDT = extern struct { - pub const Address: u32 = 0x40010000; - - /// Start the watchdog - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Watchdog timeout - pub const EVENTS_TIMEOUT = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TIMEOUT event - TIMEOUT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TIMEOUT event - TIMEOUT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Run status - pub const RUNSTATUS = mmio(Address + 0x00000400, 32, packed struct { - /// Indicates whether or not the watchdog is running - RUNSTATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Request status - pub const REQSTATUS = mmio(Address + 0x00000404, 32, packed struct { - /// Request status for RR[0] register - RR0: u1 = 0, - /// Request status for RR[1] register - RR1: u1 = 0, - /// Request status for RR[2] register - RR2: u1 = 0, - /// Request status for RR[3] register - RR3: u1 = 0, - /// Request status for RR[4] register - RR4: u1 = 0, - /// Request status for RR[5] register - RR5: u1 = 0, - /// Request status for RR[6] register - RR6: u1 = 0, - /// Request status for RR[7] register - RR7: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Counter reload value - pub const CRV = @intToPtr(*volatile u32, Address + 0x00000504); - - /// Enable register for reload request registers - pub const RREN = mmio(Address + 0x00000508, 32, packed struct { - /// Enable or disable RR[0] register - RR0: u1 = 0, - /// Enable or disable RR[1] register - RR1: u1 = 0, - /// Enable or disable RR[2] register - RR2: u1 = 0, - /// Enable or disable RR[3] register - RR3: u1 = 0, - /// Enable or disable RR[4] register - RR4: u1 = 0, - /// Enable or disable RR[5] register - RR5: u1 = 0, - /// Enable or disable RR[6] register - RR6: u1 = 0, - /// Enable or disable RR[7] register - RR7: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x0000050c, 32, packed struct { - /// Configure the watchdog to either be paused, or kept running, while the CPU - /// is sleeping - SLEEP: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Configure the watchdog to either be paused, or kept running, while the CPU - /// is halted by the debugger - HALT: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Reload request 0 - pub const RR = @intToPtr(*volatile [8]u32, Address + 0x00000600); -}; - -/// Real time counter 1 -pub const RTC1 = extern struct { - pub const Address: u32 = 0x40011000; - - /// Start RTC COUNTER - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop RTC COUNTER - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Clear RTC COUNTER - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Set COUNTER to 0xFFFFF0 - pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Event on COUNTER increment - pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Event on COUNTER overflow - pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Enable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Disable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable event routing - pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { - /// Enable or disable event routing for TICK event - TICK: u1 = 0, - /// Enable or disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Enable or disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Enable or disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Enable or disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable event routing - pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { - /// Write '1' to Enable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Enable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable event routing - pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { - /// Write '1' to Disable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current COUNTER value - pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { - /// Counter value - COUNTER: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written - /// when RTC is stopped - pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { - /// Prescaler value - PRESCALER: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); - /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { - /// Compare value - COMPARE: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000540); -}; + /// address: 0x40012518 + /// Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + pub const ACCREAD = @intToPtr(*volatile u32, base_address + 0x518); -/// Quadrature Decoder -pub const QDEC = extern struct { - pub const Address: u32 = 0x40012000; - - /// Task starting the quadrature decoder - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Task stopping the quadrature decoder - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Read and clear ACC and ACCDBL - pub const TASKS_READCLRACC = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Read and clear ACC - pub const TASKS_RDCLRACC = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Read and clear ACCDBL - pub const TASKS_RDCLRDBL = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Event being generated for every new sample value written to the SAMPLE - /// register - pub const EVENTS_SAMPLERDY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Non-null report ready - pub const EVENTS_REPORTRDY = @intToPtr(*volatile u32, Address + 0x00000104); - - /// ACC or ACCDBL register overflow - pub const EVENTS_ACCOF = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Double displacement(s) detected - pub const EVENTS_DBLRDY = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// QDEC has been stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between REPORTRDY event and READCLRACC task - REPORTRDY_READCLRACC: u1 = 0, - /// Shortcut between SAMPLERDY event and STOP task - SAMPLERDY_STOP: u1 = 0, - /// Shortcut between REPORTRDY event and RDCLRACC task - REPORTRDY_RDCLRACC: u1 = 0, - /// Shortcut between REPORTRDY event and STOP task - REPORTRDY_STOP: u1 = 0, - /// Shortcut between DBLRDY event and RDCLRDBL task - DBLRDY_RDCLRDBL: u1 = 0, - /// Shortcut between DBLRDY event and STOP task - DBLRDY_STOP: u1 = 0, - /// Shortcut between SAMPLERDY event and READCLRACC task - SAMPLERDY_READCLRACC: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for SAMPLERDY event - SAMPLERDY: u1 = 0, - /// Write '1' to Enable interrupt for REPORTRDY event - REPORTRDY: u1 = 0, - /// Write '1' to Enable interrupt for ACCOF event - ACCOF: u1 = 0, - /// Write '1' to Enable interrupt for DBLRDY event - DBLRDY: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for SAMPLERDY event - SAMPLERDY: u1 = 0, - /// Write '1' to Disable interrupt for REPORTRDY event - REPORTRDY: u1 = 0, - /// Write '1' to Disable interrupt for ACCOF event - ACCOF: u1 = 0, - /// Write '1' to Disable interrupt for DBLRDY event - DBLRDY: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable the quadrature decoder - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable the quadrature decoder - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// LED output pin polarity - pub const LEDPOL = mmio(Address + 0x00000504, 32, packed struct { - /// LED output pin polarity - LEDPOL: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Sample period - pub const SAMPLEPER = mmio(Address + 0x00000508, 32, packed struct { - /// Sample period. The SAMPLE register will be updated for every new sample - SAMPLEPER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Motion sample value - pub const SAMPLE = @intToPtr(*volatile u32, Address + 0x0000050c); - - /// Number of samples to be taken before REPORTRDY and DBLRDY events can be - /// generated - pub const REPORTPER = mmio(Address + 0x00000510, 32, packed struct { - /// Specifies the number of samples to be accumulated in the ACC register before - /// the REPORTRDY and DBLRDY events can be generated - REPORTPER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Register accumulating the valid transitions - pub const ACC = @intToPtr(*volatile u32, Address + 0x00000514); - - /// Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task - pub const ACCREAD = @intToPtr(*volatile u32, Address + 0x00000518); - - /// Enable input debounce filters - pub const DBFEN = mmio(Address + 0x00000528, 32, packed struct { + /// address: 0x40012528 /// Enable input debounce filters - DBFEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Time period the LED is switched ON prior to sampling - pub const LEDPRE = mmio(Address + 0x00000540, 32, packed struct { - /// Period in us the LED is switched on prior to sampling - LEDPRE: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Register accumulating the number of detected double transitions - pub const ACCDBL = mmio(Address + 0x00000544, 32, packed struct { - /// Register accumulating the number of detected double or illegal transitions. - /// ( SAMPLE = 2 ). - ACCDBL: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task - pub const ACCDBLREAD = mmio(Address + 0x00000548, 32, packed struct { - /// Snapshot of the ACCDBL register. This field is updated when the READCLRACC - /// or RDCLRDBL task is triggered. - ACCDBLREAD: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for LED signal - pub const LED = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for A signal - pub const A = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for B signal - pub const B = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); + pub const DBFEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x528); + + /// address: 0x40012540 + /// Time period the LED is switched ON prior to sampling + pub const LEDPRE = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x540); + + /// address: 0x40012544 + /// Register accumulating the number of detected double transitions + pub const ACCDBL = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x544); + + /// address: 0x40012548 + /// Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + pub const ACCDBLREAD = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x548); + + pub const PSEL = struct { + + /// address: 0x40012000 + /// Pin select for LED signal + pub const LED = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40012004 + /// Pin select for A signal + pub const A = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + + /// address: 0x40012008 + /// Pin select for B signal + pub const B = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x8); + }; }; -}; + /// Comparator + pub const COMP = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// Start comparator + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40013004 + /// Stop comparator + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40013008 + /// Sample comparator value + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40013100 + /// COMP is ready and output is valid + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40013104 + /// Downward crossing + pub const EVENTS_DOWN = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40013108 + /// Upward crossing + pub const EVENTS_UP = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4001310c + /// Downward or upward crossing + pub const EVENTS_CROSS = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40013200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between READY event and SAMPLE task + READY_SAMPLE: u1, + /// Shortcut between READY event and STOP task + READY_STOP: u1, + /// Shortcut between DOWN event and STOP task + DOWN_STOP: u1, + /// Shortcut between UP event and STOP task + UP_STOP: u1, + /// Shortcut between CROSS event and STOP task + CROSS_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x40013300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for READY event + READY: u1, + /// Enable or disable interrupt for DOWN event + DOWN: u1, + /// Enable or disable interrupt for UP event + UP: u1, + /// Enable or disable interrupt for CROSS event + CROSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x300); + + /// address: 0x40013304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for READY event + READY: u1, + /// Write '1' to Enable interrupt for DOWN event + DOWN: u1, + /// Write '1' to Enable interrupt for UP event + UP: u1, + /// Write '1' to Enable interrupt for CROSS event + CROSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x304); + + /// address: 0x40013308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for READY event + READY: u1, + /// Write '1' to Disable interrupt for DOWN event + DOWN: u1, + /// Write '1' to Disable interrupt for UP event + UP: u1, + /// Write '1' to Disable interrupt for CROSS event + CROSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x308); + + /// address: 0x40013400 + /// Compare result + pub const RESULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x40013500 + /// COMP enable + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); + + /// address: 0x40013504 + /// Pin select + pub const PSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x504); + + /// address: 0x40013508 + /// Reference source select for single-ended mode + pub const REFSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x508); + + /// address: 0x4001350c + /// External reference select + pub const EXTREFSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); + + /// address: 0x40013530 + /// Threshold configuration for hysteresis unit + pub const TH = @intToPtr(*volatile Mmio(32, packed struct{ + /// VDOWN = (THDOWN+1)/64*VREF + THDOWN: u6, + reserved0: u1, + reserved1: u1, + /// VUP = (THUP+1)/64*VREF + THUP: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x530); + + /// address: 0x40013534 + /// Mode configuration + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Speed and power modes + SP: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Main operation modes + MAIN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x534); + + /// address: 0x40013538 + /// Comparator hysteresis enable + pub const HYST = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x538); -/// Comparator -pub const COMP = extern struct { - pub const Address: u32 = 0x40013000; - - /// Start comparator - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop comparator - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Sample comparator value - pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000008); - - /// COMP is ready and output is valid - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Downward crossing - pub const EVENTS_DOWN = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Upward crossing - pub const EVENTS_UP = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Downward or upward crossing - pub const EVENTS_CROSS = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between READY event and SAMPLE task - READY_SAMPLE: u1 = 0, - /// Shortcut between READY event and STOP task - READY_STOP: u1 = 0, - /// Shortcut between DOWN event and STOP task - DOWN_STOP: u1 = 0, - /// Shortcut between UP event and STOP task - UP_STOP: u1 = 0, - /// Shortcut between CROSS event and STOP task - CROSS_STOP: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for READY event - READY: u1 = 0, - /// Enable or disable interrupt for DOWN event - DOWN: u1 = 0, - /// Enable or disable interrupt for UP event - UP: u1 = 0, - /// Enable or disable interrupt for CROSS event - CROSS: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Enable interrupt for DOWN event - DOWN: u1 = 0, - /// Write '1' to Enable interrupt for UP event - UP: u1 = 0, - /// Write '1' to Enable interrupt for CROSS event - CROSS: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Disable interrupt for DOWN event - DOWN: u1 = 0, - /// Write '1' to Disable interrupt for UP event - UP: u1 = 0, - /// Write '1' to Disable interrupt for CROSS event - CROSS: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Compare result - pub const RESULT = mmio(Address + 0x00000400, 32, packed struct { - /// Result of last compare. Decision point SAMPLE task. - RESULT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// COMP enable - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable COMP - ENABLE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pin select - pub const PSEL = mmio(Address + 0x00000504, 32, packed struct { - /// Analog pin select - PSEL: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reference source select for single-ended mode - pub const REFSEL = mmio(Address + 0x00000508, 32, packed struct { + /// address: 0x4001353c + /// Current source select on analog input + pub const ISOURCE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x53c); + }; + /// Low Power Comparator + pub const LPCOMP = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// Start comparator + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40013004 + /// Stop comparator + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40013008 + /// Sample comparator value + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40013100 + /// LPCOMP is ready and output is valid + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40013104 + /// Downward crossing + pub const EVENTS_DOWN = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40013108 + /// Upward crossing + pub const EVENTS_UP = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4001310c + /// Downward or upward crossing + pub const EVENTS_CROSS = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40013200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between READY event and SAMPLE task + READY_SAMPLE: u1, + /// Shortcut between READY event and STOP task + READY_STOP: u1, + /// Shortcut between DOWN event and STOP task + DOWN_STOP: u1, + /// Shortcut between UP event and STOP task + UP_STOP: u1, + /// Shortcut between CROSS event and STOP task + CROSS_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x40013304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for READY event + READY: u1, + /// Write '1' to Enable interrupt for DOWN event + DOWN: u1, + /// Write '1' to Enable interrupt for UP event + UP: u1, + /// Write '1' to Enable interrupt for CROSS event + CROSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x304); + + /// address: 0x40013308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for READY event + READY: u1, + /// Write '1' to Disable interrupt for DOWN event + DOWN: u1, + /// Write '1' to Disable interrupt for UP event + UP: u1, + /// Write '1' to Disable interrupt for CROSS event + CROSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x308); + + /// address: 0x40013400 + /// Compare result + pub const RESULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x40013500 + /// Enable LPCOMP + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); + + /// address: 0x40013504 + /// Input pin select + pub const PSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x504); + + /// address: 0x40013508 /// Reference select - REFSEL: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External reference select - pub const EXTREFSEL = mmio(Address + 0x0000050c, 32, packed struct { - /// External analog reference select - EXTREFSEL: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Threshold configuration for hysteresis unit - pub const TH = mmio(Address + 0x00000530, 32, packed struct { - /// VDOWN = (THDOWN+1)/64*VREF - THDOWN: u6 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// VUP = (THUP+1)/64*VREF - THUP: u6 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Mode configuration - pub const MODE = mmio(Address + 0x00000534, 32, packed struct { - /// Speed and power modes - SP: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Main operation modes - MAIN: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Comparator hysteresis enable - pub const HYST = mmio(Address + 0x00000538, 32, packed struct { - /// Comparator hysteresis - HYST: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current source select on analog input - pub const ISOURCE = mmio(Address + 0x0000053c, 32, packed struct { - /// Comparator hysteresis - ISOURCE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const REFSEL = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x508); -/// Low Power Comparator -pub const LPCOMP = extern struct { - pub const Address: u32 = 0x40013000; - - /// Start comparator - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop comparator - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Sample comparator value - pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000008); - - /// LPCOMP is ready and output is valid - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Downward crossing - pub const EVENTS_DOWN = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Upward crossing - pub const EVENTS_UP = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Downward or upward crossing - pub const EVENTS_CROSS = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between READY event and SAMPLE task - READY_SAMPLE: u1 = 0, - /// Shortcut between READY event and STOP task - READY_STOP: u1 = 0, - /// Shortcut between DOWN event and STOP task - DOWN_STOP: u1 = 0, - /// Shortcut between UP event and STOP task - UP_STOP: u1 = 0, - /// Shortcut between CROSS event and STOP task - CROSS_STOP: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Enable interrupt for DOWN event - DOWN: u1 = 0, - /// Write '1' to Enable interrupt for UP event - UP: u1 = 0, - /// Write '1' to Enable interrupt for CROSS event - CROSS: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Disable interrupt for DOWN event - DOWN: u1 = 0, - /// Write '1' to Disable interrupt for UP event - UP: u1 = 0, - /// Write '1' to Disable interrupt for CROSS event - CROSS: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Compare result - pub const RESULT = mmio(Address + 0x00000400, 32, packed struct { - /// Result of last compare. Decision point SAMPLE task. - RESULT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable LPCOMP - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable LPCOMP - ENABLE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Input pin select - pub const PSEL = mmio(Address + 0x00000504, 32, packed struct { - /// Analog pin select - PSEL: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reference select - pub const REFSEL = mmio(Address + 0x00000508, 32, packed struct { - /// Reference select - REFSEL: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External reference select - pub const EXTREFSEL = mmio(Address + 0x0000050c, 32, packed struct { - /// External analog reference select - EXTREFSEL: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog detect configuration - pub const ANADETECT = mmio(Address + 0x00000520, 32, packed struct { - /// Analog detect configuration - ANADETECT: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Comparator hysteresis enable - pub const HYST = mmio(Address + 0x00000538, 32, packed struct { - /// Comparator hysteresis enable - HYST: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + /// address: 0x4001350c + /// External reference select + pub const EXTREFSEL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x50c); -/// Software interrupt 0 -pub const SWI0 = extern struct { - pub const Address: u32 = 0x40014000; + /// address: 0x40013520 + /// Analog detect configuration + pub const ANADETECT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x520); - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + /// address: 0x40013538 + /// Comparator hysteresis enable + pub const HYST = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x538); + }; + /// Software interrupt 0 + pub const SWI0 = struct { + pub const base_address = 0x40014000; -/// Event Generator Unit 0 -pub const EGU0 = extern struct { - pub const Address: u32 = 0x40014000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x40014000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 0 + pub const EGU0 = struct { + pub const base_address = 0x40014000; + + /// address: 0x40014000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40014100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40014300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40014304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40014308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Software interrupt 1 + pub const SWI1 = struct { + pub const base_address = 0x40015000; -/// Software interrupt 1 -pub const SWI1 = extern struct { - pub const Address: u32 = 0x40015000; + /// address: 0x40015000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 1 + pub const EGU1 = struct { + pub const base_address = 0x40015000; + + /// address: 0x40015000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40015100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40015300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40015304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40015308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Software interrupt 2 + pub const SWI2 = struct { + pub const base_address = 0x40016000; - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + /// address: 0x40016000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 2 + pub const EGU2 = struct { + pub const base_address = 0x40016000; + + /// address: 0x40016000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40016100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40016300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40016304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40016308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Software interrupt 3 + pub const SWI3 = struct { + pub const base_address = 0x40017000; -/// Event Generator Unit 1 -pub const EGU1 = extern struct { - pub const Address: u32 = 0x40015000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x40017000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 3 + pub const EGU3 = struct { + pub const base_address = 0x40017000; + + /// address: 0x40017000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40017100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40017300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40017304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40017308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Software interrupt 4 + pub const SWI4 = struct { + pub const base_address = 0x40018000; -/// Software interrupt 2 -pub const SWI2 = extern struct { - pub const Address: u32 = 0x40016000; + /// address: 0x40018000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 4 + pub const EGU4 = struct { + pub const base_address = 0x40018000; + + /// address: 0x40018000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40018100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40018300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40018304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40018308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Software interrupt 5 + pub const SWI5 = struct { + pub const base_address = 0x40019000; - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + /// address: 0x40019000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 5 + pub const EGU5 = struct { + pub const base_address = 0x40019000; + + /// address: 0x40019000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40019100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40019300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40019304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40019308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Timer/Counter 3 + pub const TIMER3 = struct { + pub const base_address = 0x4001a000; + + /// address: 0x4001a000 + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4001a004 + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4001a008 + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4001a00c + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4001a010 + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x4001a040 + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); + + /// address: 0x4001a140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); + + /// address: 0x4001a200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1, + reserved0: u1, + reserved1: u1, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x4001a304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x4001a308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x4001a504 + /// Timer mode selection + pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); + + /// address: 0x4001a508 + /// Configure the number of bits used by the TIMER + pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); + + /// address: 0x4001a510 + /// Timer prescaler register + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x4001a540 + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); + }; + /// Timer/Counter 4 + pub const TIMER4 = struct { + pub const base_address = 0x4001b000; + + /// address: 0x4001b000 + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4001b004 + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4001b008 + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4001b00c + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4001b010 + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x4001b040 + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); + + /// address: 0x4001b140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); + + /// address: 0x4001b200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1, + reserved0: u1, + reserved1: u1, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x4001b304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x4001b308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x4001b504 + /// Timer mode selection + pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); + + /// address: 0x4001b508 + /// Configure the number of bits used by the TIMER + pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); + + /// address: 0x4001b510 + /// Timer prescaler register + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x4001b540 + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); + }; + /// Pulse Width Modulation Unit 0 + pub const PWM0 = struct { + pub const base_address = 0x4001c000; + + /// address: 0x4001c004 + /// Stops PWM pulse generation on all channels at the end of current PWM period, and + /// stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4001c008 + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, base_address + 0x8); + + /// address: 0x4001c010 + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x4001c104 + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4001c108 + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, base_address + 0x108); + + /// address: 0x4001c110 + /// Description collection[0]: Emitted at end of every sequence 0, when last value + /// from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, base_address + 0x110); + + /// address: 0x4001c118 + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x4001c11c + /// Concatenated sequences have been played the amount of times defined in LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x4001c200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x4001c300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x300); + + /// address: 0x4001c304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x304); + + /// address: 0x4001c308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x308); + + /// address: 0x4001c500 + /// PWM module enable register + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x4001c504 + /// Selects operating mode of the wave counter + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Selects up or up and down as wave counter mode + UPDOWN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x504); + + /// address: 0x4001c508 + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x508); + + /// address: 0x4001c50c + /// Configuration for PWM_CLK + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); + + /// address: 0x4001c510 + /// Configuration of the decoder + pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Selects source for advancing the active sequence + MODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x510); + + /// address: 0x4001c514 + /// Amount of playback of a loop + pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct{ + /// Amount of playback of pattern cycles + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x514); + + pub const SEQ = @ptrCast(*volatile [2]packed struct { + /// Description cluster[0]: Beginning address in Data RAM of this sequence + PTR: u32, + + /// Description cluster[0]: Amount of values (duty cycles) in this sequence + CNT: MmioInt(32, u15), + + /// Description cluster[0]: Amount of additional PWM periods between samples loaded + /// into compare register + REFRESH: Mmio(32, packed struct{ + /// Amount of additional PWM periods between samples loaded into compare register + /// (load every REFRESH.CNT+1 PWM periods) + CNT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), + + /// Description cluster[0]: Time added after the sequence + ENDDELAY: Mmio(32, packed struct{ + /// Time added after the sequence in PWM periods + CNT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), + padding0: u32, + padding1: u32, + padding2: u32, + padding3: u32, + }, base_address + 0x520); + + pub const PSEL = struct { + + /// address: 0x4001c000 + /// Description collection[0]: Output pin select for PWM channel 0 + pub const OUT = @intToPtr(*volatile [4]Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + }; + }; + /// Pulse Density Modulation (Digital Microphone) Interface + pub const PDM = struct { + pub const base_address = 0x4001d000; + + /// address: 0x4001d000 + /// Starts continuous PDM transfer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4001d004 + /// Stops PDM transfer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4001d100 + /// PDM transfer has started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4001d104 + /// PDM transfer has finished + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4001d108 + /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last + /// sample after a STOP task has been received) to Data RAM + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4001d300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for STARTED event + STARTED: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + /// Enable or disable interrupt for END event + END: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x300); + + /// address: 0x4001d304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x4001d308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x4001d500 + /// PDM module enable register + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x4001d504 + /// PDM clock generator control + pub const PDMCLKCTRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// PDM_CLK frequency + FREQ: u32, + }), base_address + 0x504); + + /// address: 0x4001d508 + /// Defines the routing of the connected PDM microphones' signals + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Mono or stereo operation + OPERATION: u1, + /// Defines on which PDM_CLK edge Left (or mono) is sampled + EDGE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x508); + + /// address: 0x4001d518 + /// Left output gain adjustment + pub const GAINL = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x518); + + /// address: 0x4001d51c + /// Right output gain adjustment + pub const GAINR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + pub const PSEL = struct { + + /// address: 0x4001d000 + /// Pin number configuration for PDM CLK signal + pub const CLK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x4001d004 + /// Pin number configuration for PDM DIN signal + pub const DIN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + }; + + pub const SAMPLE = struct { + + /// address: 0x4001d000 + /// RAM address pointer to write samples to with EasyDMA + pub const PTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address to write PDM samples to over DMA + SAMPLEPTR: u32, + }), base_address + 0x0); + + /// address: 0x4001d004 + /// Number of samples to allocate memory for in EasyDMA mode + pub const MAXCNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Length of DMA RAM allocation in number of samples + BUFFSIZE: u15, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + }; + }; + /// Non Volatile Memory Controller + pub const NVMC = struct { + pub const base_address = 0x4001e000; + + /// address: 0x4001e400 + /// Ready flag + pub const READY = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x4001e504 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Program memory access mode. It is strongly recommended to only activate erase + /// and write modes when they are actively used. Enabling write or erase will + /// invalidate the cache and keep it invalidated. + WEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x504); + + /// address: 0x4001e508 + /// Register for erasing a page in Code area + pub const ERASEPAGE = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4001e508 + /// Deprecated register - Register for erasing a page in Code area. Equivalent to + /// ERASEPAGE. + pub const ERASEPCR1 = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4001e50c + /// Register for erasing all non-volatile user memory + pub const ERASEALL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x50c); + + /// address: 0x4001e510 + /// Deprecated register - Register for erasing a page in Code area. Equivalent to + /// ERASEPAGE. + pub const ERASEPCR0 = @intToPtr(*volatile u32, base_address + 0x510); + + /// address: 0x4001e514 + /// Register for erasing User Information Configuration Registers + pub const ERASEUICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x514); + + /// address: 0x4001e540 + /// I-Code cache configuration register. + pub const ICACHECNF = @intToPtr(*volatile Mmio(32, packed struct{ + /// Cache enable + CACHEEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Cache profiling enable + CACHEPROFEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x540); + + /// address: 0x4001e548 + /// I-Code cache hit counter. + pub const IHIT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of cache hits + HITS: u32, + }), base_address + 0x548); + + /// address: 0x4001e54c + /// I-Code cache miss counter. + pub const IMISS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of cache misses + MISSES: u32, + }), base_address + 0x54c); + }; + /// Programmable Peripheral Interconnect + pub const PPI = struct { + pub const base_address = 0x4001f000; + + /// address: 0x4001f500 + /// Channel enable register + pub const CHEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable channel 0 + CH0: u1, + /// Enable or disable channel 1 + CH1: u1, + /// Enable or disable channel 2 + CH2: u1, + /// Enable or disable channel 3 + CH3: u1, + /// Enable or disable channel 4 + CH4: u1, + /// Enable or disable channel 5 + CH5: u1, + /// Enable or disable channel 6 + CH6: u1, + /// Enable or disable channel 7 + CH7: u1, + /// Enable or disable channel 8 + CH8: u1, + /// Enable or disable channel 9 + CH9: u1, + /// Enable or disable channel 10 + CH10: u1, + /// Enable or disable channel 11 + CH11: u1, + /// Enable or disable channel 12 + CH12: u1, + /// Enable or disable channel 13 + CH13: u1, + /// Enable or disable channel 14 + CH14: u1, + /// Enable or disable channel 15 + CH15: u1, + /// Enable or disable channel 16 + CH16: u1, + /// Enable or disable channel 17 + CH17: u1, + /// Enable or disable channel 18 + CH18: u1, + /// Enable or disable channel 19 + CH19: u1, + /// Enable or disable channel 20 + CH20: u1, + /// Enable or disable channel 21 + CH21: u1, + /// Enable or disable channel 22 + CH22: u1, + /// Enable or disable channel 23 + CH23: u1, + /// Enable or disable channel 24 + CH24: u1, + /// Enable or disable channel 25 + CH25: u1, + /// Enable or disable channel 26 + CH26: u1, + /// Enable or disable channel 27 + CH27: u1, + /// Enable or disable channel 28 + CH28: u1, + /// Enable or disable channel 29 + CH29: u1, + /// Enable or disable channel 30 + CH30: u1, + /// Enable or disable channel 31 + CH31: u1, + }), base_address + 0x500); + + /// address: 0x4001f504 + /// Channel enable set register + pub const CHENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 0 enable set register. Writing '0' has no effect + CH0: u1, + /// Channel 1 enable set register. Writing '0' has no effect + CH1: u1, + /// Channel 2 enable set register. Writing '0' has no effect + CH2: u1, + /// Channel 3 enable set register. Writing '0' has no effect + CH3: u1, + /// Channel 4 enable set register. Writing '0' has no effect + CH4: u1, + /// Channel 5 enable set register. Writing '0' has no effect + CH5: u1, + /// Channel 6 enable set register. Writing '0' has no effect + CH6: u1, + /// Channel 7 enable set register. Writing '0' has no effect + CH7: u1, + /// Channel 8 enable set register. Writing '0' has no effect + CH8: u1, + /// Channel 9 enable set register. Writing '0' has no effect + CH9: u1, + /// Channel 10 enable set register. Writing '0' has no effect + CH10: u1, + /// Channel 11 enable set register. Writing '0' has no effect + CH11: u1, + /// Channel 12 enable set register. Writing '0' has no effect + CH12: u1, + /// Channel 13 enable set register. Writing '0' has no effect + CH13: u1, + /// Channel 14 enable set register. Writing '0' has no effect + CH14: u1, + /// Channel 15 enable set register. Writing '0' has no effect + CH15: u1, + /// Channel 16 enable set register. Writing '0' has no effect + CH16: u1, + /// Channel 17 enable set register. Writing '0' has no effect + CH17: u1, + /// Channel 18 enable set register. Writing '0' has no effect + CH18: u1, + /// Channel 19 enable set register. Writing '0' has no effect + CH19: u1, + /// Channel 20 enable set register. Writing '0' has no effect + CH20: u1, + /// Channel 21 enable set register. Writing '0' has no effect + CH21: u1, + /// Channel 22 enable set register. Writing '0' has no effect + CH22: u1, + /// Channel 23 enable set register. Writing '0' has no effect + CH23: u1, + /// Channel 24 enable set register. Writing '0' has no effect + CH24: u1, + /// Channel 25 enable set register. Writing '0' has no effect + CH25: u1, + /// Channel 26 enable set register. Writing '0' has no effect + CH26: u1, + /// Channel 27 enable set register. Writing '0' has no effect + CH27: u1, + /// Channel 28 enable set register. Writing '0' has no effect + CH28: u1, + /// Channel 29 enable set register. Writing '0' has no effect + CH29: u1, + /// Channel 30 enable set register. Writing '0' has no effect + CH30: u1, + /// Channel 31 enable set register. Writing '0' has no effect + CH31: u1, + }), base_address + 0x504); + + /// address: 0x4001f508 + /// Channel enable clear register + pub const CHENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 0 enable clear register. Writing '0' has no effect + CH0: u1, + /// Channel 1 enable clear register. Writing '0' has no effect + CH1: u1, + /// Channel 2 enable clear register. Writing '0' has no effect + CH2: u1, + /// Channel 3 enable clear register. Writing '0' has no effect + CH3: u1, + /// Channel 4 enable clear register. Writing '0' has no effect + CH4: u1, + /// Channel 5 enable clear register. Writing '0' has no effect + CH5: u1, + /// Channel 6 enable clear register. Writing '0' has no effect + CH6: u1, + /// Channel 7 enable clear register. Writing '0' has no effect + CH7: u1, + /// Channel 8 enable clear register. Writing '0' has no effect + CH8: u1, + /// Channel 9 enable clear register. Writing '0' has no effect + CH9: u1, + /// Channel 10 enable clear register. Writing '0' has no effect + CH10: u1, + /// Channel 11 enable clear register. Writing '0' has no effect + CH11: u1, + /// Channel 12 enable clear register. Writing '0' has no effect + CH12: u1, + /// Channel 13 enable clear register. Writing '0' has no effect + CH13: u1, + /// Channel 14 enable clear register. Writing '0' has no effect + CH14: u1, + /// Channel 15 enable clear register. Writing '0' has no effect + CH15: u1, + /// Channel 16 enable clear register. Writing '0' has no effect + CH16: u1, + /// Channel 17 enable clear register. Writing '0' has no effect + CH17: u1, + /// Channel 18 enable clear register. Writing '0' has no effect + CH18: u1, + /// Channel 19 enable clear register. Writing '0' has no effect + CH19: u1, + /// Channel 20 enable clear register. Writing '0' has no effect + CH20: u1, + /// Channel 21 enable clear register. Writing '0' has no effect + CH21: u1, + /// Channel 22 enable clear register. Writing '0' has no effect + CH22: u1, + /// Channel 23 enable clear register. Writing '0' has no effect + CH23: u1, + /// Channel 24 enable clear register. Writing '0' has no effect + CH24: u1, + /// Channel 25 enable clear register. Writing '0' has no effect + CH25: u1, + /// Channel 26 enable clear register. Writing '0' has no effect + CH26: u1, + /// Channel 27 enable clear register. Writing '0' has no effect + CH27: u1, + /// Channel 28 enable clear register. Writing '0' has no effect + CH28: u1, + /// Channel 29 enable clear register. Writing '0' has no effect + CH29: u1, + /// Channel 30 enable clear register. Writing '0' has no effect + CH30: u1, + /// Channel 31 enable clear register. Writing '0' has no effect + CH31: u1, + }), base_address + 0x508); + + /// address: 0x4001f800 + /// Description collection[0]: Channel group 0 + pub const CHG = @intToPtr(*volatile [6]Mmio(32, packed struct{ + /// Include or exclude channel 0 + CH0: u1, + /// Include or exclude channel 1 + CH1: u1, + /// Include or exclude channel 2 + CH2: u1, + /// Include or exclude channel 3 + CH3: u1, + /// Include or exclude channel 4 + CH4: u1, + /// Include or exclude channel 5 + CH5: u1, + /// Include or exclude channel 6 + CH6: u1, + /// Include or exclude channel 7 + CH7: u1, + /// Include or exclude channel 8 + CH8: u1, + /// Include or exclude channel 9 + CH9: u1, + /// Include or exclude channel 10 + CH10: u1, + /// Include or exclude channel 11 + CH11: u1, + /// Include or exclude channel 12 + CH12: u1, + /// Include or exclude channel 13 + CH13: u1, + /// Include or exclude channel 14 + CH14: u1, + /// Include or exclude channel 15 + CH15: u1, + /// Include or exclude channel 16 + CH16: u1, + /// Include or exclude channel 17 + CH17: u1, + /// Include or exclude channel 18 + CH18: u1, + /// Include or exclude channel 19 + CH19: u1, + /// Include or exclude channel 20 + CH20: u1, + /// Include or exclude channel 21 + CH21: u1, + /// Include or exclude channel 22 + CH22: u1, + /// Include or exclude channel 23 + CH23: u1, + /// Include or exclude channel 24 + CH24: u1, + /// Include or exclude channel 25 + CH25: u1, + /// Include or exclude channel 26 + CH26: u1, + /// Include or exclude channel 27 + CH27: u1, + /// Include or exclude channel 28 + CH28: u1, + /// Include or exclude channel 29 + CH29: u1, + /// Include or exclude channel 30 + CH30: u1, + /// Include or exclude channel 31 + CH31: u1, + }), base_address + 0x800); + + /// Channel group tasks + pub const TASKS_CHG = @ptrCast(*volatile [6]packed struct { + /// Description cluster[0]: Enable channel group 0 + EN: u32, + + /// Description cluster[0]: Disable channel group 0 + DIS: u32, + }, base_address + 0x0); + + /// PPI Channel + pub const CH = @ptrCast(*volatile [20]packed struct { + /// Description cluster[0]: Channel 0 event end-point + EEP: u32, + + /// Description cluster[0]: Channel 0 task end-point + TEP: u32, + }, base_address + 0x510); + + /// Fork + pub const FORK = @ptrCast(*volatile [32]packed struct { + /// Description cluster[0]: Channel 0 task end-point + TEP: u32, + }, base_address + 0x910); + }; + /// Memory Watch Unit + pub const MWU = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Enable or disable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Enable or disable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Enable or disable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Enable or disable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Enable or disable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Enable or disable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Enable or disable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable or disable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Enable or disable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Enable or disable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Enable or disable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x300); + + /// address: 0x40020304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Write '1' to Enable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Write '1' to Enable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Write '1' to Enable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Write '1' to Enable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Write '1' to Enable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Write '1' to Enable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Write '1' to Enable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Write '1' to Enable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Write '1' to Enable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Write '1' to Enable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x304); + + /// address: 0x40020308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Write '1' to Disable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Write '1' to Disable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Write '1' to Disable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Write '1' to Disable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Write '1' to Disable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Write '1' to Disable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Write '1' to Disable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Write '1' to Disable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Write '1' to Disable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Write '1' to Disable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x308); + + /// address: 0x40020320 + /// Enable or disable non-maskable interrupt + pub const NMIEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Enable or disable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Enable or disable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Enable or disable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Enable or disable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Enable or disable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Enable or disable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Enable or disable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable or disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Enable or disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Enable or disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Enable or disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x320); + + /// address: 0x40020324 + /// Enable non-maskable interrupt + pub const NMIENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Write '1' to Enable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Write '1' to Enable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Write '1' to Enable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x324); + + /// address: 0x40020328 + /// Disable non-maskable interrupt + pub const NMIENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Write '1' to Disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Write '1' to Disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Write '1' to Disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x328); + + /// address: 0x40020510 + /// Enable/disable regions watch + pub const REGIONEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable/disable write access watch in region[0] + RGN0WA: u1, + /// Enable/disable read access watch in region[0] + RGN0RA: u1, + /// Enable/disable write access watch in region[1] + RGN1WA: u1, + /// Enable/disable read access watch in region[1] + RGN1RA: u1, + /// Enable/disable write access watch in region[2] + RGN2WA: u1, + /// Enable/disable read access watch in region[2] + RGN2RA: u1, + /// Enable/disable write access watch in region[3] + RGN3WA: u1, + /// Enable/disable read access watch in region[3] + RGN3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable/disable write access watch in PREGION[0] + PRGN0WA: u1, + /// Enable/disable read access watch in PREGION[0] + PRGN0RA: u1, + /// Enable/disable write access watch in PREGION[1] + PRGN1WA: u1, + /// Enable/disable read access watch in PREGION[1] + PRGN1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x510); + + /// address: 0x40020514 + /// Enable regions watch + pub const REGIONENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable write access watch in region[0] + RGN0WA: u1, + /// Enable read access watch in region[0] + RGN0RA: u1, + /// Enable write access watch in region[1] + RGN1WA: u1, + /// Enable read access watch in region[1] + RGN1RA: u1, + /// Enable write access watch in region[2] + RGN2WA: u1, + /// Enable read access watch in region[2] + RGN2RA: u1, + /// Enable write access watch in region[3] + RGN3WA: u1, + /// Enable read access watch in region[3] + RGN3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable write access watch in PREGION[0] + PRGN0WA: u1, + /// Enable read access watch in PREGION[0] + PRGN0RA: u1, + /// Enable write access watch in PREGION[1] + PRGN1WA: u1, + /// Enable read access watch in PREGION[1] + PRGN1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x514); + + /// address: 0x40020518 + /// Disable regions watch + pub const REGIONENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Disable write access watch in region[0] + RGN0WA: u1, + /// Disable read access watch in region[0] + RGN0RA: u1, + /// Disable write access watch in region[1] + RGN1WA: u1, + /// Disable read access watch in region[1] + RGN1RA: u1, + /// Disable write access watch in region[2] + RGN2WA: u1, + /// Disable read access watch in region[2] + RGN2RA: u1, + /// Disable write access watch in region[3] + RGN3WA: u1, + /// Disable read access watch in region[3] + RGN3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Disable write access watch in PREGION[0] + PRGN0WA: u1, + /// Disable read access watch in PREGION[0] + PRGN0RA: u1, + /// Disable write access watch in PREGION[1] + PRGN1WA: u1, + /// Disable read access watch in PREGION[1] + PRGN1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x518); + + pub const EVENTS_REGION = @ptrCast(*volatile [4]packed struct { + /// Description cluster[0]: Write access to region 0 detected + WA: u32, + + /// Description cluster[0]: Read access to region 0 detected + RA: u32, + }, base_address + 0x100); + + pub const EVENTS_PREGION = @ptrCast(*volatile [2]packed struct { + /// Description cluster[0]: Write access to peripheral region 0 detected + WA: u32, + + /// Description cluster[0]: Read access to peripheral region 0 detected + RA: u32, + }, base_address + 0x160); + + pub const PERREGION = @ptrCast(*volatile [2]packed struct { + /// Description cluster[0]: Source of event/interrupt in region 0, write access + /// detected while corresponding subregion was enabled for watching + SUBSTATWA: Mmio(32, packed struct{ + /// Subregion 0 in region 0 (write '1' to clear) + SR0: u1, + /// Subregion 1 in region 0 (write '1' to clear) + SR1: u1, + /// Subregion 2 in region 0 (write '1' to clear) + SR2: u1, + /// Subregion 3 in region 0 (write '1' to clear) + SR3: u1, + /// Subregion 4 in region 0 (write '1' to clear) + SR4: u1, + /// Subregion 5 in region 0 (write '1' to clear) + SR5: u1, + /// Subregion 6 in region 0 (write '1' to clear) + SR6: u1, + /// Subregion 7 in region 0 (write '1' to clear) + SR7: u1, + /// Subregion 8 in region 0 (write '1' to clear) + SR8: u1, + /// Subregion 9 in region 0 (write '1' to clear) + SR9: u1, + /// Subregion 10 in region 0 (write '1' to clear) + SR10: u1, + /// Subregion 11 in region 0 (write '1' to clear) + SR11: u1, + /// Subregion 12 in region 0 (write '1' to clear) + SR12: u1, + /// Subregion 13 in region 0 (write '1' to clear) + SR13: u1, + /// Subregion 14 in region 0 (write '1' to clear) + SR14: u1, + /// Subregion 15 in region 0 (write '1' to clear) + SR15: u1, + /// Subregion 16 in region 0 (write '1' to clear) + SR16: u1, + /// Subregion 17 in region 0 (write '1' to clear) + SR17: u1, + /// Subregion 18 in region 0 (write '1' to clear) + SR18: u1, + /// Subregion 19 in region 0 (write '1' to clear) + SR19: u1, + /// Subregion 20 in region 0 (write '1' to clear) + SR20: u1, + /// Subregion 21 in region 0 (write '1' to clear) + SR21: u1, + /// Subregion 22 in region 0 (write '1' to clear) + SR22: u1, + /// Subregion 23 in region 0 (write '1' to clear) + SR23: u1, + /// Subregion 24 in region 0 (write '1' to clear) + SR24: u1, + /// Subregion 25 in region 0 (write '1' to clear) + SR25: u1, + /// Subregion 26 in region 0 (write '1' to clear) + SR26: u1, + /// Subregion 27 in region 0 (write '1' to clear) + SR27: u1, + /// Subregion 28 in region 0 (write '1' to clear) + SR28: u1, + /// Subregion 29 in region 0 (write '1' to clear) + SR29: u1, + /// Subregion 30 in region 0 (write '1' to clear) + SR30: u1, + /// Subregion 31 in region 0 (write '1' to clear) + SR31: u1, + }), + + /// Description cluster[0]: Source of event/interrupt in region 0, read access + /// detected while corresponding subregion was enabled for watching + SUBSTATRA: Mmio(32, packed struct{ + /// Subregion 0 in region 0 (write '1' to clear) + SR0: u1, + /// Subregion 1 in region 0 (write '1' to clear) + SR1: u1, + /// Subregion 2 in region 0 (write '1' to clear) + SR2: u1, + /// Subregion 3 in region 0 (write '1' to clear) + SR3: u1, + /// Subregion 4 in region 0 (write '1' to clear) + SR4: u1, + /// Subregion 5 in region 0 (write '1' to clear) + SR5: u1, + /// Subregion 6 in region 0 (write '1' to clear) + SR6: u1, + /// Subregion 7 in region 0 (write '1' to clear) + SR7: u1, + /// Subregion 8 in region 0 (write '1' to clear) + SR8: u1, + /// Subregion 9 in region 0 (write '1' to clear) + SR9: u1, + /// Subregion 10 in region 0 (write '1' to clear) + SR10: u1, + /// Subregion 11 in region 0 (write '1' to clear) + SR11: u1, + /// Subregion 12 in region 0 (write '1' to clear) + SR12: u1, + /// Subregion 13 in region 0 (write '1' to clear) + SR13: u1, + /// Subregion 14 in region 0 (write '1' to clear) + SR14: u1, + /// Subregion 15 in region 0 (write '1' to clear) + SR15: u1, + /// Subregion 16 in region 0 (write '1' to clear) + SR16: u1, + /// Subregion 17 in region 0 (write '1' to clear) + SR17: u1, + /// Subregion 18 in region 0 (write '1' to clear) + SR18: u1, + /// Subregion 19 in region 0 (write '1' to clear) + SR19: u1, + /// Subregion 20 in region 0 (write '1' to clear) + SR20: u1, + /// Subregion 21 in region 0 (write '1' to clear) + SR21: u1, + /// Subregion 22 in region 0 (write '1' to clear) + SR22: u1, + /// Subregion 23 in region 0 (write '1' to clear) + SR23: u1, + /// Subregion 24 in region 0 (write '1' to clear) + SR24: u1, + /// Subregion 25 in region 0 (write '1' to clear) + SR25: u1, + /// Subregion 26 in region 0 (write '1' to clear) + SR26: u1, + /// Subregion 27 in region 0 (write '1' to clear) + SR27: u1, + /// Subregion 28 in region 0 (write '1' to clear) + SR28: u1, + /// Subregion 29 in region 0 (write '1' to clear) + SR29: u1, + /// Subregion 30 in region 0 (write '1' to clear) + SR30: u1, + /// Subregion 31 in region 0 (write '1' to clear) + SR31: u1, + }), + }, base_address + 0x400); + + pub const REGION = @ptrCast(*volatile [4]packed struct { + /// Description cluster[0]: Start address for region 0 + START: u32, + + /// Description cluster[0]: End address of region 0 + END: u32, + padding0: u32, + padding1: u32, + }, base_address + 0x600); + + pub const PREGION = @ptrCast(*volatile [2]packed struct { + /// Description cluster[0]: Reserved for future use + START: u32, + + /// Description cluster[0]: Reserved for future use + END: u32, + + /// Description cluster[0]: Subregions of region 0 + SUBS: Mmio(32, packed struct{ + /// Include or exclude subregion 0 in region + SR0: u1, + /// Include or exclude subregion 1 in region + SR1: u1, + /// Include or exclude subregion 2 in region + SR2: u1, + /// Include or exclude subregion 3 in region + SR3: u1, + /// Include or exclude subregion 4 in region + SR4: u1, + /// Include or exclude subregion 5 in region + SR5: u1, + /// Include or exclude subregion 6 in region + SR6: u1, + /// Include or exclude subregion 7 in region + SR7: u1, + /// Include or exclude subregion 8 in region + SR8: u1, + /// Include or exclude subregion 9 in region + SR9: u1, + /// Include or exclude subregion 10 in region + SR10: u1, + /// Include or exclude subregion 11 in region + SR11: u1, + /// Include or exclude subregion 12 in region + SR12: u1, + /// Include or exclude subregion 13 in region + SR13: u1, + /// Include or exclude subregion 14 in region + SR14: u1, + /// Include or exclude subregion 15 in region + SR15: u1, + /// Include or exclude subregion 16 in region + SR16: u1, + /// Include or exclude subregion 17 in region + SR17: u1, + /// Include or exclude subregion 18 in region + SR18: u1, + /// Include or exclude subregion 19 in region + SR19: u1, + /// Include or exclude subregion 20 in region + SR20: u1, + /// Include or exclude subregion 21 in region + SR21: u1, + /// Include or exclude subregion 22 in region + SR22: u1, + /// Include or exclude subregion 23 in region + SR23: u1, + /// Include or exclude subregion 24 in region + SR24: u1, + /// Include or exclude subregion 25 in region + SR25: u1, + /// Include or exclude subregion 26 in region + SR26: u1, + /// Include or exclude subregion 27 in region + SR27: u1, + /// Include or exclude subregion 28 in region + SR28: u1, + /// Include or exclude subregion 29 in region + SR29: u1, + /// Include or exclude subregion 30 in region + SR30: u1, + /// Include or exclude subregion 31 in region + SR31: u1, + }), + padding0: u32, + }, base_address + 0x6c0); + }; + /// Pulse Width Modulation Unit 1 + pub const PWM1 = struct { + pub const base_address = 0x40021000; + + /// address: 0x40021004 + /// Stops PWM pulse generation on all channels at the end of current PWM period, and + /// stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40021008 + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, base_address + 0x8); + + /// address: 0x40021010 + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40021104 + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40021108 + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, base_address + 0x108); + + /// address: 0x40021110 + /// Description collection[0]: Emitted at end of every sequence 0, when last value + /// from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, base_address + 0x110); + + /// address: 0x40021118 + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x4002111c + /// Concatenated sequences have been played the amount of times defined in LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40021200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x40021300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x300); + + /// address: 0x40021304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x304); + + /// address: 0x40021308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x308); + + /// address: 0x40021500 + /// PWM module enable register + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x40021504 + /// Selects operating mode of the wave counter + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Selects up or up and down as wave counter mode + UPDOWN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x504); + + /// address: 0x40021508 + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x508); + + /// address: 0x4002150c + /// Configuration for PWM_CLK + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); + + /// address: 0x40021510 + /// Configuration of the decoder + pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Selects source for advancing the active sequence + MODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x510); + + /// address: 0x40021514 + /// Amount of playback of a loop + pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct{ + /// Amount of playback of pattern cycles + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x514); + }; + /// Pulse Width Modulation Unit 2 + pub const PWM2 = struct { + pub const base_address = 0x40022000; + + /// address: 0x40022004 + /// Stops PWM pulse generation on all channels at the end of current PWM period, and + /// stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40022008 + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, base_address + 0x8); + + /// address: 0x40022010 + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40022104 + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40022108 + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, base_address + 0x108); + + /// address: 0x40022110 + /// Description collection[0]: Emitted at end of every sequence 0, when last value + /// from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, base_address + 0x110); + + /// address: 0x40022118 + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x4002211c + /// Concatenated sequences have been played the amount of times defined in LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40022200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x40022300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x300); + + /// address: 0x40022304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x304); + + /// address: 0x40022308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x308); + + /// address: 0x40022500 + /// PWM module enable register + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x40022504 + /// Selects operating mode of the wave counter + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Selects up or up and down as wave counter mode + UPDOWN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x504); + + /// address: 0x40022508 + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x508); + + /// address: 0x4002250c + /// Configuration for PWM_CLK + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); + + /// address: 0x40022510 + /// Configuration of the decoder + pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Selects source for advancing the active sequence + MODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x510); + + /// address: 0x40022514 + /// Amount of playback of a loop + pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct{ + /// Amount of playback of pattern cycles + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x514); + }; + /// Serial Peripheral Interface Master with EasyDMA 2 + pub const SPIM2 = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023010 + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40023014 + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4002301c + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40023020 + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40023104 + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40023110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40023118 + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x40023120 + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x4002314c + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40023200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Shortcut between END event and START task + END_START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x200); + + /// address: 0x40023304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x40023308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x40023500 + /// Enable SPIM + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40023524 + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40023554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x400235c0 + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + }; + /// SPI Slave 2 + pub const SPIS2 = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023024 + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x40023028 + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40023104 + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40023110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40023128 + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x40023200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x200); + + /// address: 0x40023304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x304); + + /// address: 0x40023308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x308); + + /// address: 0x40023400 + /// Semaphore status register + pub const SEMSTAT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x400); + + /// address: 0x40023440 + /// Status from last transaction + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// TX buffer over-read detected, and prevented + OVERREAD: u1, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x440); + + /// address: 0x40023500 + /// Enable SPI slave + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40023554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x4002355c + /// Default character. Character clocked out in case of an ignored transaction. + pub const DEF = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x55c); -/// Event Generator Unit 2 -pub const EGU2 = extern struct { - pub const Address: u32 = 0x40016000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x400235c0 + /// Over-read character + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + }; + /// Serial Peripheral Interface 2 + pub const SPI2 = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023108 + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40023304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x40023308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x40023500 + /// Enable SPI + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40023518 + /// RXD register + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); -/// Software interrupt 3 -pub const SWI3 = extern struct { - pub const Address: u32 = 0x40017000; + /// address: 0x4002351c + /// TXD register + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + /// address: 0x40023524 + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40023554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + }; + /// Real time counter 2 + pub const RTC2 = struct { + pub const base_address = 0x40024000; + + /// address: 0x40024000 + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40024004 + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40024008 + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4002400c + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40024100 + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40024104 + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40024140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, base_address + 0x140); + + /// address: 0x40024304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TICK event + TICK: u1, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x40024308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TICK event + TICK: u1, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x40024340 + /// Enable or disable event routing + pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable event routing for TICK event + TICK: u1, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x340); + + /// address: 0x40024344 + /// Enable event routing + pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable event routing for TICK event + TICK: u1, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x344); + + /// address: 0x40024348 + /// Disable event routing + pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable event routing for TICK event + TICK: u1, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x348); + + /// address: 0x40024504 + /// Current COUNTER value + pub const COUNTER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x504); + + /// address: 0x40024508 + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x508); + + /// address: 0x40024540 + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct{ + /// Compare value + COMPARE: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x540); + }; + /// Inter-IC Sound + pub const I2S = struct { + pub const base_address = 0x40025000; + + /// address: 0x40025000 + /// Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40025004 + /// Stops I2S transfer. Also stops MCK generator. Triggering this task will cause + /// the {event:STOPPED} event to be generated. + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40025104 + /// The RXD.PTR register has been copied to internal double-buffers. When the I2S + /// module is started and RX is enabled, this event will be generated for every + /// RXTXD.MAXCNT words that are received on the SDIN pin. + pub const EVENTS_RXPTRUPD = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40025108 + /// I2S transfer stopped. + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40025114 + /// The TDX.PTR register has been copied to internal double-buffers. When the I2S + /// module is started and TX is enabled, this event will be generated for every + /// RXTXD.MAXCNT words that are sent on the SDOUT pin. + pub const EVENTS_TXPTRUPD = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x40025300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for RXPTRUPD event + RXPTRUPD: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Enable or disable interrupt for TXPTRUPD event + TXPTRUPD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x300); + + /// address: 0x40025304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for RXPTRUPD event + RXPTRUPD: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for TXPTRUPD event + TXPTRUPD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x304); + + /// address: 0x40025308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for RXPTRUPD event + RXPTRUPD: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for TXPTRUPD event + TXPTRUPD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x308); + + /// address: 0x40025500 + /// Enable I2S module. + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + pub const CONFIG = struct { -/// Event Generator Unit 3 -pub const EGU3 = extern struct { - pub const Address: u32 = 0x40017000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x40025000 + /// I2S mode. + pub const MODE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0); -/// Software interrupt 4 -pub const SWI4 = extern struct { - pub const Address: u32 = 0x40018000; + /// address: 0x40025004 + /// Reception (RX) enable. + pub const RXEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4); - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + /// address: 0x40025008 + /// Transmission (TX) enable. + pub const TXEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8); -/// Event Generator Unit 4 -pub const EGU4 = extern struct { - pub const Address: u32 = 0x40018000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x4002500c + /// Master clock generator enable. + pub const MCKEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xc); -/// Software interrupt 5 -pub const SWI5 = extern struct { - pub const Address: u32 = 0x40019000; + /// address: 0x40025010 + /// Master clock generator frequency. + pub const MCKFREQ = @intToPtr(*volatile u32, base_address + 0x10); - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + /// address: 0x40025014 + /// MCK / LRCK ratio. + pub const RATIO = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x14); -/// Event Generator Unit 5 -pub const EGU5 = extern struct { - pub const Address: u32 = 0x40019000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x40025018 + /// Sample width. + pub const SWIDTH = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x18); -/// Timer/Counter 3 -pub const TIMER3 = extern struct { - pub const Address: u32 = 0x4001a000; - - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1 = 0, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1 = 0, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1 = 0, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1 = 0, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1 = 0, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1 = 0, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1 = 0, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1 = 0, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1 = 0, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1 = 0, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer mode selection - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Timer mode - MODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configure the number of bits used by the TIMER - pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { - /// Timer bit width - BITMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer prescaler register - pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { - /// Prescaler value - PRESCALER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); -}; + /// address: 0x4002501c + /// Alignment of sample within a frame. + pub const ALIGN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x1c); -/// Timer/Counter 4 -pub const TIMER4 = extern struct { - pub const Address: u32 = 0x4001b000; - - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1 = 0, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1 = 0, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1 = 0, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1 = 0, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1 = 0, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1 = 0, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1 = 0, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1 = 0, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1 = 0, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1 = 0, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer mode selection - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Timer mode - MODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configure the number of bits used by the TIMER - pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { - /// Timer bit width - BITMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer prescaler register - pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { - /// Prescaler value - PRESCALER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); -}; + /// address: 0x40025020 + /// Frame format. + pub const FORMAT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x20); -/// Pulse Width Modulation Unit 0 -pub const PWM0 = extern struct { - pub const Address: u32 = 0x4001c000; - - /// Stops PWM pulse generation on all channels at the end of current PWM period, - /// and stops sequence playback - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Steps by one value in the current sequence on all enabled channels if - /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not - /// running. - pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Response to STOP task, emitted when PWM pulses are no longer generated - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Emitted at the end of each PWM period - pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); - - /// Concatenated sequences have been played the amount of times defined in - /// LOOP.CNT - pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between SEQEND[0] event and STOP task - SEQEND0_STOP: u1 = 0, - /// Shortcut between SEQEND[1] event and STOP task - SEQEND1_STOP: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[0] task - LOOPSDONE_SEQSTART0: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[1] task - LOOPSDONE_SEQSTART1: u1 = 0, - /// Shortcut between LOOPSDONE event and STOP task - LOOPSDONE_STOP: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Enable or disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Enable or disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Enable or disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Enable or disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Enable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Enable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PWM module enable register - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable PWM module - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Selects operating mode of the wave counter - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Selects up or up and down as wave counter mode - UPDOWN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Value up to which the pulse generator counter counts - pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { - /// Value up to which the pulse generator counter counts. This register is - /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. - COUNTERTOP: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration for PWM_CLK - pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { - /// Pre-scaler of PWM_CLK - PRESCALER: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration of the decoder - pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { - /// How a sequence is read from RAM and spread to the compare register - LOAD: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Selects source for advancing the active sequence - MODE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Amount of playback of a loop - pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { - /// Amount of playback of pattern cycles - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Loads the first PWM value on all enabled channels - /// from sequence 0, and starts playing that sequence at the rate defined in - /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not - /// running. - pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); - /// Description collection[0]: First PWM period started on sequence 0 - pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); - /// Description collection[0]: Emitted at end of every sequence 0, when last - /// value from RAM has been applied to wave counter - pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); - - pub const PSEL = struct { - /// Description collection[0]: Output pin select for PWM channel 0 - pub const OUT = @intToPtr(*volatile [4]MMIO(32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }), Address + 0x00000000); + /// address: 0x40025024 + /// Enable channels. + pub const CHANNELS = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x24); + }; + + pub const RXD = struct { + + /// address: 0x40025000 + /// Receive buffer RAM start address. + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + }; + + pub const TXD = struct { + + /// address: 0x40025000 + /// Transmit buffer RAM start address. + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + }; + + pub const RXTXD = struct { + + /// address: 0x40025000 + /// Size of RXD and TXD buffers. + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x0); + }; + + pub const PSEL = struct { + + /// address: 0x40025000 + /// Pin select for MCK signal. + pub const MCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40025004 + /// Pin select for SCK signal. + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + + /// address: 0x40025008 + /// Pin select for LRCK signal. + pub const LRCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x8); + + /// address: 0x4002500c + /// Pin select for SDIN signal. + pub const SDIN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0xc); + + /// address: 0x40025010 + /// Pin select for SDOUT signal. + pub const SDOUT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x10); + }; }; -}; + /// FPU + pub const FPU = struct { + pub const base_address = 0x40026000; -/// Pulse Density Modulation (Digital Microphone) Interface -pub const PDM = extern struct { - pub const Address: u32 = 0x4001d000; - - /// Starts continuous PDM transfer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stops PDM transfer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// PDM transfer has started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000100); - - /// PDM transfer has finished - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last - /// sample after a STOP task has been received) to Data RAM - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for STARTED event - STARTED: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Enable or disable interrupt for END event - END: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PDM module enable register - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable PDM module - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PDM clock generator control - pub const PDMCLKCTRL = mmio(Address + 0x00000504, 32, packed struct { - /// PDM_CLK frequency - FREQ: u32 = 0, - }); - - /// Defines the routing of the connected PDM microphones' signals - pub const MODE = mmio(Address + 0x00000508, 32, packed struct { - /// Mono or stereo operation - OPERATION: u1 = 0, - /// Defines on which PDM_CLK edge Left (or mono) is sampled - EDGE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Left output gain adjustment - pub const GAINL = mmio(Address + 0x00000518, 32, packed struct { - /// Left output gain adjustment, in 0.5 dB steps, around the default module gain - /// (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain - /// adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB - /// gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust - GAINL: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Right output gain adjustment - pub const GAINR = mmio(Address + 0x0000051c, 32, packed struct { - /// Right output gain adjustment, in 0.5 dB steps, around the default module - /// gain (see electrical parameters) - GAINR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin number configuration for PDM CLK signal - pub const CLK = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin number configuration for PDM DIN signal - pub const DIN = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); + /// address: 0x40026000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); }; - - pub const SAMPLE = struct { - - /// RAM address pointer to write samples to with EasyDMA - pub const PTR = mmio(Address + 0x00000000, 32, packed struct { - /// Address to write PDM samples to over DMA - SAMPLEPTR: u32 = 0, - }); - - /// Number of samples to allocate memory for in EasyDMA mode - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { - /// Length of DMA RAM allocation in number of samples - BUFFSIZE: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + /// GPIO Port 1 + pub const P0 = struct { + pub const base_address = 0x50000000; + + /// address: 0x50000504 + /// Write GPIO port + pub const OUT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin 0 + PIN0: u1, + /// Pin 1 + PIN1: u1, + /// Pin 2 + PIN2: u1, + /// Pin 3 + PIN3: u1, + /// Pin 4 + PIN4: u1, + /// Pin 5 + PIN5: u1, + /// Pin 6 + PIN6: u1, + /// Pin 7 + PIN7: u1, + /// Pin 8 + PIN8: u1, + /// Pin 9 + PIN9: u1, + /// Pin 10 + PIN10: u1, + /// Pin 11 + PIN11: u1, + /// Pin 12 + PIN12: u1, + /// Pin 13 + PIN13: u1, + /// Pin 14 + PIN14: u1, + /// Pin 15 + PIN15: u1, + /// Pin 16 + PIN16: u1, + /// Pin 17 + PIN17: u1, + /// Pin 18 + PIN18: u1, + /// Pin 19 + PIN19: u1, + /// Pin 20 + PIN20: u1, + /// Pin 21 + PIN21: u1, + /// Pin 22 + PIN22: u1, + /// Pin 23 + PIN23: u1, + /// Pin 24 + PIN24: u1, + /// Pin 25 + PIN25: u1, + /// Pin 26 + PIN26: u1, + /// Pin 27 + PIN27: u1, + /// Pin 28 + PIN28: u1, + /// Pin 29 + PIN29: u1, + /// Pin 30 + PIN30: u1, + /// Pin 31 + PIN31: u1, + }), base_address + 0x504); + + /// address: 0x50000508 + /// Set individual bits in GPIO port + pub const OUTSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin 0 + PIN0: u1, + /// Pin 1 + PIN1: u1, + /// Pin 2 + PIN2: u1, + /// Pin 3 + PIN3: u1, + /// Pin 4 + PIN4: u1, + /// Pin 5 + PIN5: u1, + /// Pin 6 + PIN6: u1, + /// Pin 7 + PIN7: u1, + /// Pin 8 + PIN8: u1, + /// Pin 9 + PIN9: u1, + /// Pin 10 + PIN10: u1, + /// Pin 11 + PIN11: u1, + /// Pin 12 + PIN12: u1, + /// Pin 13 + PIN13: u1, + /// Pin 14 + PIN14: u1, + /// Pin 15 + PIN15: u1, + /// Pin 16 + PIN16: u1, + /// Pin 17 + PIN17: u1, + /// Pin 18 + PIN18: u1, + /// Pin 19 + PIN19: u1, + /// Pin 20 + PIN20: u1, + /// Pin 21 + PIN21: u1, + /// Pin 22 + PIN22: u1, + /// Pin 23 + PIN23: u1, + /// Pin 24 + PIN24: u1, + /// Pin 25 + PIN25: u1, + /// Pin 26 + PIN26: u1, + /// Pin 27 + PIN27: u1, + /// Pin 28 + PIN28: u1, + /// Pin 29 + PIN29: u1, + /// Pin 30 + PIN30: u1, + /// Pin 31 + PIN31: u1, + }), base_address + 0x508); + + /// address: 0x5000050c + /// Clear individual bits in GPIO port + pub const OUTCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin 0 + PIN0: u1, + /// Pin 1 + PIN1: u1, + /// Pin 2 + PIN2: u1, + /// Pin 3 + PIN3: u1, + /// Pin 4 + PIN4: u1, + /// Pin 5 + PIN5: u1, + /// Pin 6 + PIN6: u1, + /// Pin 7 + PIN7: u1, + /// Pin 8 + PIN8: u1, + /// Pin 9 + PIN9: u1, + /// Pin 10 + PIN10: u1, + /// Pin 11 + PIN11: u1, + /// Pin 12 + PIN12: u1, + /// Pin 13 + PIN13: u1, + /// Pin 14 + PIN14: u1, + /// Pin 15 + PIN15: u1, + /// Pin 16 + PIN16: u1, + /// Pin 17 + PIN17: u1, + /// Pin 18 + PIN18: u1, + /// Pin 19 + PIN19: u1, + /// Pin 20 + PIN20: u1, + /// Pin 21 + PIN21: u1, + /// Pin 22 + PIN22: u1, + /// Pin 23 + PIN23: u1, + /// Pin 24 + PIN24: u1, + /// Pin 25 + PIN25: u1, + /// Pin 26 + PIN26: u1, + /// Pin 27 + PIN27: u1, + /// Pin 28 + PIN28: u1, + /// Pin 29 + PIN29: u1, + /// Pin 30 + PIN30: u1, + /// Pin 31 + PIN31: u1, + }), base_address + 0x50c); + + /// address: 0x50000510 + /// Read GPIO port + pub const IN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin 0 + PIN0: u1, + /// Pin 1 + PIN1: u1, + /// Pin 2 + PIN2: u1, + /// Pin 3 + PIN3: u1, + /// Pin 4 + PIN4: u1, + /// Pin 5 + PIN5: u1, + /// Pin 6 + PIN6: u1, + /// Pin 7 + PIN7: u1, + /// Pin 8 + PIN8: u1, + /// Pin 9 + PIN9: u1, + /// Pin 10 + PIN10: u1, + /// Pin 11 + PIN11: u1, + /// Pin 12 + PIN12: u1, + /// Pin 13 + PIN13: u1, + /// Pin 14 + PIN14: u1, + /// Pin 15 + PIN15: u1, + /// Pin 16 + PIN16: u1, + /// Pin 17 + PIN17: u1, + /// Pin 18 + PIN18: u1, + /// Pin 19 + PIN19: u1, + /// Pin 20 + PIN20: u1, + /// Pin 21 + PIN21: u1, + /// Pin 22 + PIN22: u1, + /// Pin 23 + PIN23: u1, + /// Pin 24 + PIN24: u1, + /// Pin 25 + PIN25: u1, + /// Pin 26 + PIN26: u1, + /// Pin 27 + PIN27: u1, + /// Pin 28 + PIN28: u1, + /// Pin 29 + PIN29: u1, + /// Pin 30 + PIN30: u1, + /// Pin 31 + PIN31: u1, + }), base_address + 0x510); + + /// address: 0x50000514 + /// Direction of GPIO pins + pub const DIR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin 0 + PIN0: u1, + /// Pin 1 + PIN1: u1, + /// Pin 2 + PIN2: u1, + /// Pin 3 + PIN3: u1, + /// Pin 4 + PIN4: u1, + /// Pin 5 + PIN5: u1, + /// Pin 6 + PIN6: u1, + /// Pin 7 + PIN7: u1, + /// Pin 8 + PIN8: u1, + /// Pin 9 + PIN9: u1, + /// Pin 10 + PIN10: u1, + /// Pin 11 + PIN11: u1, + /// Pin 12 + PIN12: u1, + /// Pin 13 + PIN13: u1, + /// Pin 14 + PIN14: u1, + /// Pin 15 + PIN15: u1, + /// Pin 16 + PIN16: u1, + /// Pin 17 + PIN17: u1, + /// Pin 18 + PIN18: u1, + /// Pin 19 + PIN19: u1, + /// Pin 20 + PIN20: u1, + /// Pin 21 + PIN21: u1, + /// Pin 22 + PIN22: u1, + /// Pin 23 + PIN23: u1, + /// Pin 24 + PIN24: u1, + /// Pin 25 + PIN25: u1, + /// Pin 26 + PIN26: u1, + /// Pin 27 + PIN27: u1, + /// Pin 28 + PIN28: u1, + /// Pin 29 + PIN29: u1, + /// Pin 30 + PIN30: u1, + /// Pin 31 + PIN31: u1, + }), base_address + 0x514); + + /// address: 0x50000518 + /// DIR set register + pub const DIRSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set as output pin 0 + PIN0: u1, + /// Set as output pin 1 + PIN1: u1, + /// Set as output pin 2 + PIN2: u1, + /// Set as output pin 3 + PIN3: u1, + /// Set as output pin 4 + PIN4: u1, + /// Set as output pin 5 + PIN5: u1, + /// Set as output pin 6 + PIN6: u1, + /// Set as output pin 7 + PIN7: u1, + /// Set as output pin 8 + PIN8: u1, + /// Set as output pin 9 + PIN9: u1, + /// Set as output pin 10 + PIN10: u1, + /// Set as output pin 11 + PIN11: u1, + /// Set as output pin 12 + PIN12: u1, + /// Set as output pin 13 + PIN13: u1, + /// Set as output pin 14 + PIN14: u1, + /// Set as output pin 15 + PIN15: u1, + /// Set as output pin 16 + PIN16: u1, + /// Set as output pin 17 + PIN17: u1, + /// Set as output pin 18 + PIN18: u1, + /// Set as output pin 19 + PIN19: u1, + /// Set as output pin 20 + PIN20: u1, + /// Set as output pin 21 + PIN21: u1, + /// Set as output pin 22 + PIN22: u1, + /// Set as output pin 23 + PIN23: u1, + /// Set as output pin 24 + PIN24: u1, + /// Set as output pin 25 + PIN25: u1, + /// Set as output pin 26 + PIN26: u1, + /// Set as output pin 27 + PIN27: u1, + /// Set as output pin 28 + PIN28: u1, + /// Set as output pin 29 + PIN29: u1, + /// Set as output pin 30 + PIN30: u1, + /// Set as output pin 31 + PIN31: u1, + }), base_address + 0x518); + + /// address: 0x5000051c + /// DIR clear register + pub const DIRCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set as input pin 0 + PIN0: u1, + /// Set as input pin 1 + PIN1: u1, + /// Set as input pin 2 + PIN2: u1, + /// Set as input pin 3 + PIN3: u1, + /// Set as input pin 4 + PIN4: u1, + /// Set as input pin 5 + PIN5: u1, + /// Set as input pin 6 + PIN6: u1, + /// Set as input pin 7 + PIN7: u1, + /// Set as input pin 8 + PIN8: u1, + /// Set as input pin 9 + PIN9: u1, + /// Set as input pin 10 + PIN10: u1, + /// Set as input pin 11 + PIN11: u1, + /// Set as input pin 12 + PIN12: u1, + /// Set as input pin 13 + PIN13: u1, + /// Set as input pin 14 + PIN14: u1, + /// Set as input pin 15 + PIN15: u1, + /// Set as input pin 16 + PIN16: u1, + /// Set as input pin 17 + PIN17: u1, + /// Set as input pin 18 + PIN18: u1, + /// Set as input pin 19 + PIN19: u1, + /// Set as input pin 20 + PIN20: u1, + /// Set as input pin 21 + PIN21: u1, + /// Set as input pin 22 + PIN22: u1, + /// Set as input pin 23 + PIN23: u1, + /// Set as input pin 24 + PIN24: u1, + /// Set as input pin 25 + PIN25: u1, + /// Set as input pin 26 + PIN26: u1, + /// Set as input pin 27 + PIN27: u1, + /// Set as input pin 28 + PIN28: u1, + /// Set as input pin 29 + PIN29: u1, + /// Set as input pin 30 + PIN30: u1, + /// Set as input pin 31 + PIN31: u1, + }), base_address + 0x51c); + + /// address: 0x50000520 + /// Latch register indicating what GPIO pins that have met the criteria set in the + /// PIN_CNF[n].SENSE registers + pub const LATCH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write + /// '1' to clear. + PIN0: u1, + /// Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write + /// '1' to clear. + PIN1: u1, + /// Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write + /// '1' to clear. + PIN2: u1, + /// Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write + /// '1' to clear. + PIN3: u1, + /// Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write + /// '1' to clear. + PIN4: u1, + /// Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write + /// '1' to clear. + PIN5: u1, + /// Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write + /// '1' to clear. + PIN6: u1, + /// Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write + /// '1' to clear. + PIN7: u1, + /// Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write + /// '1' to clear. + PIN8: u1, + /// Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write + /// '1' to clear. + PIN9: u1, + /// Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write + /// '1' to clear. + PIN10: u1, + /// Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write + /// '1' to clear. + PIN11: u1, + /// Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write + /// '1' to clear. + PIN12: u1, + /// Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write + /// '1' to clear. + PIN13: u1, + /// Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write + /// '1' to clear. + PIN14: u1, + /// Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write + /// '1' to clear. + PIN15: u1, + /// Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write + /// '1' to clear. + PIN16: u1, + /// Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write + /// '1' to clear. + PIN17: u1, + /// Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write + /// '1' to clear. + PIN18: u1, + /// Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write + /// '1' to clear. + PIN19: u1, + /// Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write + /// '1' to clear. + PIN20: u1, + /// Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write + /// '1' to clear. + PIN21: u1, + /// Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write + /// '1' to clear. + PIN22: u1, + /// Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write + /// '1' to clear. + PIN23: u1, + /// Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write + /// '1' to clear. + PIN24: u1, + /// Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write + /// '1' to clear. + PIN25: u1, + /// Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write + /// '1' to clear. + PIN26: u1, + /// Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write + /// '1' to clear. + PIN27: u1, + /// Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write + /// '1' to clear. + PIN28: u1, + /// Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write + /// '1' to clear. + PIN29: u1, + /// Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write + /// '1' to clear. + PIN30: u1, + /// Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write + /// '1' to clear. + PIN31: u1, + }), base_address + 0x520); + + /// address: 0x50000524 + /// Select between default DETECT signal behaviour and LDETECT mode + pub const DETECTMODE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x524); + + /// address: 0x50000700 + /// Description collection[0]: Configuration of GPIO pins + pub const PIN_CNF = @intToPtr(*volatile [32]Mmio(32, packed struct{ + /// Pin direction. Same physical register as DIR register + DIR: u1, + /// Connect or disconnect input buffer + INPUT: u1, + /// Pull configuration + PULL: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Drive configuration + DRIVE: u3, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Pin sensing mechanism + SENSE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x700); }; }; -/// Non Volatile Memory Controller -pub const NVMC = extern struct { - pub const Address: u32 = 0x4001e000; - - /// Ready flag - pub const READY = mmio(Address + 0x00000400, 32, packed struct { - /// NVMC is ready or busy - READY: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000504, 32, packed struct { - /// Program memory access mode. It is strongly recommended to only activate - /// erase and write modes when they are actively used. Enabling write or erase - /// will invalidate the cache and keep it invalidated. - WEN: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Register for erasing a page in Code area - pub const ERASEPAGE = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Deprecated register - Register for erasing a page in Code area. Equivalent - /// to ERASEPAGE. - pub const ERASEPCR1 = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Register for erasing all non-volatile user memory - pub const ERASEALL = mmio(Address + 0x0000050c, 32, packed struct { - /// Erase all non-volatile memory including UICR registers. Note that code erase - /// has to be enabled by CONFIG.EEN before the UICR can be erased. - ERASEALL: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Deprecated register - Register for erasing a page in Code area. Equivalent - /// to ERASEPAGE. - pub const ERASEPCR0 = @intToPtr(*volatile u32, Address + 0x00000510); - - /// Register for erasing User Information Configuration Registers - pub const ERASEUICR = mmio(Address + 0x00000514, 32, packed struct { - /// Register starting erase of all User Information Configuration Registers. - /// Note that code erase has to be enabled by CONFIG.EEN before the UICR can be - /// erased. - ERASEUICR: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I-Code cache configuration register. - pub const ICACHECNF = mmio(Address + 0x00000540, 32, packed struct { - /// Cache enable - CACHEEN: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Cache profiling enable - CACHEPROFEN: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I-Code cache hit counter. - pub const IHIT = mmio(Address + 0x00000548, 32, packed struct { - /// Number of cache hits - HITS: u32 = 0, - }); - - /// I-Code cache miss counter. - pub const IMISS = mmio(Address + 0x0000054c, 32, packed struct { - /// Number of cache misses - MISSES: u32 = 0, - }); -}; - -/// Programmable Peripheral Interconnect -pub const PPI = extern struct { - pub const Address: u32 = 0x4001f000; - - /// Channel enable register - pub const CHEN = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable channel 0 - CH0: u1 = 0, - /// Enable or disable channel 1 - CH1: u1 = 0, - /// Enable or disable channel 2 - CH2: u1 = 0, - /// Enable or disable channel 3 - CH3: u1 = 0, - /// Enable or disable channel 4 - CH4: u1 = 0, - /// Enable or disable channel 5 - CH5: u1 = 0, - /// Enable or disable channel 6 - CH6: u1 = 0, - /// Enable or disable channel 7 - CH7: u1 = 0, - /// Enable or disable channel 8 - CH8: u1 = 0, - /// Enable or disable channel 9 - CH9: u1 = 0, - /// Enable or disable channel 10 - CH10: u1 = 0, - /// Enable or disable channel 11 - CH11: u1 = 0, - /// Enable or disable channel 12 - CH12: u1 = 0, - /// Enable or disable channel 13 - CH13: u1 = 0, - /// Enable or disable channel 14 - CH14: u1 = 0, - /// Enable or disable channel 15 - CH15: u1 = 0, - /// Enable or disable channel 16 - CH16: u1 = 0, - /// Enable or disable channel 17 - CH17: u1 = 0, - /// Enable or disable channel 18 - CH18: u1 = 0, - /// Enable or disable channel 19 - CH19: u1 = 0, - /// Enable or disable channel 20 - CH20: u1 = 0, - /// Enable or disable channel 21 - CH21: u1 = 0, - /// Enable or disable channel 22 - CH22: u1 = 0, - /// Enable or disable channel 23 - CH23: u1 = 0, - /// Enable or disable channel 24 - CH24: u1 = 0, - /// Enable or disable channel 25 - CH25: u1 = 0, - /// Enable or disable channel 26 - CH26: u1 = 0, - /// Enable or disable channel 27 - CH27: u1 = 0, - /// Enable or disable channel 28 - CH28: u1 = 0, - /// Enable or disable channel 29 - CH29: u1 = 0, - /// Enable or disable channel 30 - CH30: u1 = 0, - /// Enable or disable channel 31 - CH31: u1 = 0, - }); - - /// Channel enable set register - pub const CHENSET = mmio(Address + 0x00000504, 32, packed struct { - /// Channel 0 enable set register. Writing '0' has no effect - CH0: u1 = 0, - /// Channel 1 enable set register. Writing '0' has no effect - CH1: u1 = 0, - /// Channel 2 enable set register. Writing '0' has no effect - CH2: u1 = 0, - /// Channel 3 enable set register. Writing '0' has no effect - CH3: u1 = 0, - /// Channel 4 enable set register. Writing '0' has no effect - CH4: u1 = 0, - /// Channel 5 enable set register. Writing '0' has no effect - CH5: u1 = 0, - /// Channel 6 enable set register. Writing '0' has no effect - CH6: u1 = 0, - /// Channel 7 enable set register. Writing '0' has no effect - CH7: u1 = 0, - /// Channel 8 enable set register. Writing '0' has no effect - CH8: u1 = 0, - /// Channel 9 enable set register. Writing '0' has no effect - CH9: u1 = 0, - /// Channel 10 enable set register. Writing '0' has no effect - CH10: u1 = 0, - /// Channel 11 enable set register. Writing '0' has no effect - CH11: u1 = 0, - /// Channel 12 enable set register. Writing '0' has no effect - CH12: u1 = 0, - /// Channel 13 enable set register. Writing '0' has no effect - CH13: u1 = 0, - /// Channel 14 enable set register. Writing '0' has no effect - CH14: u1 = 0, - /// Channel 15 enable set register. Writing '0' has no effect - CH15: u1 = 0, - /// Channel 16 enable set register. Writing '0' has no effect - CH16: u1 = 0, - /// Channel 17 enable set register. Writing '0' has no effect - CH17: u1 = 0, - /// Channel 18 enable set register. Writing '0' has no effect - CH18: u1 = 0, - /// Channel 19 enable set register. Writing '0' has no effect - CH19: u1 = 0, - /// Channel 20 enable set register. Writing '0' has no effect - CH20: u1 = 0, - /// Channel 21 enable set register. Writing '0' has no effect - CH21: u1 = 0, - /// Channel 22 enable set register. Writing '0' has no effect - CH22: u1 = 0, - /// Channel 23 enable set register. Writing '0' has no effect - CH23: u1 = 0, - /// Channel 24 enable set register. Writing '0' has no effect - CH24: u1 = 0, - /// Channel 25 enable set register. Writing '0' has no effect - CH25: u1 = 0, - /// Channel 26 enable set register. Writing '0' has no effect - CH26: u1 = 0, - /// Channel 27 enable set register. Writing '0' has no effect - CH27: u1 = 0, - /// Channel 28 enable set register. Writing '0' has no effect - CH28: u1 = 0, - /// Channel 29 enable set register. Writing '0' has no effect - CH29: u1 = 0, - /// Channel 30 enable set register. Writing '0' has no effect - CH30: u1 = 0, - /// Channel 31 enable set register. Writing '0' has no effect - CH31: u1 = 0, - }); - - /// Channel enable clear register - pub const CHENCLR = mmio(Address + 0x00000508, 32, packed struct { - /// Channel 0 enable clear register. Writing '0' has no effect - CH0: u1 = 0, - /// Channel 1 enable clear register. Writing '0' has no effect - CH1: u1 = 0, - /// Channel 2 enable clear register. Writing '0' has no effect - CH2: u1 = 0, - /// Channel 3 enable clear register. Writing '0' has no effect - CH3: u1 = 0, - /// Channel 4 enable clear register. Writing '0' has no effect - CH4: u1 = 0, - /// Channel 5 enable clear register. Writing '0' has no effect - CH5: u1 = 0, - /// Channel 6 enable clear register. Writing '0' has no effect - CH6: u1 = 0, - /// Channel 7 enable clear register. Writing '0' has no effect - CH7: u1 = 0, - /// Channel 8 enable clear register. Writing '0' has no effect - CH8: u1 = 0, - /// Channel 9 enable clear register. Writing '0' has no effect - CH9: u1 = 0, - /// Channel 10 enable clear register. Writing '0' has no effect - CH10: u1 = 0, - /// Channel 11 enable clear register. Writing '0' has no effect - CH11: u1 = 0, - /// Channel 12 enable clear register. Writing '0' has no effect - CH12: u1 = 0, - /// Channel 13 enable clear register. Writing '0' has no effect - CH13: u1 = 0, - /// Channel 14 enable clear register. Writing '0' has no effect - CH14: u1 = 0, - /// Channel 15 enable clear register. Writing '0' has no effect - CH15: u1 = 0, - /// Channel 16 enable clear register. Writing '0' has no effect - CH16: u1 = 0, - /// Channel 17 enable clear register. Writing '0' has no effect - CH17: u1 = 0, - /// Channel 18 enable clear register. Writing '0' has no effect - CH18: u1 = 0, - /// Channel 19 enable clear register. Writing '0' has no effect - CH19: u1 = 0, - /// Channel 20 enable clear register. Writing '0' has no effect - CH20: u1 = 0, - /// Channel 21 enable clear register. Writing '0' has no effect - CH21: u1 = 0, - /// Channel 22 enable clear register. Writing '0' has no effect - CH22: u1 = 0, - /// Channel 23 enable clear register. Writing '0' has no effect - CH23: u1 = 0, - /// Channel 24 enable clear register. Writing '0' has no effect - CH24: u1 = 0, - /// Channel 25 enable clear register. Writing '0' has no effect - CH25: u1 = 0, - /// Channel 26 enable clear register. Writing '0' has no effect - CH26: u1 = 0, - /// Channel 27 enable clear register. Writing '0' has no effect - CH27: u1 = 0, - /// Channel 28 enable clear register. Writing '0' has no effect - CH28: u1 = 0, - /// Channel 29 enable clear register. Writing '0' has no effect - CH29: u1 = 0, - /// Channel 30 enable clear register. Writing '0' has no effect - CH30: u1 = 0, - /// Channel 31 enable clear register. Writing '0' has no effect - CH31: u1 = 0, - }); - /// Description collection[0]: Channel group 0 - pub const CHG = @intToPtr(*volatile [6]MMIO(32, packed struct { - /// Include or exclude channel 0 - CH0: u1 = 0, - /// Include or exclude channel 1 - CH1: u1 = 0, - /// Include or exclude channel 2 - CH2: u1 = 0, - /// Include or exclude channel 3 - CH3: u1 = 0, - /// Include or exclude channel 4 - CH4: u1 = 0, - /// Include or exclude channel 5 - CH5: u1 = 0, - /// Include or exclude channel 6 - CH6: u1 = 0, - /// Include or exclude channel 7 - CH7: u1 = 0, - /// Include or exclude channel 8 - CH8: u1 = 0, - /// Include or exclude channel 9 - CH9: u1 = 0, - /// Include or exclude channel 10 - CH10: u1 = 0, - /// Include or exclude channel 11 - CH11: u1 = 0, - /// Include or exclude channel 12 - CH12: u1 = 0, - /// Include or exclude channel 13 - CH13: u1 = 0, - /// Include or exclude channel 14 - CH14: u1 = 0, - /// Include or exclude channel 15 - CH15: u1 = 0, - /// Include or exclude channel 16 - CH16: u1 = 0, - /// Include or exclude channel 17 - CH17: u1 = 0, - /// Include or exclude channel 18 - CH18: u1 = 0, - /// Include or exclude channel 19 - CH19: u1 = 0, - /// Include or exclude channel 20 - CH20: u1 = 0, - /// Include or exclude channel 21 - CH21: u1 = 0, - /// Include or exclude channel 22 - CH22: u1 = 0, - /// Include or exclude channel 23 - CH23: u1 = 0, - /// Include or exclude channel 24 - CH24: u1 = 0, - /// Include or exclude channel 25 - CH25: u1 = 0, - /// Include or exclude channel 26 - CH26: u1 = 0, - /// Include or exclude channel 27 - CH27: u1 = 0, - /// Include or exclude channel 28 - CH28: u1 = 0, - /// Include or exclude channel 29 - CH29: u1 = 0, - /// Include or exclude channel 30 - CH30: u1 = 0, - /// Include or exclude channel 31 - CH31: u1 = 0, - }), Address + 0x00000800); -}; +const std = @import("std"); -/// Memory Watch Unit -pub const MWU = extern struct { - pub const Address: u32 = 0x40020000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Enable or disable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Enable or disable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Enable or disable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Enable or disable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Enable or disable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Enable or disable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Enable or disable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Enable or disable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Enable or disable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Enable or disable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Write '1' to Enable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Write '1' to Enable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Write '1' to Enable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Write '1' to Disable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Write '1' to Disable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Write '1' to Disable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable non-maskable interrupt - pub const NMIEN = mmio(Address + 0x00000320, 32, packed struct { - /// Enable or disable non-maskable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Enable or disable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Enable or disable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Enable or disable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable non-maskable interrupt - pub const NMIENSET = mmio(Address + 0x00000324, 32, packed struct { - /// Write '1' to Enable non-maskable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable non-maskable interrupt - pub const NMIENCLR = mmio(Address + 0x00000328, 32, packed struct { - /// Write '1' to Disable non-maskable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable/disable regions watch - pub const REGIONEN = mmio(Address + 0x00000510, 32, packed struct { - /// Enable/disable write access watch in region[0] - RGN0WA: u1 = 0, - /// Enable/disable read access watch in region[0] - RGN0RA: u1 = 0, - /// Enable/disable write access watch in region[1] - RGN1WA: u1 = 0, - /// Enable/disable read access watch in region[1] - RGN1RA: u1 = 0, - /// Enable/disable write access watch in region[2] - RGN2WA: u1 = 0, - /// Enable/disable read access watch in region[2] - RGN2RA: u1 = 0, - /// Enable/disable write access watch in region[3] - RGN3WA: u1 = 0, - /// Enable/disable read access watch in region[3] - RGN3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable/disable write access watch in PREGION[0] - PRGN0WA: u1 = 0, - /// Enable/disable read access watch in PREGION[0] - PRGN0RA: u1 = 0, - /// Enable/disable write access watch in PREGION[1] - PRGN1WA: u1 = 0, - /// Enable/disable read access watch in PREGION[1] - PRGN1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable regions watch - pub const REGIONENSET = mmio(Address + 0x00000514, 32, packed struct { - /// Enable write access watch in region[0] - RGN0WA: u1 = 0, - /// Enable read access watch in region[0] - RGN0RA: u1 = 0, - /// Enable write access watch in region[1] - RGN1WA: u1 = 0, - /// Enable read access watch in region[1] - RGN1RA: u1 = 0, - /// Enable write access watch in region[2] - RGN2WA: u1 = 0, - /// Enable read access watch in region[2] - RGN2RA: u1 = 0, - /// Enable write access watch in region[3] - RGN3WA: u1 = 0, - /// Enable read access watch in region[3] - RGN3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable write access watch in PREGION[0] - PRGN0WA: u1 = 0, - /// Enable read access watch in PREGION[0] - PRGN0RA: u1 = 0, - /// Enable write access watch in PREGION[1] - PRGN1WA: u1 = 0, - /// Enable read access watch in PREGION[1] - PRGN1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable regions watch - pub const REGIONENCLR = mmio(Address + 0x00000518, 32, packed struct { - /// Disable write access watch in region[0] - RGN0WA: u1 = 0, - /// Disable read access watch in region[0] - RGN0RA: u1 = 0, - /// Disable write access watch in region[1] - RGN1WA: u1 = 0, - /// Disable read access watch in region[1] - RGN1RA: u1 = 0, - /// Disable write access watch in region[2] - RGN2WA: u1 = 0, - /// Disable read access watch in region[2] - RGN2RA: u1 = 0, - /// Disable write access watch in region[3] - RGN3WA: u1 = 0, - /// Disable read access watch in region[3] - RGN3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Disable write access watch in PREGION[0] - PRGN0WA: u1 = 0, - /// Disable read access watch in PREGION[0] - PRGN0RA: u1 = 0, - /// Disable write access watch in PREGION[1] - PRGN1WA: u1 = 0, - /// Disable read access watch in PREGION[1] - PRGN1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} -/// Pulse Width Modulation Unit 1 -pub const PWM1 = extern struct { - pub const Address: u32 = 0x40021000; - - /// Stops PWM pulse generation on all channels at the end of current PWM period, - /// and stops sequence playback - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Steps by one value in the current sequence on all enabled channels if - /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not - /// running. - pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Response to STOP task, emitted when PWM pulses are no longer generated - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Emitted at the end of each PWM period - pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); - - /// Concatenated sequences have been played the amount of times defined in - /// LOOP.CNT - pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between SEQEND[0] event and STOP task - SEQEND0_STOP: u1 = 0, - /// Shortcut between SEQEND[1] event and STOP task - SEQEND1_STOP: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[0] task - LOOPSDONE_SEQSTART0: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[1] task - LOOPSDONE_SEQSTART1: u1 = 0, - /// Shortcut between LOOPSDONE event and STOP task - LOOPSDONE_STOP: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Enable or disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Enable or disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Enable or disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Enable or disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Enable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Enable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PWM module enable register - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable PWM module - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Selects operating mode of the wave counter - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Selects up or up and down as wave counter mode - UPDOWN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Value up to which the pulse generator counter counts - pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { - /// Value up to which the pulse generator counter counts. This register is - /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. - COUNTERTOP: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration for PWM_CLK - pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { - /// Pre-scaler of PWM_CLK - PRESCALER: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration of the decoder - pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { - /// How a sequence is read from RAM and spread to the compare register - LOAD: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Selects source for advancing the active sequence - MODE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Amount of playback of a loop - pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { - /// Amount of playback of pattern cycles - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Loads the first PWM value on all enabled channels - /// from sequence 0, and starts playing that sequence at the rate defined in - /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not - /// running. - pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); - /// Description collection[0]: First PWM period started on sequence 0 - pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); - /// Description collection[0]: Emitted at end of every sequence 0, when last - /// value from RAM has been applied to wave counter - pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); -}; +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); -/// Pulse Width Modulation Unit 2 -pub const PWM2 = extern struct { - pub const Address: u32 = 0x40022000; - - /// Stops PWM pulse generation on all channels at the end of current PWM period, - /// and stops sequence playback - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Steps by one value in the current sequence on all enabled channels if - /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not - /// running. - pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Response to STOP task, emitted when PWM pulses are no longer generated - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Emitted at the end of each PWM period - pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); - - /// Concatenated sequences have been played the amount of times defined in - /// LOOP.CNT - pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between SEQEND[0] event and STOP task - SEQEND0_STOP: u1 = 0, - /// Shortcut between SEQEND[1] event and STOP task - SEQEND1_STOP: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[0] task - LOOPSDONE_SEQSTART0: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[1] task - LOOPSDONE_SEQSTART1: u1 = 0, - /// Shortcut between LOOPSDONE event and STOP task - LOOPSDONE_STOP: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Enable or disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Enable or disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Enable or disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Enable or disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Enable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Enable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PWM module enable register - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable PWM module - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Selects operating mode of the wave counter - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Selects up or up and down as wave counter mode - UPDOWN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Value up to which the pulse generator counter counts - pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { - /// Value up to which the pulse generator counter counts. This register is - /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. - COUNTERTOP: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration for PWM_CLK - pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { - /// Pre-scaler of PWM_CLK - PRESCALER: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration of the decoder - pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { - /// How a sequence is read from RAM and spread to the compare register - LOAD: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Selects source for advancing the active sequence - MODE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Amount of playback of a loop - pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { - /// Amount of playback of pattern cycles - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Loads the first PWM value on all enabled channels - /// from sequence 0, and starts playing that sequence at the rate defined in - /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not - /// running. - pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); - /// Description collection[0]: First PWM period started on sequence 0 - pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); - /// Description collection[0]: Emitted at end of every sequence 0, when last - /// value from RAM has been applied to wave counter - pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); -}; + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); -/// Serial Peripheral Interface Master with EasyDMA 2 -pub const SPIM2 = extern struct { - pub const Address: u32 = 0x40023000; - - /// Start SPI transaction - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Stop SPI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend SPI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume SPI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// SPI transaction has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// End of RXD buffer and TXD buffer reached - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); - - /// End of TXD buffer reached - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); - - /// Transaction started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and START task - END_START: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPIM - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPIM - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency. Accuracy depends on the HFCLK source selected. - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character. Character clocked out in case and over-read of the TXD - /// buffer. - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character clocked out in case and over-read of the TXD - /// buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + const IntT = std.meta.Int(.unsigned, size); -/// SPI Slave 2 -pub const SPIS2 = extern struct { - pub const Address: u32 = 0x40023000; - - /// Acquire SPI semaphore - pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); - - /// Release SPI semaphore, enabling the SPI slave to acquire it - pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); - - /// Granted transaction completed - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Semaphore acquired - pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and ACQUIRE task - END_ACQUIRE: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Semaphore status register - pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { - /// Semaphore status - SEMSTAT: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status from last transaction - pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { - /// TX buffer over-read detected, and prevented - OVERREAD: u1 = 0, - /// RX buffer overflow detected, and prevented - OVERFLOW: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI slave - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI slave - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Default character. Character clocked out in case of an ignored transaction. - pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { - /// Default character. Character clocked out in case of an ignored transaction. - DEF: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character clocked out after an over-read of the - /// transmit buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); -/// Serial Peripheral Interface 2 -pub const SPI2 = extern struct { - pub const Address: u32 = 0x40023000; - - /// TXD byte sent and RXD byte received - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { - /// RX data received. Double buffered - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { - /// TX data to send. Double buffered - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + return extern struct { + const Self = @This(); -/// Real time counter 2 -pub const RTC2 = extern struct { - pub const Address: u32 = 0x40024000; - - /// Start RTC COUNTER - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop RTC COUNTER - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Clear RTC COUNTER - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Set COUNTER to 0xFFFFF0 - pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Event on COUNTER increment - pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Event on COUNTER overflow - pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Enable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Disable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable event routing - pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { - /// Enable or disable event routing for TICK event - TICK: u1 = 0, - /// Enable or disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Enable or disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Enable or disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Enable or disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable event routing - pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { - /// Write '1' to Enable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Enable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable event routing - pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { - /// Write '1' to Disable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current COUNTER value - pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { - /// Counter value - COUNTER: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written - /// when RTC is stopped - pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { - /// Prescaler value - PRESCALER: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); - /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { - /// Compare value - COMPARE: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000540); -}; + raw: IntT, -/// Inter-IC Sound -pub const I2S = extern struct { - pub const Address: u32 = 0x40025000; - - /// Starts continuous I2S transfer. Also starts MCK generator when this is - /// enabled. - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stops I2S transfer. Also stops MCK generator. Triggering this task will - /// cause the {event:STOPPED} event to be generated. - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// The RXD.PTR register has been copied to internal double-buffers. When the - /// I2S module is started and RX is enabled, this event will be generated for - /// every RXTXD.MAXCNT words that are received on the SDIN pin. - pub const EVENTS_RXPTRUPD = @intToPtr(*volatile u32, Address + 0x00000104); - - /// I2S transfer stopped. - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000108); - - /// The TDX.PTR register has been copied to internal double-buffers. When the - /// I2S module is started and TX is enabled, this event will be generated for - /// every RXTXD.MAXCNT words that are sent on the SDOUT pin. - pub const EVENTS_TXPTRUPD = @intToPtr(*volatile u32, Address + 0x00000114); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for RXPTRUPD event - RXPTRUPD: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for TXPTRUPD event - TXPTRUPD: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for RXPTRUPD event - RXPTRUPD: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for TXPTRUPD event - TXPTRUPD: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for RXPTRUPD event - RXPTRUPD: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for TXPTRUPD event - TXPTRUPD: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable I2S module. - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable I2S module. - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const CONFIG = struct { - - /// I2S mode. - pub const MODE = mmio(Address + 0x00000000, 32, packed struct { - /// I2S mode. - MODE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reception (RX) enable. - pub const RXEN = mmio(Address + 0x00000004, 32, packed struct { - /// Reception (RX) enable. - RXEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmission (TX) enable. - pub const TXEN = mmio(Address + 0x00000008, 32, packed struct { - /// Transmission (TX) enable. - TXEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Master clock generator enable. - pub const MCKEN = mmio(Address + 0x0000000c, 32, packed struct { - /// Master clock generator enable. - MCKEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Master clock generator frequency. - pub const MCKFREQ = @intToPtr(*volatile u32, Address + 0x00000010); - - /// MCK / LRCK ratio. - pub const RATIO = mmio(Address + 0x00000014, 32, packed struct { - /// MCK / LRCK ratio. - RATIO: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Sample width. - pub const SWIDTH = mmio(Address + 0x00000018, 32, packed struct { - /// Sample width. - SWIDTH: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Alignment of sample within a frame. - pub const ALIGN = mmio(Address + 0x0000001c, 32, packed struct { - /// Alignment of sample within a frame. - ALIGN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Frame format. - pub const FORMAT = mmio(Address + 0x00000020, 32, packed struct { - /// Frame format. - FORMAT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable channels. - pub const CHANNELS = mmio(Address + 0x00000024, 32, packed struct { - /// Enable channels. - CHANNELS: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const underlying_type = PackedT; - pub const RXD = struct { + pub fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } - /// Receive buffer RAM start address. - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); - }; + pub fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } - pub const TXD = struct { + pub fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } - /// Transmit buffer RAM start address. - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + pub fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } }; +} - pub const RXTXD = struct { - - /// Size of RXD and TXD buffers. - pub const MAXCNT = mmio(Address + 0x00000000, 32, packed struct { - /// Size of RXD and TXD buffers in number of 32 bit words. - MAXCNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); - pub const PSEL = struct { - - /// Pin select for MCK signal. - pub const MCK = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for SCK signal. - pub const SCK = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for LRCK signal. - pub const LRCK = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for SDIN signal. - pub const SDIN = mmio(Address + 0x0000000c, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for SDOUT signal. - pub const SDOUT = mmio(Address + 0x00000010, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - }; -}; + raw: std.meta.Int(.unsigned, size), -/// FPU -pub const FPU = extern struct { - pub const Address: u32 = 0x40026000; + pub fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + pub fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); -/// GPIO Port 1 -pub const P0 = extern struct { - pub const Address: u32 = 0x50000000; - - /// Write GPIO port - pub const OUT = mmio(Address + 0x00000504, 32, packed struct { - /// Pin 0 - PIN0: u1 = 0, - /// Pin 1 - PIN1: u1 = 0, - /// Pin 2 - PIN2: u1 = 0, - /// Pin 3 - PIN3: u1 = 0, - /// Pin 4 - PIN4: u1 = 0, - /// Pin 5 - PIN5: u1 = 0, - /// Pin 6 - PIN6: u1 = 0, - /// Pin 7 - PIN7: u1 = 0, - /// Pin 8 - PIN8: u1 = 0, - /// Pin 9 - PIN9: u1 = 0, - /// Pin 10 - PIN10: u1 = 0, - /// Pin 11 - PIN11: u1 = 0, - /// Pin 12 - PIN12: u1 = 0, - /// Pin 13 - PIN13: u1 = 0, - /// Pin 14 - PIN14: u1 = 0, - /// Pin 15 - PIN15: u1 = 0, - /// Pin 16 - PIN16: u1 = 0, - /// Pin 17 - PIN17: u1 = 0, - /// Pin 18 - PIN18: u1 = 0, - /// Pin 19 - PIN19: u1 = 0, - /// Pin 20 - PIN20: u1 = 0, - /// Pin 21 - PIN21: u1 = 0, - /// Pin 22 - PIN22: u1 = 0, - /// Pin 23 - PIN23: u1 = 0, - /// Pin 24 - PIN24: u1 = 0, - /// Pin 25 - PIN25: u1 = 0, - /// Pin 26 - PIN26: u1 = 0, - /// Pin 27 - PIN27: u1 = 0, - /// Pin 28 - PIN28: u1 = 0, - /// Pin 29 - PIN29: u1 = 0, - /// Pin 30 - PIN30: u1 = 0, - /// Pin 31 - PIN31: u1 = 0, - }); - - /// Set individual bits in GPIO port - pub const OUTSET = mmio(Address + 0x00000508, 32, packed struct { - /// Pin 0 - PIN0: u1 = 0, - /// Pin 1 - PIN1: u1 = 0, - /// Pin 2 - PIN2: u1 = 0, - /// Pin 3 - PIN3: u1 = 0, - /// Pin 4 - PIN4: u1 = 0, - /// Pin 5 - PIN5: u1 = 0, - /// Pin 6 - PIN6: u1 = 0, - /// Pin 7 - PIN7: u1 = 0, - /// Pin 8 - PIN8: u1 = 0, - /// Pin 9 - PIN9: u1 = 0, - /// Pin 10 - PIN10: u1 = 0, - /// Pin 11 - PIN11: u1 = 0, - /// Pin 12 - PIN12: u1 = 0, - /// Pin 13 - PIN13: u1 = 0, - /// Pin 14 - PIN14: u1 = 0, - /// Pin 15 - PIN15: u1 = 0, - /// Pin 16 - PIN16: u1 = 0, - /// Pin 17 - PIN17: u1 = 0, - /// Pin 18 - PIN18: u1 = 0, - /// Pin 19 - PIN19: u1 = 0, - /// Pin 20 - PIN20: u1 = 0, - /// Pin 21 - PIN21: u1 = 0, - /// Pin 22 - PIN22: u1 = 0, - /// Pin 23 - PIN23: u1 = 0, - /// Pin 24 - PIN24: u1 = 0, - /// Pin 25 - PIN25: u1 = 0, - /// Pin 26 - PIN26: u1 = 0, - /// Pin 27 - PIN27: u1 = 0, - /// Pin 28 - PIN28: u1 = 0, - /// Pin 29 - PIN29: u1 = 0, - /// Pin 30 - PIN30: u1 = 0, - /// Pin 31 - PIN31: u1 = 0, - }); - - /// Clear individual bits in GPIO port - pub const OUTCLR = mmio(Address + 0x0000050c, 32, packed struct { - /// Pin 0 - PIN0: u1 = 0, - /// Pin 1 - PIN1: u1 = 0, - /// Pin 2 - PIN2: u1 = 0, - /// Pin 3 - PIN3: u1 = 0, - /// Pin 4 - PIN4: u1 = 0, - /// Pin 5 - PIN5: u1 = 0, - /// Pin 6 - PIN6: u1 = 0, - /// Pin 7 - PIN7: u1 = 0, - /// Pin 8 - PIN8: u1 = 0, - /// Pin 9 - PIN9: u1 = 0, - /// Pin 10 - PIN10: u1 = 0, - /// Pin 11 - PIN11: u1 = 0, - /// Pin 12 - PIN12: u1 = 0, - /// Pin 13 - PIN13: u1 = 0, - /// Pin 14 - PIN14: u1 = 0, - /// Pin 15 - PIN15: u1 = 0, - /// Pin 16 - PIN16: u1 = 0, - /// Pin 17 - PIN17: u1 = 0, - /// Pin 18 - PIN18: u1 = 0, - /// Pin 19 - PIN19: u1 = 0, - /// Pin 20 - PIN20: u1 = 0, - /// Pin 21 - PIN21: u1 = 0, - /// Pin 22 - PIN22: u1 = 0, - /// Pin 23 - PIN23: u1 = 0, - /// Pin 24 - PIN24: u1 = 0, - /// Pin 25 - PIN25: u1 = 0, - /// Pin 26 - PIN26: u1 = 0, - /// Pin 27 - PIN27: u1 = 0, - /// Pin 28 - PIN28: u1 = 0, - /// Pin 29 - PIN29: u1 = 0, - /// Pin 30 - PIN30: u1 = 0, - /// Pin 31 - PIN31: u1 = 0, - }); - - /// Read GPIO port - pub const IN = mmio(Address + 0x00000510, 32, packed struct { - /// Pin 0 - PIN0: u1 = 0, - /// Pin 1 - PIN1: u1 = 0, - /// Pin 2 - PIN2: u1 = 0, - /// Pin 3 - PIN3: u1 = 0, - /// Pin 4 - PIN4: u1 = 0, - /// Pin 5 - PIN5: u1 = 0, - /// Pin 6 - PIN6: u1 = 0, - /// Pin 7 - PIN7: u1 = 0, - /// Pin 8 - PIN8: u1 = 0, - /// Pin 9 - PIN9: u1 = 0, - /// Pin 10 - PIN10: u1 = 0, - /// Pin 11 - PIN11: u1 = 0, - /// Pin 12 - PIN12: u1 = 0, - /// Pin 13 - PIN13: u1 = 0, - /// Pin 14 - PIN14: u1 = 0, - /// Pin 15 - PIN15: u1 = 0, - /// Pin 16 - PIN16: u1 = 0, - /// Pin 17 - PIN17: u1 = 0, - /// Pin 18 - PIN18: u1 = 0, - /// Pin 19 - PIN19: u1 = 0, - /// Pin 20 - PIN20: u1 = 0, - /// Pin 21 - PIN21: u1 = 0, - /// Pin 22 - PIN22: u1 = 0, - /// Pin 23 - PIN23: u1 = 0, - /// Pin 24 - PIN24: u1 = 0, - /// Pin 25 - PIN25: u1 = 0, - /// Pin 26 - PIN26: u1 = 0, - /// Pin 27 - PIN27: u1 = 0, - /// Pin 28 - PIN28: u1 = 0, - /// Pin 29 - PIN29: u1 = 0, - /// Pin 30 - PIN30: u1 = 0, - /// Pin 31 - PIN31: u1 = 0, - }); - - /// Direction of GPIO pins - pub const DIR = mmio(Address + 0x00000514, 32, packed struct { - /// Pin 0 - PIN0: u1 = 0, - /// Pin 1 - PIN1: u1 = 0, - /// Pin 2 - PIN2: u1 = 0, - /// Pin 3 - PIN3: u1 = 0, - /// Pin 4 - PIN4: u1 = 0, - /// Pin 5 - PIN5: u1 = 0, - /// Pin 6 - PIN6: u1 = 0, - /// Pin 7 - PIN7: u1 = 0, - /// Pin 8 - PIN8: u1 = 0, - /// Pin 9 - PIN9: u1 = 0, - /// Pin 10 - PIN10: u1 = 0, - /// Pin 11 - PIN11: u1 = 0, - /// Pin 12 - PIN12: u1 = 0, - /// Pin 13 - PIN13: u1 = 0, - /// Pin 14 - PIN14: u1 = 0, - /// Pin 15 - PIN15: u1 = 0, - /// Pin 16 - PIN16: u1 = 0, - /// Pin 17 - PIN17: u1 = 0, - /// Pin 18 - PIN18: u1 = 0, - /// Pin 19 - PIN19: u1 = 0, - /// Pin 20 - PIN20: u1 = 0, - /// Pin 21 - PIN21: u1 = 0, - /// Pin 22 - PIN22: u1 = 0, - /// Pin 23 - PIN23: u1 = 0, - /// Pin 24 - PIN24: u1 = 0, - /// Pin 25 - PIN25: u1 = 0, - /// Pin 26 - PIN26: u1 = 0, - /// Pin 27 - PIN27: u1 = 0, - /// Pin 28 - PIN28: u1 = 0, - /// Pin 29 - PIN29: u1 = 0, - /// Pin 30 - PIN30: u1 = 0, - /// Pin 31 - PIN31: u1 = 0, - }); - - /// DIR set register - pub const DIRSET = mmio(Address + 0x00000518, 32, packed struct { - /// Set as output pin 0 - PIN0: u1 = 0, - /// Set as output pin 1 - PIN1: u1 = 0, - /// Set as output pin 2 - PIN2: u1 = 0, - /// Set as output pin 3 - PIN3: u1 = 0, - /// Set as output pin 4 - PIN4: u1 = 0, - /// Set as output pin 5 - PIN5: u1 = 0, - /// Set as output pin 6 - PIN6: u1 = 0, - /// Set as output pin 7 - PIN7: u1 = 0, - /// Set as output pin 8 - PIN8: u1 = 0, - /// Set as output pin 9 - PIN9: u1 = 0, - /// Set as output pin 10 - PIN10: u1 = 0, - /// Set as output pin 11 - PIN11: u1 = 0, - /// Set as output pin 12 - PIN12: u1 = 0, - /// Set as output pin 13 - PIN13: u1 = 0, - /// Set as output pin 14 - PIN14: u1 = 0, - /// Set as output pin 15 - PIN15: u1 = 0, - /// Set as output pin 16 - PIN16: u1 = 0, - /// Set as output pin 17 - PIN17: u1 = 0, - /// Set as output pin 18 - PIN18: u1 = 0, - /// Set as output pin 19 - PIN19: u1 = 0, - /// Set as output pin 20 - PIN20: u1 = 0, - /// Set as output pin 21 - PIN21: u1 = 0, - /// Set as output pin 22 - PIN22: u1 = 0, - /// Set as output pin 23 - PIN23: u1 = 0, - /// Set as output pin 24 - PIN24: u1 = 0, - /// Set as output pin 25 - PIN25: u1 = 0, - /// Set as output pin 26 - PIN26: u1 = 0, - /// Set as output pin 27 - PIN27: u1 = 0, - /// Set as output pin 28 - PIN28: u1 = 0, - /// Set as output pin 29 - PIN29: u1 = 0, - /// Set as output pin 30 - PIN30: u1 = 0, - /// Set as output pin 31 - PIN31: u1 = 0, - }); - - /// DIR clear register - pub const DIRCLR = mmio(Address + 0x0000051c, 32, packed struct { - /// Set as input pin 0 - PIN0: u1 = 0, - /// Set as input pin 1 - PIN1: u1 = 0, - /// Set as input pin 2 - PIN2: u1 = 0, - /// Set as input pin 3 - PIN3: u1 = 0, - /// Set as input pin 4 - PIN4: u1 = 0, - /// Set as input pin 5 - PIN5: u1 = 0, - /// Set as input pin 6 - PIN6: u1 = 0, - /// Set as input pin 7 - PIN7: u1 = 0, - /// Set as input pin 8 - PIN8: u1 = 0, - /// Set as input pin 9 - PIN9: u1 = 0, - /// Set as input pin 10 - PIN10: u1 = 0, - /// Set as input pin 11 - PIN11: u1 = 0, - /// Set as input pin 12 - PIN12: u1 = 0, - /// Set as input pin 13 - PIN13: u1 = 0, - /// Set as input pin 14 - PIN14: u1 = 0, - /// Set as input pin 15 - PIN15: u1 = 0, - /// Set as input pin 16 - PIN16: u1 = 0, - /// Set as input pin 17 - PIN17: u1 = 0, - /// Set as input pin 18 - PIN18: u1 = 0, - /// Set as input pin 19 - PIN19: u1 = 0, - /// Set as input pin 20 - PIN20: u1 = 0, - /// Set as input pin 21 - PIN21: u1 = 0, - /// Set as input pin 22 - PIN22: u1 = 0, - /// Set as input pin 23 - PIN23: u1 = 0, - /// Set as input pin 24 - PIN24: u1 = 0, - /// Set as input pin 25 - PIN25: u1 = 0, - /// Set as input pin 26 - PIN26: u1 = 0, - /// Set as input pin 27 - PIN27: u1 = 0, - /// Set as input pin 28 - PIN28: u1 = 0, - /// Set as input pin 29 - PIN29: u1 = 0, - /// Set as input pin 30 - PIN30: u1 = 0, - /// Set as input pin 31 - PIN31: u1 = 0, - }); - - /// Latch register indicating what GPIO pins that have met the criteria set in - /// the PIN_CNF[n].SENSE registers - pub const LATCH = mmio(Address + 0x00000520, 32, packed struct { - /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. - /// Write '1' to clear. - PIN0: u1 = 0, - /// Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. - /// Write '1' to clear. - PIN1: u1 = 0, - /// Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. - /// Write '1' to clear. - PIN2: u1 = 0, - /// Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. - /// Write '1' to clear. - PIN3: u1 = 0, - /// Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. - /// Write '1' to clear. - PIN4: u1 = 0, - /// Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. - /// Write '1' to clear. - PIN5: u1 = 0, - /// Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. - /// Write '1' to clear. - PIN6: u1 = 0, - /// Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. - /// Write '1' to clear. - PIN7: u1 = 0, - /// Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. - /// Write '1' to clear. - PIN8: u1 = 0, - /// Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. - /// Write '1' to clear. - PIN9: u1 = 0, - /// Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. - /// Write '1' to clear. - PIN10: u1 = 0, - /// Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. - /// Write '1' to clear. - PIN11: u1 = 0, - /// Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. - /// Write '1' to clear. - PIN12: u1 = 0, - /// Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. - /// Write '1' to clear. - PIN13: u1 = 0, - /// Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. - /// Write '1' to clear. - PIN14: u1 = 0, - /// Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. - /// Write '1' to clear. - PIN15: u1 = 0, - /// Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. - /// Write '1' to clear. - PIN16: u1 = 0, - /// Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. - /// Write '1' to clear. - PIN17: u1 = 0, - /// Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. - /// Write '1' to clear. - PIN18: u1 = 0, - /// Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. - /// Write '1' to clear. - PIN19: u1 = 0, - /// Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. - /// Write '1' to clear. - PIN20: u1 = 0, - /// Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. - /// Write '1' to clear. - PIN21: u1 = 0, - /// Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. - /// Write '1' to clear. - PIN22: u1 = 0, - /// Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. - /// Write '1' to clear. - PIN23: u1 = 0, - /// Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. - /// Write '1' to clear. - PIN24: u1 = 0, - /// Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. - /// Write '1' to clear. - PIN25: u1 = 0, - /// Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. - /// Write '1' to clear. - PIN26: u1 = 0, - /// Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. - /// Write '1' to clear. - PIN27: u1 = 0, - /// Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. - /// Write '1' to clear. - PIN28: u1 = 0, - /// Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. - /// Write '1' to clear. - PIN29: u1 = 0, - /// Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. - /// Write '1' to clear. - PIN30: u1 = 0, - /// Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. - /// Write '1' to clear. - PIN31: u1 = 0, - }); - - /// Select between default DETECT signal behaviour and LDETECT mode - pub const DETECTMODE = mmio(Address + 0x00000524, 32, packed struct { - /// Select between default DETECT signal behaviour and LDETECT mode - DETECTMODE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Configuration of GPIO pins - pub const PIN_CNF = @intToPtr(*volatile [32]MMIO(32, packed struct { - /// Pin direction. Same physical register as DIR register - DIR: u1 = 0, - /// Connect or disconnect input buffer - INPUT: u1 = 0, - /// Pull configuration - PULL: u2 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Drive configuration - DRIVE: u3 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Pin sensing mechanism - SENSE: u2 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000700); -}; + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} -const std = @import("std"); -const root = @import("root"); -const cpu = @import("cpu"); -const config = @import("microzig-config"); const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm }; -fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { - return InterruptVector{ - .C = struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt: " ++ str); - } - }.unhandledInterrupt, - }; -} - -pub const VectorTable = extern struct { - initial_stack_pointer: u32 = config.end_of_stack, - Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, - NMI: InterruptVector = makeUnhandledHandler("NMI"), - HardFault: InterruptVector = makeUnhandledHandler("HardFault"), - MemManage: InterruptVector = makeUnhandledHandler("MemManage"), - BusFault: InterruptVector = makeUnhandledHandler("BusFault"), - UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), - - reserved: [4]u32 = .{ 0, 0, 0, 0 }, - SVCall: InterruptVector = makeUnhandledHandler("SVCall"), - DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), - reserved1: u32 = 0, - - PendSV: InterruptVector = makeUnhandledHandler("PendSV"), - SysTick: InterruptVector = makeUnhandledHandler("SysTick"), - - POWER_CLOCK: InterruptVector = makeUnhandledHandler("POWER_CLOCK"), - RADIO: InterruptVector = makeUnhandledHandler("RADIO"), - UARTE0_UART0: InterruptVector = makeUnhandledHandler("UARTE0_UART0"), - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: InterruptVector = makeUnhandledHandler("SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0"), - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: InterruptVector = makeUnhandledHandler("SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1"), - NFCT: InterruptVector = makeUnhandledHandler("NFCT"), - GPIOTE: InterruptVector = makeUnhandledHandler("GPIOTE"), - SAADC: InterruptVector = makeUnhandledHandler("SAADC"), - TIMER0: InterruptVector = makeUnhandledHandler("TIMER0"), - TIMER1: InterruptVector = makeUnhandledHandler("TIMER1"), - TIMER2: InterruptVector = makeUnhandledHandler("TIMER2"), - RTC0: InterruptVector = makeUnhandledHandler("RTC0"), - TEMP: InterruptVector = makeUnhandledHandler("TEMP"), - RNG: InterruptVector = makeUnhandledHandler("RNG"), - ECB: InterruptVector = makeUnhandledHandler("ECB"), - CCM_AAR: InterruptVector = makeUnhandledHandler("CCM_AAR"), - WDT: InterruptVector = makeUnhandledHandler("WDT"), - RTC1: InterruptVector = makeUnhandledHandler("RTC1"), - QDEC: InterruptVector = makeUnhandledHandler("QDEC"), - COMP_LPCOMP: InterruptVector = makeUnhandledHandler("COMP_LPCOMP"), - SWI0_EGU0: InterruptVector = makeUnhandledHandler("SWI0_EGU0"), - SWI1_EGU1: InterruptVector = makeUnhandledHandler("SWI1_EGU1"), - SWI2_EGU2: InterruptVector = makeUnhandledHandler("SWI2_EGU2"), - SWI3_EGU3: InterruptVector = makeUnhandledHandler("SWI3_EGU3"), - SWI4_EGU4: InterruptVector = makeUnhandledHandler("SWI4_EGU4"), - SWI5_EGU5: InterruptVector = makeUnhandledHandler("SWI5_EGU5"), - TIMER3: InterruptVector = makeUnhandledHandler("TIMER3"), - TIMER4: InterruptVector = makeUnhandledHandler("TIMER4"), - PWM0: InterruptVector = makeUnhandledHandler("PWM0"), - PDM: InterruptVector = makeUnhandledHandler("PDM"), - reserved2: u32 = 0, - reserved3: u32 = 0, - MWU: InterruptVector = makeUnhandledHandler("MWU"), - PWM1: InterruptVector = makeUnhandledHandler("PWM1"), - PWM2: InterruptVector = makeUnhandledHandler("PWM2"), - SPIM2_SPIS2_SPI2: InterruptVector = makeUnhandledHandler("SPIM2_SPIS2_SPI2"), - RTC2: InterruptVector = makeUnhandledHandler("RTC2"), - I2S: InterruptVector = makeUnhandledHandler("I2S"), - FPU: InterruptVector = makeUnhandledHandler("FPU"), -}; - -fn isValidField(field_name: []const u8) bool { - return !std.mem.startsWith(u8, field_name, "reserved") and - !std.mem.eql(u8, field_name, "initial_stack_pointer") and - !std.mem.eql(u8, field_name, "reset"); -} - -export const vectors: VectorTable linksection("microzig_flash_start") = blk: { - var temp: VectorTable = .{}; - if (@hasDecl(root, "vector_table")) { - const vector_table = root.vector_table; - if (@typeInfo(vector_table) != .Struct) - @compileLog("root.vector_table must be a struct"); - - inline for (@typeInfo(vector_table).Struct.decls) |decl| { - const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; - const handler = @field(vector_table, decl.name); - - if (!@hasField(VectorTable, decl.name)) { - var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; - inline for (std.meta.fields(VectorTable)) |field| { - if (isValidField(field.name)) { - msg = msg ++ " " ++ field.name ++ "\n"; - } - } - - @compileError(msg); - } - - if (!isValidField(decl.name)) - @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); - - @field(temp, decl.name) = switch (calling_convention) { - .C => .{ .C = handler }, - .Naked => .{ .Naked = handler }, - // for unspecified calling convention we are going to generate small wrapper - .Unspecified => .{ - .C = struct { - fn wrapper() callconv(.C) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - }, - - else => @compileError("unsupported calling convention for function " ++ decl.name), - }; +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); } - } - break :blk temp; + }.tmp, }; diff --git a/src/modules/chips/stm32f103/registers.zig b/src/modules/chips/stm32f103/registers.zig index f56973f..6c72470 100644 --- a/src/modules/chips/stm32f103/registers.zig +++ b/src/modules/chips/stm32f103/registers.zig @@ -1,22512 +1,23556 @@ -// generated using svd2zig.py -// DO NOT EDIT -// based on STM32F103xx version 1.3 -const microzig_mmio = @import("microzig-mmio"); -const mmio = microzig_mmio.mmio; -const MMIO = microzig_mmio.MMIO; -const Name = "STM32F103xx"; - -/// Flexible static memory controller -pub const FSMC = extern struct { - pub const Address: u32 = 0xa0000000; - - /// SRAM/NOR-Flash chip-select control register 1 - pub const BCR1 = mmio(Address + 0x00000000, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 1 - pub const BTR1 = mmio(Address + 0x00000004, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 2 - pub const BCR2 = mmio(Address + 0x00000008, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 2 - pub const BTR2 = mmio(Address + 0x0000000c, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 3 - pub const BCR3 = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 3 - pub const BTR3 = mmio(Address + 0x00000014, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 4 - pub const BCR4 = mmio(Address + 0x00000018, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 4 - pub const BTR4 = mmio(Address + 0x0000001c, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PC Card/NAND Flash control register 2 - pub const PCR2 = mmio(Address + 0x00000060, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 2 - pub const SR2 = mmio(Address + 0x00000064, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 2 - pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct {}); - - /// Attribute memory space timing register 2 - pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct { - /// Attribute memory x setup time - ATTSETx: u8 = 0, - /// Attribute memory x wait time - ATTWAITx: u8 = 0, - /// Attribute memory x hold time - ATTHOLDx: u8 = 0, - /// Attribute memory x databus HiZ time - ATTHIZx: u8 = 0, - }); - - /// ECC result register 2 - pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct { - /// ECC result - ECCx: u32 = 0, - }); - - /// PC Card/NAND Flash control register 3 - pub const PCR3 = mmio(Address + 0x00000080, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 3 - pub const SR3 = mmio(Address + 0x00000084, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 3 - pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct {}); - - /// Attribute memory space timing register 3 - pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct {}); - - /// ECC result register 3 - pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct {}); - - /// PC Card/NAND Flash control register 4 - pub const PCR4 = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 4 - pub const SR4 = mmio(Address + 0x000000a4, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 4 - pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct {}); - - /// Attribute memory space timing register 4 - pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct {}); - - /// I/O space timing register 4 - pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct {}); - - /// SRAM/NOR-Flash write timing registers 1 - pub const BWTR1 = mmio(Address + 0x00000104, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 2 - pub const BWTR2 = mmio(Address + 0x0000010c, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 3 - pub const BWTR3 = mmio(Address + 0x00000114, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 4 - pub const BWTR4 = mmio(Address + 0x0000011c, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Power control -pub const PWR = extern struct { - pub const Address: u32 = 0x40007000; - - /// Power control register (PWR_CR) - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// Low Power Deep Sleep - LPDS: u1 = 0, - /// Power Down Deep Sleep - PDDS: u1 = 0, - /// Clear Wake-up Flag - CWUF: u1 = 0, - /// Clear STANDBY Flag - CSBF: u1 = 0, - /// Power Voltage Detector Enable - PVDE: u1 = 0, - /// PVD Level Selection - PLS: u3 = 0, - /// Disable Backup Domain write protection - DBP: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Power control register (PWR_CR) - pub const CSR = mmio(Address + 0x00000004, 32, packed struct { - /// Wake-Up Flag - WUF: u1 = 0, - /// STANDBY Flag - SBF: u1 = 0, - /// PVD Output - PVDO: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable WKUP pin - EWUP: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Reset and clock control -pub const RCC = extern struct { - pub const Address: u32 = 0x40021000; - - /// Clock control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// Internal High Speed clock enable - HSION: u1 = 0, - /// Internal High Speed clock ready flag - HSIRDY: u1 = 0, - reserved1: u1 = 0, - /// Internal High Speed clock trimming - HSITRIM: u5 = 0, - /// Internal High Speed clock Calibration - HSICAL: u8 = 0, - /// External High Speed clock enable - HSEON: u1 = 0, - /// External High Speed clock ready flag - HSERDY: u1 = 0, - /// External High Speed clock Bypass - HSEBYP: u1 = 0, - /// Clock Security System enable - CSSON: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// PLL enable - PLLON: u1 = 0, - /// PLL clock ready flag - PLLRDY: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock configuration register (RCC_CFGR) - pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { - /// System clock Switch - SW: u2 = 0, - /// System Clock Switch Status - SWS: u2 = 0, - /// AHB prescaler - HPRE: u4 = 0, - /// APB Low speed prescaler (APB1) - PPRE1: u3 = 0, - /// APB High speed prescaler (APB2) - PPRE2: u3 = 0, - /// ADC prescaler - ADCPRE: u2 = 0, - /// PLL entry clock source - PLLSRC: u1 = 0, - /// HSE divider for PLL entry - PLLXTPRE: u1 = 0, - /// PLL Multiplication Factor - PLLMUL: u4 = 0, - /// USB OTG FS prescaler - OTGFSPRE: u1 = 0, - reserved1: u1 = 0, - /// Microcontroller clock output - MCO: u3 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock interrupt register (RCC_CIR) - pub const CIR = mmio(Address + 0x00000008, 32, packed struct { - /// LSI Ready Interrupt flag - LSIRDYF: u1 = 0, - /// LSE Ready Interrupt flag - LSERDYF: u1 = 0, - /// HSI Ready Interrupt flag - HSIRDYF: u1 = 0, - /// HSE Ready Interrupt flag - HSERDYF: u1 = 0, - /// PLL Ready Interrupt flag - PLLRDYF: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Clock Security System Interrupt flag - CSSF: u1 = 0, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1 = 0, - /// LSE Ready Interrupt Enable - LSERDYIE: u1 = 0, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1 = 0, - /// HSE Ready Interrupt Enable - HSERDYIE: u1 = 0, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// LSI Ready Interrupt Clear - LSIRDYC: u1 = 0, - /// LSE Ready Interrupt Clear - LSERDYC: u1 = 0, - /// HSI Ready Interrupt Clear - HSIRDYC: u1 = 0, - /// HSE Ready Interrupt Clear - HSERDYC: u1 = 0, - /// PLL Ready Interrupt Clear - PLLRDYC: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Clock security system interrupt clear - CSSC: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB2 peripheral reset register (RCC_APB2RSTR) - pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { - /// Alternate function I/O reset - AFIORST: u1 = 0, - reserved1: u1 = 0, - /// IO port A reset - IOPARST: u1 = 0, - /// IO port B reset - IOPBRST: u1 = 0, - /// IO port C reset - IOPCRST: u1 = 0, - /// IO port D reset - IOPDRST: u1 = 0, - /// IO port E reset - IOPERST: u1 = 0, - /// IO port F reset - IOPFRST: u1 = 0, - /// IO port G reset - IOPGRST: u1 = 0, - /// ADC 1 interface reset - ADC1RST: u1 = 0, - /// ADC 2 interface reset - ADC2RST: u1 = 0, - /// TIM1 timer reset - TIM1RST: u1 = 0, - /// SPI 1 reset - SPI1RST: u1 = 0, - /// TIM8 timer reset - TIM8RST: u1 = 0, - /// USART1 reset - USART1RST: u1 = 0, - /// ADC 3 interface reset - ADC3RST: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// TIM9 timer reset - TIM9RST: u1 = 0, - /// TIM10 timer reset - TIM10RST: u1 = 0, - /// TIM11 timer reset - TIM11RST: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB1 peripheral reset register (RCC_APB1RSTR) - pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { - /// Timer 2 reset - TIM2RST: u1 = 0, - /// Timer 3 reset - TIM3RST: u1 = 0, - /// Timer 4 reset - TIM4RST: u1 = 0, - /// Timer 5 reset - TIM5RST: u1 = 0, - /// Timer 6 reset - TIM6RST: u1 = 0, - /// Timer 7 reset - TIM7RST: u1 = 0, - /// Timer 12 reset - TIM12RST: u1 = 0, - /// Timer 13 reset - TIM13RST: u1 = 0, - /// Timer 14 reset - TIM14RST: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Window watchdog reset - WWDGRST: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// SPI2 reset - SPI2RST: u1 = 0, - /// SPI3 reset - SPI3RST: u1 = 0, - reserved5: u1 = 0, - /// USART 2 reset - USART2RST: u1 = 0, - /// USART 3 reset - USART3RST: u1 = 0, - /// UART 4 reset - UART4RST: u1 = 0, - /// UART 5 reset - UART5RST: u1 = 0, - /// I2C1 reset - I2C1RST: u1 = 0, - /// I2C2 reset - I2C2RST: u1 = 0, - /// USB reset - USBRST: u1 = 0, - reserved6: u1 = 0, - /// CAN reset - CANRST: u1 = 0, - reserved7: u1 = 0, - /// Backup interface reset - BKPRST: u1 = 0, - /// Power interface reset - PWRRST: u1 = 0, - /// DAC interface reset - DACRST: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// AHB Peripheral Clock enable register (RCC_AHBENR) - pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { - /// DMA1 clock enable - DMA1EN: u1 = 0, - /// DMA2 clock enable - DMA2EN: u1 = 0, - /// SRAM interface clock enable - SRAMEN: u1 = 0, - reserved1: u1 = 0, - /// FLITF clock enable - FLITFEN: u1 = 0, - reserved2: u1 = 0, - /// CRC clock enable - CRCEN: u1 = 0, - reserved3: u1 = 0, - /// FSMC clock enable - FSMCEN: u1 = 0, - reserved4: u1 = 0, - /// SDIO clock enable - SDIOEN: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB2 peripheral clock enable register (RCC_APB2ENR) - pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { - /// Alternate function I/O clock enable - AFIOEN: u1 = 0, - reserved1: u1 = 0, - /// I/O port A clock enable - IOPAEN: u1 = 0, - /// I/O port B clock enable - IOPBEN: u1 = 0, - /// I/O port C clock enable - IOPCEN: u1 = 0, - /// I/O port D clock enable - IOPDEN: u1 = 0, - /// I/O port E clock enable - IOPEEN: u1 = 0, - /// I/O port F clock enable - IOPFEN: u1 = 0, - /// I/O port G clock enable - IOPGEN: u1 = 0, - /// ADC 1 interface clock enable - ADC1EN: u1 = 0, - /// ADC 2 interface clock enable - ADC2EN: u1 = 0, - /// TIM1 Timer clock enable - TIM1EN: u1 = 0, - /// SPI 1 clock enable - SPI1EN: u1 = 0, - /// TIM8 Timer clock enable - TIM8EN: u1 = 0, - /// USART1 clock enable - USART1EN: u1 = 0, - /// ADC3 interface clock enable - ADC3EN: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// TIM9 Timer clock enable - TIM9EN: u1 = 0, - /// TIM10 Timer clock enable - TIM10EN: u1 = 0, - /// TIM11 Timer clock enable - TIM11EN: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB1 peripheral clock enable register (RCC_APB1ENR) - pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { - /// Timer 2 clock enable - TIM2EN: u1 = 0, - /// Timer 3 clock enable - TIM3EN: u1 = 0, - /// Timer 4 clock enable - TIM4EN: u1 = 0, - /// Timer 5 clock enable - TIM5EN: u1 = 0, - /// Timer 6 clock enable - TIM6EN: u1 = 0, - /// Timer 7 clock enable - TIM7EN: u1 = 0, - /// Timer 12 clock enable - TIM12EN: u1 = 0, - /// Timer 13 clock enable - TIM13EN: u1 = 0, - /// Timer 14 clock enable - TIM14EN: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Window watchdog clock enable - WWDGEN: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// SPI 2 clock enable - SPI2EN: u1 = 0, - /// SPI 3 clock enable - SPI3EN: u1 = 0, - reserved5: u1 = 0, - /// USART 2 clock enable - USART2EN: u1 = 0, - /// USART 3 clock enable - USART3EN: u1 = 0, - /// UART 4 clock enable - UART4EN: u1 = 0, - /// UART 5 clock enable - UART5EN: u1 = 0, - /// I2C 1 clock enable - I2C1EN: u1 = 0, - /// I2C 2 clock enable - I2C2EN: u1 = 0, - /// USB clock enable - USBEN: u1 = 0, - reserved6: u1 = 0, - /// CAN clock enable - CANEN: u1 = 0, - reserved7: u1 = 0, - /// Backup interface clock enable - BKPEN: u1 = 0, - /// Power interface clock enable - PWREN: u1 = 0, - /// DAC interface clock enable - DACEN: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup domain control register (RCC_BDCR) - pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { - /// External Low Speed oscillator enable - LSEON: u1 = 0, - /// External Low Speed oscillator ready - LSERDY: u1 = 0, - /// External Low Speed oscillator bypass - LSEBYP: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// RTC clock source selection - RTCSEL: u2 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// RTC clock enable - RTCEN: u1 = 0, - /// Backup domain software reset - BDRST: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control/status register (RCC_CSR) - pub const CSR = mmio(Address + 0x00000024, 32, packed struct { - /// Internal low speed oscillator enable - LSION: u1 = 0, - /// Internal low speed oscillator ready - LSIRDY: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Remove reset flag - RMVF: u1 = 0, - reserved23: u1 = 0, - /// PIN reset flag - PINRSTF: u1 = 0, - /// POR/PDR reset flag - PORRSTF: u1 = 0, - /// Software reset flag - SFTRSTF: u1 = 0, - /// Independent watchdog reset flag - IWDGRSTF: u1 = 0, - /// Window watchdog reset flag - WWDGRSTF: u1 = 0, - /// Low-power reset flag - LPWRRSTF: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOA = extern struct { - pub const Address: u32 = 0x40010800; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOB = extern struct { - pub const Address: u32 = 0x40010c00; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOC = extern struct { - pub const Address: u32 = 0x40011000; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOD = extern struct { - pub const Address: u32 = 0x40011400; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOE = extern struct { - pub const Address: u32 = 0x40011800; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOF = extern struct { - pub const Address: u32 = 0x40011c00; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOG = extern struct { - pub const Address: u32 = 0x40012000; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Alternate function I/O -pub const AFIO = extern struct { - pub const Address: u32 = 0x40010000; - - /// Event Control Register (AFIO_EVCR) - pub const EVCR = mmio(Address + 0x00000000, 32, packed struct { - /// Pin selection - PIN: u4 = 0, - /// Port selection - PORT: u3 = 0, - /// Event Output Enable - EVOE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// AF remap and debug I/O configuration register (AFIO_MAPR) - pub const MAPR = mmio(Address + 0x00000004, 32, packed struct { - /// SPI1 remapping - SPI1_REMAP: u1 = 0, - /// I2C1 remapping - I2C1_REMAP: u1 = 0, - /// USART1 remapping - USART1_REMAP: u1 = 0, - /// USART2 remapping - USART2_REMAP: u1 = 0, - /// USART3 remapping - USART3_REMAP: u2 = 0, - /// TIM1 remapping - TIM1_REMAP: u2 = 0, - /// TIM2 remapping - TIM2_REMAP: u2 = 0, - /// TIM3 remapping - TIM3_REMAP: u2 = 0, - /// TIM4 remapping - TIM4_REMAP: u1 = 0, - /// CAN1 remapping - CAN_REMAP: u2 = 0, - /// Port D0/Port D1 mapping on OSCIN/OSCOUT - PD01_REMAP: u1 = 0, - /// Set and cleared by software - TIM5CH4_IREMAP: u1 = 0, - /// ADC 1 External trigger injected conversion remapping - ADC1_ETRGINJ_REMAP: u1 = 0, - /// ADC 1 external trigger regular conversion remapping - ADC1_ETRGREG_REMAP: u1 = 0, - /// ADC 2 external trigger injected conversion remapping - ADC2_ETRGINJ_REMAP: u1 = 0, - /// ADC 2 external trigger regular conversion remapping - ADC2_ETRGREG_REMAP: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Serial wire JTAG configuration - SWJ_CFG: u3 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External interrupt configuration register 1 (AFIO_EXTICR1) - pub const EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { - /// EXTI0 configuration - EXTI0: u4 = 0, - /// EXTI1 configuration - EXTI1: u4 = 0, - /// EXTI2 configuration - EXTI2: u4 = 0, - /// EXTI3 configuration - EXTI3: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External interrupt configuration register 2 (AFIO_EXTICR2) - pub const EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { - /// EXTI4 configuration - EXTI4: u4 = 0, - /// EXTI5 configuration - EXTI5: u4 = 0, - /// EXTI6 configuration - EXTI6: u4 = 0, - /// EXTI7 configuration - EXTI7: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External interrupt configuration register 3 (AFIO_EXTICR3) - pub const EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { - /// EXTI8 configuration - EXTI8: u4 = 0, - /// EXTI9 configuration - EXTI9: u4 = 0, - /// EXTI10 configuration - EXTI10: u4 = 0, - /// EXTI11 configuration - EXTI11: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External interrupt configuration register 4 (AFIO_EXTICR4) - pub const EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { - /// EXTI12 configuration - EXTI12: u4 = 0, - /// EXTI13 configuration - EXTI13: u4 = 0, - /// EXTI14 configuration - EXTI14: u4 = 0, - /// EXTI15 configuration - EXTI15: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// AF remap and debug I/O configuration register - pub const MAPR2 = mmio(Address + 0x0000001c, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// TIM9 remapping - TIM9_REMAP: u1 = 0, - /// TIM10 remapping - TIM10_REMAP: u1 = 0, - /// TIM11 remapping - TIM11_REMAP: u1 = 0, - /// TIM13 remapping - TIM13_REMAP: u1 = 0, - /// TIM14 remapping - TIM14_REMAP: u1 = 0, - /// NADV connect/disconnect - FSMC_NADV: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// EXTI -pub const EXTI = extern struct { - pub const Address: u32 = 0x40010400; - - /// Interrupt mask register (EXTI_IMR) - pub const IMR = mmio(Address + 0x00000000, 32, packed struct { - /// Interrupt Mask on line 0 - MR0: u1 = 0, - /// Interrupt Mask on line 1 - MR1: u1 = 0, - /// Interrupt Mask on line 2 - MR2: u1 = 0, - /// Interrupt Mask on line 3 - MR3: u1 = 0, - /// Interrupt Mask on line 4 - MR4: u1 = 0, - /// Interrupt Mask on line 5 - MR5: u1 = 0, - /// Interrupt Mask on line 6 - MR6: u1 = 0, - /// Interrupt Mask on line 7 - MR7: u1 = 0, - /// Interrupt Mask on line 8 - MR8: u1 = 0, - /// Interrupt Mask on line 9 - MR9: u1 = 0, - /// Interrupt Mask on line 10 - MR10: u1 = 0, - /// Interrupt Mask on line 11 - MR11: u1 = 0, - /// Interrupt Mask on line 12 - MR12: u1 = 0, - /// Interrupt Mask on line 13 - MR13: u1 = 0, - /// Interrupt Mask on line 14 - MR14: u1 = 0, - /// Interrupt Mask on line 15 - MR15: u1 = 0, - /// Interrupt Mask on line 16 - MR16: u1 = 0, - /// Interrupt Mask on line 17 - MR17: u1 = 0, - /// Interrupt Mask on line 18 - MR18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Event mask register (EXTI_EMR) - pub const EMR = mmio(Address + 0x00000004, 32, packed struct { - /// Event Mask on line 0 - MR0: u1 = 0, - /// Event Mask on line 1 - MR1: u1 = 0, - /// Event Mask on line 2 - MR2: u1 = 0, - /// Event Mask on line 3 - MR3: u1 = 0, - /// Event Mask on line 4 - MR4: u1 = 0, - /// Event Mask on line 5 - MR5: u1 = 0, - /// Event Mask on line 6 - MR6: u1 = 0, - /// Event Mask on line 7 - MR7: u1 = 0, - /// Event Mask on line 8 - MR8: u1 = 0, - /// Event Mask on line 9 - MR9: u1 = 0, - /// Event Mask on line 10 - MR10: u1 = 0, - /// Event Mask on line 11 - MR11: u1 = 0, - /// Event Mask on line 12 - MR12: u1 = 0, - /// Event Mask on line 13 - MR13: u1 = 0, - /// Event Mask on line 14 - MR14: u1 = 0, - /// Event Mask on line 15 - MR15: u1 = 0, - /// Event Mask on line 16 - MR16: u1 = 0, - /// Event Mask on line 17 - MR17: u1 = 0, - /// Event Mask on line 18 - MR18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Rising Trigger selection register (EXTI_RTSR) - pub const RTSR = mmio(Address + 0x00000008, 32, packed struct { - /// Rising trigger event configuration of line 0 - TR0: u1 = 0, - /// Rising trigger event configuration of line 1 - TR1: u1 = 0, - /// Rising trigger event configuration of line 2 - TR2: u1 = 0, - /// Rising trigger event configuration of line 3 - TR3: u1 = 0, - /// Rising trigger event configuration of line 4 - TR4: u1 = 0, - /// Rising trigger event configuration of line 5 - TR5: u1 = 0, - /// Rising trigger event configuration of line 6 - TR6: u1 = 0, - /// Rising trigger event configuration of line 7 - TR7: u1 = 0, - /// Rising trigger event configuration of line 8 - TR8: u1 = 0, - /// Rising trigger event configuration of line 9 - TR9: u1 = 0, - /// Rising trigger event configuration of line 10 - TR10: u1 = 0, - /// Rising trigger event configuration of line 11 - TR11: u1 = 0, - /// Rising trigger event configuration of line 12 - TR12: u1 = 0, - /// Rising trigger event configuration of line 13 - TR13: u1 = 0, - /// Rising trigger event configuration of line 14 - TR14: u1 = 0, - /// Rising trigger event configuration of line 15 - TR15: u1 = 0, - /// Rising trigger event configuration of line 16 - TR16: u1 = 0, - /// Rising trigger event configuration of line 17 - TR17: u1 = 0, - /// Rising trigger event configuration of line 18 - TR18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Falling Trigger selection register (EXTI_FTSR) - pub const FTSR = mmio(Address + 0x0000000c, 32, packed struct { - /// Falling trigger event configuration of line 0 - TR0: u1 = 0, - /// Falling trigger event configuration of line 1 - TR1: u1 = 0, - /// Falling trigger event configuration of line 2 - TR2: u1 = 0, - /// Falling trigger event configuration of line 3 - TR3: u1 = 0, - /// Falling trigger event configuration of line 4 - TR4: u1 = 0, - /// Falling trigger event configuration of line 5 - TR5: u1 = 0, - /// Falling trigger event configuration of line 6 - TR6: u1 = 0, - /// Falling trigger event configuration of line 7 - TR7: u1 = 0, - /// Falling trigger event configuration of line 8 - TR8: u1 = 0, - /// Falling trigger event configuration of line 9 - TR9: u1 = 0, - /// Falling trigger event configuration of line 10 - TR10: u1 = 0, - /// Falling trigger event configuration of line 11 - TR11: u1 = 0, - /// Falling trigger event configuration of line 12 - TR12: u1 = 0, - /// Falling trigger event configuration of line 13 - TR13: u1 = 0, - /// Falling trigger event configuration of line 14 - TR14: u1 = 0, - /// Falling trigger event configuration of line 15 - TR15: u1 = 0, - /// Falling trigger event configuration of line 16 - TR16: u1 = 0, - /// Falling trigger event configuration of line 17 - TR17: u1 = 0, - /// Falling trigger event configuration of line 18 - TR18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Software interrupt event register (EXTI_SWIER) - pub const SWIER = mmio(Address + 0x00000010, 32, packed struct { - /// Software Interrupt on line 0 - SWIER0: u1 = 0, - /// Software Interrupt on line 1 - SWIER1: u1 = 0, - /// Software Interrupt on line 2 - SWIER2: u1 = 0, - /// Software Interrupt on line 3 - SWIER3: u1 = 0, - /// Software Interrupt on line 4 - SWIER4: u1 = 0, - /// Software Interrupt on line 5 - SWIER5: u1 = 0, - /// Software Interrupt on line 6 - SWIER6: u1 = 0, - /// Software Interrupt on line 7 - SWIER7: u1 = 0, - /// Software Interrupt on line 8 - SWIER8: u1 = 0, - /// Software Interrupt on line 9 - SWIER9: u1 = 0, - /// Software Interrupt on line 10 - SWIER10: u1 = 0, - /// Software Interrupt on line 11 - SWIER11: u1 = 0, - /// Software Interrupt on line 12 - SWIER12: u1 = 0, - /// Software Interrupt on line 13 - SWIER13: u1 = 0, - /// Software Interrupt on line 14 - SWIER14: u1 = 0, - /// Software Interrupt on line 15 - SWIER15: u1 = 0, - /// Software Interrupt on line 16 - SWIER16: u1 = 0, - /// Software Interrupt on line 17 - SWIER17: u1 = 0, - /// Software Interrupt on line 18 - SWIER18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pending register (EXTI_PR) - pub const PR = mmio(Address + 0x00000014, 32, packed struct { - /// Pending bit 0 - PR0: u1 = 0, - /// Pending bit 1 - PR1: u1 = 0, - /// Pending bit 2 - PR2: u1 = 0, - /// Pending bit 3 - PR3: u1 = 0, - /// Pending bit 4 - PR4: u1 = 0, - /// Pending bit 5 - PR5: u1 = 0, - /// Pending bit 6 - PR6: u1 = 0, - /// Pending bit 7 - PR7: u1 = 0, - /// Pending bit 8 - PR8: u1 = 0, - /// Pending bit 9 - PR9: u1 = 0, - /// Pending bit 10 - PR10: u1 = 0, - /// Pending bit 11 - PR11: u1 = 0, - /// Pending bit 12 - PR12: u1 = 0, - /// Pending bit 13 - PR13: u1 = 0, - /// Pending bit 14 - PR14: u1 = 0, - /// Pending bit 15 - PR15: u1 = 0, - /// Pending bit 16 - PR16: u1 = 0, - /// Pending bit 17 - PR17: u1 = 0, - /// Pending bit 18 - PR18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// DMA controller -pub const DMA1 = extern struct { - pub const Address: u32 = 0x40020000; - - /// DMA interrupt status register (DMA_ISR) - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - /// Channel 1 Global interrupt flag - GIF1: u1 = 0, - /// Channel 1 Transfer Complete flag - TCIF1: u1 = 0, - /// Channel 1 Half Transfer Complete flag - HTIF1: u1 = 0, - /// Channel 1 Transfer Error flag - TEIF1: u1 = 0, - /// Channel 2 Global interrupt flag - GIF2: u1 = 0, - /// Channel 2 Transfer Complete flag - TCIF2: u1 = 0, - /// Channel 2 Half Transfer Complete flag - HTIF2: u1 = 0, - /// Channel 2 Transfer Error flag - TEIF2: u1 = 0, - /// Channel 3 Global interrupt flag - GIF3: u1 = 0, - /// Channel 3 Transfer Complete flag - TCIF3: u1 = 0, - /// Channel 3 Half Transfer Complete flag - HTIF3: u1 = 0, - /// Channel 3 Transfer Error flag - TEIF3: u1 = 0, - /// Channel 4 Global interrupt flag - GIF4: u1 = 0, - /// Channel 4 Transfer Complete flag - TCIF4: u1 = 0, - /// Channel 4 Half Transfer Complete flag - HTIF4: u1 = 0, - /// Channel 4 Transfer Error flag - TEIF4: u1 = 0, - /// Channel 5 Global interrupt flag - GIF5: u1 = 0, - /// Channel 5 Transfer Complete flag - TCIF5: u1 = 0, - /// Channel 5 Half Transfer Complete flag - HTIF5: u1 = 0, - /// Channel 5 Transfer Error flag - TEIF5: u1 = 0, - /// Channel 6 Global interrupt flag - GIF6: u1 = 0, - /// Channel 6 Transfer Complete flag - TCIF6: u1 = 0, - /// Channel 6 Half Transfer Complete flag - HTIF6: u1 = 0, - /// Channel 6 Transfer Error flag - TEIF6: u1 = 0, - /// Channel 7 Global interrupt flag - GIF7: u1 = 0, - /// Channel 7 Transfer Complete flag - TCIF7: u1 = 0, - /// Channel 7 Half Transfer Complete flag - HTIF7: u1 = 0, - /// Channel 7 Transfer Error flag - TEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA interrupt flag clear register (DMA_IFCR) - pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - /// Channel 1 Global interrupt clear - CGIF1: u1 = 0, - /// Channel 1 Transfer Complete clear - CTCIF1: u1 = 0, - /// Channel 1 Half Transfer clear - CHTIF1: u1 = 0, - /// Channel 1 Transfer Error clear - CTEIF1: u1 = 0, - /// Channel 2 Global interrupt clear - CGIF2: u1 = 0, - /// Channel 2 Transfer Complete clear - CTCIF2: u1 = 0, - /// Channel 2 Half Transfer clear - CHTIF2: u1 = 0, - /// Channel 2 Transfer Error clear - CTEIF2: u1 = 0, - /// Channel 3 Global interrupt clear - CGIF3: u1 = 0, - /// Channel 3 Transfer Complete clear - CTCIF3: u1 = 0, - /// Channel 3 Half Transfer clear - CHTIF3: u1 = 0, - /// Channel 3 Transfer Error clear - CTEIF3: u1 = 0, - /// Channel 4 Global interrupt clear - CGIF4: u1 = 0, - /// Channel 4 Transfer Complete clear - CTCIF4: u1 = 0, - /// Channel 4 Half Transfer clear - CHTIF4: u1 = 0, - /// Channel 4 Transfer Error clear - CTEIF4: u1 = 0, - /// Channel 5 Global interrupt clear - CGIF5: u1 = 0, - /// Channel 5 Transfer Complete clear - CTCIF5: u1 = 0, - /// Channel 5 Half Transfer clear - CHTIF5: u1 = 0, - /// Channel 5 Transfer Error clear - CTEIF5: u1 = 0, - /// Channel 6 Global interrupt clear - CGIF6: u1 = 0, - /// Channel 6 Transfer Complete clear - CTCIF6: u1 = 0, - /// Channel 6 Half Transfer clear - CHTIF6: u1 = 0, - /// Channel 6 Transfer Error clear - CTEIF6: u1 = 0, - /// Channel 7 Global interrupt clear - CGIF7: u1 = 0, - /// Channel 7 Transfer Complete clear - CTCIF7: u1 = 0, - /// Channel 7 Half Transfer clear - CHTIF7: u1 = 0, - /// Channel 7 Transfer Error clear - CTEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 number of data register - pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 peripheral address register - pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 1 memory address register - pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 number of data register - pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 peripheral address register - pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 2 memory address register - pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 number of data register - pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 peripheral address register - pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 3 memory address register - pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 number of data register - pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 peripheral address register - pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 4 memory address register - pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 number of data register - pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 peripheral address register - pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 5 memory address register - pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 number of data register - pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 peripheral address register - pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 6 memory address register - pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 number of data register - pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 peripheral address register - pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 7 memory address register - pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); -}; - -/// DMA controller -pub const DMA2 = extern struct { - pub const Address: u32 = 0x40020400; - - /// DMA interrupt status register (DMA_ISR) - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - /// Channel 1 Global interrupt flag - GIF1: u1 = 0, - /// Channel 1 Transfer Complete flag - TCIF1: u1 = 0, - /// Channel 1 Half Transfer Complete flag - HTIF1: u1 = 0, - /// Channel 1 Transfer Error flag - TEIF1: u1 = 0, - /// Channel 2 Global interrupt flag - GIF2: u1 = 0, - /// Channel 2 Transfer Complete flag - TCIF2: u1 = 0, - /// Channel 2 Half Transfer Complete flag - HTIF2: u1 = 0, - /// Channel 2 Transfer Error flag - TEIF2: u1 = 0, - /// Channel 3 Global interrupt flag - GIF3: u1 = 0, - /// Channel 3 Transfer Complete flag - TCIF3: u1 = 0, - /// Channel 3 Half Transfer Complete flag - HTIF3: u1 = 0, - /// Channel 3 Transfer Error flag - TEIF3: u1 = 0, - /// Channel 4 Global interrupt flag - GIF4: u1 = 0, - /// Channel 4 Transfer Complete flag - TCIF4: u1 = 0, - /// Channel 4 Half Transfer Complete flag - HTIF4: u1 = 0, - /// Channel 4 Transfer Error flag - TEIF4: u1 = 0, - /// Channel 5 Global interrupt flag - GIF5: u1 = 0, - /// Channel 5 Transfer Complete flag - TCIF5: u1 = 0, - /// Channel 5 Half Transfer Complete flag - HTIF5: u1 = 0, - /// Channel 5 Transfer Error flag - TEIF5: u1 = 0, - /// Channel 6 Global interrupt flag - GIF6: u1 = 0, - /// Channel 6 Transfer Complete flag - TCIF6: u1 = 0, - /// Channel 6 Half Transfer Complete flag - HTIF6: u1 = 0, - /// Channel 6 Transfer Error flag - TEIF6: u1 = 0, - /// Channel 7 Global interrupt flag - GIF7: u1 = 0, - /// Channel 7 Transfer Complete flag - TCIF7: u1 = 0, - /// Channel 7 Half Transfer Complete flag - HTIF7: u1 = 0, - /// Channel 7 Transfer Error flag - TEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA interrupt flag clear register (DMA_IFCR) - pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - /// Channel 1 Global interrupt clear - CGIF1: u1 = 0, - /// Channel 1 Transfer Complete clear - CTCIF1: u1 = 0, - /// Channel 1 Half Transfer clear - CHTIF1: u1 = 0, - /// Channel 1 Transfer Error clear - CTEIF1: u1 = 0, - /// Channel 2 Global interrupt clear - CGIF2: u1 = 0, - /// Channel 2 Transfer Complete clear - CTCIF2: u1 = 0, - /// Channel 2 Half Transfer clear - CHTIF2: u1 = 0, - /// Channel 2 Transfer Error clear - CTEIF2: u1 = 0, - /// Channel 3 Global interrupt clear - CGIF3: u1 = 0, - /// Channel 3 Transfer Complete clear - CTCIF3: u1 = 0, - /// Channel 3 Half Transfer clear - CHTIF3: u1 = 0, - /// Channel 3 Transfer Error clear - CTEIF3: u1 = 0, - /// Channel 4 Global interrupt clear - CGIF4: u1 = 0, - /// Channel 4 Transfer Complete clear - CTCIF4: u1 = 0, - /// Channel 4 Half Transfer clear - CHTIF4: u1 = 0, - /// Channel 4 Transfer Error clear - CTEIF4: u1 = 0, - /// Channel 5 Global interrupt clear - CGIF5: u1 = 0, - /// Channel 5 Transfer Complete clear - CTCIF5: u1 = 0, - /// Channel 5 Half Transfer clear - CHTIF5: u1 = 0, - /// Channel 5 Transfer Error clear - CTEIF5: u1 = 0, - /// Channel 6 Global interrupt clear - CGIF6: u1 = 0, - /// Channel 6 Transfer Complete clear - CTCIF6: u1 = 0, - /// Channel 6 Half Transfer clear - CHTIF6: u1 = 0, - /// Channel 6 Transfer Error clear - CTEIF6: u1 = 0, - /// Channel 7 Global interrupt clear - CGIF7: u1 = 0, - /// Channel 7 Transfer Complete clear - CTCIF7: u1 = 0, - /// Channel 7 Half Transfer clear - CHTIF7: u1 = 0, - /// Channel 7 Transfer Error clear - CTEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 number of data register - pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 peripheral address register - pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 1 memory address register - pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 number of data register - pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 peripheral address register - pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 2 memory address register - pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 number of data register - pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 peripheral address register - pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 3 memory address register - pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 number of data register - pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 peripheral address register - pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 4 memory address register - pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 number of data register - pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 peripheral address register - pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 5 memory address register - pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 number of data register - pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 peripheral address register - pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 6 memory address register - pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 number of data register - pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 peripheral address register - pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 7 memory address register - pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); -}; - -/// Secure digital input/output interface -pub const SDIO = extern struct { - pub const Address: u32 = 0x40018000; - - /// Bits 1:0 = PWRCTRL: Power supply control bits - pub const POWER = mmio(Address + 0x00000000, 32, packed struct { - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDI clock control register (SDIO_CLKCR) - pub const CLKCR = mmio(Address + 0x00000004, 32, packed struct { - /// Clock divide factor - CLKDIV: u8 = 0, - /// Clock enable bit - CLKEN: u1 = 0, - /// Power saving configuration bit - PWRSAV: u1 = 0, - /// Clock divider bypass enable bit - BYPASS: u1 = 0, - /// Wide bus mode enable bit - WIDBUS: u2 = 0, - /// SDIO_CK dephasing selection bit - NEGEDGE: u1 = 0, - /// HW Flow Control enable - HWFC_EN: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Bits 31:0 = : Command argument - pub const ARG = mmio(Address + 0x00000008, 32, packed struct { - /// Command argument - CMDARG: u32 = 0, - }); - - /// SDIO command register (SDIO_CMD) - pub const CMD = mmio(Address + 0x0000000c, 32, packed struct { - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDIO command register - pub const RESPCMD = mmio(Address + 0x00000010, 32, packed struct { - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Bits 31:0 = CARDSTATUS1 - pub const RESPI1 = mmio(Address + 0x00000014, 32, packed struct {}); - - /// Bits 31:0 = CARDSTATUS2 - pub const RESP2 = mmio(Address + 0x00000018, 32, packed struct {}); - - /// Bits 31:0 = CARDSTATUS3 - pub const RESP3 = mmio(Address + 0x0000001c, 32, packed struct {}); - - /// Bits 31:0 = CARDSTATUS4 - pub const RESP4 = mmio(Address + 0x00000020, 32, packed struct {}); - - /// Bits 31:0 = DATATIME: Data timeout period - pub const DTIMER = mmio(Address + 0x00000024, 32, packed struct { - /// Data timeout period - DATATIME: u32 = 0, - }); - - /// Bits 24:0 = DATALENGTH: Data length value - pub const DLEN = mmio(Address + 0x00000028, 32, packed struct { - /// Data length value - DATALENGTH: u25 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDIO data control register (SDIO_DCTRL) - pub const DCTRL = mmio(Address + 0x0000002c, 32, packed struct { - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Bits 24:0 = DATACOUNT: Data count value - pub const DCOUNT = mmio(Address + 0x00000030, 32, packed struct { - /// Data count value - DATACOUNT: u25 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDIO status register (SDIO_STA) - pub const STA = mmio(Address + 0x00000034, 32, packed struct { - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDIO interrupt clear register (SDIO_ICR) - pub const ICR = mmio(Address + 0x00000038, 32, packed struct { - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDIO mask register (SDIO_MASK) - pub const MASK = mmio(Address + 0x0000003c, 32, packed struct { - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read - /// from the FIFO - pub const FIFOCNT = mmio(Address + 0x00000048, 32, packed struct { - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// bits 31:0 = FIFOData: Receive and transmit FIFO data - pub const FIFO = mmio(Address + 0x00000080, 32, packed struct {}); -}; - -/// Real time clock -pub const RTC = extern struct { - pub const Address: u32 = 0x40002800; - - /// RTC Control Register High - pub const CRH = mmio(Address + 0x00000000, 32, packed struct { - /// Second interrupt Enable - SECIE: u1 = 0, - /// Alarm interrupt Enable - ALRIE: u1 = 0, - /// Overflow interrupt Enable - OWIE: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Control Register Low - pub const CRL = mmio(Address + 0x00000004, 32, packed struct { - /// Second Flag - SECF: u1 = 0, - /// Alarm Flag - ALRF: u1 = 0, - /// Overflow Flag - OWF: u1 = 0, - /// Registers Synchronized Flag - RSF: u1 = 0, - /// Configuration Flag - CNF: u1 = 0, - /// RTC operation OFF - RTOFF: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Prescaler Load Register High - pub const PRLH = mmio(Address + 0x00000008, 32, packed struct { - /// RTC Prescaler Load Register High - PRLH: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Prescaler Load Register Low - pub const PRLL = mmio(Address + 0x0000000c, 32, packed struct { - /// RTC Prescaler Divider Register Low - PRLL: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Prescaler Divider Register High - pub const DIVH = mmio(Address + 0x00000010, 32, packed struct { - /// RTC prescaler divider register high - DIVH: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Prescaler Divider Register Low - pub const DIVL = mmio(Address + 0x00000014, 32, packed struct { - /// RTC prescaler divider register Low - DIVL: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Counter Register High - pub const CNTH = mmio(Address + 0x00000018, 32, packed struct { - /// RTC counter register high - CNTH: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Counter Register Low - pub const CNTL = mmio(Address + 0x0000001c, 32, packed struct { - /// RTC counter register Low - CNTL: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Alarm Register High - pub const ALRH = mmio(Address + 0x00000020, 32, packed struct { - /// RTC alarm register high - ALRH: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Alarm Register Low - pub const ALRL = mmio(Address + 0x00000024, 32, packed struct { - /// RTC alarm register low - ALRL: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Backup registers -pub const BKP = extern struct { - pub const Address: u32 = 0x40006c04; - - /// Backup data register (BKP_DR) - pub const DR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Backup data - D1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Backup data - D2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Backup data - D3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR4 = mmio(Address + 0x0000000c, 32, packed struct { - /// Backup data - D4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR5 = mmio(Address + 0x00000010, 32, packed struct { - /// Backup data - D5: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR6 = mmio(Address + 0x00000014, 32, packed struct { - /// Backup data - D6: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR7 = mmio(Address + 0x00000018, 32, packed struct { - /// Backup data - D7: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR8 = mmio(Address + 0x0000001c, 32, packed struct { - /// Backup data - D8: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR9 = mmio(Address + 0x00000020, 32, packed struct { - /// Backup data - D9: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR10 = mmio(Address + 0x00000024, 32, packed struct { - /// Backup data - D10: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC clock calibration register (BKP_RTCCR) - pub const RTCCR = mmio(Address + 0x00000028, 32, packed struct { - /// Calibration value - CAL: u7 = 0, - /// Calibration Clock Output - CCO: u1 = 0, - /// Alarm or second output enable - ASOE: u1 = 0, - /// Alarm or second output selection - ASOS: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup control register (BKP_CR) - pub const CR = mmio(Address + 0x0000002c, 32, packed struct { - /// Tamper pin enable - TPE: u1 = 0, - /// Tamper pin active level - TPAL: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// BKP_CSR control/status register (BKP_CSR) - pub const CSR = mmio(Address + 0x00000030, 32, packed struct { - /// Clear Tamper event - CTE: u1 = 0, - /// Clear Tamper Interrupt - CTI: u1 = 0, - /// Tamper Pin interrupt enable - TPIE: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Tamper Event Flag - TEF: u1 = 0, - /// Tamper Interrupt Flag - TIF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR11 = mmio(Address + 0x0000003c, 32, packed struct { - /// Backup data - DR11: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR12 = mmio(Address + 0x00000040, 32, packed struct { - /// Backup data - DR12: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR13 = mmio(Address + 0x00000044, 32, packed struct { - /// Backup data - DR13: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR14 = mmio(Address + 0x00000048, 32, packed struct { - /// Backup data - D14: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR15 = mmio(Address + 0x0000004c, 32, packed struct { - /// Backup data - D15: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR16 = mmio(Address + 0x00000050, 32, packed struct { - /// Backup data - D16: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR17 = mmio(Address + 0x00000054, 32, packed struct { - /// Backup data - D17: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR18 = mmio(Address + 0x00000058, 32, packed struct { - /// Backup data - D18: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR19 = mmio(Address + 0x0000005c, 32, packed struct { - /// Backup data - D19: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR20 = mmio(Address + 0x00000060, 32, packed struct { - /// Backup data - D20: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR21 = mmio(Address + 0x00000064, 32, packed struct { - /// Backup data - D21: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR22 = mmio(Address + 0x00000068, 32, packed struct { - /// Backup data - D22: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR23 = mmio(Address + 0x0000006c, 32, packed struct { - /// Backup data - D23: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR24 = mmio(Address + 0x00000070, 32, packed struct { - /// Backup data - D24: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR25 = mmio(Address + 0x00000074, 32, packed struct { - /// Backup data - D25: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR26 = mmio(Address + 0x00000078, 32, packed struct { - /// Backup data - D26: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR27 = mmio(Address + 0x0000007c, 32, packed struct { - /// Backup data - D27: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR28 = mmio(Address + 0x00000080, 32, packed struct { - /// Backup data - D28: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR29 = mmio(Address + 0x00000084, 32, packed struct { - /// Backup data - D29: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR30 = mmio(Address + 0x00000088, 32, packed struct { - /// Backup data - D30: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR31 = mmio(Address + 0x0000008c, 32, packed struct { - /// Backup data - D31: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR32 = mmio(Address + 0x00000090, 32, packed struct { - /// Backup data - D32: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR33 = mmio(Address + 0x00000094, 32, packed struct { - /// Backup data - D33: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR34 = mmio(Address + 0x00000098, 32, packed struct { - /// Backup data - D34: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR35 = mmio(Address + 0x0000009c, 32, packed struct { - /// Backup data - D35: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR36 = mmio(Address + 0x000000a0, 32, packed struct { - /// Backup data - D36: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR37 = mmio(Address + 0x000000a4, 32, packed struct { - /// Backup data - D37: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR38 = mmio(Address + 0x000000a8, 32, packed struct { - /// Backup data - D38: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR39 = mmio(Address + 0x000000ac, 32, packed struct { - /// Backup data - D39: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR40 = mmio(Address + 0x000000b0, 32, packed struct { - /// Backup data - D40: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR41 = mmio(Address + 0x000000b4, 32, packed struct { - /// Backup data - D41: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR42 = mmio(Address + 0x000000b8, 32, packed struct { - /// Backup data - D42: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Independent watchdog -pub const IWDG = extern struct { - pub const Address: u32 = 0x40003000; - - /// Key register (IWDG_KR) - pub const KR = mmio(Address + 0x00000000, 32, packed struct { - /// Key value - KEY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Prescaler register (IWDG_PR) - pub const PR = mmio(Address + 0x00000004, 32, packed struct { - /// Prescaler divider - PR: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reload register (IWDG_RLR) - pub const RLR = mmio(Address + 0x00000008, 32, packed struct { - /// Watchdog counter reload value - RL: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register (IWDG_SR) - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - /// Watchdog prescaler value update - PVU: u1 = 0, - /// Watchdog counter reload value update - RVU: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Window watchdog -pub const WWDG = extern struct { - pub const Address: u32 = 0x40002c00; - - /// Control register (WWDG_CR) - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// 7-bit counter (MSB to LSB) - T: u7 = 0, - /// Activation bit - WDGA: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register (WWDG_CFR) - pub const CFR = mmio(Address + 0x00000004, 32, packed struct { - /// 7-bit window value - W: u7 = 0, - /// Timer Base - WDGTB: u2 = 0, - /// Early Wakeup Interrupt - EWI: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register (WWDG_SR) - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Early Wakeup Interrupt - EWI: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Advanced timer -pub const TIM1 = extern struct { - pub const Address: u32 = 0x40012c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - /// Output Idle state 2 - OIS2N: u1 = 0, - /// Output Idle state 3 - OIS3: u1 = 0, - /// Output Idle state 3 - OIS3N: u1 = 0, - /// Output Idle state 4 - OIS4: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - /// Output Compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - /// Output Compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - ICPCS: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PCS: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - OC4CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - /// Capture/Compare 2 complementary output enable - CC2NE: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - /// Capture/Compare 3 complementary output enable - CC3NE: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Advanced timer -pub const TIM8 = extern struct { - pub const Address: u32 = 0x40013400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - /// Output Idle state 2 - OIS2N: u1 = 0, - /// Output Idle state 3 - OIS3: u1 = 0, - /// Output Idle state 3 - OIS3N: u1 = 0, - /// Output Idle state 4 - OIS4: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - /// Output Compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - /// Output Compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - ICPCS: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PCS: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - OC4CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - /// Capture/Compare 2 complementary output enable - CC2NE: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - /// Capture/Compare 3 complementary output enable - CC3NE: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM2 = extern struct { - pub const Address: u32 = 0x40000000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM3 = extern struct { - pub const Address: u32 = 0x40000400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM4 = extern struct { - pub const Address: u32 = 0x40000800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM5 = extern struct { - pub const Address: u32 = 0x40000c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM9 = extern struct { - pub const Address: u32 = 0x40014c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM12 = extern struct { - pub const Address: u32 = 0x40001800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM10 = extern struct { - pub const Address: u32 = 0x40015000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - reserved1: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM11 = extern struct { - pub const Address: u32 = 0x40015400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - reserved1: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM13 = extern struct { - pub const Address: u32 = 0x40001c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - reserved1: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM14 = extern struct { - pub const Address: u32 = 0x40002000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - reserved1: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Basic timer -pub const TIM6 = extern struct { - pub const Address: u32 = 0x40001000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Basic timer -pub const TIM7 = extern struct { - pub const Address: u32 = 0x40001400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Inter integrated circuit -pub const I2C1 = extern struct { - pub const Address: u32 = 0x40005400; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Peripheral enable - PE: u1 = 0, - /// SMBus mode - SMBUS: u1 = 0, - reserved1: u1 = 0, - /// SMBus type - SMBTYPE: u1 = 0, - /// ARP enable - ENARP: u1 = 0, - /// PEC enable - ENPEC: u1 = 0, - /// General call enable - ENGC: u1 = 0, - /// Clock stretching disable (Slave mode) - NOSTRETCH: u1 = 0, - /// Start generation - START: u1 = 0, - /// Stop generation - STOP: u1 = 0, - /// Acknowledge enable - ACK: u1 = 0, - /// Acknowledge/PEC Position (for data reception) - POS: u1 = 0, - /// Packet error checking - PEC: u1 = 0, - /// SMBus alert - ALERT: u1 = 0, - reserved2: u1 = 0, - /// Software reset - SWRST: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Peripheral clock frequency - FREQ: u6 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Error interrupt enable - ITERREN: u1 = 0, - /// Event interrupt enable - ITEVTEN: u1 = 0, - /// Buffer interrupt enable - ITBUFEN: u1 = 0, - /// DMA requests enable - DMAEN: u1 = 0, - /// DMA last transfer - LAST: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Interface address - ADD0: u1 = 0, - /// Interface address - ADD7: u7 = 0, - /// Interface address - ADD10: u2 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Addressing mode (slave mode) - ADDMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - /// Dual addressing mode enable - ENDUAL: u1 = 0, - /// Interface address - ADD2: u7 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data register - pub const DR = mmio(Address + 0x00000010, 32, packed struct { - /// 8-bit data register - DR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register 1 - pub const SR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Start bit (Master mode) - SB: u1 = 0, - /// Address sent (master mode)/matched (slave mode) - ADDR: u1 = 0, - /// Byte transfer finished - BTF: u1 = 0, - /// 10-bit header sent (Master mode) - ADD10: u1 = 0, - /// Stop detection (slave mode) - STOPF: u1 = 0, - reserved1: u1 = 0, - /// Data register not empty (receivers) - RxNE: u1 = 0, - /// Data register empty (transmitters) - TxE: u1 = 0, - /// Bus error - BERR: u1 = 0, - /// Arbitration lost (master mode) - ARLO: u1 = 0, - /// Acknowledge failure - AF: u1 = 0, - /// Overrun/Underrun - OVR: u1 = 0, - /// PEC Error in reception - PECERR: u1 = 0, - reserved2: u1 = 0, - /// Timeout or Tlow error - TIMEOUT: u1 = 0, - /// SMBus alert - SMBALERT: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register 2 - pub const SR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Master/slave - MSL: u1 = 0, - /// Bus busy - BUSY: u1 = 0, - /// Transmitter/receiver - TRA: u1 = 0, - reserved1: u1 = 0, - /// General call address (Slave mode) - GENCALL: u1 = 0, - /// SMBus device default address (Slave mode) - SMBDEFAULT: u1 = 0, - /// SMBus host header (Slave mode) - SMBHOST: u1 = 0, - /// Dual flag (Slave mode) - DUALF: u1 = 0, - /// acket error checking register - PEC: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock control register - pub const CCR = mmio(Address + 0x0000001c, 32, packed struct { - /// Clock control register in Fast/Standard mode (Master mode) - CCR: u12 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Fast mode duty cycle - DUTY: u1 = 0, - /// I2C master mode selection - F_S: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TRISE register - pub const TRISE = mmio(Address + 0x00000020, 32, packed struct { - /// Maximum rise time in Fast/Standard mode (Master mode) - TRISE: u6 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Inter integrated circuit -pub const I2C2 = extern struct { - pub const Address: u32 = 0x40005800; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Peripheral enable - PE: u1 = 0, - /// SMBus mode - SMBUS: u1 = 0, - reserved1: u1 = 0, - /// SMBus type - SMBTYPE: u1 = 0, - /// ARP enable - ENARP: u1 = 0, - /// PEC enable - ENPEC: u1 = 0, - /// General call enable - ENGC: u1 = 0, - /// Clock stretching disable (Slave mode) - NOSTRETCH: u1 = 0, - /// Start generation - START: u1 = 0, - /// Stop generation - STOP: u1 = 0, - /// Acknowledge enable - ACK: u1 = 0, - /// Acknowledge/PEC Position (for data reception) - POS: u1 = 0, - /// Packet error checking - PEC: u1 = 0, - /// SMBus alert - ALERT: u1 = 0, - reserved2: u1 = 0, - /// Software reset - SWRST: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Peripheral clock frequency - FREQ: u6 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Error interrupt enable - ITERREN: u1 = 0, - /// Event interrupt enable - ITEVTEN: u1 = 0, - /// Buffer interrupt enable - ITBUFEN: u1 = 0, - /// DMA requests enable - DMAEN: u1 = 0, - /// DMA last transfer - LAST: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Interface address - ADD0: u1 = 0, - /// Interface address - ADD7: u7 = 0, - /// Interface address - ADD10: u2 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Addressing mode (slave mode) - ADDMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - /// Dual addressing mode enable - ENDUAL: u1 = 0, - /// Interface address - ADD2: u7 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data register - pub const DR = mmio(Address + 0x00000010, 32, packed struct { - /// 8-bit data register - DR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register 1 - pub const SR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Start bit (Master mode) - SB: u1 = 0, - /// Address sent (master mode)/matched (slave mode) - ADDR: u1 = 0, - /// Byte transfer finished - BTF: u1 = 0, - /// 10-bit header sent (Master mode) - ADD10: u1 = 0, - /// Stop detection (slave mode) - STOPF: u1 = 0, - reserved1: u1 = 0, - /// Data register not empty (receivers) - RxNE: u1 = 0, - /// Data register empty (transmitters) - TxE: u1 = 0, - /// Bus error - BERR: u1 = 0, - /// Arbitration lost (master mode) - ARLO: u1 = 0, - /// Acknowledge failure - AF: u1 = 0, - /// Overrun/Underrun - OVR: u1 = 0, - /// PEC Error in reception - PECERR: u1 = 0, - reserved2: u1 = 0, - /// Timeout or Tlow error - TIMEOUT: u1 = 0, - /// SMBus alert - SMBALERT: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register 2 - pub const SR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Master/slave - MSL: u1 = 0, - /// Bus busy - BUSY: u1 = 0, - /// Transmitter/receiver - TRA: u1 = 0, - reserved1: u1 = 0, - /// General call address (Slave mode) - GENCALL: u1 = 0, - /// SMBus device default address (Slave mode) - SMBDEFAULT: u1 = 0, - /// SMBus host header (Slave mode) - SMBHOST: u1 = 0, - /// Dual flag (Slave mode) - DUALF: u1 = 0, - /// acket error checking register - PEC: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock control register - pub const CCR = mmio(Address + 0x0000001c, 32, packed struct { - /// Clock control register in Fast/Standard mode (Master mode) - CCR: u12 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Fast mode duty cycle - DUTY: u1 = 0, - /// I2C master mode selection - F_S: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TRISE register - pub const TRISE = mmio(Address + 0x00000020, 32, packed struct { - /// Maximum rise time in Fast/Standard mode (Master mode) - TRISE: u6 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface -pub const SPI1 = extern struct { - pub const Address: u32 = 0x40013000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// Data frame format - DFF: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { +// this file is generated by regz +// +// device: STM32F103xx + +pub const registers = struct { + /// Flexible static memory controller + pub const FSMC = struct { + pub const base_address = 0xa0000000; + + /// address: 0xa0000000 + /// SRAM/NOR-Flash chip-select control register + /// 1 + pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + reserved1: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0xa0000004 + /// SRAM/NOR-Flash chip-select timing register + /// 1 + pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x4); + + /// address: 0xa0000008 + /// SRAM/NOR-Flash chip-select control register + /// 2 + pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x8); + + /// address: 0xa000000c + /// SRAM/NOR-Flash chip-select timing register + /// 2 + pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0xa0000010 + /// SRAM/NOR-Flash chip-select control register + /// 3 + pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0xa0000014 + /// SRAM/NOR-Flash chip-select timing register + /// 3 + pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0xa0000018 + /// SRAM/NOR-Flash chip-select control register + /// 4 + pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x18); + + /// address: 0xa000001c + /// SRAM/NOR-Flash chip-select timing register + /// 4 + pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x1c); + + /// address: 0xa0000060 + /// PC Card/NAND Flash control register + /// 2 + pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x60); + + /// address: 0xa0000064 + /// FIFO status and interrupt register + /// 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x64); + + /// address: 0xa0000068 + /// Common memory space timing register + /// 2 + pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x68); + + /// address: 0xa000006c + /// Attribute memory space timing register + /// 2 + pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Attribute memory x setup + /// time + ATTSETx: u8, + /// Attribute memory x wait + /// time + ATTWAITx: u8, + /// Attribute memory x hold + /// time + ATTHOLDx: u8, + /// Attribute memory x databus HiZ + /// time + ATTHIZx: u8, + }), base_address + 0x6c); + + /// address: 0xa0000074 + /// ECC result register 2 + pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ECC result + ECCx: u32, + }), base_address + 0x74); + + /// address: 0xa0000080 + /// PC Card/NAND Flash control register + /// 3 + pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x80); + + /// address: 0xa0000084 + /// FIFO status and interrupt register + /// 3 + pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x84); + + /// address: 0xa0000088 + /// Common memory space timing register + /// 3 + pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x88); + + /// address: 0xa000008c + /// Attribute memory space timing register + /// 3 + pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x8c); + + /// address: 0xa0000094 + /// ECC result register 3 + pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ECCx + ECCx: u32, + }), base_address + 0x94); + + /// address: 0xa00000a0 + /// PC Card/NAND Flash control register + /// 4 + pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0xa0); + + /// address: 0xa00000a4 + /// FIFO status and interrupt register + /// 4 + pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xa4); + + /// address: 0xa00000a8 + /// Common memory space timing register + /// 4 + pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0xa8); + + /// address: 0xa00000ac + /// Attribute memory space timing register + /// 4 + pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0xac); + + /// address: 0xa00000b0 + /// I/O space timing register 4 + pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), base_address + 0xb0); + + /// address: 0xa0000104 + /// SRAM/NOR-Flash write timing registers + /// 1 + pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x104); + + /// address: 0xa000010c + /// SRAM/NOR-Flash write timing registers + /// 2 + pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x10c); + + /// address: 0xa0000114 + /// SRAM/NOR-Flash write timing registers + /// 3 + pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x114); + + /// address: 0xa000011c + /// SRAM/NOR-Flash write timing registers + /// 4 + pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x11c); + }; + /// Power control + pub const PWR = struct { + pub const base_address = 0x40007000; + + /// address: 0x40007000 + /// Power control register + /// (PWR_CR) + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Power Deep Sleep + LPDS: u1, + /// Power Down Deep Sleep + PDDS: u1, + /// Clear Wake-up Flag + CWUF: u1, + /// Clear STANDBY Flag + CSBF: u1, + /// Power Voltage Detector + /// Enable + PVDE: u1, + /// PVD Level Selection + PLS: u3, + /// Disable Backup Domain write + /// protection + DBP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40007004 + /// Power control register + /// (PWR_CR) + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Wake-Up Flag + WUF: u1, + /// STANDBY Flag + SBF: u1, + /// PVD Output + PVDO: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Enable WKUP pin + EWUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x4); + }; + /// Reset and clock control + pub const RCC = struct { + pub const base_address = 0x40021000; + + /// address: 0x40021000 + /// Clock control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Internal High Speed clock + /// enable + HSION: u1, + /// Internal High Speed clock ready + /// flag + HSIRDY: u1, + reserved0: u1, + /// Internal High Speed clock + /// trimming + HSITRIM: u5, + /// Internal High Speed clock + /// Calibration + HSICAL: u8, + /// External High Speed clock + /// enable + HSEON: u1, + /// External High Speed clock ready + /// flag + HSERDY: u1, + /// External High Speed clock + /// Bypass + HSEBYP: u1, + /// Clock Security System + /// enable + CSSON: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40021004 + /// Clock configuration register + /// (RCC_CFGR) + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// System clock Switch + SW: u2, + /// System Clock Switch Status + SWS: u2, + /// AHB prescaler + HPRE: u4, + /// APB Low speed prescaler + /// (APB1) + PPRE1: u3, + /// APB High speed prescaler + /// (APB2) + PPRE2: u3, + /// ADC prescaler + ADCPRE: u2, + /// PLL entry clock source + PLLSRC: u1, + /// HSE divider for PLL entry + PLLXTPRE: u1, + /// PLL Multiplication Factor + PLLMUL: u4, + /// USB OTG FS prescaler + OTGFSPRE: u1, + reserved0: u1, + /// Microcontroller clock + /// output + MCO: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40021008 + /// Clock interrupt register + /// (RCC_CIR) + pub const CIR = @intToPtr(*volatile Mmio(32, packed struct{ + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + reserved0: u1, + reserved1: u1, + /// Clock Security System Interrupt + /// flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + reserved5: u1, + reserved6: u1, + /// Clock security system interrupt + /// clear + CSSC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4002100c + /// APB2 peripheral reset register + /// (RCC_APB2RSTR) + pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function I/O + /// reset + AFIORST: u1, + reserved0: u1, + /// IO port A reset + IOPARST: u1, + /// IO port B reset + IOPBRST: u1, + /// IO port C reset + IOPCRST: u1, + /// IO port D reset + IOPDRST: u1, + /// IO port E reset + IOPERST: u1, + /// IO port F reset + IOPFRST: u1, + /// IO port G reset + IOPGRST: u1, + /// ADC 1 interface reset + ADC1RST: u1, + /// ADC 2 interface reset + ADC2RST: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + /// ADC 3 interface reset + ADC3RST: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TIM9 timer reset + TIM9RST: u1, + /// TIM10 timer reset + TIM10RST: u1, + /// TIM11 timer reset + TIM11RST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0xc); + + /// address: 0x40021010 + /// APB1 peripheral reset register + /// (RCC_APB1RSTR) + pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 4 reset + TIM4RST: u1, + /// Timer 5 reset + TIM5RST: u1, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + /// Timer 12 reset + TIM12RST: u1, + /// Timer 13 reset + TIM13RST: u1, + /// Timer 14 reset + TIM14RST: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog reset + WWDGRST: u1, + reserved2: u1, + reserved3: u1, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved4: u1, + /// USART 2 reset + USART2RST: u1, + /// USART 3 reset + USART3RST: u1, + /// UART 4 reset + UART4RST: u1, + /// UART 5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved5: u1, + /// CAN reset + CANRST: u1, + reserved6: u1, + /// Backup interface reset + BKPRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40021014 + /// AHB Peripheral Clock enable register + /// (RCC_AHBENR) + pub const AHBENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock + /// enable + SRAMEN: u1, + reserved0: u1, + /// FLITF clock enable + FLITFEN: u1, + reserved1: u1, + /// CRC clock enable + CRCEN: u1, + reserved2: u1, + /// FSMC clock enable + FSMCEN: u1, + reserved3: u1, + /// SDIO clock enable + SDIOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x40021018 + /// APB2 peripheral clock enable register + /// (RCC_APB2ENR) + pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function I/O clock + /// enable + AFIOEN: u1, + reserved0: u1, + /// I/O port A clock enable + IOPAEN: u1, + /// I/O port B clock enable + IOPBEN: u1, + /// I/O port C clock enable + IOPCEN: u1, + /// I/O port D clock enable + IOPDEN: u1, + /// I/O port E clock enable + IOPEEN: u1, + /// I/O port F clock enable + IOPFEN: u1, + /// I/O port G clock enable + IOPGEN: u1, + /// ADC 1 interface clock + /// enable + ADC1EN: u1, + /// ADC 2 interface clock + /// enable + ADC2EN: u1, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + /// TIM8 Timer clock enable + TIM8EN: u1, + /// USART1 clock enable + USART1EN: u1, + /// ADC3 interface clock + /// enable + ADC3EN: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TIM9 Timer clock enable + TIM9EN: u1, + /// TIM10 Timer clock enable + TIM10EN: u1, + /// TIM11 Timer clock enable + TIM11EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x18); + + /// address: 0x4002101c + /// APB1 peripheral clock enable register + /// (RCC_APB1ENR) + pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + /// Timer 5 clock enable + TIM5EN: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + /// Timer 12 clock enable + TIM12EN: u1, + /// Timer 13 clock enable + TIM13EN: u1, + /// Timer 14 clock enable + TIM14EN: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog clock + /// enable + WWDGEN: u1, + reserved2: u1, + reserved3: u1, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved4: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// UART 4 clock enable + UART4EN: u1, + /// UART 5 clock enable + UART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved5: u1, + /// CAN clock enable + CANEN: u1, + reserved6: u1, + /// Backup interface clock + /// enable + BKPEN: u1, + /// Power interface clock + /// enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x1c); + + /// address: 0x40021020 + /// Backup domain control register + /// (RCC_BDCR) + pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// External Low Speed oscillator + /// enable + LSEON: u1, + /// External Low Speed oscillator + /// ready + LSERDY: u1, + /// External Low Speed oscillator + /// bypass + LSEBYP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RTC clock source selection + RTCSEL: u2, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software + /// reset + BDRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x20); + + /// address: 0x40021024 + /// Control/status register + /// (RCC_CSR) + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Internal low speed oscillator + /// enable + LSION: u1, + /// Internal low speed oscillator + /// ready + LSIRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Remove reset flag + RMVF: u1, + reserved22: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset + /// flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), base_address + 0x24); + }; + /// General purpose I/O + pub const GPIOA = struct { + pub const base_address = 0x40010800; + + /// address: 0x40010800 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40010804 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40010808 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001080c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40010810 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40010814 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40010818 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOB = struct { + pub const base_address = 0x40010c00; + + /// address: 0x40010c00 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40010c04 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40010c08 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40010c0c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40010c10 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40010c14 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40010c18 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOC = struct { + pub const base_address = 0x40011000; + + /// address: 0x40011000 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40011004 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40011008 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001100c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011010 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40011014 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40011018 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOD = struct { + pub const base_address = 0x40011400; + + /// address: 0x40011400 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40011404 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40011408 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001140c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011410 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40011414 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40011418 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOE = struct { + pub const base_address = 0x40011800; + + /// address: 0x40011800 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40011804 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40011808 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001180c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011810 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40011814 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40011818 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOF = struct { + pub const base_address = 0x40011c00; + + /// address: 0x40011c00 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40011c04 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40011c08 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40011c0c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011c10 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40011c14 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40011c18 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOG = struct { + pub const base_address = 0x40012000; + + /// address: 0x40012000 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40012004 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40012008 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001200c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40012010 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40012014 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40012018 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + /// Alternate function I/O + pub const AFIO = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// Event Control Register + /// (AFIO_EVCR) + pub const EVCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin selection + PIN: u4, + /// Port selection + PORT: u3, + /// Event Output Enable + EVOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40010004 + /// AF remap and debug I/O configuration + /// register (AFIO_MAPR) + pub const MAPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SPI1 remapping + SPI1_REMAP: u1, + /// I2C1 remapping + I2C1_REMAP: u1, + /// USART1 remapping + USART1_REMAP: u1, + /// USART2 remapping + USART2_REMAP: u1, + /// USART3 remapping + USART3_REMAP: u2, + /// TIM1 remapping + TIM1_REMAP: u2, + /// TIM2 remapping + TIM2_REMAP: u2, + /// TIM3 remapping + TIM3_REMAP: u2, + /// TIM4 remapping + TIM4_REMAP: u1, + /// CAN1 remapping + CAN_REMAP: u2, + /// Port D0/Port D1 mapping on + /// OSCIN/OSCOUT + PD01_REMAP: u1, + /// Set and cleared by + /// software + TIM5CH4_IREMAP: u1, + /// ADC 1 External trigger injected + /// conversion remapping + ADC1_ETRGINJ_REMAP: u1, + /// ADC 1 external trigger regular + /// conversion remapping + ADC1_ETRGREG_REMAP: u1, + /// ADC 2 external trigger injected + /// conversion remapping + ADC2_ETRGINJ_REMAP: u1, + /// ADC 2 external trigger regular + /// conversion remapping + ADC2_ETRGREG_REMAP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Serial wire JTAG + /// configuration + SWJ_CFG: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40010008 + /// External interrupt configuration register 1 + /// (AFIO_EXTICR1) + pub const EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI0 configuration + EXTI0: u4, + /// EXTI1 configuration + EXTI1: u4, + /// EXTI2 configuration + EXTI2: u4, + /// EXTI3 configuration + EXTI3: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001000c + /// External interrupt configuration register 2 + /// (AFIO_EXTICR2) + pub const EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI4 configuration + EXTI4: u4, + /// EXTI5 configuration + EXTI5: u4, + /// EXTI6 configuration + EXTI6: u4, + /// EXTI7 configuration + EXTI7: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40010010 + /// External interrupt configuration register 3 + /// (AFIO_EXTICR3) + pub const EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI8 configuration + EXTI8: u4, + /// EXTI9 configuration + EXTI9: u4, + /// EXTI10 configuration + EXTI10: u4, + /// EXTI11 configuration + EXTI11: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40010014 + /// External interrupt configuration register 4 + /// (AFIO_EXTICR4) + pub const EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI12 configuration + EXTI12: u4, + /// EXTI13 configuration + EXTI13: u4, + /// EXTI14 configuration + EXTI14: u4, + /// EXTI15 configuration + EXTI15: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x4001001c + /// AF remap and debug I/O configuration + /// register + pub const MAPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// TIM9 remapping + TIM9_REMAP: u1, + /// TIM10 remapping + TIM10_REMAP: u1, + /// TIM11 remapping + TIM11_REMAP: u1, + /// TIM13 remapping + TIM13_REMAP: u1, + /// TIM14 remapping + TIM14_REMAP: u1, + /// NADV connect/disconnect + FSMC_NADV: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c); + }; + /// EXTI + pub const EXTI = struct { + pub const base_address = 0x40010400; + + /// address: 0x40010400 + /// Interrupt mask register + /// (EXTI_IMR) + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interrupt Mask on line 0 + MR0: u1, + /// Interrupt Mask on line 1 + MR1: u1, + /// Interrupt Mask on line 2 + MR2: u1, + /// Interrupt Mask on line 3 + MR3: u1, + /// Interrupt Mask on line 4 + MR4: u1, + /// Interrupt Mask on line 5 + MR5: u1, + /// Interrupt Mask on line 6 + MR6: u1, + /// Interrupt Mask on line 7 + MR7: u1, + /// Interrupt Mask on line 8 + MR8: u1, + /// Interrupt Mask on line 9 + MR9: u1, + /// Interrupt Mask on line 10 + MR10: u1, + /// Interrupt Mask on line 11 + MR11: u1, + /// Interrupt Mask on line 12 + MR12: u1, + /// Interrupt Mask on line 13 + MR13: u1, + /// Interrupt Mask on line 14 + MR14: u1, + /// Interrupt Mask on line 15 + MR15: u1, + /// Interrupt Mask on line 16 + MR16: u1, + /// Interrupt Mask on line 17 + MR17: u1, + /// Interrupt Mask on line 18 + MR18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x0); + + /// address: 0x40010404 + /// Event mask register (EXTI_EMR) + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Event Mask on line 0 + MR0: u1, + /// Event Mask on line 1 + MR1: u1, + /// Event Mask on line 2 + MR2: u1, + /// Event Mask on line 3 + MR3: u1, + /// Event Mask on line 4 + MR4: u1, + /// Event Mask on line 5 + MR5: u1, + /// Event Mask on line 6 + MR6: u1, + /// Event Mask on line 7 + MR7: u1, + /// Event Mask on line 8 + MR8: u1, + /// Event Mask on line 9 + MR9: u1, + /// Event Mask on line 10 + MR10: u1, + /// Event Mask on line 11 + MR11: u1, + /// Event Mask on line 12 + MR12: u1, + /// Event Mask on line 13 + MR13: u1, + /// Event Mask on line 14 + MR14: u1, + /// Event Mask on line 15 + MR15: u1, + /// Event Mask on line 16 + MR16: u1, + /// Event Mask on line 17 + MR17: u1, + /// Event Mask on line 18 + MR18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x4); + + /// address: 0x40010408 + /// Rising Trigger selection register + /// (EXTI_RTSR) + pub const RTSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rising trigger event configuration of + /// line 0 + TR0: u1, + /// Rising trigger event configuration of + /// line 1 + TR1: u1, + /// Rising trigger event configuration of + /// line 2 + TR2: u1, + /// Rising trigger event configuration of + /// line 3 + TR3: u1, + /// Rising trigger event configuration of + /// line 4 + TR4: u1, + /// Rising trigger event configuration of + /// line 5 + TR5: u1, + /// Rising trigger event configuration of + /// line 6 + TR6: u1, + /// Rising trigger event configuration of + /// line 7 + TR7: u1, + /// Rising trigger event configuration of + /// line 8 + TR8: u1, + /// Rising trigger event configuration of + /// line 9 + TR9: u1, + /// Rising trigger event configuration of + /// line 10 + TR10: u1, + /// Rising trigger event configuration of + /// line 11 + TR11: u1, + /// Rising trigger event configuration of + /// line 12 + TR12: u1, + /// Rising trigger event configuration of + /// line 13 + TR13: u1, + /// Rising trigger event configuration of + /// line 14 + TR14: u1, + /// Rising trigger event configuration of + /// line 15 + TR15: u1, + /// Rising trigger event configuration of + /// line 16 + TR16: u1, + /// Rising trigger event configuration of + /// line 17 + TR17: u1, + /// Rising trigger event configuration of + /// line 18 + TR18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x8); + + /// address: 0x4001040c + /// Falling Trigger selection register + /// (EXTI_FTSR) + pub const FTSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Falling trigger event configuration of + /// line 0 + TR0: u1, + /// Falling trigger event configuration of + /// line 1 + TR1: u1, + /// Falling trigger event configuration of + /// line 2 + TR2: u1, + /// Falling trigger event configuration of + /// line 3 + TR3: u1, + /// Falling trigger event configuration of + /// line 4 + TR4: u1, + /// Falling trigger event configuration of + /// line 5 + TR5: u1, + /// Falling trigger event configuration of + /// line 6 + TR6: u1, + /// Falling trigger event configuration of + /// line 7 + TR7: u1, + /// Falling trigger event configuration of + /// line 8 + TR8: u1, + /// Falling trigger event configuration of + /// line 9 + TR9: u1, + /// Falling trigger event configuration of + /// line 10 + TR10: u1, + /// Falling trigger event configuration of + /// line 11 + TR11: u1, + /// Falling trigger event configuration of + /// line 12 + TR12: u1, + /// Falling trigger event configuration of + /// line 13 + TR13: u1, + /// Falling trigger event configuration of + /// line 14 + TR14: u1, + /// Falling trigger event configuration of + /// line 15 + TR15: u1, + /// Falling trigger event configuration of + /// line 16 + TR16: u1, + /// Falling trigger event configuration of + /// line 17 + TR17: u1, + /// Falling trigger event configuration of + /// line 18 + TR18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xc); + + /// address: 0x40010410 + /// Software interrupt event register + /// (EXTI_SWIER) + pub const SWIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Software Interrupt on line + /// 0 + SWIER0: u1, + /// Software Interrupt on line + /// 1 + SWIER1: u1, + /// Software Interrupt on line + /// 2 + SWIER2: u1, + /// Software Interrupt on line + /// 3 + SWIER3: u1, + /// Software Interrupt on line + /// 4 + SWIER4: u1, + /// Software Interrupt on line + /// 5 + SWIER5: u1, + /// Software Interrupt on line + /// 6 + SWIER6: u1, + /// Software Interrupt on line + /// 7 + SWIER7: u1, + /// Software Interrupt on line + /// 8 + SWIER8: u1, + /// Software Interrupt on line + /// 9 + SWIER9: u1, + /// Software Interrupt on line + /// 10 + SWIER10: u1, + /// Software Interrupt on line + /// 11 + SWIER11: u1, + /// Software Interrupt on line + /// 12 + SWIER12: u1, + /// Software Interrupt on line + /// 13 + SWIER13: u1, + /// Software Interrupt on line + /// 14 + SWIER14: u1, + /// Software Interrupt on line + /// 15 + SWIER15: u1, + /// Software Interrupt on line + /// 16 + SWIER16: u1, + /// Software Interrupt on line + /// 17 + SWIER17: u1, + /// Software Interrupt on line + /// 18 + SWIER18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x10); + + /// address: 0x40010414 + /// Pending register (EXTI_PR) + pub const PR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pending bit 0 + PR0: u1, + /// Pending bit 1 + PR1: u1, + /// Pending bit 2 + PR2: u1, + /// Pending bit 3 + PR3: u1, + /// Pending bit 4 + PR4: u1, + /// Pending bit 5 + PR5: u1, + /// Pending bit 6 + PR6: u1, + /// Pending bit 7 + PR7: u1, + /// Pending bit 8 + PR8: u1, + /// Pending bit 9 + PR9: u1, + /// Pending bit 10 + PR10: u1, + /// Pending bit 11 + PR11: u1, + /// Pending bit 12 + PR12: u1, + /// Pending bit 13 + PR13: u1, + /// Pending bit 14 + PR14: u1, + /// Pending bit 15 + PR15: u1, + /// Pending bit 16 + PR16: u1, + /// Pending bit 17 + PR17: u1, + /// Pending bit 18 + PR18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x14); + }; + /// DMA controller + pub const DMA1 = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020000 + /// DMA interrupt status register + /// (DMA_ISR) + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// flag + GIF1: u1, + /// Channel 1 Transfer Complete + /// flag + TCIF1: u1, + /// Channel 1 Half Transfer Complete + /// flag + HTIF1: u1, + /// Channel 1 Transfer Error + /// flag + TEIF1: u1, + /// Channel 2 Global interrupt + /// flag + GIF2: u1, + /// Channel 2 Transfer Complete + /// flag + TCIF2: u1, + /// Channel 2 Half Transfer Complete + /// flag + HTIF2: u1, + /// Channel 2 Transfer Error + /// flag + TEIF2: u1, + /// Channel 3 Global interrupt + /// flag + GIF3: u1, + /// Channel 3 Transfer Complete + /// flag + TCIF3: u1, + /// Channel 3 Half Transfer Complete + /// flag + HTIF3: u1, + /// Channel 3 Transfer Error + /// flag + TEIF3: u1, + /// Channel 4 Global interrupt + /// flag + GIF4: u1, + /// Channel 4 Transfer Complete + /// flag + TCIF4: u1, + /// Channel 4 Half Transfer Complete + /// flag + HTIF4: u1, + /// Channel 4 Transfer Error + /// flag + TEIF4: u1, + /// Channel 5 Global interrupt + /// flag + GIF5: u1, + /// Channel 5 Transfer Complete + /// flag + TCIF5: u1, + /// Channel 5 Half Transfer Complete + /// flag + HTIF5: u1, + /// Channel 5 Transfer Error + /// flag + TEIF5: u1, + /// Channel 6 Global interrupt + /// flag + GIF6: u1, + /// Channel 6 Transfer Complete + /// flag + TCIF6: u1, + /// Channel 6 Half Transfer Complete + /// flag + HTIF6: u1, + /// Channel 6 Transfer Error + /// flag + TEIF6: u1, + /// Channel 7 Global interrupt + /// flag + GIF7: u1, + /// Channel 7 Transfer Complete + /// flag + TCIF7: u1, + /// Channel 7 Half Transfer Complete + /// flag + HTIF7: u1, + /// Channel 7 Transfer Error + /// flag + TEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40020004 + /// DMA interrupt flag clear register + /// (DMA_IFCR) + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// clear + CGIF1: u1, + /// Channel 1 Transfer Complete + /// clear + CTCIF1: u1, + /// Channel 1 Half Transfer + /// clear + CHTIF1: u1, + /// Channel 1 Transfer Error + /// clear + CTEIF1: u1, + /// Channel 2 Global interrupt + /// clear + CGIF2: u1, + /// Channel 2 Transfer Complete + /// clear + CTCIF2: u1, + /// Channel 2 Half Transfer + /// clear + CHTIF2: u1, + /// Channel 2 Transfer Error + /// clear + CTEIF2: u1, + /// Channel 3 Global interrupt + /// clear + CGIF3: u1, + /// Channel 3 Transfer Complete + /// clear + CTCIF3: u1, + /// Channel 3 Half Transfer + /// clear + CHTIF3: u1, + /// Channel 3 Transfer Error + /// clear + CTEIF3: u1, + /// Channel 4 Global interrupt + /// clear + CGIF4: u1, + /// Channel 4 Transfer Complete + /// clear + CTCIF4: u1, + /// Channel 4 Half Transfer + /// clear + CHTIF4: u1, + /// Channel 4 Transfer Error + /// clear + CTEIF4: u1, + /// Channel 5 Global interrupt + /// clear + CGIF5: u1, + /// Channel 5 Transfer Complete + /// clear + CTCIF5: u1, + /// Channel 5 Half Transfer + /// clear + CHTIF5: u1, + /// Channel 5 Transfer Error + /// clear + CTEIF5: u1, + /// Channel 6 Global interrupt + /// clear + CGIF6: u1, + /// Channel 6 Transfer Complete + /// clear + CTCIF6: u1, + /// Channel 6 Half Transfer + /// clear + CHTIF6: u1, + /// Channel 6 Transfer Error + /// clear + CTEIF6: u1, + /// Channel 7 Global interrupt + /// clear + CGIF7: u1, + /// Channel 7 Transfer Complete + /// clear + CTCIF7: u1, + /// Channel 7 Half Transfer + /// clear + CHTIF7: u1, + /// Channel 7 Transfer Error + /// clear + CTEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40020008 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x8); + + /// address: 0x4002000c + /// DMA channel 1 number of data + /// register + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40020010 + /// DMA channel 1 peripheral address + /// register + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x10); + + /// address: 0x40020014 + /// DMA channel 1 memory address + /// register + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x14); + + /// address: 0x4002001c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40020020 + /// DMA channel 2 number of data + /// register + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40020024 + /// DMA channel 2 peripheral address + /// register + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x24); + + /// address: 0x40020028 + /// DMA channel 2 memory address + /// register + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x28); + + /// address: 0x40020030 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x30); + + /// address: 0x40020034 + /// DMA channel 3 number of data + /// register + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40020038 + /// DMA channel 3 peripheral address + /// register + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x38); + + /// address: 0x4002003c + /// DMA channel 3 memory address + /// register + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x3c); + + /// address: 0x40020044 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x44); + + /// address: 0x40020048 + /// DMA channel 4 number of data + /// register + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002004c + /// DMA channel 4 peripheral address + /// register + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x4c); + + /// address: 0x40020050 + /// DMA channel 4 memory address + /// register + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x50); + + /// address: 0x40020058 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x58); + + /// address: 0x4002005c + /// DMA channel 5 number of data + /// register + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40020060 + /// DMA channel 5 peripheral address + /// register + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40020064 + /// DMA channel 5 memory address + /// register + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x64); + + /// address: 0x4002006c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x6c); + + /// address: 0x40020070 + /// DMA channel 6 number of data + /// register + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x70); + + /// address: 0x40020074 + /// DMA channel 6 peripheral address + /// register + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x74); + + /// address: 0x40020078 + /// DMA channel 6 memory address + /// register + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x78); + + /// address: 0x40020080 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40020084 + /// DMA channel 7 number of data + /// register + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x40020088 + /// DMA channel 7 peripheral address + /// register + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x88); + + /// address: 0x4002008c + /// DMA channel 7 memory address + /// register + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x8c); + }; + pub const DMA2 = struct { + pub const base_address = 0x40020400; + + /// address: 0x40020400 + /// DMA interrupt status register + /// (DMA_ISR) + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// flag + GIF1: u1, + /// Channel 1 Transfer Complete + /// flag + TCIF1: u1, + /// Channel 1 Half Transfer Complete + /// flag + HTIF1: u1, + /// Channel 1 Transfer Error + /// flag + TEIF1: u1, + /// Channel 2 Global interrupt + /// flag + GIF2: u1, + /// Channel 2 Transfer Complete + /// flag + TCIF2: u1, + /// Channel 2 Half Transfer Complete + /// flag + HTIF2: u1, + /// Channel 2 Transfer Error + /// flag + TEIF2: u1, + /// Channel 3 Global interrupt + /// flag + GIF3: u1, + /// Channel 3 Transfer Complete + /// flag + TCIF3: u1, + /// Channel 3 Half Transfer Complete + /// flag + HTIF3: u1, + /// Channel 3 Transfer Error + /// flag + TEIF3: u1, + /// Channel 4 Global interrupt + /// flag + GIF4: u1, + /// Channel 4 Transfer Complete + /// flag + TCIF4: u1, + /// Channel 4 Half Transfer Complete + /// flag + HTIF4: u1, + /// Channel 4 Transfer Error + /// flag + TEIF4: u1, + /// Channel 5 Global interrupt + /// flag + GIF5: u1, + /// Channel 5 Transfer Complete + /// flag + TCIF5: u1, + /// Channel 5 Half Transfer Complete + /// flag + HTIF5: u1, + /// Channel 5 Transfer Error + /// flag + TEIF5: u1, + /// Channel 6 Global interrupt + /// flag + GIF6: u1, + /// Channel 6 Transfer Complete + /// flag + TCIF6: u1, + /// Channel 6 Half Transfer Complete + /// flag + HTIF6: u1, + /// Channel 6 Transfer Error + /// flag + TEIF6: u1, + /// Channel 7 Global interrupt + /// flag + GIF7: u1, + /// Channel 7 Transfer Complete + /// flag + TCIF7: u1, + /// Channel 7 Half Transfer Complete + /// flag + HTIF7: u1, + /// Channel 7 Transfer Error + /// flag + TEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40020404 + /// DMA interrupt flag clear register + /// (DMA_IFCR) + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// clear + CGIF1: u1, + /// Channel 1 Transfer Complete + /// clear + CTCIF1: u1, + /// Channel 1 Half Transfer + /// clear + CHTIF1: u1, + /// Channel 1 Transfer Error + /// clear + CTEIF1: u1, + /// Channel 2 Global interrupt + /// clear + CGIF2: u1, + /// Channel 2 Transfer Complete + /// clear + CTCIF2: u1, + /// Channel 2 Half Transfer + /// clear + CHTIF2: u1, + /// Channel 2 Transfer Error + /// clear + CTEIF2: u1, + /// Channel 3 Global interrupt + /// clear + CGIF3: u1, + /// Channel 3 Transfer Complete + /// clear + CTCIF3: u1, + /// Channel 3 Half Transfer + /// clear + CHTIF3: u1, + /// Channel 3 Transfer Error + /// clear + CTEIF3: u1, + /// Channel 4 Global interrupt + /// clear + CGIF4: u1, + /// Channel 4 Transfer Complete + /// clear + CTCIF4: u1, + /// Channel 4 Half Transfer + /// clear + CHTIF4: u1, + /// Channel 4 Transfer Error + /// clear + CTEIF4: u1, + /// Channel 5 Global interrupt + /// clear + CGIF5: u1, + /// Channel 5 Transfer Complete + /// clear + CTCIF5: u1, + /// Channel 5 Half Transfer + /// clear + CHTIF5: u1, + /// Channel 5 Transfer Error + /// clear + CTEIF5: u1, + /// Channel 6 Global interrupt + /// clear + CGIF6: u1, + /// Channel 6 Transfer Complete + /// clear + CTCIF6: u1, + /// Channel 6 Half Transfer + /// clear + CHTIF6: u1, + /// Channel 6 Transfer Error + /// clear + CTEIF6: u1, + /// Channel 7 Global interrupt + /// clear + CGIF7: u1, + /// Channel 7 Transfer Complete + /// clear + CTCIF7: u1, + /// Channel 7 Half Transfer + /// clear + CHTIF7: u1, + /// Channel 7 Transfer Error + /// clear + CTEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40020408 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x8); + + /// address: 0x4002040c + /// DMA channel 1 number of data + /// register + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40020410 + /// DMA channel 1 peripheral address + /// register + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x10); + + /// address: 0x40020414 + /// DMA channel 1 memory address + /// register + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x14); + + /// address: 0x4002041c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40020420 + /// DMA channel 2 number of data + /// register + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40020424 + /// DMA channel 2 peripheral address + /// register + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x24); + + /// address: 0x40020428 + /// DMA channel 2 memory address + /// register + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x28); + + /// address: 0x40020430 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x30); + + /// address: 0x40020434 + /// DMA channel 3 number of data + /// register + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40020438 + /// DMA channel 3 peripheral address + /// register + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x38); + + /// address: 0x4002043c + /// DMA channel 3 memory address + /// register + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x3c); + + /// address: 0x40020444 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x44); + + /// address: 0x40020448 + /// DMA channel 4 number of data + /// register + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002044c + /// DMA channel 4 peripheral address + /// register + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x4c); + + /// address: 0x40020450 + /// DMA channel 4 memory address + /// register + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x50); + + /// address: 0x40020458 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x58); + + /// address: 0x4002045c + /// DMA channel 5 number of data + /// register + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40020460 + /// DMA channel 5 peripheral address + /// register + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40020464 + /// DMA channel 5 memory address + /// register + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x64); + + /// address: 0x4002046c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x6c); + + /// address: 0x40020470 + /// DMA channel 6 number of data + /// register + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x70); + + /// address: 0x40020474 + /// DMA channel 6 peripheral address + /// register + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x74); + + /// address: 0x40020478 + /// DMA channel 6 memory address + /// register + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x78); + + /// address: 0x40020480 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40020484 + /// DMA channel 7 number of data + /// register + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x40020488 + /// DMA channel 7 peripheral address + /// register + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x88); + + /// address: 0x4002048c + /// DMA channel 7 memory address + /// register + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x8c); + }; + /// Secure digital input/output + /// interface + pub const SDIO = struct { + pub const base_address = 0x40018000; + + /// address: 0x40018000 + /// Bits 1:0 = PWRCTRL: Power supply control + /// bits + pub const POWER = @intToPtr(*volatile Mmio(32, packed struct{ + /// PWRCTRL + PWRCTRL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x0); + + /// address: 0x40018004 + /// SDI clock control register + /// (SDIO_CLKCR) + pub const CLKCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock divide factor + CLKDIV: u8, + /// Clock enable bit + CLKEN: u1, + /// Power saving configuration + /// bit + PWRSAV: u1, + /// Clock divider bypass enable + /// bit + BYPASS: u1, + /// Wide bus mode enable bit + WIDBUS: u2, + /// SDIO_CK dephasing selection + /// bit + NEGEDGE: u1, + /// HW Flow Control enable + HWFC_EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40018008 + /// Bits 31:0 = : Command argument + pub const ARG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Command argument + CMDARG: u32, + }), base_address + 0x8); + + /// address: 0x4001800c + /// SDIO command register + /// (SDIO_CMD) + pub const CMD = @intToPtr(*volatile Mmio(32, packed struct{ + /// CMDINDEX + CMDINDEX: u6, + /// WAITRESP + WAITRESP: u2, + /// WAITINT + WAITINT: u1, + /// WAITPEND + WAITPEND: u1, + /// CPSMEN + CPSMEN: u1, + /// SDIOSuspend + SDIOSuspend: u1, + /// ENCMDcompl + ENCMDcompl: u1, + /// nIEN + nIEN: u1, + /// CE_ATACMD + CE_ATACMD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40018010 + /// SDIO command register + pub const RESPCMD = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x10); + + /// address: 0x40018014 + /// Bits 31:0 = CARDSTATUS1 + pub const RESPI1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CARDSTATUS1 + CARDSTATUS1: u32, + }), base_address + 0x14); + + /// address: 0x40018018 + /// Bits 31:0 = CARDSTATUS2 + pub const RESP2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CARDSTATUS2 + CARDSTATUS2: u32, + }), base_address + 0x18); + + /// address: 0x4001801c + /// Bits 31:0 = CARDSTATUS3 + pub const RESP3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CARDSTATUS3 + CARDSTATUS3: u32, + }), base_address + 0x1c); + + /// address: 0x40018020 + /// Bits 31:0 = CARDSTATUS4 + pub const RESP4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CARDSTATUS4 + CARDSTATUS4: u32, + }), base_address + 0x20); + + /// address: 0x40018024 + /// Bits 31:0 = DATATIME: Data timeout + /// period + pub const DTIMER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data timeout period + DATATIME: u32, + }), base_address + 0x24); + + /// address: 0x40018028 + /// Bits 24:0 = DATALENGTH: Data length + /// value + pub const DLEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data length value + DATALENGTH: u25, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x28); + + /// address: 0x4001802c + /// SDIO data control register + /// (SDIO_DCTRL) + pub const DCTRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// DTEN + DTEN: u1, + /// DTDIR + DTDIR: u1, + /// DTMODE + DTMODE: u1, + /// DMAEN + DMAEN: u1, + /// DBLOCKSIZE + DBLOCKSIZE: u4, + /// PWSTART + PWSTART: u1, + /// PWSTOP + PWSTOP: u1, + /// RWMOD + RWMOD: u1, + /// SDIOEN + SDIOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40018030 + /// Bits 24:0 = DATACOUNT: Data count + /// value + pub const DCOUNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data count value + DATACOUNT: u25, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + + /// address: 0x40018034 + /// SDIO status register + /// (SDIO_STA) + pub const STA = @intToPtr(*volatile Mmio(32, packed struct{ + /// CCRCFAIL + CCRCFAIL: u1, + /// DCRCFAIL + DCRCFAIL: u1, + /// CTIMEOUT + CTIMEOUT: u1, + /// DTIMEOUT + DTIMEOUT: u1, + /// TXUNDERR + TXUNDERR: u1, + /// RXOVERR + RXOVERR: u1, + /// CMDREND + CMDREND: u1, + /// CMDSENT + CMDSENT: u1, + /// DATAEND + DATAEND: u1, + /// STBITERR + STBITERR: u1, + /// DBCKEND + DBCKEND: u1, + /// CMDACT + CMDACT: u1, + /// TXACT + TXACT: u1, + /// RXACT + RXACT: u1, + /// TXFIFOHE + TXFIFOHE: u1, + /// RXFIFOHF + RXFIFOHF: u1, + /// TXFIFOF + TXFIFOF: u1, + /// RXFIFOF + RXFIFOF: u1, + /// TXFIFOE + TXFIFOE: u1, + /// RXFIFOE + RXFIFOE: u1, + /// TXDAVL + TXDAVL: u1, + /// RXDAVL + RXDAVL: u1, + /// SDIOIT + SDIOIT: u1, + /// CEATAEND + CEATAEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x40018038 + /// SDIO interrupt clear register + /// (SDIO_ICR) + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CCRCFAILC + CCRCFAILC: u1, + /// DCRCFAILC + DCRCFAILC: u1, + /// CTIMEOUTC + CTIMEOUTC: u1, + /// DTIMEOUTC + DTIMEOUTC: u1, + /// TXUNDERRC + TXUNDERRC: u1, + /// RXOVERRC + RXOVERRC: u1, + /// CMDRENDC + CMDRENDC: u1, + /// CMDSENTC + CMDSENTC: u1, + /// DATAENDC + DATAENDC: u1, + /// STBITERRC + STBITERRC: u1, + /// DBCKENDC + DBCKENDC: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// SDIOITC + SDIOITC: u1, + /// CEATAENDC + CEATAENDC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x38); + + /// address: 0x4001803c + /// SDIO mask register (SDIO_MASK) + pub const MASK = @intToPtr(*volatile Mmio(32, packed struct{ + /// CCRCFAILIE + CCRCFAILIE: u1, + /// DCRCFAILIE + DCRCFAILIE: u1, + /// CTIMEOUTIE + CTIMEOUTIE: u1, + /// DTIMEOUTIE + DTIMEOUTIE: u1, + /// TXUNDERRIE + TXUNDERRIE: u1, + /// RXOVERRIE + RXOVERRIE: u1, + /// CMDRENDIE + CMDRENDIE: u1, + /// CMDSENTIE + CMDSENTIE: u1, + /// DATAENDIE + DATAENDIE: u1, + /// STBITERRIE + STBITERRIE: u1, + /// DBACKENDIE + DBACKENDIE: u1, + /// CMDACTIE + CMDACTIE: u1, + /// TXACTIE + TXACTIE: u1, + /// RXACTIE + RXACTIE: u1, + /// TXFIFOHEIE + TXFIFOHEIE: u1, + /// RXFIFOHFIE + RXFIFOHFIE: u1, + /// TXFIFOFIE + TXFIFOFIE: u1, + /// RXFIFOFIE + RXFIFOFIE: u1, + /// TXFIFOEIE + TXFIFOEIE: u1, + /// RXFIFOEIE + RXFIFOEIE: u1, + /// TXDAVLIE + TXDAVLIE: u1, + /// RXDAVLIE + RXDAVLIE: u1, + /// SDIOITIE + SDIOITIE: u1, + /// CEATENDIE + CEATENDIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x3c); + + /// address: 0x40018048 + /// Bits 23:0 = FIFOCOUNT: Remaining number of + /// words to be written to or read from the + /// FIFO + pub const FIFOCNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// FIF0COUNT + FIF0COUNT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x48); + + /// address: 0x40018080 + /// bits 31:0 = FIFOData: Receive and transmit + /// FIFO data + pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct{ + /// FIFOData + FIFOData: u32, + }), base_address + 0x80); + }; + /// Real time clock + pub const RTC = struct { + pub const base_address = 0x40002800; + + /// address: 0x40002800 + /// RTC Control Register High + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second interrupt Enable + SECIE: u1, + /// Alarm interrupt Enable + ALRIE: u1, + /// Overflow interrupt Enable + OWIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x40002804 + /// RTC Control Register Low + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second Flag + SECF: u1, + /// Alarm Flag + ALRF: u1, + /// Overflow Flag + OWF: u1, + /// Registers Synchronized + /// Flag + RSF: u1, + /// Configuration Flag + CNF: u1, + /// RTC operation OFF + RTOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x4); + + /// address: 0x40002808 + /// RTC Prescaler Load Register + /// High + pub const PRLH = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x8); + + /// address: 0x4000280c + /// RTC Prescaler Load Register + /// Low + pub const PRLL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40002810 + /// RTC Prescaler Divider Register + /// High + pub const DIVH = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x10); + + /// address: 0x40002814 + /// RTC Prescaler Divider Register + /// Low + pub const DIVL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14); + + /// address: 0x40002818 + /// RTC Counter Register High + pub const CNTH = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x18); + + /// address: 0x4000281c + /// RTC Counter Register Low + pub const CNTL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c); + + /// address: 0x40002820 + /// RTC Alarm Register High + pub const ALRH = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x20); + + /// address: 0x40002824 + /// RTC Alarm Register Low + pub const ALRL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + }; + /// Backup registers + pub const BKP = struct { + pub const base_address = 0x40006c04; + + /// address: 0x40006c04 + /// Backup data register (BKP_DR) + pub const DR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D1: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40006c08 + /// Backup data register (BKP_DR) + pub const DR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D2: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40006c0c + /// Backup data register (BKP_DR) + pub const DR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D3: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40006c10 + /// Backup data register (BKP_DR) + pub const DR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D4: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40006c14 + /// Backup data register (BKP_DR) + pub const DR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D5: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40006c18 + /// Backup data register (BKP_DR) + pub const DR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D6: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40006c1c + /// Backup data register (BKP_DR) + pub const DR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D7: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40006c20 + /// Backup data register (BKP_DR) + pub const DR8 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D8: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40006c24 + /// Backup data register (BKP_DR) + pub const DR9 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D9: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40006c28 + /// Backup data register (BKP_DR) + pub const DR10 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D10: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x40006c40 + /// Backup data register (BKP_DR) + pub const DR11 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40006c44 + /// Backup data register (BKP_DR) + pub const DR12 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40006c48 + /// Backup data register (BKP_DR) + pub const DR13 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x44); + + /// address: 0x40006c4c + /// Backup data register (BKP_DR) + pub const DR14 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D14: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x40006c50 + /// Backup data register (BKP_DR) + pub const DR15 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D15: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40006c54 + /// Backup data register (BKP_DR) + pub const DR16 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D16: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x50); + + /// address: 0x40006c58 + /// Backup data register (BKP_DR) + pub const DR17 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D17: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x54); + + /// address: 0x40006c5c + /// Backup data register (BKP_DR) + pub const DR18 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D18: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x58); + + /// address: 0x40006c60 + /// Backup data register (BKP_DR) + pub const DR19 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D19: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40006c64 + /// Backup data register (BKP_DR) + pub const DR20 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D20: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x60); + + /// address: 0x40006c68 + /// Backup data register (BKP_DR) + pub const DR21 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D21: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x64); + + /// address: 0x40006c6c + /// Backup data register (BKP_DR) + pub const DR22 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D22: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x68); + + /// address: 0x40006c70 + /// Backup data register (BKP_DR) + pub const DR23 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D23: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x6c); + + /// address: 0x40006c74 + /// Backup data register (BKP_DR) + pub const DR24 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D24: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x70); + + /// address: 0x40006c78 + /// Backup data register (BKP_DR) + pub const DR25 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D25: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x74); + + /// address: 0x40006c7c + /// Backup data register (BKP_DR) + pub const DR26 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D26: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x78); + + /// address: 0x40006c80 + /// Backup data register (BKP_DR) + pub const DR27 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D27: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x7c); + + /// address: 0x40006c84 + /// Backup data register (BKP_DR) + pub const DR28 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D28: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x80); + + /// address: 0x40006c88 + /// Backup data register (BKP_DR) + pub const DR29 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D29: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x40006c8c + /// Backup data register (BKP_DR) + pub const DR30 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D30: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x88); + + /// address: 0x40006c90 + /// Backup data register (BKP_DR) + pub const DR31 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D31: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x40006c94 + /// Backup data register (BKP_DR) + pub const DR32 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D32: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x90); + + /// address: 0x40006c98 + /// Backup data register (BKP_DR) + pub const DR33 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D33: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x94); + + /// address: 0x40006c9c + /// Backup data register (BKP_DR) + pub const DR34 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D34: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x98); + + /// address: 0x40006ca0 + /// Backup data register (BKP_DR) + pub const DR35 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D35: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x9c); + + /// address: 0x40006ca4 + /// Backup data register (BKP_DR) + pub const DR36 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D36: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa0); + + /// address: 0x40006ca8 + /// Backup data register (BKP_DR) + pub const DR37 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D37: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa4); + + /// address: 0x40006cac + /// Backup data register (BKP_DR) + pub const DR38 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D38: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa8); + + /// address: 0x40006cb0 + /// Backup data register (BKP_DR) + pub const DR39 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D39: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xac); + + /// address: 0x40006cb4 + /// Backup data register (BKP_DR) + pub const DR40 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D40: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xb0); + + /// address: 0x40006cb8 + /// Backup data register (BKP_DR) + pub const DR41 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D41: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xb4); + + /// address: 0x40006cbc + /// Backup data register (BKP_DR) + pub const DR42 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D42: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xb8); + + /// address: 0x40006c2c + /// RTC clock calibration register + /// (BKP_RTCCR) + pub const RTCCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Calibration value + CAL: u7, + /// Calibration Clock Output + CCO: u1, + /// Alarm or second output + /// enable + ASOE: u1, + /// Alarm or second output + /// selection + ASOS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x28); + + /// address: 0x40006c30 + /// Backup control register + /// (BKP_CR) + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tamper pin enable + TPE: u1, + /// Tamper pin active level + TPAL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x2c); + + /// address: 0x40006c34 + /// BKP_CSR control/status register + /// (BKP_CSR) + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clear Tamper event + CTE: u1, + /// Clear Tamper Interrupt + CTI: u1, + /// Tamper Pin interrupt + /// enable + TPIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Tamper Event Flag + TEF: u1, + /// Tamper Interrupt Flag + TIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x30); + }; + /// Independent watchdog + pub const IWDG = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Key register (IWDG_KR) + pub const KR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Key value + KEY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Prescaler register (IWDG_PR) + pub const PR = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); + + /// address: 0x40003008 + /// Reload register (IWDG_RLR) + pub const RLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Watchdog counter reload + /// value + RL: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// Status register (IWDG_SR) + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Watchdog prescaler value + /// update + PVU: u1, + /// Watchdog counter reload value + /// update + RVU: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + }; + /// Window watchdog + pub const WWDG = struct { + pub const base_address = 0x40002c00; + + /// address: 0x40002c00 + /// Control register (WWDG_CR) + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7-bit counter (MSB to LSB) + T: u7, + /// Activation bit + WDGA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40002c04 + /// Configuration register + /// (WWDG_CFR) + pub const CFR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7-bit window value + W: u7, + /// Timer Base + WDGTB: u2, + /// Early Wakeup Interrupt + EWI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x40002c08 + /// Status register (WWDG_SR) + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Early Wakeup Interrupt + EWI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + }; + /// Advanced timer + pub const TIM1 = struct { + pub const base_address = 0x40012c00; + + /// address: 0x40012c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40012c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40012c08 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40012c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40012c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved0: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40012c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40012c18 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40012c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40012c1c + /// capture/compare mode register (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40012c1c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40012c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40012c24 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40012c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40012c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40012c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40012c38 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x40012c3c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40012c40 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40012c48 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x40012c4c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40012c30 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40012c44 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + }; + pub const TIM8 = struct { + pub const base_address = 0x40013400; + + /// address: 0x40013400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40013404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40013408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001340c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40013410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved0: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40013414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40013418 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40013418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001341c + /// capture/compare mode register (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4001341c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40013420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40013424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40013428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001342c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40013434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40013438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001343c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40013440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40013448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001344c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40013430 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40013444 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + }; + /// General purpose timer + pub const TIM2 = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000000c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000001c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000001c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved2: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved4: u1, + reserved5: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40000024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40000028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000002c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40000034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40000038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4000003c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40000040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40000048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000004c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM3 = struct { + pub const base_address = 0x40000400; + + /// address: 0x40000400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000040c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000041c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000041c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved2: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved4: u1, + reserved5: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40000424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40000428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000042c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40000434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40000438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4000043c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40000440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40000448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000044c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM4 = struct { + pub const base_address = 0x40000800; + + /// address: 0x40000800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000080c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000081c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000081c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved2: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved4: u1, + reserved5: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40000824 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40000828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000082c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40000834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40000838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4000083c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40000840 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40000848 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000084c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM5 = struct { + pub const base_address = 0x40000c00; + + /// address: 0x40000c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000c08 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40000c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000c18 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000c1c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000c1c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved2: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved4: u1, + reserved5: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40000c24 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40000c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40000c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40000c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40000c38 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x40000c3c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40000c40 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40000c48 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x40000c4c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + /// General purpose timer + pub const TIM9 = struct { + pub const base_address = 0x40014c00; + + /// address: 0x40014c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40014c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40014c08 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x40014c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt enable + TIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xc); + + /// address: 0x40014c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt flag + TIF: u1, + reserved3: u1, + reserved4: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40014c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40014c18 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40014c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40014c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40014c24 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40014c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40014c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014c38 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + pub const TIM12 = struct { + pub const base_address = 0x40001800; + + /// address: 0x40001800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40001804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40001808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4000180c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt enable + TIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xc); + + /// address: 0x40001810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt flag + TIF: u1, + reserved3: u1, + reserved4: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40001814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40001818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40001818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40001820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40001824 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000182c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40001834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40001838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + /// General purpose timer + pub const TIM10 = struct { + pub const base_address = 0x40015000; + + /// address: 0x40015000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40015004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4001500c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40015010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40015014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40015018 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + reserved0: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40015018 + /// capture/compare mode register (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40015020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40015024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40015028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001502c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40015034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM11 = struct { + pub const base_address = 0x40015400; + + /// address: 0x40015400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40015404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4001540c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40015410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40015414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40015418 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + reserved0: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40015418 + /// capture/compare mode register (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40015420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40015424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40015428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001542c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40015434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM13 = struct { + pub const base_address = 0x40001c00; + + /// address: 0x40001c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40001c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40001c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40001c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40001c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40001c18 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + reserved0: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40001c18 + /// capture/compare mode register (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40001c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40001c24 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40001c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40001c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM14 = struct { + pub const base_address = 0x40002000; + + /// address: 0x40002000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40002004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000200c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40002010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40002014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40002018 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + reserved0: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40002018 + /// capture/compare mode register (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40002020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40002024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40002028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000202c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40002034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + /// Basic timer + pub const TIM6 = struct { + pub const base_address = 0x40001000; + + /// address: 0x40001000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40001004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000100c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000102c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + pub const TIM7 = struct { + pub const base_address = 0x40001400; + + /// address: 0x40001400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40001404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000140c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000142c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + /// Inter integrated circuit + pub const I2C1 = struct { + pub const base_address = 0x40005400; + + /// address: 0x40005400 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005404 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005408 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000540c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005410 /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface -pub const SPI2 = extern struct { - pub const Address: u32 = 0x40003800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// Data frame format - DFF: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005414 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005418 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000541c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005420 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + }; + pub const I2C2 = struct { + pub const base_address = 0x40005800; + + /// address: 0x40005800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005808 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000580c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005810 /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005814 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005818 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000581c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005820 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + }; + /// Serial peripheral interface + pub const SPI1 = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40013008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4001300c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013010 /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001301c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI2 = struct { + pub const base_address = 0x40003800; + + /// address: 0x40003800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003808 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4000380c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003810 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003818 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000381c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003820 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI3 = struct { + pub const base_address = 0x40003c00; + + /// address: 0x40003c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003c08 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x40003c0c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003c10 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003c14 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003c18 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40003c1c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003c20 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + /// Universal synchronous asynchronous receiver + /// transmitter + pub const USART1 = struct { + pub const base_address = 0x40013800; + + /// address: 0x40013800 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40013804 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40013808 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001380c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40013810 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40013814 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x40013818 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART2 = struct { + pub const base_address = 0x40004400; + + /// address: 0x40004400 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004404 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004408 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000440c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40004410 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004414 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x40004418 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART3 = struct { + pub const base_address = 0x40004800; + + /// address: 0x40004800 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004804 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004808 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000480c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40004810 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004814 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x40004818 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + /// Analog to digital converter + pub const ADC1 = struct { + pub const base_address = 0x40012400; + + /// address: 0x40012400 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40012404 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + /// Dual mode selection + DUALMOD: u4, + reserved0: u1, + reserved1: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40012408 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A/D converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + /// A/D calibration + CAL: u1, + /// Reset calibration + RSTCAL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Direct memory access mode + DMA: u1, + reserved4: u1, + reserved5: u1, + /// Data alignment + ALIGN: u1, + /// External event select for injected + /// group + JEXTSEL: u3, + /// External trigger conversion mode for + /// injected channels + JEXTTRIG: u1, + reserved6: u1, + /// External event select for regular + /// group + EXTSEL: u3, + /// External trigger conversion mode for + /// regular channels + EXTTRIG: u1, + /// Start conversion of injected + /// channels + JSWSTART: u1, + /// Start conversion of regular + /// channels + SWSTART: u1, + /// Temperature sensor and VREFINT + /// enable + TSVREFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4001240c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 10 sample time + /// selection + SMP10: u3, + /// Channel 11 sample time + /// selection + SMP11: u3, + /// Channel 12 sample time + /// selection + SMP12: u3, + /// Channel 13 sample time + /// selection + SMP13: u3, + /// Channel 14 sample time + /// selection + SMP14: u3, + /// Channel 15 sample time + /// selection + SMP15: u3, + /// Channel 16 sample time + /// selection + SMP16: u3, + /// Channel 17 sample time + /// selection + SMP17: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40012410 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 0 sample time + /// selection + SMP0: u3, + /// Channel 1 sample time + /// selection + SMP1: u3, + /// Channel 2 sample time + /// selection + SMP2: u3, + /// Channel 3 sample time + /// selection + SMP3: u3, + /// Channel 4 sample time + /// selection + SMP4: u3, + /// Channel 5 sample time + /// selection + SMP5: u3, + /// Channel 6 sample time + /// selection + SMP6: u3, + /// Channel 7 sample time + /// selection + SMP7: u3, + /// Channel 8 sample time + /// selection + SMP8: u3, + /// Channel 9 sample time + /// selection + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40012414 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012418 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001241c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012420 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012424 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012428 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001242c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012430 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012434 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012438 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001243c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012440 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012444 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012448 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001244c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Regular data + DATA: u16, + /// ADC2 data + ADC2DATA: u16, + }), base_address + 0x4c); + }; + /// Analog to digital converter + pub const ADC2 = struct { + pub const base_address = 0x40012800; + + /// address: 0x40012800 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40012804 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40012808 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A/D converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + /// A/D calibration + CAL: u1, + /// Reset calibration + RSTCAL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Direct memory access mode + DMA: u1, + reserved4: u1, + reserved5: u1, + /// Data alignment + ALIGN: u1, + /// External event select for injected + /// group + JEXTSEL: u3, + /// External trigger conversion mode for + /// injected channels + JEXTTRIG: u1, + reserved6: u1, + /// External event select for regular + /// group + EXTSEL: u3, + /// External trigger conversion mode for + /// regular channels + EXTTRIG: u1, + /// Start conversion of injected + /// channels + JSWSTART: u1, + /// Start conversion of regular + /// channels + SWSTART: u1, + /// Temperature sensor and VREFINT + /// enable + TSVREFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4001280c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 10 sample time + /// selection + SMP10: u3, + /// Channel 11 sample time + /// selection + SMP11: u3, + /// Channel 12 sample time + /// selection + SMP12: u3, + /// Channel 13 sample time + /// selection + SMP13: u3, + /// Channel 14 sample time + /// selection + SMP14: u3, + /// Channel 15 sample time + /// selection + SMP15: u3, + /// Channel 16 sample time + /// selection + SMP16: u3, + /// Channel 17 sample time + /// selection + SMP17: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40012810 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 0 sample time + /// selection + SMP0: u3, + /// Channel 1 sample time + /// selection + SMP1: u3, + /// Channel 2 sample time + /// selection + SMP2: u3, + /// Channel 3 sample time + /// selection + SMP3: u3, + /// Channel 4 sample time + /// selection + SMP4: u3, + /// Channel 5 sample time + /// selection + SMP5: u3, + /// Channel 6 sample time + /// selection + SMP6: u3, + /// Channel 7 sample time + /// selection + SMP7: u3, + /// Channel 8 sample time + /// selection + SMP8: u3, + /// Channel 9 sample time + /// selection + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40012814 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012818 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001281c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012820 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012824 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012828 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001282c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012830 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012834 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012838 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001283c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012840 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012844 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012848 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001284c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const ADC3 = struct { + pub const base_address = 0x40013c00; + + /// address: 0x40013c00 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40013c04 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40013c08 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A/D converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + /// A/D calibration + CAL: u1, + /// Reset calibration + RSTCAL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Direct memory access mode + DMA: u1, + reserved4: u1, + reserved5: u1, + /// Data alignment + ALIGN: u1, + /// External event select for injected + /// group + JEXTSEL: u3, + /// External trigger conversion mode for + /// injected channels + JEXTTRIG: u1, + reserved6: u1, + /// External event select for regular + /// group + EXTSEL: u3, + /// External trigger conversion mode for + /// regular channels + EXTTRIG: u1, + /// Start conversion of injected + /// channels + JSWSTART: u1, + /// Start conversion of regular + /// channels + SWSTART: u1, + /// Temperature sensor and VREFINT + /// enable + TSVREFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x40013c0c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 10 sample time + /// selection + SMP10: u3, + /// Channel 11 sample time + /// selection + SMP11: u3, + /// Channel 12 sample time + /// selection + SMP12: u3, + /// Channel 13 sample time + /// selection + SMP13: u3, + /// Channel 14 sample time + /// selection + SMP14: u3, + /// Channel 15 sample time + /// selection + SMP15: u3, + /// Channel 16 sample time + /// selection + SMP16: u3, + /// Channel 17 sample time + /// selection + SMP17: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40013c10 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 0 sample time + /// selection + SMP0: u3, + /// Channel 1 sample time + /// selection + SMP1: u3, + /// Channel 2 sample time + /// selection + SMP2: u3, + /// Channel 3 sample time + /// selection + SMP3: u3, + /// Channel 4 sample time + /// selection + SMP4: u3, + /// Channel 5 sample time + /// selection + SMP5: u3, + /// Channel 6 sample time + /// selection + SMP6: u3, + /// Channel 7 sample time + /// selection + SMP7: u3, + /// Channel 8 sample time + /// selection + SMP8: u3, + /// Channel 9 sample time + /// selection + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40013c14 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40013c18 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x40013c1c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013c20 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40013c24 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40013c28 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x40013c2c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40013c30 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40013c34 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40013c38 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x40013c3c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40013c40 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40013c44 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40013c48 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x40013c4c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + /// Controller area network + pub const CAN = struct { + pub const base_address = 0x40006400; + + /// address: 0x40006400 + /// CAN_MCR + pub const CAN_MCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006404 + /// CAN_MSR + pub const CAN_MSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006408 + /// CAN_TSR + pub const CAN_TSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox + /// 0 + TME0: u1, + /// Lowest priority flag for mailbox + /// 1 + TME1: u1, + /// Lowest priority flag for mailbox + /// 2 + TME2: u1, + /// Lowest priority flag for mailbox + /// 0 + LOW0: u1, + /// Lowest priority flag for mailbox + /// 1 + LOW1: u1, + /// Lowest priority flag for mailbox + /// 2 + LOW2: u1, + }), base_address + 0x8); + + /// address: 0x4000640c + /// CAN_RF0R + pub const CAN_RF0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// FMP0 + FMP0: u2, + reserved0: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006410 + /// CAN_RF1R + pub const CAN_RF1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// FMP1 + FMP1: u2, + reserved0: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006414 + /// CAN_IER + pub const CAN_IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved0: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006418 + /// CAN_ESR + pub const CAN_ESR = @intToPtr(*volatile Mmio(32, packed struct{ + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved0: u1, + /// LEC + LEC: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), base_address + 0x18); + + /// address: 0x4000641c + /// CAN_BTR + pub const CAN_BTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// BRP + BRP: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved6: u1, + /// SJW + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), base_address + 0x1c); + + /// address: 0x40006580 + /// CAN_TI0R + pub const CAN_TI0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x180); + + /// address: 0x40006584 + /// CAN_TDT0R + pub const CAN_TDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x184); + + /// address: 0x40006588 + /// CAN_TDL0R + pub const CAN_TDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x188); + + /// address: 0x4000658c + /// CAN_TDH0R + pub const CAN_TDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x18c); + + /// address: 0x40006590 + /// CAN_TI1R + pub const CAN_TI1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x190); + + /// address: 0x40006594 + /// CAN_TDT1R + pub const CAN_TDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x194); + + /// address: 0x40006598 + /// CAN_TDL1R + pub const CAN_TDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x198); + + /// address: 0x4000659c + /// CAN_TDH1R + pub const CAN_TDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x19c); + + /// address: 0x400065a0 + /// CAN_TI2R + pub const CAN_TI2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1a0); + + /// address: 0x400065a4 + /// CAN_TDT2R + pub const CAN_TDT2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x1a4); + + /// address: 0x400065a8 + /// CAN_TDL2R + pub const CAN_TDL2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1a8); + + /// address: 0x400065ac + /// CAN_TDH2R + pub const CAN_TDH2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1ac); + + /// address: 0x400065b0 + /// CAN_RI0R + pub const CAN_RI0R = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1b0); + + /// address: 0x400065b4 + /// CAN_RDT0R + pub const CAN_RDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1b4); + + /// address: 0x400065b8 + /// CAN_RDL0R + pub const CAN_RDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1b8); + + /// address: 0x400065bc + /// CAN_RDH0R + pub const CAN_RDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1bc); + + /// address: 0x400065c0 + /// CAN_RI1R + pub const CAN_RI1R = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1c0); + + /// address: 0x400065c4 + /// CAN_RDT1R + pub const CAN_RDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1c4); + + /// address: 0x400065c8 + /// CAN_RDL1R + pub const CAN_RDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1c8); + + /// address: 0x400065cc + /// CAN_RDH1R + pub const CAN_RDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006600 + /// CAN_FMR + pub const CAN_FMR = @intToPtr(*volatile Mmio(32, packed struct{ + /// FINIT + FINIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x200); + + /// address: 0x40006604 + /// CAN_FM1R + pub const CAN_FM1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x204); + + /// address: 0x4000660c + /// CAN_FS1R + pub const CAN_FS1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20c); + + /// address: 0x40006614 + /// CAN_FFA1R + pub const CAN_FFA1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter FIFO assignment for filter + /// 0 + FFA0: u1, + /// Filter FIFO assignment for filter + /// 1 + FFA1: u1, + /// Filter FIFO assignment for filter + /// 2 + FFA2: u1, + /// Filter FIFO assignment for filter + /// 3 + FFA3: u1, + /// Filter FIFO assignment for filter + /// 4 + FFA4: u1, + /// Filter FIFO assignment for filter + /// 5 + FFA5: u1, + /// Filter FIFO assignment for filter + /// 6 + FFA6: u1, + /// Filter FIFO assignment for filter + /// 7 + FFA7: u1, + /// Filter FIFO assignment for filter + /// 8 + FFA8: u1, + /// Filter FIFO assignment for filter + /// 9 + FFA9: u1, + /// Filter FIFO assignment for filter + /// 10 + FFA10: u1, + /// Filter FIFO assignment for filter + /// 11 + FFA11: u1, + /// Filter FIFO assignment for filter + /// 12 + FFA12: u1, + /// Filter FIFO assignment for filter + /// 13 + FFA13: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x214); + + /// address: 0x4000661c + /// CAN_FA1R + pub const CAN_FA1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x21c); + + /// address: 0x40006640 + /// Filter bank 0 register 1 + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x240); + + /// address: 0x40006644 + /// Filter bank 0 register 2 + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x244); + + /// address: 0x40006648 + /// Filter bank 1 register 1 + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x248); + + /// address: 0x4000664c + /// Filter bank 1 register 2 + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x24c); + + /// address: 0x40006650 + /// Filter bank 2 register 1 + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x250); + + /// address: 0x40006654 + /// Filter bank 2 register 2 + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x254); + + /// address: 0x40006658 + /// Filter bank 3 register 1 + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x258); + + /// address: 0x4000665c + /// Filter bank 3 register 2 + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x25c); + + /// address: 0x40006660 + /// Filter bank 4 register 1 + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x260); + + /// address: 0x40006664 + /// Filter bank 4 register 2 + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x264); + + /// address: 0x40006668 + /// Filter bank 5 register 1 + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x268); + + /// address: 0x4000666c + /// Filter bank 5 register 2 + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x26c); + + /// address: 0x40006670 + /// Filter bank 6 register 1 + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x270); + + /// address: 0x40006674 + /// Filter bank 6 register 2 + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x274); + + /// address: 0x40006678 + /// Filter bank 7 register 1 + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x278); + + /// address: 0x4000667c + /// Filter bank 7 register 2 + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x27c); + + /// address: 0x40006680 + /// Filter bank 8 register 1 + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x280); + + /// address: 0x40006684 + /// Filter bank 8 register 2 + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x284); + + /// address: 0x40006688 + /// Filter bank 9 register 1 + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x288); + + /// address: 0x4000668c + /// Filter bank 9 register 2 + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x28c); + + /// address: 0x40006690 + /// Filter bank 10 register 1 + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x290); + + /// address: 0x40006694 + /// Filter bank 10 register 2 + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x294); + + /// address: 0x40006698 + /// Filter bank 11 register 1 + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x298); + + /// address: 0x4000669c + /// Filter bank 11 register 2 + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x29c); + + /// address: 0x400066a0 + /// Filter bank 4 register 1 + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a0); + + /// address: 0x400066a4 + /// Filter bank 12 register 2 + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a4); + + /// address: 0x400066a8 + /// Filter bank 13 register 1 + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a8); + + /// address: 0x400066ac + /// Filter bank 13 register 2 + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ac); + }; + /// Digital to analog converter + pub const DAC = struct { + pub const base_address = 0x40007400; + + /// address: 0x40007400 + /// Control register (DAC_CR) + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 enable + EN1: u1, + /// DAC channel1 output buffer + /// disable + BOFF1: u1, + /// DAC channel1 trigger + /// enable + TEN1: u1, + /// DAC channel1 trigger + /// selection + TSEL1: u3, + /// DAC channel1 noise/triangle wave + /// generation enable + WAVE1: u2, + /// DAC channel1 mask/amplitude + /// selector + MAMP1: u4, + /// DAC channel1 DMA enable + DMAEN1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DAC channel2 enable + EN2: u1, + /// DAC channel2 output buffer + /// disable + BOFF2: u1, + /// DAC channel2 trigger + /// enable + TEN2: u1, + /// DAC channel2 trigger + /// selection + TSEL2: u3, + /// DAC channel2 noise/triangle wave + /// generation enable + WAVE2: u2, + /// DAC channel2 mask/amplitude + /// selector + MAMP2: u4, + /// DAC channel2 DMA enable + DMAEN2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0x40007404 + /// DAC software trigger register + /// (DAC_SWTRIGR) + pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 software + /// trigger + SWTRIG1: u1, + /// DAC channel2 software + /// trigger + SWTRIG2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40007408 + /// DAC channel1 12-bit right-aligned data + /// holding register(DAC_DHR12R1) + pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000740c + /// DAC channel1 12-bit left aligned data + /// holding register (DAC_DHR12L1) + pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007410 + /// DAC channel1 8-bit right aligned data + /// holding register (DAC_DHR8R1) + pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40007414 + /// DAC channel2 12-bit right aligned data + /// holding register (DAC_DHR12R2) + pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007418 + /// DAC channel2 12-bit left aligned data + /// holding register (DAC_DHR12L2) + pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000741c + /// DAC channel2 8-bit right-aligned data + /// holding register (DAC_DHR8R2) + pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1c); + + /// address: 0x40007420 + /// Dual DAC 12-bit right-aligned data holding + /// register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 + /// Reserved + pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x40007424 + /// DUAL DAC 12-bit left aligned data holding + /// register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 + /// Reserved + pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + }), base_address + 0x24); + + /// address: 0x40007428 + /// DUAL DAC 8-bit right aligned data holding + /// register (DAC_DHR8RD), Bits 31:16 Reserved + pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000742c + /// DAC channel1 data output register + /// (DAC_DOR1) + pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 data output + DACC1DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40007430 + /// DAC channel2 data output register + /// (DAC_DOR2) + pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 data output + DACC2DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x30); + }; + /// Debug support + pub const DBG = struct { + pub const base_address = 0xe0042000; + + /// address: 0xe0042000 + /// DBGMCU_IDCODE + pub const IDCODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// DEV_ID + DEV_ID: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// REV_ID + REV_ID: u16, + }), base_address + 0x0); + + /// address: 0xe0042004 + /// DBGMCU_CR + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved0: u1, + reserved1: u1, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, + /// DBG_IWDG_STOP + DBG_IWDG_STOP: u1, + /// DBG_WWDG_STOP + DBG_WWDG_STOP: u1, + /// DBG_TIM1_STOP + DBG_TIM1_STOP: u1, + /// DBG_TIM2_STOP + DBG_TIM2_STOP: u1, + /// DBG_TIM3_STOP + DBG_TIM3_STOP: u1, + /// DBG_TIM4_STOP + DBG_TIM4_STOP: u1, + /// DBG_CAN1_STOP + DBG_CAN1_STOP: u1, + /// DBG_I2C1_SMBUS_TIMEOUT + DBG_I2C1_SMBUS_TIMEOUT: u1, + /// DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT: u1, + /// DBG_TIM8_STOP + DBG_TIM8_STOP: u1, + /// DBG_TIM5_STOP + DBG_TIM5_STOP: u1, + /// DBG_TIM6_STOP + DBG_TIM6_STOP: u1, + /// DBG_TIM7_STOP + DBG_TIM7_STOP: u1, + /// DBG_CAN2_STOP + DBG_CAN2_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x4); + }; + /// Universal asynchronous receiver + /// transmitter + pub const UART4 = struct { + pub const base_address = 0x40004c00; + + /// address: 0x40004c00 + /// UART4_SR + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40004c04 + /// UART4_DR + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004c08 + /// UART4_BRR + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DIV_Fraction + DIV_Fraction: u4, + /// DIV_Mantissa + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40004c0c + /// UART4_CR1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40004c10 + /// UART4_CR2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004c14 + /// UART4_CR3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + }; + /// Universal asynchronous receiver + /// transmitter + pub const UART5 = struct { + pub const base_address = 0x40005000; + + /// address: 0x40005000 + /// UART4_SR + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// PE + PE: u1, + /// FE + FE: u1, + /// NE + NE: u1, + /// ORE + ORE: u1, + /// IDLE + IDLE: u1, + /// RXNE + RXNE: u1, + /// TC + TC: u1, + /// TXE + TXE: u1, + /// LBD + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// UART4_DR + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40005008 + /// UART4_BRR + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DIV_Fraction + DIV_Fraction: u4, + /// DIV_Mantissa + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000500c + /// UART4_CR1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SBK + SBK: u1, + /// RWU + RWU: u1, + /// RE + RE: u1, + /// TE + TE: u1, + /// IDLEIE + IDLEIE: u1, + /// RXNEIE + RXNEIE: u1, + /// TCIE + TCIE: u1, + /// TXEIE + TXEIE: u1, + /// PEIE + PEIE: u1, + /// PS + PS: u1, + /// PCE + PCE: u1, + /// WAKE + WAKE: u1, + /// M + M: u1, + /// UE + UE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40005010 + /// UART4_CR2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADD + ADD: u4, + reserved0: u1, + /// LBDL + LBDL: u1, + /// LBDIE + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP + STOP: u2, + /// LINEN + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40005014 + /// UART4_CR3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA enable transmitter + DMAT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + }; + /// CRC calculation unit + pub const CRC = struct { + pub const base_address = 0x40023000; -/// Serial peripheral interface -pub const SPI3 = extern struct { - pub const Address: u32 = 0x40003c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// Data frame format - DFF: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + /// address: 0x40023000 /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const DR = @intToPtr(*volatile u32, base_address + 0x0); -/// Universal synchronous asynchronous receiver transmitter -pub const USART1 = extern struct { - pub const Address: u32 = 0x40013800; - - /// Status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise error flag - NE: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// IDLE line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBD: u1 = 0, - /// CTS flag - CTS: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data register - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - /// Data value - DR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 1 - pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Send break - SBK: u1 = 0, - /// Receiver wakeup - RWU: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// TXE interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// USART enable - UE: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Address of the USART node - ADD: u4 = 0, - reserved1: u1 = 0, - /// lin break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved2: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + /// address: 0x40023004 + /// Independent Data register + pub const IDR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40023008 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit + RESET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + }; + /// FLASH + pub const FLASH = struct { + pub const base_address = 0x40022000; + + /// address: 0x40022000 + /// Flash access control register + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Latency + LATENCY: u3, + /// Flash half cycle access + /// enable + HLFCYA: u1, + /// Prefetch buffer enable + PRFTBE: u1, + /// Prefetch buffer status + PRFTBS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40022004 + /// Flash key register + pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct{ + /// FPEC key + KEY: u32, + }), base_address + 0x4); + + /// address: 0x40022008 + /// Flash option key register + pub const OPTKEYR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Option byte key + OPTKEY: u32, + }), base_address + 0x8); + + /// address: 0x4002200c + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Busy + BSY: u1, + reserved0: u1, + /// Programming error + PGERR: u1, + reserved1: u1, + /// Write protection error + WRPRTERR: u1, + /// End of operation + EOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40022010 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Programming + PG: u1, + /// Page Erase + PER: u1, + /// Mass Erase + MER: u1, + reserved0: u1, + /// Option byte programming + OPTPG: u1, + /// Option byte erase + OPTER: u1, + /// Start + STRT: u1, + /// Lock + LOCK: u1, + reserved1: u1, + /// Option bytes write enable + OPTWRE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved2: u1, + /// End of operation interrupt + /// enable + EOPIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40022014 + /// Flash address register + pub const AR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Flash Address + FAR: u32, + }), base_address + 0x14); + + /// address: 0x4002201c + /// Option byte register + pub const OBR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Option byte error + OPTERR: u1, + /// Read protection + RDPRT: u1, + /// WDG_SW + WDG_SW: u1, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Data0 + Data0: u8, + /// Data1 + Data1: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x1c); + + /// address: 0x40022020 + /// Write protection register + pub const WRPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write protect + WRP: u32, + }), base_address + 0x20); + }; + /// Nested Vectored Interrupt + /// Controller + pub const NVIC = struct { + pub const base_address = 0xe000e000; + + /// address: 0xe000e004 + /// Interrupt Controller Type + /// Register + pub const ICTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Total number of interrupt lines in + /// groups + INTLINESNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x4); + + /// address: 0xe000ef00 + /// Software Triggered Interrupt + /// Register + pub const STIR = @intToPtr(*volatile Mmio(32, packed struct{ + /// interrupt to be triggered + INTID: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xf00); + + /// address: 0xe000e100 + /// Interrupt Set-Enable Register + pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETENA + SETENA: u32, + }), base_address + 0x100); + + /// address: 0xe000e104 + /// Interrupt Set-Enable Register + pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETENA + SETENA: u32, + }), base_address + 0x104); + + /// address: 0xe000e180 + /// Interrupt Clear-Enable + /// Register + pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRENA + CLRENA: u32, + }), base_address + 0x180); + + /// address: 0xe000e184 + /// Interrupt Clear-Enable + /// Register + pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRENA + CLRENA: u32, + }), base_address + 0x184); + + /// address: 0xe000e200 + /// Interrupt Set-Pending Register + pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETPEND + SETPEND: u32, + }), base_address + 0x200); + + /// address: 0xe000e204 + /// Interrupt Set-Pending Register + pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETPEND + SETPEND: u32, + }), base_address + 0x204); + + /// address: 0xe000e280 + /// Interrupt Clear-Pending + /// Register + pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x280); + + /// address: 0xe000e284 + /// Interrupt Clear-Pending + /// Register + pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x284); + + /// address: 0xe000e300 + /// Interrupt Active Bit Register + pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x300); + + /// address: 0xe000e304 + /// Interrupt Active Bit Register + pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x304); + + /// address: 0xe000e400 + /// Interrupt Priority Register + pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x400); + + /// address: 0xe000e404 + /// Interrupt Priority Register + pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x404); + + /// address: 0xe000e408 + /// Interrupt Priority Register + pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x408); + + /// address: 0xe000e40c + /// Interrupt Priority Register + pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x40c); + + /// address: 0xe000e410 + /// Interrupt Priority Register + pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x410); + + /// address: 0xe000e414 + /// Interrupt Priority Register + pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x414); + + /// address: 0xe000e418 + /// Interrupt Priority Register + pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x418); + + /// address: 0xe000e41c + /// Interrupt Priority Register + pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x41c); + + /// address: 0xe000e420 + /// Interrupt Priority Register + pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x420); + + /// address: 0xe000e424 + /// Interrupt Priority Register + pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x424); + + /// address: 0xe000e428 + /// Interrupt Priority Register + pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x428); + + /// address: 0xe000e42c + /// Interrupt Priority Register + pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x42c); + + /// address: 0xe000e430 + /// Interrupt Priority Register + pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x430); + + /// address: 0xe000e434 + /// Interrupt Priority Register + pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x434); + + /// address: 0xe000e438 + /// Interrupt Priority Register + pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x438); + }; + /// Universal serial bus full-speed device + /// interface + pub const USB = struct { + pub const base_address = 0x40005c00; + + /// address: 0x40005c00 + /// endpoint 0 register + pub const EP0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005c04 + /// endpoint 1 register + pub const EP1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40005c08 + /// endpoint 2 register + pub const EP2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40005c0c + /// endpoint 3 register + pub const EP3R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005c10 + /// endpoint 4 register + pub const EP4R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40005c14 + /// endpoint 5 register + pub const EP5R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005c18 + /// endpoint 6 register + pub const EP6R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40005c1c + /// endpoint 7 register + pub const EP7R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005c40 + /// control register + pub const CNTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Force USB Reset + FRES: u1, + /// Power down + PDWN: u1, + /// Low-power mode + LPMODE: u1, + /// Force suspend + FSUSP: u1, + /// Resume request + RESUME: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Expected start of frame interrupt + /// mask + ESOFM: u1, + /// Start of frame interrupt + /// mask + SOFM: u1, + /// USB reset interrupt mask + RESETM: u1, + /// Suspend mode interrupt + /// mask + SUSPM: u1, + /// Wakeup interrupt mask + WKUPM: u1, + /// Error interrupt mask + ERRM: u1, + /// Packet memory area over / underrun + /// interrupt mask + PMAOVRM: u1, + /// Correct transfer interrupt + /// mask + CTRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40005c44 + /// interrupt status register + pub const ISTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint Identifier + EP_ID: u4, + /// Direction of transaction + DIR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Expected start frame + ESOF: u1, + /// start of frame + SOF: u1, + /// reset request + RESET: u1, + /// Suspend mode request + SUSP: u1, + /// Wakeup + WKUP: u1, + /// Error + ERR: u1, + /// Packet memory area over / + /// underrun + PMAOVR: u1, + /// Correct transfer + CTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40005c48 + /// frame number register + pub const FNR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Frame number + FN: u11, + /// Lost SOF + LSOF: u2, + /// Locked + LCK: u1, + /// Receive data - line status + RXDM: u1, + /// Receive data + line status + RXDP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x40005c4c + /// device address + pub const DADDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Device address + ADD: u7, + /// Enable function + EF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4c); + + /// address: 0x40005c50 + /// Buffer table address + pub const BTABLE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x50); + }; }; -/// Universal synchronous asynchronous receiver transmitter -pub const USART2 = extern struct { - pub const Address: u32 = 0x40004400; - - /// Status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise error flag - NE: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// IDLE line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBD: u1 = 0, - /// CTS flag - CTS: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data register - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - /// Data value - DR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 1 - pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Send break - SBK: u1 = 0, - /// Receiver wakeup - RWU: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// TXE interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// USART enable - UE: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Address of the USART node - ADD: u4 = 0, - reserved1: u1 = 0, - /// lin break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved2: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; +const std = @import("std"); -/// Universal synchronous asynchronous receiver transmitter -pub const USART3 = extern struct { - pub const Address: u32 = 0x40004800; - - /// Status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise error flag - NE: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// IDLE line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBD: u1 = 0, - /// CTS flag - CTS: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data register - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - /// Data value - DR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 1 - pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Send break - SBK: u1 = 0, - /// Receiver wakeup - RWU: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// TXE interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// USART enable - UE: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Address of the USART node - ADD: u4 = 0, - reserved1: u1 = 0, - /// lin break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved2: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} -/// Analog to digital converter -pub const ADC1 = extern struct { - pub const Address: u32 = 0x40012400; - - /// status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Analog watchdog flag - AWD: u1 = 0, - /// Regular channel end of conversion - EOC: u1 = 0, - /// Injected channel end of conversion - JEOC: u1 = 0, - /// Injected channel start flag - JSTRT: u1 = 0, - /// Regular channel start flag - STRT: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - /// Analog watchdog channel select bits - AWDCH: u5 = 0, - /// Interrupt enable for EOC - EOCIE: u1 = 0, - /// Analog watchdog interrupt enable - AWDIE: u1 = 0, - /// Interrupt enable for injected channels - JEOCIE: u1 = 0, - /// Scan mode - SCAN: u1 = 0, - /// Enable the watchdog on a single channel in scan mode - AWDSGL: u1 = 0, - /// Automatic injected group conversion - JAUTO: u1 = 0, - /// Discontinuous mode on regular channels - DISCEN: u1 = 0, - /// Discontinuous mode on injected channels - JDISCEN: u1 = 0, - /// Discontinuous mode channel count - DISCNUM: u3 = 0, - /// Dual mode selection - DUALMOD: u4 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Analog watchdog enable on injected channels - JAWDEN: u1 = 0, - /// Analog watchdog enable on regular channels - AWDEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - /// A/D converter ON / OFF - ADON: u1 = 0, - /// Continuous conversion - CONT: u1 = 0, - /// A/D calibration - CAL: u1 = 0, - /// Reset calibration - RSTCAL: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Direct memory access mode - DMA: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Data alignment - ALIGN: u1 = 0, - /// External event select for injected group - JEXTSEL: u3 = 0, - /// External trigger conversion mode for injected channels - JEXTTRIG: u1 = 0, - reserved7: u1 = 0, - /// External event select for regular group - EXTSEL: u3 = 0, - /// External trigger conversion mode for regular channels - EXTTRIG: u1 = 0, - /// Start conversion of injected channels - JSWSTART: u1 = 0, - /// Start conversion of regular channels - SWSTART: u1 = 0, - /// Temperature sensor and VREFINT enable - TSVREFE: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Channel 10 sample time selection - SMP10: u3 = 0, - /// Channel 11 sample time selection - SMP11: u3 = 0, - /// Channel 12 sample time selection - SMP12: u3 = 0, - /// Channel 13 sample time selection - SMP13: u3 = 0, - /// Channel 14 sample time selection - SMP14: u3 = 0, - /// Channel 15 sample time selection - SMP15: u3 = 0, - /// Channel 16 sample time selection - SMP16: u3 = 0, - /// Channel 17 sample time selection - SMP17: u3 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Channel 0 sample time selection - SMP0: u3 = 0, - /// Channel 1 sample time selection - SMP1: u3 = 0, - /// Channel 2 sample time selection - SMP2: u3 = 0, - /// Channel 3 sample time selection - SMP3: u3 = 0, - /// Channel 4 sample time selection - SMP4: u3 = 0, - /// Channel 5 sample time selection - SMP5: u3 = 0, - /// Channel 6 sample time selection - SMP6: u3 = 0, - /// Channel 7 sample time selection - SMP7: u3 = 0, - /// Channel 8 sample time selection - SMP8: u3 = 0, - /// Channel 9 sample time selection - SMP9: u3 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Data offset for injected channel x - JOFFSET1: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Data offset for injected channel x - JOFFSET2: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - /// Data offset for injected channel x - JOFFSET3: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - /// Data offset for injected channel x - JOFFSET4: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog higher threshold register - pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - /// Analog watchdog higher threshold - HT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog lower threshold register - pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - /// Analog watchdog lower threshold - LT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - /// 13th conversion in regular sequence - SQ13: u5 = 0, - /// 14th conversion in regular sequence - SQ14: u5 = 0, - /// 15th conversion in regular sequence - SQ15: u5 = 0, - /// 16th conversion in regular sequence - SQ16: u5 = 0, - /// Regular channel sequence length - L: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - /// 7th conversion in regular sequence - SQ7: u5 = 0, - /// 8th conversion in regular sequence - SQ8: u5 = 0, - /// 9th conversion in regular sequence - SQ9: u5 = 0, - /// 10th conversion in regular sequence - SQ10: u5 = 0, - /// 11th conversion in regular sequence - SQ11: u5 = 0, - /// 12th conversion in regular sequence - SQ12: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - /// 1st conversion in regular sequence - SQ1: u5 = 0, - /// 2nd conversion in regular sequence - SQ2: u5 = 0, - /// 3rd conversion in regular sequence - SQ3: u5 = 0, - /// 4th conversion in regular sequence - SQ4: u5 = 0, - /// 5th conversion in regular sequence - SQ5: u5 = 0, - /// 6th conversion in regular sequence - SQ6: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - /// 1st conversion in injected sequence - JSQ1: u5 = 0, - /// 2nd conversion in injected sequence - JSQ2: u5 = 0, - /// 3rd conversion in injected sequence - JSQ3: u5 = 0, - /// 4th conversion in injected sequence - JSQ4: u5 = 0, - /// Injected sequence length - JL: u2 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular data register - pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - /// Regular data - DATA: u16 = 0, - /// ADC2 data - ADC2DATA: u16 = 0, - }); -}; +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); -/// Analog to digital converter -pub const ADC2 = extern struct { - pub const Address: u32 = 0x40012800; - - /// status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Analog watchdog flag - AWD: u1 = 0, - /// Regular channel end of conversion - EOC: u1 = 0, - /// Injected channel end of conversion - JEOC: u1 = 0, - /// Injected channel start flag - JSTRT: u1 = 0, - /// Regular channel start flag - STRT: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - /// Analog watchdog channel select bits - AWDCH: u5 = 0, - /// Interrupt enable for EOC - EOCIE: u1 = 0, - /// Analog watchdog interrupt enable - AWDIE: u1 = 0, - /// Interrupt enable for injected channels - JEOCIE: u1 = 0, - /// Scan mode - SCAN: u1 = 0, - /// Enable the watchdog on a single channel in scan mode - AWDSGL: u1 = 0, - /// Automatic injected group conversion - JAUTO: u1 = 0, - /// Discontinuous mode on regular channels - DISCEN: u1 = 0, - /// Discontinuous mode on injected channels - JDISCEN: u1 = 0, - /// Discontinuous mode channel count - DISCNUM: u3 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Analog watchdog enable on injected channels - JAWDEN: u1 = 0, - /// Analog watchdog enable on regular channels - AWDEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - /// A/D converter ON / OFF - ADON: u1 = 0, - /// Continuous conversion - CONT: u1 = 0, - /// A/D calibration - CAL: u1 = 0, - /// Reset calibration - RSTCAL: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Direct memory access mode - DMA: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Data alignment - ALIGN: u1 = 0, - /// External event select for injected group - JEXTSEL: u3 = 0, - /// External trigger conversion mode for injected channels - JEXTTRIG: u1 = 0, - reserved7: u1 = 0, - /// External event select for regular group - EXTSEL: u3 = 0, - /// External trigger conversion mode for regular channels - EXTTRIG: u1 = 0, - /// Start conversion of injected channels - JSWSTART: u1 = 0, - /// Start conversion of regular channels - SWSTART: u1 = 0, - /// Temperature sensor and VREFINT enable - TSVREFE: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Channel 10 sample time selection - SMP10: u3 = 0, - /// Channel 11 sample time selection - SMP11: u3 = 0, - /// Channel 12 sample time selection - SMP12: u3 = 0, - /// Channel 13 sample time selection - SMP13: u3 = 0, - /// Channel 14 sample time selection - SMP14: u3 = 0, - /// Channel 15 sample time selection - SMP15: u3 = 0, - /// Channel 16 sample time selection - SMP16: u3 = 0, - /// Channel 17 sample time selection - SMP17: u3 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Channel 0 sample time selection - SMP0: u3 = 0, - /// Channel 1 sample time selection - SMP1: u3 = 0, - /// Channel 2 sample time selection - SMP2: u3 = 0, - /// Channel 3 sample time selection - SMP3: u3 = 0, - /// Channel 4 sample time selection - SMP4: u3 = 0, - /// Channel 5 sample time selection - SMP5: u3 = 0, - /// Channel 6 sample time selection - SMP6: u3 = 0, - /// Channel 7 sample time selection - SMP7: u3 = 0, - /// Channel 8 sample time selection - SMP8: u3 = 0, - /// Channel 9 sample time selection - SMP9: u3 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Data offset for injected channel x - JOFFSET1: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Data offset for injected channel x - JOFFSET2: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - /// Data offset for injected channel x - JOFFSET3: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - /// Data offset for injected channel x - JOFFSET4: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog higher threshold register - pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - /// Analog watchdog higher threshold - HT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog lower threshold register - pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - /// Analog watchdog lower threshold - LT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - /// 13th conversion in regular sequence - SQ13: u5 = 0, - /// 14th conversion in regular sequence - SQ14: u5 = 0, - /// 15th conversion in regular sequence - SQ15: u5 = 0, - /// 16th conversion in regular sequence - SQ16: u5 = 0, - /// Regular channel sequence length - L: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - /// 7th conversion in regular sequence - SQ7: u5 = 0, - /// 8th conversion in regular sequence - SQ8: u5 = 0, - /// 9th conversion in regular sequence - SQ9: u5 = 0, - /// 10th conversion in regular sequence - SQ10: u5 = 0, - /// 11th conversion in regular sequence - SQ11: u5 = 0, - /// 12th conversion in regular sequence - SQ12: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - /// 1st conversion in regular sequence - SQ1: u5 = 0, - /// 2nd conversion in regular sequence - SQ2: u5 = 0, - /// 3rd conversion in regular sequence - SQ3: u5 = 0, - /// 4th conversion in regular sequence - SQ4: u5 = 0, - /// 5th conversion in regular sequence - SQ5: u5 = 0, - /// 6th conversion in regular sequence - SQ6: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - /// 1st conversion in injected sequence - JSQ1: u5 = 0, - /// 2nd conversion in injected sequence - JSQ2: u5 = 0, - /// 3rd conversion in injected sequence - JSQ3: u5 = 0, - /// 4th conversion in injected sequence - JSQ4: u5 = 0, - /// Injected sequence length - JL: u2 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular data register - pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - /// Regular data - DATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); -/// Analog to digital converter -pub const ADC3 = extern struct { - pub const Address: u32 = 0x40013c00; - - /// status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Analog watchdog flag - AWD: u1 = 0, - /// Regular channel end of conversion - EOC: u1 = 0, - /// Injected channel end of conversion - JEOC: u1 = 0, - /// Injected channel start flag - JSTRT: u1 = 0, - /// Regular channel start flag - STRT: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - /// Analog watchdog channel select bits - AWDCH: u5 = 0, - /// Interrupt enable for EOC - EOCIE: u1 = 0, - /// Analog watchdog interrupt enable - AWDIE: u1 = 0, - /// Interrupt enable for injected channels - JEOCIE: u1 = 0, - /// Scan mode - SCAN: u1 = 0, - /// Enable the watchdog on a single channel in scan mode - AWDSGL: u1 = 0, - /// Automatic injected group conversion - JAUTO: u1 = 0, - /// Discontinuous mode on regular channels - DISCEN: u1 = 0, - /// Discontinuous mode on injected channels - JDISCEN: u1 = 0, - /// Discontinuous mode channel count - DISCNUM: u3 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Analog watchdog enable on injected channels - JAWDEN: u1 = 0, - /// Analog watchdog enable on regular channels - AWDEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - /// A/D converter ON / OFF - ADON: u1 = 0, - /// Continuous conversion - CONT: u1 = 0, - /// A/D calibration - CAL: u1 = 0, - /// Reset calibration - RSTCAL: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Direct memory access mode - DMA: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Data alignment - ALIGN: u1 = 0, - /// External event select for injected group - JEXTSEL: u3 = 0, - /// External trigger conversion mode for injected channels - JEXTTRIG: u1 = 0, - reserved7: u1 = 0, - /// External event select for regular group - EXTSEL: u3 = 0, - /// External trigger conversion mode for regular channels - EXTTRIG: u1 = 0, - /// Start conversion of injected channels - JSWSTART: u1 = 0, - /// Start conversion of regular channels - SWSTART: u1 = 0, - /// Temperature sensor and VREFINT enable - TSVREFE: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Channel 10 sample time selection - SMP10: u3 = 0, - /// Channel 11 sample time selection - SMP11: u3 = 0, - /// Channel 12 sample time selection - SMP12: u3 = 0, - /// Channel 13 sample time selection - SMP13: u3 = 0, - /// Channel 14 sample time selection - SMP14: u3 = 0, - /// Channel 15 sample time selection - SMP15: u3 = 0, - /// Channel 16 sample time selection - SMP16: u3 = 0, - /// Channel 17 sample time selection - SMP17: u3 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Channel 0 sample time selection - SMP0: u3 = 0, - /// Channel 1 sample time selection - SMP1: u3 = 0, - /// Channel 2 sample time selection - SMP2: u3 = 0, - /// Channel 3 sample time selection - SMP3: u3 = 0, - /// Channel 4 sample time selection - SMP4: u3 = 0, - /// Channel 5 sample time selection - SMP5: u3 = 0, - /// Channel 6 sample time selection - SMP6: u3 = 0, - /// Channel 7 sample time selection - SMP7: u3 = 0, - /// Channel 8 sample time selection - SMP8: u3 = 0, - /// Channel 9 sample time selection - SMP9: u3 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Data offset for injected channel x - JOFFSET1: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Data offset for injected channel x - JOFFSET2: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - /// Data offset for injected channel x - JOFFSET3: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - /// Data offset for injected channel x - JOFFSET4: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog higher threshold register - pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - /// Analog watchdog higher threshold - HT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog lower threshold register - pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - /// Analog watchdog lower threshold - LT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - /// 13th conversion in regular sequence - SQ13: u5 = 0, - /// 14th conversion in regular sequence - SQ14: u5 = 0, - /// 15th conversion in regular sequence - SQ15: u5 = 0, - /// 16th conversion in regular sequence - SQ16: u5 = 0, - /// Regular channel sequence length - L: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - /// 7th conversion in regular sequence - SQ7: u5 = 0, - /// 8th conversion in regular sequence - SQ8: u5 = 0, - /// 9th conversion in regular sequence - SQ9: u5 = 0, - /// 10th conversion in regular sequence - SQ10: u5 = 0, - /// 11th conversion in regular sequence - SQ11: u5 = 0, - /// 12th conversion in regular sequence - SQ12: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - /// 1st conversion in regular sequence - SQ1: u5 = 0, - /// 2nd conversion in regular sequence - SQ2: u5 = 0, - /// 3rd conversion in regular sequence - SQ3: u5 = 0, - /// 4th conversion in regular sequence - SQ4: u5 = 0, - /// 5th conversion in regular sequence - SQ5: u5 = 0, - /// 6th conversion in regular sequence - SQ6: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - /// 1st conversion in injected sequence - JSQ1: u5 = 0, - /// 2nd conversion in injected sequence - JSQ2: u5 = 0, - /// 3rd conversion in injected sequence - JSQ3: u5 = 0, - /// 4th conversion in injected sequence - JSQ4: u5 = 0, - /// Injected sequence length - JL: u2 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular data register - pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - /// Regular data - DATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + const IntT = std.meta.Int(.unsigned, size); -/// Controller area network -pub const CAN = extern struct { - pub const Address: u32 = 0x40006400; - - /// CAN_MCR - pub const CAN_MCR = mmio(Address + 0x00000000, 32, packed struct { - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_MSR - pub const CAN_MSR = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_TSR - pub const CAN_TSR = mmio(Address + 0x00000008, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Lowest priority flag for mailbox 0 - TME0: u1 = 0, - /// Lowest priority flag for mailbox 1 - TME1: u1 = 0, - /// Lowest priority flag for mailbox 2 - TME2: u1 = 0, - /// Lowest priority flag for mailbox 0 - LOW0: u1 = 0, - /// Lowest priority flag for mailbox 1 - LOW1: u1 = 0, - /// Lowest priority flag for mailbox 2 - LOW2: u1 = 0, - }); - - /// CAN_RF0R - pub const CAN_RF0R = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_RF1R - pub const CAN_RF1R = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_IER - pub const CAN_IER = mmio(Address + 0x00000014, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_ESR - pub const CAN_ESR = mmio(Address + 0x00000018, 32, packed struct { - reserved1: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - }); - - /// CAN_BTR - pub const CAN_BTR = mmio(Address + 0x0000001c, 32, packed struct { - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved7: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - }); - - /// CAN_TI0R - pub const CAN_TI0R = mmio(Address + 0x00000180, 32, packed struct {}); - - /// CAN_TDT0R - pub const CAN_TDT0R = mmio(Address + 0x00000184, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// CAN_TDL0R - pub const CAN_TDL0R = mmio(Address + 0x00000188, 32, packed struct {}); - - /// CAN_TDH0R - pub const CAN_TDH0R = mmio(Address + 0x0000018c, 32, packed struct {}); - - /// CAN_TI1R - pub const CAN_TI1R = mmio(Address + 0x00000190, 32, packed struct {}); - - /// CAN_TDT1R - pub const CAN_TDT1R = mmio(Address + 0x00000194, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// CAN_TDL1R - pub const CAN_TDL1R = mmio(Address + 0x00000198, 32, packed struct {}); - - /// CAN_TDH1R - pub const CAN_TDH1R = mmio(Address + 0x0000019c, 32, packed struct {}); - - /// CAN_TI2R - pub const CAN_TI2R = mmio(Address + 0x000001a0, 32, packed struct {}); - - /// CAN_TDT2R - pub const CAN_TDT2R = mmio(Address + 0x000001a4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// CAN_TDL2R - pub const CAN_TDL2R = mmio(Address + 0x000001a8, 32, packed struct {}); - - /// CAN_TDH2R - pub const CAN_TDH2R = mmio(Address + 0x000001ac, 32, packed struct {}); - - /// CAN_RI0R - pub const CAN_RI0R = mmio(Address + 0x000001b0, 32, packed struct { - reserved1: u1 = 0, - }); - - /// CAN_RDT0R - pub const CAN_RDT0R = mmio(Address + 0x000001b4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// CAN_RDL0R - pub const CAN_RDL0R = mmio(Address + 0x000001b8, 32, packed struct {}); - - /// CAN_RDH0R - pub const CAN_RDH0R = mmio(Address + 0x000001bc, 32, packed struct {}); - - /// CAN_RI1R - pub const CAN_RI1R = mmio(Address + 0x000001c0, 32, packed struct { - reserved1: u1 = 0, - }); - - /// CAN_RDT1R - pub const CAN_RDT1R = mmio(Address + 0x000001c4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// CAN_RDL1R - pub const CAN_RDL1R = mmio(Address + 0x000001c8, 32, packed struct {}); - - /// CAN_RDH1R - pub const CAN_RDH1R = mmio(Address + 0x000001cc, 32, packed struct {}); - - /// CAN_FMR - pub const CAN_FMR = mmio(Address + 0x00000200, 32, packed struct { - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_FM1R - pub const CAN_FM1R = mmio(Address + 0x00000204, 32, packed struct { - /// Filter mode - FBM0: u1 = 0, - /// Filter mode - FBM1: u1 = 0, - /// Filter mode - FBM2: u1 = 0, - /// Filter mode - FBM3: u1 = 0, - /// Filter mode - FBM4: u1 = 0, - /// Filter mode - FBM5: u1 = 0, - /// Filter mode - FBM6: u1 = 0, - /// Filter mode - FBM7: u1 = 0, - /// Filter mode - FBM8: u1 = 0, - /// Filter mode - FBM9: u1 = 0, - /// Filter mode - FBM10: u1 = 0, - /// Filter mode - FBM11: u1 = 0, - /// Filter mode - FBM12: u1 = 0, - /// Filter mode - FBM13: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_FS1R - pub const CAN_FS1R = mmio(Address + 0x0000020c, 32, packed struct { - /// Filter scale configuration - FSC0: u1 = 0, - /// Filter scale configuration - FSC1: u1 = 0, - /// Filter scale configuration - FSC2: u1 = 0, - /// Filter scale configuration - FSC3: u1 = 0, - /// Filter scale configuration - FSC4: u1 = 0, - /// Filter scale configuration - FSC5: u1 = 0, - /// Filter scale configuration - FSC6: u1 = 0, - /// Filter scale configuration - FSC7: u1 = 0, - /// Filter scale configuration - FSC8: u1 = 0, - /// Filter scale configuration - FSC9: u1 = 0, - /// Filter scale configuration - FSC10: u1 = 0, - /// Filter scale configuration - FSC11: u1 = 0, - /// Filter scale configuration - FSC12: u1 = 0, - /// Filter scale configuration - FSC13: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_FFA1R - pub const CAN_FFA1R = mmio(Address + 0x00000214, 32, packed struct { - /// Filter FIFO assignment for filter 0 - FFA0: u1 = 0, - /// Filter FIFO assignment for filter 1 - FFA1: u1 = 0, - /// Filter FIFO assignment for filter 2 - FFA2: u1 = 0, - /// Filter FIFO assignment for filter 3 - FFA3: u1 = 0, - /// Filter FIFO assignment for filter 4 - FFA4: u1 = 0, - /// Filter FIFO assignment for filter 5 - FFA5: u1 = 0, - /// Filter FIFO assignment for filter 6 - FFA6: u1 = 0, - /// Filter FIFO assignment for filter 7 - FFA7: u1 = 0, - /// Filter FIFO assignment for filter 8 - FFA8: u1 = 0, - /// Filter FIFO assignment for filter 9 - FFA9: u1 = 0, - /// Filter FIFO assignment for filter 10 - FFA10: u1 = 0, - /// Filter FIFO assignment for filter 11 - FFA11: u1 = 0, - /// Filter FIFO assignment for filter 12 - FFA12: u1 = 0, - /// Filter FIFO assignment for filter 13 - FFA13: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_FA1R - pub const CAN_FA1R = mmio(Address + 0x0000021c, 32, packed struct { - /// Filter active - FACT0: u1 = 0, - /// Filter active - FACT1: u1 = 0, - /// Filter active - FACT2: u1 = 0, - /// Filter active - FACT3: u1 = 0, - /// Filter active - FACT4: u1 = 0, - /// Filter active - FACT5: u1 = 0, - /// Filter active - FACT6: u1 = 0, - /// Filter active - FACT7: u1 = 0, - /// Filter active - FACT8: u1 = 0, - /// Filter active - FACT9: u1 = 0, - /// Filter active - FACT10: u1 = 0, - /// Filter active - FACT11: u1 = 0, - /// Filter active - FACT12: u1 = 0, - /// Filter active - FACT13: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Filter bank 0 register 1 - pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 0 register 2 - pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 1 register 1 - pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 1 register 2 - pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 2 register 1 - pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 2 register 2 - pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 3 register 1 - pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 3 register 2 - pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 1 - pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 2 - pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 5 register 1 - pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 5 register 2 - pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 6 register 1 - pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 6 register 2 - pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 7 register 1 - pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 7 register 2 - pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 8 register 1 - pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 8 register 2 - pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 9 register 1 - pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 9 register 2 - pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 10 register 1 - pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 10 register 2 - pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 11 register 1 - pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 11 register 2 - pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 1 - pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 12 register 2 - pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 13 register 1 - pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 13 register 2 - pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); -}; + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); -/// Digital to analog converter -pub const DAC = extern struct { - pub const Address: u32 = 0x40007400; - - /// Control register (DAC_CR) - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// DAC channel1 enable - EN1: u1 = 0, - /// DAC channel1 output buffer disable - BOFF1: u1 = 0, - /// DAC channel1 trigger enable - TEN1: u1 = 0, - /// DAC channel1 trigger selection - TSEL1: u3 = 0, - /// DAC channel1 noise/triangle wave generation enable - WAVE1: u2 = 0, - /// DAC channel1 mask/amplitude selector - MAMP1: u4 = 0, - /// DAC channel1 DMA enable - DMAEN1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 enable - EN2: u1 = 0, - /// DAC channel2 output buffer disable - BOFF2: u1 = 0, - /// DAC channel2 trigger enable - TEN2: u1 = 0, - /// DAC channel2 trigger selection - TSEL2: u3 = 0, - /// DAC channel2 noise/triangle wave generation enable - WAVE2: u2 = 0, - /// DAC channel2 mask/amplitude selector - MAMP2: u4 = 0, - /// DAC channel2 DMA enable - DMAEN2: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC software trigger register (DAC_SWTRIGR) - pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { - /// DAC channel1 software trigger - SWTRIG1: u1 = 0, - /// DAC channel2 software trigger - SWTRIG2: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1) - pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { - /// DAC channel1 12-bit right-aligned data - DACC1DHR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) - pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel1 12-bit left-aligned data - DACC1DHR: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) - pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { - /// DAC channel1 8-bit right-aligned data - DACC1DHR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) - pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { - /// DAC channel2 12-bit right-aligned data - DACC2DHR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) - pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 12-bit left-aligned data - DACC2DHR: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) - pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { - /// DAC channel2 8-bit right-aligned data - DACC2DHR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits - /// 31:28 Reserved, Bits 15:12 Reserved - pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { - /// DAC channel1 12-bit right-aligned data - DACC1DHR: u12 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 12-bit right-aligned data - DACC2DHR: u12 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 - /// Reserved, Bits 3:0 Reserved - pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel1 12-bit left-aligned data - DACC1DHR: u12 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// DAC channel2 12-bit right-aligned data - DACC2DHR: u12 = 0, - }); - - /// DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 - /// Reserved - pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { - /// DAC channel1 8-bit right-aligned data - DACC1DHR: u8 = 0, - /// DAC channel2 8-bit right-aligned data - DACC2DHR: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel1 data output register (DAC_DOR1) - pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { - /// DAC channel1 data output - DACC1DOR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel2 data output register (DAC_DOR2) - pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { - /// DAC channel2 data output - DACC2DOR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + return extern struct { + const Self = @This(); -/// Debug support -pub const DBG = extern struct { - pub const Address: u32 = 0xe0042000; - - /// DBGMCU_IDCODE - pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// DBGMCU_CR - pub const CR = mmio(Address + 0x00000004, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + raw: IntT, -/// Universal asynchronous receiver transmitter -pub const UART4 = extern struct { - pub const Address: u32 = 0x40004c00; - - /// UART4_SR - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise error flag - NE: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// IDLE line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBD: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_DR - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_BRR - pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR1 - pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Send break - SBK: u1 = 0, - /// Receiver wakeup - RWU: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// TXE interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// USART enable - UE: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR2 - pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Address of the USART node - ADD: u4 = 0, - reserved1: u1 = 0, - /// lin break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR3 - pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const underlying_type = PackedT; -/// Universal asynchronous receiver transmitter -pub const UART5 = extern struct { - pub const Address: u32 = 0x40005000; - - /// UART4_SR - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_DR - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_BRR - pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR1 - pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR2 - pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR3 - pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } -/// CRC calculation unit -pub const CRC = extern struct { - pub const Address: u32 = 0x40023000; + pub fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } - /// Data register - pub const DR = @intToPtr(*volatile u32, Address + 0x00000000); + pub fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } - /// Independent Data register - pub const IDR = mmio(Address + 0x00000004, 32, packed struct { - /// Independent Data register - IDR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - /// Reset bit - RESET: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} -/// FLASH -pub const FLASH = extern struct { - pub const Address: u32 = 0x40022000; - - /// Flash access control register - pub const ACR = mmio(Address + 0x00000000, 32, packed struct { - /// Latency - LATENCY: u3 = 0, - /// Flash half cycle access enable - HLFCYA: u1 = 0, - /// Prefetch buffer enable - PRFTBE: u1 = 0, - /// Prefetch buffer status - PRFTBS: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Flash key register - pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { - /// FPEC key - KEY: u32 = 0, - }); - - /// Flash option key register - pub const OPTKEYR = mmio(Address + 0x00000008, 32, packed struct { - /// Option byte key - OPTKEY: u32 = 0, - }); - - /// Status register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - /// Busy - BSY: u1 = 0, - reserved1: u1 = 0, - /// Programming error - PGERR: u1 = 0, - reserved2: u1 = 0, - /// Write protection error - WRPRTERR: u1 = 0, - /// End of operation - EOP: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register - pub const CR = mmio(Address + 0x00000010, 32, packed struct { - /// Programming - PG: u1 = 0, - /// Page Erase - PER: u1 = 0, - /// Mass Erase - MER: u1 = 0, - reserved1: u1 = 0, - /// Option byte programming - OPTPG: u1 = 0, - /// Option byte erase - OPTER: u1 = 0, - /// Start - STRT: u1 = 0, - /// Lock - LOCK: u1 = 0, - reserved2: u1 = 0, - /// Option bytes write enable - OPTWRE: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - reserved3: u1 = 0, - /// End of operation interrupt enable - EOPIE: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Flash address register - pub const AR = mmio(Address + 0x00000014, 32, packed struct { - /// Flash Address - FAR: u32 = 0, - }); - - /// Option byte register - pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { - /// Option byte error - OPTERR: u1 = 0, - /// Read protection - RDPRT: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Write protection register - pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { - /// Write protect - WRP: u32 = 0, - }); -}; +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); -/// Nested Vectored Interrupt Controller -pub const NVIC = extern struct { - pub const Address: u32 = 0xe000e000; - - /// Interrupt Controller Type Register - pub const ICTR = mmio(Address + 0x00000004, 32, packed struct { - /// Total number of interrupt lines in groups - INTLINESNUM: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt Set-Enable Register - pub const ISER0 = mmio(Address + 0x00000100, 32, packed struct {}); - - /// Interrupt Set-Enable Register - pub const ISER1 = mmio(Address + 0x00000104, 32, packed struct {}); - - /// Interrupt Clear-Enable Register - pub const ICER0 = mmio(Address + 0x00000180, 32, packed struct {}); - - /// Interrupt Clear-Enable Register - pub const ICER1 = mmio(Address + 0x00000184, 32, packed struct {}); - - /// Interrupt Set-Pending Register - pub const ISPR0 = mmio(Address + 0x00000200, 32, packed struct {}); - - /// Interrupt Set-Pending Register - pub const ISPR1 = mmio(Address + 0x00000204, 32, packed struct {}); - - /// Interrupt Clear-Pending Register - pub const ICPR0 = mmio(Address + 0x00000280, 32, packed struct {}); - - /// Interrupt Clear-Pending Register - pub const ICPR1 = mmio(Address + 0x00000284, 32, packed struct {}); - - /// Interrupt Active Bit Register - pub const IABR0 = mmio(Address + 0x00000300, 32, packed struct {}); - - /// Interrupt Active Bit Register - pub const IABR1 = mmio(Address + 0x00000304, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR0 = mmio(Address + 0x00000400, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR1 = mmio(Address + 0x00000404, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR2 = mmio(Address + 0x00000408, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR3 = mmio(Address + 0x0000040c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR4 = mmio(Address + 0x00000410, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR5 = mmio(Address + 0x00000414, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR6 = mmio(Address + 0x00000418, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR7 = mmio(Address + 0x0000041c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR8 = mmio(Address + 0x00000420, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR9 = mmio(Address + 0x00000424, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR10 = mmio(Address + 0x00000428, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR11 = mmio(Address + 0x0000042c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR12 = mmio(Address + 0x00000430, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR13 = mmio(Address + 0x00000434, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR14 = mmio(Address + 0x00000438, 32, packed struct {}); - - /// Software Triggered Interrupt Register - pub const STIR = mmio(Address + 0x00000f00, 32, packed struct { - /// interrupt to be triggered - INTID: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + raw: std.meta.Int(.unsigned, size), -/// Universal serial bus full-speed device interface -pub const USB = extern struct { - pub const Address: u32 = 0x40005c00; - - /// endpoint 0 register - pub const EP0R = mmio(Address + 0x00000000, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 1 register - pub const EP1R = mmio(Address + 0x00000004, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 2 register - pub const EP2R = mmio(Address + 0x00000008, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 3 register - pub const EP3R = mmio(Address + 0x0000000c, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 4 register - pub const EP4R = mmio(Address + 0x00000010, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 5 register - pub const EP5R = mmio(Address + 0x00000014, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 6 register - pub const EP6R = mmio(Address + 0x00000018, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 7 register - pub const EP7R = mmio(Address + 0x0000001c, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CNTR = mmio(Address + 0x00000040, 32, packed struct { - /// Force USB Reset - FRES: u1 = 0, - /// Power down - PDWN: u1 = 0, - /// Low-power mode - LPMODE: u1 = 0, - /// Force suspend - FSUSP: u1 = 0, - /// Resume request - RESUME: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Expected start of frame interrupt mask - ESOFM: u1 = 0, - /// Start of frame interrupt mask - SOFM: u1 = 0, - /// USB reset interrupt mask - RESETM: u1 = 0, - /// Suspend mode interrupt mask - SUSPM: u1 = 0, - /// Wakeup interrupt mask - WKUPM: u1 = 0, - /// Error interrupt mask - ERRM: u1 = 0, - /// Packet memory area over / underrun interrupt mask - PMAOVRM: u1 = 0, - /// Correct transfer interrupt mask - CTRM: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt status register - pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { - /// Endpoint Identifier - EP_ID: u4 = 0, - /// Direction of transaction - DIR: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Expected start frame - ESOF: u1 = 0, - /// start of frame - SOF: u1 = 0, - /// reset request - RESET: u1 = 0, - /// Suspend mode request - SUSP: u1 = 0, - /// Wakeup - WKUP: u1 = 0, - /// Error - ERR: u1 = 0, - /// Packet memory area over / underrun - PMAOVR: u1 = 0, - /// Correct transfer - CTR: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// frame number register - pub const FNR = mmio(Address + 0x00000048, 32, packed struct { - /// Frame number - FN: u11 = 0, - /// Lost SOF - LSOF: u2 = 0, - /// Locked - LCK: u1 = 0, - /// Receive data - line status - RXDM: u1 = 0, - /// Receive data + line status - RXDP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// device address - pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { - /// Device address - ADD: u7 = 0, - /// Enable function - EF: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Buffer table address - pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Buffer table - BTABLE: u13 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } -const std = @import("std"); -const root = @import("root"); -const cpu = @import("cpu"); -const config = @import("microzig-config"); -const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; + pub fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); -fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { - return InterruptVector{ - .C = struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt: " ++ str); - } - }.unhandledInterrupt, + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } }; } -pub const VectorTable = extern struct { - initial_stack_pointer: u32 = config.end_of_stack, - Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, - NMI: InterruptVector = makeUnhandledHandler("NMI"), - HardFault: InterruptVector = makeUnhandledHandler("HardFault"), - MemManage: InterruptVector = makeUnhandledHandler("MemManage"), - BusFault: InterruptVector = makeUnhandledHandler("BusFault"), - UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), - - reserved: [4]u32 = .{ 0, 0, 0, 0 }, - SVCall: InterruptVector = makeUnhandledHandler("SVCall"), - DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), - reserved1: u32 = 0, - - PendSV: InterruptVector = makeUnhandledHandler("PendSV"), - SysTick: InterruptVector = makeUnhandledHandler("SysTick"), - - /// Window Watchdog interrupt - WWDG: InterruptVector = makeUnhandledHandler("WWDG"), - /// PVD through EXTI line detection interrupt - PVD: InterruptVector = makeUnhandledHandler("PVD"), - /// Tamper interrupt - TAMPER: InterruptVector = makeUnhandledHandler("TAMPER"), - /// RTC global interrupt - RTC: InterruptVector = makeUnhandledHandler("RTC"), - /// Flash global interrupt - FLASH: InterruptVector = makeUnhandledHandler("FLASH"), - /// RCC global interrupt - RCC: InterruptVector = makeUnhandledHandler("RCC"), - /// EXTI Line0 interrupt - EXTI0: InterruptVector = makeUnhandledHandler("EXTI0"), - /// EXTI Line1 interrupt - EXTI1: InterruptVector = makeUnhandledHandler("EXTI1"), - /// EXTI Line2 interrupt - EXTI2: InterruptVector = makeUnhandledHandler("EXTI2"), - /// EXTI Line3 interrupt - EXTI3: InterruptVector = makeUnhandledHandler("EXTI3"), - /// EXTI Line4 interrupt - EXTI4: InterruptVector = makeUnhandledHandler("EXTI4"), - /// DMA1 Channel1 global interrupt - DMA1_Channel1: InterruptVector = makeUnhandledHandler("DMA1_Channel1"), - /// DMA1 Channel2 global interrupt - DMA1_Channel2: InterruptVector = makeUnhandledHandler("DMA1_Channel2"), - /// DMA1 Channel3 global interrupt - DMA1_Channel3: InterruptVector = makeUnhandledHandler("DMA1_Channel3"), - /// DMA1 Channel4 global interrupt - DMA1_Channel4: InterruptVector = makeUnhandledHandler("DMA1_Channel4"), - /// DMA1 Channel5 global interrupt - DMA1_Channel5: InterruptVector = makeUnhandledHandler("DMA1_Channel5"), - /// DMA1 Channel6 global interrupt - DMA1_Channel6: InterruptVector = makeUnhandledHandler("DMA1_Channel6"), - /// DMA1 Channel7 global interrupt - DMA1_Channel7: InterruptVector = makeUnhandledHandler("DMA1_Channel7"), - /// ADC1 global interrupt; ADC2 global interrupt - ADC: InterruptVector = makeUnhandledHandler("ADC"), - /// CAN1 TX interrupts - CAN1_TX: InterruptVector = makeUnhandledHandler("CAN1_TX"), - /// CAN1 RX0 interrupts - CAN1_RX0: InterruptVector = makeUnhandledHandler("CAN1_RX0"), - /// CAN1 RX1 interrupt - CAN1_RX1: InterruptVector = makeUnhandledHandler("CAN1_RX1"), - /// CAN1 SCE interrupt - CAN1_SCE: InterruptVector = makeUnhandledHandler("CAN1_SCE"), - /// EXTI Line[9:5] interrupts - EXTI9_5: InterruptVector = makeUnhandledHandler("EXTI9_5"), - /// TIM1 Break interrupt and TIM9 global interrupt - TIM1_BRK_TIM9: InterruptVector = makeUnhandledHandler("TIM1_BRK_TIM9"), - /// TIM1 Update interrupt and TIM10 global interrupt - TIM1_UP_TIM10: InterruptVector = makeUnhandledHandler("TIM1_UP_TIM10"), - /// TIM1 Trigger and Commutation interrupts and TIM11 global interrupt - TIM1_TRG_COM_TIM11: InterruptVector = makeUnhandledHandler("TIM1_TRG_COM_TIM11"), - /// TIM1 Capture Compare interrupt - TIM1_CC: InterruptVector = makeUnhandledHandler("TIM1_CC"), - /// TIM2 global interrupt - TIM2: InterruptVector = makeUnhandledHandler("TIM2"), - /// TIM3 global interrupt - TIM3: InterruptVector = makeUnhandledHandler("TIM3"), - /// TIM4 global interrupt - TIM4: InterruptVector = makeUnhandledHandler("TIM4"), - /// I2C1 event interrupt - I2C1_EV: InterruptVector = makeUnhandledHandler("I2C1_EV"), - /// I2C1 error interrupt - I2C1_ER: InterruptVector = makeUnhandledHandler("I2C1_ER"), - /// I2C2 event interrupt - I2C2_EV: InterruptVector = makeUnhandledHandler("I2C2_EV"), - /// I2C2 error interrupt - I2C2_ER: InterruptVector = makeUnhandledHandler("I2C2_ER"), - /// SPI1 global interrupt - SPI1: InterruptVector = makeUnhandledHandler("SPI1"), - /// SPI2 global interrupt - SPI2: InterruptVector = makeUnhandledHandler("SPI2"), - /// USART1 global interrupt - USART1: InterruptVector = makeUnhandledHandler("USART1"), - /// USART2 global interrupt - USART2: InterruptVector = makeUnhandledHandler("USART2"), - /// USART3 global interrupt - USART3: InterruptVector = makeUnhandledHandler("USART3"), - /// EXTI Line[15:10] interrupts - EXTI15_10: InterruptVector = makeUnhandledHandler("EXTI15_10"), - /// RTC Alarms through EXTI line interrupt - RTCAlarm: InterruptVector = makeUnhandledHandler("RTCAlarm"), - /// USB Device FS Wakeup through EXTI line interrupt - USB_FS_WKUP: InterruptVector = makeUnhandledHandler("USB_FS_WKUP"), - /// TIM8 Break interrupt and TIM12 global interrupt - TIM8_BRK_TIM12: InterruptVector = makeUnhandledHandler("TIM8_BRK_TIM12"), - /// TIM8 Update interrupt and TIM13 global interrupt - TIM8_UP_TIM13: InterruptVector = makeUnhandledHandler("TIM8_UP_TIM13"), - /// TIM8 Trigger and Commutation interrupts and TIM14 global interrupt - TIM8_TRG_COM_TIM14: InterruptVector = makeUnhandledHandler("TIM8_TRG_COM_TIM14"), - /// TIM8 Capture Compare interrupt - TIM8_CC: InterruptVector = makeUnhandledHandler("TIM8_CC"), - /// ADC3 global interrupt - ADC3: InterruptVector = makeUnhandledHandler("ADC3"), - /// FSMC global interrupt - FSMC: InterruptVector = makeUnhandledHandler("FSMC"), - /// SDIO global interrupt - SDIO: InterruptVector = makeUnhandledHandler("SDIO"), - /// TIM5 global interrupt - TIM5: InterruptVector = makeUnhandledHandler("TIM5"), - /// SPI3 global interrupt - SPI3: InterruptVector = makeUnhandledHandler("SPI3"), - /// UART4 global interrupt - UART4: InterruptVector = makeUnhandledHandler("UART4"), - /// UART5 global interrupt - UART5: InterruptVector = makeUnhandledHandler("UART5"), - /// TIM6 global interrupt - TIM6: InterruptVector = makeUnhandledHandler("TIM6"), - /// TIM7 global interrupt - TIM7: InterruptVector = makeUnhandledHandler("TIM7"), - /// DMA2 Channel1 global interrupt - DMA2_Channel1: InterruptVector = makeUnhandledHandler("DMA2_Channel1"), - /// DMA2 Channel2 global interrupt - DMA2_Channel2: InterruptVector = makeUnhandledHandler("DMA2_Channel2"), - /// DMA2 Channel3 global interrupt - DMA2_Channel3: InterruptVector = makeUnhandledHandler("DMA2_Channel3"), - /// DMA2 Channel4 and DMA2 Channel5 global interrupt - DMA2_Channel4_5: InterruptVector = makeUnhandledHandler("DMA2_Channel4_5"), -}; - -fn isValidField(field_name: []const u8) bool { - return !std.mem.startsWith(u8, field_name, "reserved") and - !std.mem.eql(u8, field_name, "initial_stack_pointer") and - !std.mem.eql(u8, field_name, "reset"); +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); } -export const vectors: VectorTable linksection("microzig_flash_start") = blk: { - var temp: VectorTable = .{}; - if (@hasDecl(root, "vector_table")) { - const vector_table = root.vector_table; - if (@typeInfo(vector_table) != .Struct) - @compileLog("root.vector_table must be a struct"); - - inline for (@typeInfo(vector_table).Struct.decls) |decl| { - const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; - const handler = @field(vector_table, decl.name); - - if (!@hasField(VectorTable, decl.name)) { - var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; - inline for (std.meta.fields(VectorTable)) |field| { - if (isValidField(field.name)) { - msg = msg ++ " " ++ field.name ++ "\n"; - } - } - - @compileError(msg); - } +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; - if (!isValidField(decl.name)) - @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); - - @field(temp, decl.name) = switch (calling_convention) { - .C => .{ .C = handler }, - .Naked => .{ .Naked = handler }, - // for unspecified calling convention we are going to generate small wrapper - .Unspecified => .{ - .C = struct { - fn wrapper() callconv(.C) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - }, - - else => @compileError("unsupported calling convention for function " ++ decl.name), - }; +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); } - } - break :blk temp; + }.tmp, }; diff --git a/src/modules/chips/stm32f103/stm32f103.zig b/src/modules/chips/stm32f103/stm32f103.zig index f9865cd..e2d554e 100644 --- a/src/modules/chips/stm32f103/stm32f103.zig +++ b/src/modules/chips/stm32f103/stm32f103.zig @@ -1,3 +1,2 @@ pub const cpu = @import("cpu"); -pub const registers = @import("registers.zig"); -pub const VectorTable = registers.VectorTable; +pub usingnamespace @import("registers.zig"); diff --git a/src/modules/chips/stm32f303/registers.zig b/src/modules/chips/stm32f303/registers.zig index 88c3635..f5a994a 100644 --- a/src/modules/chips/stm32f303/registers.zig +++ b/src/modules/chips/stm32f303/registers.zig @@ -1,29546 +1,34412 @@ -// generated using svd2zig.py -// DO NOT EDIT -// based on STM32F303 version 1.4 -const microzig_mmio = @import("microzig-mmio"); -const mmio = microzig_mmio.mmio; -const MMIO = microzig_mmio.MMIO; -const Name = "STM32F303"; - -/// General-purpose I/Os -pub const GPIOA = extern struct { - pub const Address: u32 = 0x48000000; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OT0: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT1: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT2: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT3: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT4: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT5: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT6: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT7: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT8: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT9: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT10: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT11: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT12: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT13: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT14: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOB = extern struct { - pub const Address: u32 = 0x48000400; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOC = extern struct { - pub const Address: u32 = 0x48000800; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOD = extern struct { - pub const Address: u32 = 0x48000c00; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOE = extern struct { - pub const Address: u32 = 0x48001000; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOF = extern struct { - pub const Address: u32 = 0x48001400; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOG = extern struct { - pub const Address: u32 = 0x48001800; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOH = extern struct { - pub const Address: u32 = 0x48001c00; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Touch sensing controller -pub const TSC = extern struct { - pub const Address: u32 = 0x40024000; - - /// control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// Touch sensing controller enable - TSCE: u1 = 0, - /// Start a new acquisition - START: u1 = 0, - /// Acquisition mode - AM: u1 = 0, - /// Synchronization pin polarity - SYNCPOL: u1 = 0, - /// I/O Default mode - IODEF: u1 = 0, - /// Max count value - MCV: u3 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// pulse generator prescaler - PGPSC: u3 = 0, - /// Spread spectrum prescaler - SSPSC: u1 = 0, - /// Spread spectrum enable - SSE: u1 = 0, - /// Spread spectrum deviation - SSD: u7 = 0, - /// Charge transfer pulse low - CTPL: u4 = 0, - /// Charge transfer pulse high - CTPH: u4 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - /// End of acquisition interrupt enable - EOAIE: u1 = 0, - /// Max count error interrupt enable - MCEIE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt clear register - pub const ICR = mmio(Address + 0x00000008, 32, packed struct { - /// End of acquisition interrupt clear - EOAIC: u1 = 0, - /// Max count error interrupt clear - MCEIC: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt status register - pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { - /// End of acquisition flag - EOAF: u1 = 0, - /// Max count error flag - MCEF: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O hysteresis control register - pub const IOHCR = mmio(Address + 0x00000010, 32, packed struct { - /// G1_IO1 Schmitt trigger hysteresis mode - G1_IO1: u1 = 0, - /// G1_IO2 Schmitt trigger hysteresis mode - G1_IO2: u1 = 0, - /// G1_IO3 Schmitt trigger hysteresis mode - G1_IO3: u1 = 0, - /// G1_IO4 Schmitt trigger hysteresis mode - G1_IO4: u1 = 0, - /// G2_IO1 Schmitt trigger hysteresis mode - G2_IO1: u1 = 0, - /// G2_IO2 Schmitt trigger hysteresis mode - G2_IO2: u1 = 0, - /// G2_IO3 Schmitt trigger hysteresis mode - G2_IO3: u1 = 0, - /// G2_IO4 Schmitt trigger hysteresis mode - G2_IO4: u1 = 0, - /// G3_IO1 Schmitt trigger hysteresis mode - G3_IO1: u1 = 0, - /// G3_IO2 Schmitt trigger hysteresis mode - G3_IO2: u1 = 0, - /// G3_IO3 Schmitt trigger hysteresis mode - G3_IO3: u1 = 0, - /// G3_IO4 Schmitt trigger hysteresis mode - G3_IO4: u1 = 0, - /// G4_IO1 Schmitt trigger hysteresis mode - G4_IO1: u1 = 0, - /// G4_IO2 Schmitt trigger hysteresis mode - G4_IO2: u1 = 0, - /// G4_IO3 Schmitt trigger hysteresis mode - G4_IO3: u1 = 0, - /// G4_IO4 Schmitt trigger hysteresis mode - G4_IO4: u1 = 0, - /// G5_IO1 Schmitt trigger hysteresis mode - G5_IO1: u1 = 0, - /// G5_IO2 Schmitt trigger hysteresis mode - G5_IO2: u1 = 0, - /// G5_IO3 Schmitt trigger hysteresis mode - G5_IO3: u1 = 0, - /// G5_IO4 Schmitt trigger hysteresis mode - G5_IO4: u1 = 0, - /// G6_IO1 Schmitt trigger hysteresis mode - G6_IO1: u1 = 0, - /// G6_IO2 Schmitt trigger hysteresis mode - G6_IO2: u1 = 0, - /// G6_IO3 Schmitt trigger hysteresis mode - G6_IO3: u1 = 0, - /// G6_IO4 Schmitt trigger hysteresis mode - G6_IO4: u1 = 0, - /// G7_IO1 Schmitt trigger hysteresis mode - G7_IO1: u1 = 0, - /// G7_IO2 Schmitt trigger hysteresis mode - G7_IO2: u1 = 0, - /// G7_IO3 Schmitt trigger hysteresis mode - G7_IO3: u1 = 0, - /// G7_IO4 Schmitt trigger hysteresis mode - G7_IO4: u1 = 0, - /// G8_IO1 Schmitt trigger hysteresis mode - G8_IO1: u1 = 0, - /// G8_IO2 Schmitt trigger hysteresis mode - G8_IO2: u1 = 0, - /// G8_IO3 Schmitt trigger hysteresis mode - G8_IO3: u1 = 0, - /// G8_IO4 Schmitt trigger hysteresis mode - G8_IO4: u1 = 0, - }); - - /// I/O analog switch control register - pub const IOASCR = mmio(Address + 0x00000018, 32, packed struct { - /// G1_IO1 analog switch enable - G1_IO1: u1 = 0, - /// G1_IO2 analog switch enable - G1_IO2: u1 = 0, - /// G1_IO3 analog switch enable - G1_IO3: u1 = 0, - /// G1_IO4 analog switch enable - G1_IO4: u1 = 0, - /// G2_IO1 analog switch enable - G2_IO1: u1 = 0, - /// G2_IO2 analog switch enable - G2_IO2: u1 = 0, - /// G2_IO3 analog switch enable - G2_IO3: u1 = 0, - /// G2_IO4 analog switch enable - G2_IO4: u1 = 0, - /// G3_IO1 analog switch enable - G3_IO1: u1 = 0, - /// G3_IO2 analog switch enable - G3_IO2: u1 = 0, - /// G3_IO3 analog switch enable - G3_IO3: u1 = 0, - /// G3_IO4 analog switch enable - G3_IO4: u1 = 0, - /// G4_IO1 analog switch enable - G4_IO1: u1 = 0, - /// G4_IO2 analog switch enable - G4_IO2: u1 = 0, - /// G4_IO3 analog switch enable - G4_IO3: u1 = 0, - /// G4_IO4 analog switch enable - G4_IO4: u1 = 0, - /// G5_IO1 analog switch enable - G5_IO1: u1 = 0, - /// G5_IO2 analog switch enable - G5_IO2: u1 = 0, - /// G5_IO3 analog switch enable - G5_IO3: u1 = 0, - /// G5_IO4 analog switch enable - G5_IO4: u1 = 0, - /// G6_IO1 analog switch enable - G6_IO1: u1 = 0, - /// G6_IO2 analog switch enable - G6_IO2: u1 = 0, - /// G6_IO3 analog switch enable - G6_IO3: u1 = 0, - /// G6_IO4 analog switch enable - G6_IO4: u1 = 0, - /// G7_IO1 analog switch enable - G7_IO1: u1 = 0, - /// G7_IO2 analog switch enable - G7_IO2: u1 = 0, - /// G7_IO3 analog switch enable - G7_IO3: u1 = 0, - /// G7_IO4 analog switch enable - G7_IO4: u1 = 0, - /// G8_IO1 analog switch enable - G8_IO1: u1 = 0, - /// G8_IO2 analog switch enable - G8_IO2: u1 = 0, - /// G8_IO3 analog switch enable - G8_IO3: u1 = 0, - /// G8_IO4 analog switch enable - G8_IO4: u1 = 0, - }); - - /// I/O sampling control register - pub const IOSCR = mmio(Address + 0x00000020, 32, packed struct { - /// G1_IO1 sampling mode - G1_IO1: u1 = 0, - /// G1_IO2 sampling mode - G1_IO2: u1 = 0, - /// G1_IO3 sampling mode - G1_IO3: u1 = 0, - /// G1_IO4 sampling mode - G1_IO4: u1 = 0, - /// G2_IO1 sampling mode - G2_IO1: u1 = 0, - /// G2_IO2 sampling mode - G2_IO2: u1 = 0, - /// G2_IO3 sampling mode - G2_IO3: u1 = 0, - /// G2_IO4 sampling mode - G2_IO4: u1 = 0, - /// G3_IO1 sampling mode - G3_IO1: u1 = 0, - /// G3_IO2 sampling mode - G3_IO2: u1 = 0, - /// G3_IO3 sampling mode - G3_IO3: u1 = 0, - /// G3_IO4 sampling mode - G3_IO4: u1 = 0, - /// G4_IO1 sampling mode - G4_IO1: u1 = 0, - /// G4_IO2 sampling mode - G4_IO2: u1 = 0, - /// G4_IO3 sampling mode - G4_IO3: u1 = 0, - /// G4_IO4 sampling mode - G4_IO4: u1 = 0, - /// G5_IO1 sampling mode - G5_IO1: u1 = 0, - /// G5_IO2 sampling mode - G5_IO2: u1 = 0, - /// G5_IO3 sampling mode - G5_IO3: u1 = 0, - /// G5_IO4 sampling mode - G5_IO4: u1 = 0, - /// G6_IO1 sampling mode - G6_IO1: u1 = 0, - /// G6_IO2 sampling mode - G6_IO2: u1 = 0, - /// G6_IO3 sampling mode - G6_IO3: u1 = 0, - /// G6_IO4 sampling mode - G6_IO4: u1 = 0, - /// G7_IO1 sampling mode - G7_IO1: u1 = 0, - /// G7_IO2 sampling mode - G7_IO2: u1 = 0, - /// G7_IO3 sampling mode - G7_IO3: u1 = 0, - /// G7_IO4 sampling mode - G7_IO4: u1 = 0, - /// G8_IO1 sampling mode - G8_IO1: u1 = 0, - /// G8_IO2 sampling mode - G8_IO2: u1 = 0, - /// G8_IO3 sampling mode - G8_IO3: u1 = 0, - /// G8_IO4 sampling mode - G8_IO4: u1 = 0, - }); - - /// I/O channel control register - pub const IOCCR = mmio(Address + 0x00000028, 32, packed struct { - /// G1_IO1 channel mode - G1_IO1: u1 = 0, - /// G1_IO2 channel mode - G1_IO2: u1 = 0, - /// G1_IO3 channel mode - G1_IO3: u1 = 0, - /// G1_IO4 channel mode - G1_IO4: u1 = 0, - /// G2_IO1 channel mode - G2_IO1: u1 = 0, - /// G2_IO2 channel mode - G2_IO2: u1 = 0, - /// G2_IO3 channel mode - G2_IO3: u1 = 0, - /// G2_IO4 channel mode - G2_IO4: u1 = 0, - /// G3_IO1 channel mode - G3_IO1: u1 = 0, - /// G3_IO2 channel mode - G3_IO2: u1 = 0, - /// G3_IO3 channel mode - G3_IO3: u1 = 0, - /// G3_IO4 channel mode - G3_IO4: u1 = 0, - /// G4_IO1 channel mode - G4_IO1: u1 = 0, - /// G4_IO2 channel mode - G4_IO2: u1 = 0, - /// G4_IO3 channel mode - G4_IO3: u1 = 0, - /// G4_IO4 channel mode - G4_IO4: u1 = 0, - /// G5_IO1 channel mode - G5_IO1: u1 = 0, - /// G5_IO2 channel mode - G5_IO2: u1 = 0, - /// G5_IO3 channel mode - G5_IO3: u1 = 0, - /// G5_IO4 channel mode - G5_IO4: u1 = 0, - /// G6_IO1 channel mode - G6_IO1: u1 = 0, - /// G6_IO2 channel mode - G6_IO2: u1 = 0, - /// G6_IO3 channel mode - G6_IO3: u1 = 0, - /// G6_IO4 channel mode - G6_IO4: u1 = 0, - /// G7_IO1 channel mode - G7_IO1: u1 = 0, - /// G7_IO2 channel mode - G7_IO2: u1 = 0, - /// G7_IO3 channel mode - G7_IO3: u1 = 0, - /// G7_IO4 channel mode - G7_IO4: u1 = 0, - /// G8_IO1 channel mode - G8_IO1: u1 = 0, - /// G8_IO2 channel mode - G8_IO2: u1 = 0, - /// G8_IO3 channel mode - G8_IO3: u1 = 0, - /// G8_IO4 channel mode - G8_IO4: u1 = 0, - }); - - /// I/O group control status register - pub const IOGCSR = mmio(Address + 0x00000030, 32, packed struct { - /// Analog I/O group x enable - G1E: u1 = 0, - /// Analog I/O group x enable - G2E: u1 = 0, - /// Analog I/O group x enable - G3E: u1 = 0, - /// Analog I/O group x enable - G4E: u1 = 0, - /// Analog I/O group x enable - G5E: u1 = 0, - /// Analog I/O group x enable - G6E: u1 = 0, - /// Analog I/O group x enable - G7E: u1 = 0, - /// Analog I/O group x enable - G8E: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Analog I/O group x status - G1S: u1 = 0, - /// Analog I/O group x status - G2S: u1 = 0, - /// Analog I/O group x status - G3S: u1 = 0, - /// Analog I/O group x status - G4S: u1 = 0, - /// Analog I/O group x status - G5S: u1 = 0, - /// Analog I/O group x status - G6S: u1 = 0, - /// Analog I/O group x status - G7S: u1 = 0, - /// Analog I/O group x status - G8S: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG1CR = mmio(Address + 0x00000034, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG2CR = mmio(Address + 0x00000038, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG3CR = mmio(Address + 0x0000003c, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG4CR = mmio(Address + 0x00000040, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG5CR = mmio(Address + 0x00000044, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG6CR = mmio(Address + 0x00000048, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG7CR = mmio(Address + 0x0000004c, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG8CR = mmio(Address + 0x00000050, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// cyclic redundancy check calculation unit -pub const CRC = extern struct { - pub const Address: u32 = 0x40023000; - - /// Data register - pub const DR = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Independent data register - pub const IDR = mmio(Address + 0x00000004, 32, packed struct { - /// General-purpose 8-bit data register bits - IDR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - /// reset bit - RESET: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Polynomial size - POLYSIZE: u2 = 0, - /// Reverse input data - REV_IN: u2 = 0, - /// Reverse output data - REV_OUT: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Initial CRC value - pub const INIT = @intToPtr(*volatile u32, Address + 0x00000010); - - /// CRC polynomial - pub const POL = @intToPtr(*volatile u32, Address + 0x00000014); -}; - -/// Flash -pub const Flash = extern struct { - pub const Address: u32 = 0x40022000; - - /// Flash access control register - pub const ACR = mmio(Address + 0x00000000, 32, packed struct { - reserved1: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Flash key register - pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { - /// Flash Key - FKEYR: u32 = 0, - }); - - /// Flash option key register - pub const OPTKEYR = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Flash status register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - /// Busy - BSY: u1 = 0, - reserved1: u1 = 0, - /// Programming error - PGERR: u1 = 0, - reserved2: u1 = 0, - /// Write protection error - WRPRT: u1 = 0, - /// End of operation - EOP: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Flash control register - pub const CR = mmio(Address + 0x00000010, 32, packed struct { - /// Programming - PG: u1 = 0, - /// Page erase - PER: u1 = 0, - /// Mass erase - MER: u1 = 0, - reserved1: u1 = 0, - /// Option byte programming - OPTPG: u1 = 0, - /// Option byte erase - OPTER: u1 = 0, - /// Start - STRT: u1 = 0, - /// Lock - LOCK: u1 = 0, - reserved2: u1 = 0, - /// Option bytes write enable - OPTWRE: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - reserved3: u1 = 0, - /// End of operation interrupt enable - EOPIE: u1 = 0, - /// Force option byte loading - FORCE_OPTLOAD: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Flash address register - pub const AR = mmio(Address + 0x00000014, 32, packed struct { - /// Flash address - FAR: u32 = 0, - }); - - /// Option byte register - pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { - /// Option byte error - OPTERR: u1 = 0, - /// Level 1 protection status - LEVEL1_PROT: u1 = 0, - /// Level 2 protection status - LEVEL2_PROT: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved6: u1 = 0, - reserved7: u1 = 0, - }); - - /// Write protection register - pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { - /// Write protect - WRP: u32 = 0, - }); -}; - -/// Reset and clock control -pub const RCC = extern struct { - pub const Address: u32 = 0x40021000; - - /// Clock control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// Internal High Speed clock enable - HSION: u1 = 0, - /// Internal High Speed clock ready flag - HSIRDY: u1 = 0, - reserved1: u1 = 0, - /// Internal High Speed clock trimming - HSITRIM: u5 = 0, - /// Internal High Speed clock Calibration - HSICAL: u8 = 0, - /// External High Speed clock enable - HSEON: u1 = 0, - /// External High Speed clock ready flag - HSERDY: u1 = 0, - /// External High Speed clock Bypass - HSEBYP: u1 = 0, - /// Clock Security System enable - CSSON: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// PLL enable - PLLON: u1 = 0, - /// PLL clock ready flag - PLLRDY: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock configuration register (RCC_CFGR) - pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { - /// System clock Switch - SW: u2 = 0, - /// System Clock Switch Status - SWS: u2 = 0, - /// AHB prescaler - HPRE: u4 = 0, - /// APB Low speed prescaler (APB1) - PPRE1: u3 = 0, - /// APB high speed prescaler (APB2) - PPRE2: u3 = 0, - reserved1: u1 = 0, - /// PLL entry clock source - PLLSRC: u2 = 0, - /// HSE divider for PLL entry - PLLXTPRE: u1 = 0, - /// PLL Multiplication Factor - PLLMUL: u4 = 0, - /// USB prescaler - USBPRES: u1 = 0, - /// I2S external clock source selection - I2SSRC: u1 = 0, - /// Microcontroller clock output - MCO: u3 = 0, - reserved2: u1 = 0, - /// Microcontroller Clock Output Flag - MCOF: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock interrupt register (RCC_CIR) - pub const CIR = mmio(Address + 0x00000008, 32, packed struct { - /// LSI Ready Interrupt flag - LSIRDYF: u1 = 0, - /// LSE Ready Interrupt flag - LSERDYF: u1 = 0, - /// HSI Ready Interrupt flag - HSIRDYF: u1 = 0, - /// HSE Ready Interrupt flag - HSERDYF: u1 = 0, - /// PLL Ready Interrupt flag - PLLRDYF: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Clock Security System Interrupt flag - CSSF: u1 = 0, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1 = 0, - /// LSE Ready Interrupt Enable - LSERDYIE: u1 = 0, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1 = 0, - /// HSE Ready Interrupt Enable - HSERDYIE: u1 = 0, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// LSI Ready Interrupt Clear - LSIRDYC: u1 = 0, - /// LSE Ready Interrupt Clear - LSERDYC: u1 = 0, - /// HSI Ready Interrupt Clear - HSIRDYC: u1 = 0, - /// HSE Ready Interrupt Clear - HSERDYC: u1 = 0, - /// PLL Ready Interrupt Clear - PLLRDYC: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Clock security system interrupt clear - CSSC: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB2 peripheral reset register (RCC_APB2RSTR) - pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { - /// SYSCFG and COMP reset - SYSCFGRST: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// TIM1 timer reset - TIM1RST: u1 = 0, - /// SPI 1 reset - SPI1RST: u1 = 0, - /// TIM8 timer reset - TIM8RST: u1 = 0, - /// USART1 reset - USART1RST: u1 = 0, - reserved11: u1 = 0, - /// TIM15 timer reset - TIM15RST: u1 = 0, - /// TIM16 timer reset - TIM16RST: u1 = 0, - /// TIM17 timer reset - TIM17RST: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB1 peripheral reset register (RCC_APB1RSTR) - pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { - /// Timer 2 reset - TIM2RST: u1 = 0, - /// Timer 3 reset - TIM3RST: u1 = 0, - /// Timer 14 reset - TIM4RST: u1 = 0, - reserved1: u1 = 0, - /// Timer 6 reset - TIM6RST: u1 = 0, - /// Timer 7 reset - TIM7RST: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Window watchdog reset - WWDGRST: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// SPI2 reset - SPI2RST: u1 = 0, - /// SPI3 reset - SPI3RST: u1 = 0, - reserved9: u1 = 0, - /// USART 2 reset - USART2RST: u1 = 0, - /// USART3 reset - USART3RST: u1 = 0, - /// UART 4 reset - UART4RST: u1 = 0, - /// UART 5 reset - UART5RST: u1 = 0, - /// I2C1 reset - I2C1RST: u1 = 0, - /// I2C2 reset - I2C2RST: u1 = 0, - /// USB reset - USBRST: u1 = 0, - reserved10: u1 = 0, - /// CAN reset - CANRST: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// Power interface reset - PWRRST: u1 = 0, - /// DAC interface reset - DACRST: u1 = 0, - /// I2C3 reset - I2C3RST: u1 = 0, - padding1: u1 = 0, - }); - - /// AHB Peripheral Clock enable register (RCC_AHBENR) - pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { - /// DMA1 clock enable - DMAEN: u1 = 0, - /// DMA2 clock enable - DMA2EN: u1 = 0, - /// SRAM interface clock enable - SRAMEN: u1 = 0, - reserved1: u1 = 0, - /// FLITF clock enable - FLITFEN: u1 = 0, - /// FMC clock enable - FMCEN: u1 = 0, - /// CRC clock enable - CRCEN: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// IO port H clock enable - IOPHEN: u1 = 0, - /// I/O port A clock enable - IOPAEN: u1 = 0, - /// I/O port B clock enable - IOPBEN: u1 = 0, - /// I/O port C clock enable - IOPCEN: u1 = 0, - /// I/O port D clock enable - IOPDEN: u1 = 0, - /// I/O port E clock enable - IOPEEN: u1 = 0, - /// I/O port F clock enable - IOPFEN: u1 = 0, - /// I/O port G clock enable - IOPGEN: u1 = 0, - /// Touch sensing controller clock enable - TSCEN: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// ADC1 and ADC2 clock enable - ADC12EN: u1 = 0, - /// ADC3 and ADC4 clock enable - ADC34EN: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB2 peripheral clock enable register (RCC_APB2ENR) - pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { - /// SYSCFG clock enable - SYSCFGEN: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// TIM1 Timer clock enable - TIM1EN: u1 = 0, - /// SPI 1 clock enable - SPI1EN: u1 = 0, - /// TIM8 Timer clock enable - TIM8EN: u1 = 0, - /// USART1 clock enable - USART1EN: u1 = 0, - reserved11: u1 = 0, - /// TIM15 timer clock enable - TIM15EN: u1 = 0, - /// TIM16 timer clock enable - TIM16EN: u1 = 0, - /// TIM17 timer clock enable - TIM17EN: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB1 peripheral clock enable register (RCC_APB1ENR) - pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { - /// Timer 2 clock enable - TIM2EN: u1 = 0, - /// Timer 3 clock enable - TIM3EN: u1 = 0, - /// Timer 4 clock enable - TIM4EN: u1 = 0, - reserved1: u1 = 0, - /// Timer 6 clock enable - TIM6EN: u1 = 0, - /// Timer 7 clock enable - TIM7EN: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Window watchdog clock enable - WWDGEN: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// SPI 2 clock enable - SPI2EN: u1 = 0, - /// SPI 3 clock enable - SPI3EN: u1 = 0, - reserved9: u1 = 0, - /// USART 2 clock enable - USART2EN: u1 = 0, - /// USART 3 clock enable - USART3EN: u1 = 0, - /// USART 4 clock enable - USART4EN: u1 = 0, - /// USART 5 clock enable - USART5EN: u1 = 0, - /// I2C 1 clock enable - I2C1EN: u1 = 0, - /// I2C 2 clock enable - I2C2EN: u1 = 0, - /// USB clock enable - USBEN: u1 = 0, - reserved10: u1 = 0, - /// CAN clock enable - CANEN: u1 = 0, - /// DAC2 interface clock enable - DAC2EN: u1 = 0, - reserved11: u1 = 0, - /// Power interface clock enable - PWREN: u1 = 0, - /// DAC interface clock enable - DACEN: u1 = 0, - /// I2C3 clock enable - I2C3EN: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup domain control register (RCC_BDCR) - pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { - /// External Low Speed oscillator enable - LSEON: u1 = 0, - /// External Low Speed oscillator ready - LSERDY: u1 = 0, - /// External Low Speed oscillator bypass - LSEBYP: u1 = 0, - /// LSE oscillator drive capability - LSEDRV: u2 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// RTC clock source selection - RTCSEL: u2 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// RTC clock enable - RTCEN: u1 = 0, - /// Backup domain software reset - BDRST: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control/status register (RCC_CSR) - pub const CSR = mmio(Address + 0x00000024, 32, packed struct { - /// Internal low speed oscillator enable - LSION: u1 = 0, - /// Internal low speed oscillator ready - LSIRDY: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Remove reset flag - RMVF: u1 = 0, - /// Option byte loader reset flag - OBLRSTF: u1 = 0, - /// PIN reset flag - PINRSTF: u1 = 0, - /// POR/PDR reset flag - PORRSTF: u1 = 0, - /// Software reset flag - SFTRSTF: u1 = 0, - /// Independent watchdog reset flag - IWDGRSTF: u1 = 0, - /// Window watchdog reset flag - WWDGRSTF: u1 = 0, - /// Low-power reset flag - LPWRRSTF: u1 = 0, - }); - - /// AHB peripheral reset register - pub const AHBRSTR = mmio(Address + 0x00000028, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// FMC reset - FMCRST: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// I/O port H reset - IOPHRST: u1 = 0, - /// I/O port A reset - IOPARST: u1 = 0, - /// I/O port B reset - IOPBRST: u1 = 0, - /// I/O port C reset - IOPCRST: u1 = 0, - /// I/O port D reset - IOPDRST: u1 = 0, - /// I/O port E reset - IOPERST: u1 = 0, - /// I/O port F reset - IOPFRST: u1 = 0, - /// Touch sensing controller reset - IOPGRST: u1 = 0, - /// Touch sensing controller reset - TSCRST: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - /// ADC1 and ADC2 reset - ADC12RST: u1 = 0, - /// ADC3 and ADC4 reset - ADC34RST: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock configuration register 2 - pub const CFGR2 = mmio(Address + 0x0000002c, 32, packed struct { - /// PREDIV division factor - PREDIV: u4 = 0, - /// ADC1 and ADC2 prescaler - ADC12PRES: u5 = 0, - /// ADC3 and ADC4 prescaler - ADC34PRES: u5 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock configuration register 3 - pub const CFGR3 = mmio(Address + 0x00000030, 32, packed struct { - /// USART1 clock source selection - USART1SW: u2 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// I2C1 clock source selection - I2C1SW: u1 = 0, - /// I2C2 clock source selection - I2C2SW: u1 = 0, - /// I2C3 clock source selection - I2C3SW: u1 = 0, - reserved3: u1 = 0, - /// Timer1 clock source selection - TIM1SW: u1 = 0, - /// Timer8 clock source selection - TIM8SW: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// USART2 clock source selection - USART2SW: u2 = 0, - /// USART3 clock source selection - USART3SW: u2 = 0, - /// UART4 clock source selection - UART4SW: u2 = 0, - /// UART5 clock source selection - UART5SW: u2 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// DMA controller 1 -pub const DMA1 = extern struct { - pub const Address: u32 = 0x40020000; - - /// DMA interrupt status register (DMA_ISR) - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - /// Channel 1 Global interrupt flag - GIF1: u1 = 0, - /// Channel 1 Transfer Complete flag - TCIF1: u1 = 0, - /// Channel 1 Half Transfer Complete flag - HTIF1: u1 = 0, - /// Channel 1 Transfer Error flag - TEIF1: u1 = 0, - /// Channel 2 Global interrupt flag - GIF2: u1 = 0, - /// Channel 2 Transfer Complete flag - TCIF2: u1 = 0, - /// Channel 2 Half Transfer Complete flag - HTIF2: u1 = 0, - /// Channel 2 Transfer Error flag - TEIF2: u1 = 0, - /// Channel 3 Global interrupt flag - GIF3: u1 = 0, - /// Channel 3 Transfer Complete flag - TCIF3: u1 = 0, - /// Channel 3 Half Transfer Complete flag - HTIF3: u1 = 0, - /// Channel 3 Transfer Error flag - TEIF3: u1 = 0, - /// Channel 4 Global interrupt flag - GIF4: u1 = 0, - /// Channel 4 Transfer Complete flag - TCIF4: u1 = 0, - /// Channel 4 Half Transfer Complete flag - HTIF4: u1 = 0, - /// Channel 4 Transfer Error flag - TEIF4: u1 = 0, - /// Channel 5 Global interrupt flag - GIF5: u1 = 0, - /// Channel 5 Transfer Complete flag - TCIF5: u1 = 0, - /// Channel 5 Half Transfer Complete flag - HTIF5: u1 = 0, - /// Channel 5 Transfer Error flag - TEIF5: u1 = 0, - /// Channel 6 Global interrupt flag - GIF6: u1 = 0, - /// Channel 6 Transfer Complete flag - TCIF6: u1 = 0, - /// Channel 6 Half Transfer Complete flag - HTIF6: u1 = 0, - /// Channel 6 Transfer Error flag - TEIF6: u1 = 0, - /// Channel 7 Global interrupt flag - GIF7: u1 = 0, - /// Channel 7 Transfer Complete flag - TCIF7: u1 = 0, - /// Channel 7 Half Transfer Complete flag - HTIF7: u1 = 0, - /// Channel 7 Transfer Error flag - TEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA interrupt flag clear register (DMA_IFCR) - pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - /// Channel 1 Global interrupt clear - CGIF1: u1 = 0, - /// Channel 1 Transfer Complete clear - CTCIF1: u1 = 0, - /// Channel 1 Half Transfer clear - CHTIF1: u1 = 0, - /// Channel 1 Transfer Error clear - CTEIF1: u1 = 0, - /// Channel 2 Global interrupt clear - CGIF2: u1 = 0, - /// Channel 2 Transfer Complete clear - CTCIF2: u1 = 0, - /// Channel 2 Half Transfer clear - CHTIF2: u1 = 0, - /// Channel 2 Transfer Error clear - CTEIF2: u1 = 0, - /// Channel 3 Global interrupt clear - CGIF3: u1 = 0, - /// Channel 3 Transfer Complete clear - CTCIF3: u1 = 0, - /// Channel 3 Half Transfer clear - CHTIF3: u1 = 0, - /// Channel 3 Transfer Error clear - CTEIF3: u1 = 0, - /// Channel 4 Global interrupt clear - CGIF4: u1 = 0, - /// Channel 4 Transfer Complete clear - CTCIF4: u1 = 0, - /// Channel 4 Half Transfer clear - CHTIF4: u1 = 0, - /// Channel 4 Transfer Error clear - CTEIF4: u1 = 0, - /// Channel 5 Global interrupt clear - CGIF5: u1 = 0, - /// Channel 5 Transfer Complete clear - CTCIF5: u1 = 0, - /// Channel 5 Half Transfer clear - CHTIF5: u1 = 0, - /// Channel 5 Transfer Error clear - CTEIF5: u1 = 0, - /// Channel 6 Global interrupt clear - CGIF6: u1 = 0, - /// Channel 6 Transfer Complete clear - CTCIF6: u1 = 0, - /// Channel 6 Half Transfer clear - CHTIF6: u1 = 0, - /// Channel 6 Transfer Error clear - CTEIF6: u1 = 0, - /// Channel 7 Global interrupt clear - CGIF7: u1 = 0, - /// Channel 7 Transfer Complete clear - CTCIF7: u1 = 0, - /// Channel 7 Half Transfer clear - CHTIF7: u1 = 0, - /// Channel 7 Transfer Error clear - CTEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 number of data register - pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 peripheral address register - pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 1 memory address register - pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 number of data register - pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 peripheral address register - pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 2 memory address register - pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 number of data register - pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 peripheral address register - pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 3 memory address register - pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 number of data register - pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 peripheral address register - pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 4 memory address register - pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 number of data register - pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 peripheral address register - pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 5 memory address register - pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 number of data register - pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 peripheral address register - pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 6 memory address register - pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 number of data register - pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 peripheral address register - pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 7 memory address register - pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); -}; - -/// DMA controller 1 -pub const DMA2 = extern struct { - pub const Address: u32 = 0x40020400; - - /// DMA interrupt status register (DMA_ISR) - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - /// Channel 1 Global interrupt flag - GIF1: u1 = 0, - /// Channel 1 Transfer Complete flag - TCIF1: u1 = 0, - /// Channel 1 Half Transfer Complete flag - HTIF1: u1 = 0, - /// Channel 1 Transfer Error flag - TEIF1: u1 = 0, - /// Channel 2 Global interrupt flag - GIF2: u1 = 0, - /// Channel 2 Transfer Complete flag - TCIF2: u1 = 0, - /// Channel 2 Half Transfer Complete flag - HTIF2: u1 = 0, - /// Channel 2 Transfer Error flag - TEIF2: u1 = 0, - /// Channel 3 Global interrupt flag - GIF3: u1 = 0, - /// Channel 3 Transfer Complete flag - TCIF3: u1 = 0, - /// Channel 3 Half Transfer Complete flag - HTIF3: u1 = 0, - /// Channel 3 Transfer Error flag - TEIF3: u1 = 0, - /// Channel 4 Global interrupt flag - GIF4: u1 = 0, - /// Channel 4 Transfer Complete flag - TCIF4: u1 = 0, - /// Channel 4 Half Transfer Complete flag - HTIF4: u1 = 0, - /// Channel 4 Transfer Error flag - TEIF4: u1 = 0, - /// Channel 5 Global interrupt flag - GIF5: u1 = 0, - /// Channel 5 Transfer Complete flag - TCIF5: u1 = 0, - /// Channel 5 Half Transfer Complete flag - HTIF5: u1 = 0, - /// Channel 5 Transfer Error flag - TEIF5: u1 = 0, - /// Channel 6 Global interrupt flag - GIF6: u1 = 0, - /// Channel 6 Transfer Complete flag - TCIF6: u1 = 0, - /// Channel 6 Half Transfer Complete flag - HTIF6: u1 = 0, - /// Channel 6 Transfer Error flag - TEIF6: u1 = 0, - /// Channel 7 Global interrupt flag - GIF7: u1 = 0, - /// Channel 7 Transfer Complete flag - TCIF7: u1 = 0, - /// Channel 7 Half Transfer Complete flag - HTIF7: u1 = 0, - /// Channel 7 Transfer Error flag - TEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA interrupt flag clear register (DMA_IFCR) - pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - /// Channel 1 Global interrupt clear - CGIF1: u1 = 0, - /// Channel 1 Transfer Complete clear - CTCIF1: u1 = 0, - /// Channel 1 Half Transfer clear - CHTIF1: u1 = 0, - /// Channel 1 Transfer Error clear - CTEIF1: u1 = 0, - /// Channel 2 Global interrupt clear - CGIF2: u1 = 0, - /// Channel 2 Transfer Complete clear - CTCIF2: u1 = 0, - /// Channel 2 Half Transfer clear - CHTIF2: u1 = 0, - /// Channel 2 Transfer Error clear - CTEIF2: u1 = 0, - /// Channel 3 Global interrupt clear - CGIF3: u1 = 0, - /// Channel 3 Transfer Complete clear - CTCIF3: u1 = 0, - /// Channel 3 Half Transfer clear - CHTIF3: u1 = 0, - /// Channel 3 Transfer Error clear - CTEIF3: u1 = 0, - /// Channel 4 Global interrupt clear - CGIF4: u1 = 0, - /// Channel 4 Transfer Complete clear - CTCIF4: u1 = 0, - /// Channel 4 Half Transfer clear - CHTIF4: u1 = 0, - /// Channel 4 Transfer Error clear - CTEIF4: u1 = 0, - /// Channel 5 Global interrupt clear - CGIF5: u1 = 0, - /// Channel 5 Transfer Complete clear - CTCIF5: u1 = 0, - /// Channel 5 Half Transfer clear - CHTIF5: u1 = 0, - /// Channel 5 Transfer Error clear - CTEIF5: u1 = 0, - /// Channel 6 Global interrupt clear - CGIF6: u1 = 0, - /// Channel 6 Transfer Complete clear - CTCIF6: u1 = 0, - /// Channel 6 Half Transfer clear - CHTIF6: u1 = 0, - /// Channel 6 Transfer Error clear - CTEIF6: u1 = 0, - /// Channel 7 Global interrupt clear - CGIF7: u1 = 0, - /// Channel 7 Transfer Complete clear - CTCIF7: u1 = 0, - /// Channel 7 Half Transfer clear - CHTIF7: u1 = 0, - /// Channel 7 Transfer Error clear - CTEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 number of data register - pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 peripheral address register - pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 1 memory address register - pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 number of data register - pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 peripheral address register - pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 2 memory address register - pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 number of data register - pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 peripheral address register - pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 3 memory address register - pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 number of data register - pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 peripheral address register - pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 4 memory address register - pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 number of data register - pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 peripheral address register - pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 5 memory address register - pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 number of data register - pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 peripheral address register - pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 6 memory address register - pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 number of data register - pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 peripheral address register - pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 7 memory address register - pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); -}; - -/// General purpose timer -pub const TIM2 = extern struct { - pub const Address: u32 = 0x40000000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit3 - SMS_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - /// Output compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - /// Output compare 3 mode bit3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 4 mode bit3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4NP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNTL: u16 = 0, - /// High counter value - CNTH: u15 = 0, - /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only - /// access - CNT_or_UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARRL: u16 = 0, - /// High Auto-reload value - ARRH: u16 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Low Capture/Compare 1 value - CCR1L: u16 = 0, - /// High Capture/Compare 1 value (on TIM2) - CCR1H: u16 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Low Capture/Compare 2 value - CCR2L: u16 = 0, - /// High Capture/Compare 2 value (on TIM2) - CCR2H: u16 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Low Capture/Compare value - CCR3L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR3H: u16 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Low Capture/Compare value - CCR4L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR4H: u16 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM3 = extern struct { - pub const Address: u32 = 0x40000400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit3 - SMS_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - /// Output compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - /// Output compare 3 mode bit3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 4 mode bit3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4NP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNTL: u16 = 0, - /// High counter value - CNTH: u15 = 0, - /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only - /// access - CNT_or_UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARRL: u16 = 0, - /// High Auto-reload value - ARRH: u16 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Low Capture/Compare 1 value - CCR1L: u16 = 0, - /// High Capture/Compare 1 value (on TIM2) - CCR1H: u16 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Low Capture/Compare 2 value - CCR2L: u16 = 0, - /// High Capture/Compare 2 value (on TIM2) - CCR2H: u16 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Low Capture/Compare value - CCR3L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR3H: u16 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Low Capture/Compare value - CCR4L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR4H: u16 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM4 = extern struct { - pub const Address: u32 = 0x40000800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit3 - SMS_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - /// Output compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - /// Output compare 3 mode bit3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 4 mode bit3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4NP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNTL: u16 = 0, - /// High counter value - CNTH: u15 = 0, - /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only - /// access - CNT_or_UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARRL: u16 = 0, - /// High Auto-reload value - ARRH: u16 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Low Capture/Compare 1 value - CCR1L: u16 = 0, - /// High Capture/Compare 1 value (on TIM2) - CCR1H: u16 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Low Capture/Compare 2 value - CCR2L: u16 = 0, - /// High Capture/Compare 2 value (on TIM2) - CCR2H: u16 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Low Capture/Compare value - CCR3L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR3H: u16 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Low Capture/Compare value - CCR4L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR4H: u16 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timers -pub const TIM15 = extern struct { - pub const Address: u32 = 0x40014000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved4: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Slave mode selection bit 3 - SMS_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - reserved2: u1 = 0, - /// Output Compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Output Compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose-timers -pub const TIM16 = extern struct { - pub const Address: u32 = 0x40014400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved4: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 1 mode - OC1M_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF Copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// option register - pub const OR = @intToPtr(*volatile u32, Address + 0x00000050); -}; - -/// General purpose timer -pub const TIM17 = extern struct { - pub const Address: u32 = 0x40014800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved4: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 1 mode - OC1M_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF Copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Universal synchronous asynchronous receiver transmitter -pub const USART1 = extern struct { - pub const Address: u32 = 0x40013800; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// USART enable - UE: u1 = 0, - /// USART enable in Stop mode - UESM: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Receiver wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// Mute mode enable - MME: u1 = 0, - /// Character match interrupt enable - CMIE: u1 = 0, - /// Oversampling mode - OVER8: u1 = 0, - /// Driver Enable deassertion time - DEDT: u5 = 0, - /// Driver Enable assertion time - DEAT: u5 = 0, - /// Receiver timeout interrupt enable - RTOIE: u1 = 0, - /// End of Block interrupt enable - EOBIE: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// 7-bit Address Detection/4-bit Address Detection - ADDM7: u1 = 0, - /// LIN break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved5: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - /// Swap TX/RX pins - SWAP: u1 = 0, - /// RX pin active level inversion - RXINV: u1 = 0, - /// TX pin active level inversion - TXINV: u1 = 0, - /// Binary data inversion - DATAINV: u1 = 0, - /// Most significant bit first - MSBFIRST: u1 = 0, - /// Auto baud rate enable - ABREN: u1 = 0, - /// Auto baud rate mode - ABRMOD: u2 = 0, - /// Receiver timeout enable - RTOEN: u1 = 0, - /// Address of the USART node - ADD0: u4 = 0, - /// Address of the USART node - ADD4: u4 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - /// One sample bit method enable - ONEBIT: u1 = 0, - /// Overrun Disable - OVRDIS: u1 = 0, - /// DMA Disable on Reception Error - DDRE: u1 = 0, - /// Driver enable mode - DEM: u1 = 0, - /// Driver enable polarity selection - DEP: u1 = 0, - reserved1: u1 = 0, - /// Smartcard auto-retry count - SCARCNT: u3 = 0, - /// Wakeup from Stop mode interrupt flag selection - WUS: u2 = 0, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - /// Receiver timeout value - RTO: u24 = 0, - /// Block Length - BLEN: u8 = 0, - }); - - /// Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - /// Auto baud rate request - ABRRQ: u1 = 0, - /// Send break request - SBKRQ: u1 = 0, - /// Mute mode request - MMRQ: u1 = 0, - /// Receive data flush request - RXFRQ: u1 = 0, - /// Transmit data flush request - TXFRQ: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise detected flag - NF: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// Idle line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBDF: u1 = 0, - /// CTS interrupt flag - CTSIF: u1 = 0, - /// CTS flag - CTS: u1 = 0, - /// Receiver timeout - RTOF: u1 = 0, - /// End of block flag - EOBF: u1 = 0, - reserved1: u1 = 0, - /// Auto baud rate error - ABRE: u1 = 0, - /// Auto baud rate flag - ABRF: u1 = 0, - /// Busy flag - BUSY: u1 = 0, - /// character match flag - CMF: u1 = 0, - /// Send break flag - SBKF: u1 = 0, - /// Receiver wakeup from Mute mode - RWU: u1 = 0, - /// Wakeup from Stop mode flag - WUF: u1 = 0, - /// Transmit enable acknowledge flag - TEACK: u1 = 0, - /// Receive enable acknowledge flag - REACK: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - /// Parity error clear flag - PECF: u1 = 0, - /// Framing error clear flag - FECF: u1 = 0, - /// Noise detected clear flag - NCF: u1 = 0, - /// Overrun error clear flag - ORECF: u1 = 0, - /// Idle line detected clear flag - IDLECF: u1 = 0, - reserved1: u1 = 0, - /// Transmission complete clear flag - TCCF: u1 = 0, - reserved2: u1 = 0, - /// LIN break detection clear flag - LBDCF: u1 = 0, - /// CTS clear flag - CTSCF: u1 = 0, - reserved3: u1 = 0, - /// Receiver timeout clear flag - RTOCF: u1 = 0, - /// End of timeout clear flag - EOBCF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Character match clear flag - CMCF: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// Wakeup from Stop mode clear flag - WUCF: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - /// Receive data value - RDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - /// Transmit data value - TDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Universal synchronous asynchronous receiver transmitter -pub const USART2 = extern struct { - pub const Address: u32 = 0x40004400; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// USART enable - UE: u1 = 0, - /// USART enable in Stop mode - UESM: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Receiver wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// Mute mode enable - MME: u1 = 0, - /// Character match interrupt enable - CMIE: u1 = 0, - /// Oversampling mode - OVER8: u1 = 0, - /// Driver Enable deassertion time - DEDT: u5 = 0, - /// Driver Enable assertion time - DEAT: u5 = 0, - /// Receiver timeout interrupt enable - RTOIE: u1 = 0, - /// End of Block interrupt enable - EOBIE: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// 7-bit Address Detection/4-bit Address Detection - ADDM7: u1 = 0, - /// LIN break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved5: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - /// Swap TX/RX pins - SWAP: u1 = 0, - /// RX pin active level inversion - RXINV: u1 = 0, - /// TX pin active level inversion - TXINV: u1 = 0, - /// Binary data inversion - DATAINV: u1 = 0, - /// Most significant bit first - MSBFIRST: u1 = 0, - /// Auto baud rate enable - ABREN: u1 = 0, - /// Auto baud rate mode - ABRMOD: u2 = 0, - /// Receiver timeout enable - RTOEN: u1 = 0, - /// Address of the USART node - ADD0: u4 = 0, - /// Address of the USART node - ADD4: u4 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - /// One sample bit method enable - ONEBIT: u1 = 0, - /// Overrun Disable - OVRDIS: u1 = 0, - /// DMA Disable on Reception Error - DDRE: u1 = 0, - /// Driver enable mode - DEM: u1 = 0, - /// Driver enable polarity selection - DEP: u1 = 0, - reserved1: u1 = 0, - /// Smartcard auto-retry count - SCARCNT: u3 = 0, - /// Wakeup from Stop mode interrupt flag selection - WUS: u2 = 0, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - /// Receiver timeout value - RTO: u24 = 0, - /// Block Length - BLEN: u8 = 0, - }); - - /// Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - /// Auto baud rate request - ABRRQ: u1 = 0, - /// Send break request - SBKRQ: u1 = 0, - /// Mute mode request - MMRQ: u1 = 0, - /// Receive data flush request - RXFRQ: u1 = 0, - /// Transmit data flush request - TXFRQ: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise detected flag - NF: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// Idle line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBDF: u1 = 0, - /// CTS interrupt flag - CTSIF: u1 = 0, - /// CTS flag - CTS: u1 = 0, - /// Receiver timeout - RTOF: u1 = 0, - /// End of block flag - EOBF: u1 = 0, - reserved1: u1 = 0, - /// Auto baud rate error - ABRE: u1 = 0, - /// Auto baud rate flag - ABRF: u1 = 0, - /// Busy flag - BUSY: u1 = 0, - /// character match flag - CMF: u1 = 0, - /// Send break flag - SBKF: u1 = 0, - /// Receiver wakeup from Mute mode - RWU: u1 = 0, - /// Wakeup from Stop mode flag - WUF: u1 = 0, - /// Transmit enable acknowledge flag - TEACK: u1 = 0, - /// Receive enable acknowledge flag - REACK: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - /// Parity error clear flag - PECF: u1 = 0, - /// Framing error clear flag - FECF: u1 = 0, - /// Noise detected clear flag - NCF: u1 = 0, - /// Overrun error clear flag - ORECF: u1 = 0, - /// Idle line detected clear flag - IDLECF: u1 = 0, - reserved1: u1 = 0, - /// Transmission complete clear flag - TCCF: u1 = 0, - reserved2: u1 = 0, - /// LIN break detection clear flag - LBDCF: u1 = 0, - /// CTS clear flag - CTSCF: u1 = 0, - reserved3: u1 = 0, - /// Receiver timeout clear flag - RTOCF: u1 = 0, - /// End of timeout clear flag - EOBCF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Character match clear flag - CMCF: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// Wakeup from Stop mode clear flag - WUCF: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - /// Receive data value - RDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - /// Transmit data value - TDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Universal synchronous asynchronous receiver transmitter -pub const USART3 = extern struct { - pub const Address: u32 = 0x40004800; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// USART enable - UE: u1 = 0, - /// USART enable in Stop mode - UESM: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Receiver wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// Mute mode enable - MME: u1 = 0, - /// Character match interrupt enable - CMIE: u1 = 0, - /// Oversampling mode - OVER8: u1 = 0, - /// Driver Enable deassertion time - DEDT: u5 = 0, - /// Driver Enable assertion time - DEAT: u5 = 0, - /// Receiver timeout interrupt enable - RTOIE: u1 = 0, - /// End of Block interrupt enable - EOBIE: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// 7-bit Address Detection/4-bit Address Detection - ADDM7: u1 = 0, - /// LIN break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved5: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - /// Swap TX/RX pins - SWAP: u1 = 0, - /// RX pin active level inversion - RXINV: u1 = 0, - /// TX pin active level inversion - TXINV: u1 = 0, - /// Binary data inversion - DATAINV: u1 = 0, - /// Most significant bit first - MSBFIRST: u1 = 0, - /// Auto baud rate enable - ABREN: u1 = 0, - /// Auto baud rate mode - ABRMOD: u2 = 0, - /// Receiver timeout enable - RTOEN: u1 = 0, - /// Address of the USART node - ADD0: u4 = 0, - /// Address of the USART node - ADD4: u4 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - /// One sample bit method enable - ONEBIT: u1 = 0, - /// Overrun Disable - OVRDIS: u1 = 0, - /// DMA Disable on Reception Error - DDRE: u1 = 0, - /// Driver enable mode - DEM: u1 = 0, - /// Driver enable polarity selection - DEP: u1 = 0, - reserved1: u1 = 0, - /// Smartcard auto-retry count - SCARCNT: u3 = 0, - /// Wakeup from Stop mode interrupt flag selection - WUS: u2 = 0, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - /// Receiver timeout value - RTO: u24 = 0, - /// Block Length - BLEN: u8 = 0, - }); - - /// Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - /// Auto baud rate request - ABRRQ: u1 = 0, - /// Send break request - SBKRQ: u1 = 0, - /// Mute mode request - MMRQ: u1 = 0, - /// Receive data flush request - RXFRQ: u1 = 0, - /// Transmit data flush request - TXFRQ: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise detected flag - NF: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// Idle line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBDF: u1 = 0, - /// CTS interrupt flag - CTSIF: u1 = 0, - /// CTS flag - CTS: u1 = 0, - /// Receiver timeout - RTOF: u1 = 0, - /// End of block flag - EOBF: u1 = 0, - reserved1: u1 = 0, - /// Auto baud rate error - ABRE: u1 = 0, - /// Auto baud rate flag - ABRF: u1 = 0, - /// Busy flag - BUSY: u1 = 0, - /// character match flag - CMF: u1 = 0, - /// Send break flag - SBKF: u1 = 0, - /// Receiver wakeup from Mute mode - RWU: u1 = 0, - /// Wakeup from Stop mode flag - WUF: u1 = 0, - /// Transmit enable acknowledge flag - TEACK: u1 = 0, - /// Receive enable acknowledge flag - REACK: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - /// Parity error clear flag - PECF: u1 = 0, - /// Framing error clear flag - FECF: u1 = 0, - /// Noise detected clear flag - NCF: u1 = 0, - /// Overrun error clear flag - ORECF: u1 = 0, - /// Idle line detected clear flag - IDLECF: u1 = 0, - reserved1: u1 = 0, - /// Transmission complete clear flag - TCCF: u1 = 0, - reserved2: u1 = 0, - /// LIN break detection clear flag - LBDCF: u1 = 0, - /// CTS clear flag - CTSCF: u1 = 0, - reserved3: u1 = 0, - /// Receiver timeout clear flag - RTOCF: u1 = 0, - /// End of timeout clear flag - EOBCF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Character match clear flag - CMCF: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// Wakeup from Stop mode clear flag - WUCF: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - /// Receive data value - RDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - /// Transmit data value - TDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Universal synchronous asynchronous receiver transmitter -pub const UART4 = extern struct { - pub const Address: u32 = 0x40004c00; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// USART enable - UE: u1 = 0, - /// USART enable in Stop mode - UESM: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Receiver wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// Mute mode enable - MME: u1 = 0, - /// Character match interrupt enable - CMIE: u1 = 0, - /// Oversampling mode - OVER8: u1 = 0, - /// Driver Enable deassertion time - DEDT: u5 = 0, - /// Driver Enable assertion time - DEAT: u5 = 0, - /// Receiver timeout interrupt enable - RTOIE: u1 = 0, - /// End of Block interrupt enable - EOBIE: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// 7-bit Address Detection/4-bit Address Detection - ADDM7: u1 = 0, - /// LIN break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved5: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - /// Swap TX/RX pins - SWAP: u1 = 0, - /// RX pin active level inversion - RXINV: u1 = 0, - /// TX pin active level inversion - TXINV: u1 = 0, - /// Binary data inversion - DATAINV: u1 = 0, - /// Most significant bit first - MSBFIRST: u1 = 0, - /// Auto baud rate enable - ABREN: u1 = 0, - /// Auto baud rate mode - ABRMOD: u2 = 0, - /// Receiver timeout enable - RTOEN: u1 = 0, - /// Address of the USART node - ADD0: u4 = 0, - /// Address of the USART node - ADD4: u4 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - /// One sample bit method enable - ONEBIT: u1 = 0, - /// Overrun Disable - OVRDIS: u1 = 0, - /// DMA Disable on Reception Error - DDRE: u1 = 0, - /// Driver enable mode - DEM: u1 = 0, - /// Driver enable polarity selection - DEP: u1 = 0, - reserved1: u1 = 0, - /// Smartcard auto-retry count - SCARCNT: u3 = 0, - /// Wakeup from Stop mode interrupt flag selection - WUS: u2 = 0, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - /// Receiver timeout value - RTO: u24 = 0, - /// Block Length - BLEN: u8 = 0, - }); - - /// Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - /// Auto baud rate request - ABRRQ: u1 = 0, - /// Send break request - SBKRQ: u1 = 0, - /// Mute mode request - MMRQ: u1 = 0, - /// Receive data flush request - RXFRQ: u1 = 0, - /// Transmit data flush request - TXFRQ: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise detected flag - NF: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// Idle line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBDF: u1 = 0, - /// CTS interrupt flag - CTSIF: u1 = 0, - /// CTS flag - CTS: u1 = 0, - /// Receiver timeout - RTOF: u1 = 0, - /// End of block flag - EOBF: u1 = 0, - reserved1: u1 = 0, - /// Auto baud rate error - ABRE: u1 = 0, - /// Auto baud rate flag - ABRF: u1 = 0, - /// Busy flag - BUSY: u1 = 0, - /// character match flag - CMF: u1 = 0, - /// Send break flag - SBKF: u1 = 0, - /// Receiver wakeup from Mute mode - RWU: u1 = 0, - /// Wakeup from Stop mode flag - WUF: u1 = 0, - /// Transmit enable acknowledge flag - TEACK: u1 = 0, - /// Receive enable acknowledge flag - REACK: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - /// Parity error clear flag - PECF: u1 = 0, - /// Framing error clear flag - FECF: u1 = 0, - /// Noise detected clear flag - NCF: u1 = 0, - /// Overrun error clear flag - ORECF: u1 = 0, - /// Idle line detected clear flag - IDLECF: u1 = 0, - reserved1: u1 = 0, - /// Transmission complete clear flag - TCCF: u1 = 0, - reserved2: u1 = 0, - /// LIN break detection clear flag - LBDCF: u1 = 0, - /// CTS clear flag - CTSCF: u1 = 0, - reserved3: u1 = 0, - /// Receiver timeout clear flag - RTOCF: u1 = 0, - /// End of timeout clear flag - EOBCF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Character match clear flag - CMCF: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// Wakeup from Stop mode clear flag - WUCF: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - /// Receive data value - RDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - /// Transmit data value - TDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Universal synchronous asynchronous receiver transmitter -pub const UART5 = extern struct { - pub const Address: u32 = 0x40005000; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// USART enable - UE: u1 = 0, - /// USART enable in Stop mode - UESM: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Receiver wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// Mute mode enable - MME: u1 = 0, - /// Character match interrupt enable - CMIE: u1 = 0, - /// Oversampling mode - OVER8: u1 = 0, - /// Driver Enable deassertion time - DEDT: u5 = 0, - /// Driver Enable assertion time - DEAT: u5 = 0, - /// Receiver timeout interrupt enable - RTOIE: u1 = 0, - /// End of Block interrupt enable - EOBIE: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// 7-bit Address Detection/4-bit Address Detection - ADDM7: u1 = 0, - /// LIN break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved5: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - /// Swap TX/RX pins - SWAP: u1 = 0, - /// RX pin active level inversion - RXINV: u1 = 0, - /// TX pin active level inversion - TXINV: u1 = 0, - /// Binary data inversion - DATAINV: u1 = 0, - /// Most significant bit first - MSBFIRST: u1 = 0, - /// Auto baud rate enable - ABREN: u1 = 0, - /// Auto baud rate mode - ABRMOD: u2 = 0, - /// Receiver timeout enable - RTOEN: u1 = 0, - /// Address of the USART node - ADD0: u4 = 0, - /// Address of the USART node - ADD4: u4 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - /// One sample bit method enable - ONEBIT: u1 = 0, - /// Overrun Disable - OVRDIS: u1 = 0, - /// DMA Disable on Reception Error - DDRE: u1 = 0, - /// Driver enable mode - DEM: u1 = 0, - /// Driver enable polarity selection - DEP: u1 = 0, - reserved1: u1 = 0, - /// Smartcard auto-retry count - SCARCNT: u3 = 0, - /// Wakeup from Stop mode interrupt flag selection - WUS: u2 = 0, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - /// Receiver timeout value - RTO: u24 = 0, - /// Block Length - BLEN: u8 = 0, - }); - - /// Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - /// Auto baud rate request - ABRRQ: u1 = 0, - /// Send break request - SBKRQ: u1 = 0, - /// Mute mode request - MMRQ: u1 = 0, - /// Receive data flush request - RXFRQ: u1 = 0, - /// Transmit data flush request - TXFRQ: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise detected flag - NF: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// Idle line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBDF: u1 = 0, - /// CTS interrupt flag - CTSIF: u1 = 0, - /// CTS flag - CTS: u1 = 0, - /// Receiver timeout - RTOF: u1 = 0, - /// End of block flag - EOBF: u1 = 0, - reserved1: u1 = 0, - /// Auto baud rate error - ABRE: u1 = 0, - /// Auto baud rate flag - ABRF: u1 = 0, - /// Busy flag - BUSY: u1 = 0, - /// character match flag - CMF: u1 = 0, - /// Send break flag - SBKF: u1 = 0, - /// Receiver wakeup from Mute mode - RWU: u1 = 0, - /// Wakeup from Stop mode flag - WUF: u1 = 0, - /// Transmit enable acknowledge flag - TEACK: u1 = 0, - /// Receive enable acknowledge flag - REACK: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - /// Parity error clear flag - PECF: u1 = 0, - /// Framing error clear flag - FECF: u1 = 0, - /// Noise detected clear flag - NCF: u1 = 0, - /// Overrun error clear flag - ORECF: u1 = 0, - /// Idle line detected clear flag - IDLECF: u1 = 0, - reserved1: u1 = 0, - /// Transmission complete clear flag - TCCF: u1 = 0, - reserved2: u1 = 0, - /// LIN break detection clear flag - LBDCF: u1 = 0, - /// CTS clear flag - CTSCF: u1 = 0, - reserved3: u1 = 0, - /// Receiver timeout clear flag - RTOCF: u1 = 0, - /// End of timeout clear flag - EOBCF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Character match clear flag - CMCF: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// Wakeup from Stop mode clear flag - WUCF: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - /// Receive data value - RDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - /// Transmit data value - TDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const SPI1 = extern struct { - pub const Address: u32 = 0x40013000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const SPI2 = extern struct { - pub const Address: u32 = 0x40003800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const SPI3 = extern struct { - pub const Address: u32 = 0x40003c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const I2S2ext = extern struct { - pub const Address: u32 = 0x40003400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const I2S3ext = extern struct { - pub const Address: u32 = 0x40004000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const SPI4 = extern struct { - pub const Address: u32 = 0x40013c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// External interrupt/event controller -pub const EXTI = extern struct { - pub const Address: u32 = 0x40010400; - - /// Interrupt mask register - pub const IMR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Interrupt Mask on line 0 - MR0: u1 = 0, - /// Interrupt Mask on line 1 - MR1: u1 = 0, - /// Interrupt Mask on line 2 - MR2: u1 = 0, - /// Interrupt Mask on line 3 - MR3: u1 = 0, - /// Interrupt Mask on line 4 - MR4: u1 = 0, - /// Interrupt Mask on line 5 - MR5: u1 = 0, - /// Interrupt Mask on line 6 - MR6: u1 = 0, - /// Interrupt Mask on line 7 - MR7: u1 = 0, - /// Interrupt Mask on line 8 - MR8: u1 = 0, - /// Interrupt Mask on line 9 - MR9: u1 = 0, - /// Interrupt Mask on line 10 - MR10: u1 = 0, - /// Interrupt Mask on line 11 - MR11: u1 = 0, - /// Interrupt Mask on line 12 - MR12: u1 = 0, - /// Interrupt Mask on line 13 - MR13: u1 = 0, - /// Interrupt Mask on line 14 - MR14: u1 = 0, - /// Interrupt Mask on line 15 - MR15: u1 = 0, - /// Interrupt Mask on line 16 - MR16: u1 = 0, - /// Interrupt Mask on line 17 - MR17: u1 = 0, - /// Interrupt Mask on line 18 - MR18: u1 = 0, - /// Interrupt Mask on line 19 - MR19: u1 = 0, - /// Interrupt Mask on line 20 - MR20: u1 = 0, - /// Interrupt Mask on line 21 - MR21: u1 = 0, - /// Interrupt Mask on line 22 - MR22: u1 = 0, - /// Interrupt Mask on line 23 - MR23: u1 = 0, - /// Interrupt Mask on line 24 - MR24: u1 = 0, - /// Interrupt Mask on line 25 - MR25: u1 = 0, - /// Interrupt Mask on line 26 - MR26: u1 = 0, - /// Interrupt Mask on line 27 - MR27: u1 = 0, - /// Interrupt Mask on line 28 - MR28: u1 = 0, - /// Interrupt Mask on line 29 - MR29: u1 = 0, - /// Interrupt Mask on line 30 - MR30: u1 = 0, - /// Interrupt Mask on line 31 - MR31: u1 = 0, - }); - - /// Event mask register - pub const EMR1 = mmio(Address + 0x00000004, 32, packed struct { - /// Event Mask on line 0 - MR0: u1 = 0, - /// Event Mask on line 1 - MR1: u1 = 0, - /// Event Mask on line 2 - MR2: u1 = 0, - /// Event Mask on line 3 - MR3: u1 = 0, - /// Event Mask on line 4 - MR4: u1 = 0, - /// Event Mask on line 5 - MR5: u1 = 0, - /// Event Mask on line 6 - MR6: u1 = 0, - /// Event Mask on line 7 - MR7: u1 = 0, - /// Event Mask on line 8 - MR8: u1 = 0, - /// Event Mask on line 9 - MR9: u1 = 0, - /// Event Mask on line 10 - MR10: u1 = 0, - /// Event Mask on line 11 - MR11: u1 = 0, - /// Event Mask on line 12 - MR12: u1 = 0, - /// Event Mask on line 13 - MR13: u1 = 0, - /// Event Mask on line 14 - MR14: u1 = 0, - /// Event Mask on line 15 - MR15: u1 = 0, - /// Event Mask on line 16 - MR16: u1 = 0, - /// Event Mask on line 17 - MR17: u1 = 0, - /// Event Mask on line 18 - MR18: u1 = 0, - /// Event Mask on line 19 - MR19: u1 = 0, - /// Event Mask on line 20 - MR20: u1 = 0, - /// Event Mask on line 21 - MR21: u1 = 0, - /// Event Mask on line 22 - MR22: u1 = 0, - /// Event Mask on line 23 - MR23: u1 = 0, - /// Event Mask on line 24 - MR24: u1 = 0, - /// Event Mask on line 25 - MR25: u1 = 0, - /// Event Mask on line 26 - MR26: u1 = 0, - /// Event Mask on line 27 - MR27: u1 = 0, - /// Event Mask on line 28 - MR28: u1 = 0, - /// Event Mask on line 29 - MR29: u1 = 0, - /// Event Mask on line 30 - MR30: u1 = 0, - /// Event Mask on line 31 - MR31: u1 = 0, - }); - - /// Rising Trigger selection register - pub const RTSR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Rising trigger event configuration of line 0 - TR0: u1 = 0, - /// Rising trigger event configuration of line 1 - TR1: u1 = 0, - /// Rising trigger event configuration of line 2 - TR2: u1 = 0, - /// Rising trigger event configuration of line 3 - TR3: u1 = 0, - /// Rising trigger event configuration of line 4 - TR4: u1 = 0, - /// Rising trigger event configuration of line 5 - TR5: u1 = 0, - /// Rising trigger event configuration of line 6 - TR6: u1 = 0, - /// Rising trigger event configuration of line 7 - TR7: u1 = 0, - /// Rising trigger event configuration of line 8 - TR8: u1 = 0, - /// Rising trigger event configuration of line 9 - TR9: u1 = 0, - /// Rising trigger event configuration of line 10 - TR10: u1 = 0, - /// Rising trigger event configuration of line 11 - TR11: u1 = 0, - /// Rising trigger event configuration of line 12 - TR12: u1 = 0, - /// Rising trigger event configuration of line 13 - TR13: u1 = 0, - /// Rising trigger event configuration of line 14 - TR14: u1 = 0, - /// Rising trigger event configuration of line 15 - TR15: u1 = 0, - /// Rising trigger event configuration of line 16 - TR16: u1 = 0, - /// Rising trigger event configuration of line 17 - TR17: u1 = 0, - /// Rising trigger event configuration of line 18 - TR18: u1 = 0, - /// Rising trigger event configuration of line 19 - TR19: u1 = 0, - /// Rising trigger event configuration of line 20 - TR20: u1 = 0, - /// Rising trigger event configuration of line 21 - TR21: u1 = 0, - /// Rising trigger event configuration of line 22 - TR22: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Rising trigger event configuration of line 29 - TR29: u1 = 0, - /// Rising trigger event configuration of line 30 - TR30: u1 = 0, - /// Rising trigger event configuration of line 31 - TR31: u1 = 0, - }); - - /// Falling Trigger selection register - pub const FTSR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Falling trigger event configuration of line 0 - TR0: u1 = 0, - /// Falling trigger event configuration of line 1 - TR1: u1 = 0, - /// Falling trigger event configuration of line 2 - TR2: u1 = 0, - /// Falling trigger event configuration of line 3 - TR3: u1 = 0, - /// Falling trigger event configuration of line 4 - TR4: u1 = 0, - /// Falling trigger event configuration of line 5 - TR5: u1 = 0, - /// Falling trigger event configuration of line 6 - TR6: u1 = 0, - /// Falling trigger event configuration of line 7 - TR7: u1 = 0, - /// Falling trigger event configuration of line 8 - TR8: u1 = 0, - /// Falling trigger event configuration of line 9 - TR9: u1 = 0, - /// Falling trigger event configuration of line 10 - TR10: u1 = 0, - /// Falling trigger event configuration of line 11 - TR11: u1 = 0, - /// Falling trigger event configuration of line 12 - TR12: u1 = 0, - /// Falling trigger event configuration of line 13 - TR13: u1 = 0, - /// Falling trigger event configuration of line 14 - TR14: u1 = 0, - /// Falling trigger event configuration of line 15 - TR15: u1 = 0, - /// Falling trigger event configuration of line 16 - TR16: u1 = 0, - /// Falling trigger event configuration of line 17 - TR17: u1 = 0, - /// Falling trigger event configuration of line 18 - TR18: u1 = 0, - /// Falling trigger event configuration of line 19 - TR19: u1 = 0, - /// Falling trigger event configuration of line 20 - TR20: u1 = 0, - /// Falling trigger event configuration of line 21 - TR21: u1 = 0, - /// Falling trigger event configuration of line 22 - TR22: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Falling trigger event configuration of line 29 - TR29: u1 = 0, - /// Falling trigger event configuration of line 30. - TR30: u1 = 0, - /// Falling trigger event configuration of line 31 - TR31: u1 = 0, - }); - - /// Software interrupt event register - pub const SWIER1 = mmio(Address + 0x00000010, 32, packed struct { - /// Software Interrupt on line 0 - SWIER0: u1 = 0, - /// Software Interrupt on line 1 - SWIER1: u1 = 0, - /// Software Interrupt on line 2 - SWIER2: u1 = 0, - /// Software Interrupt on line 3 - SWIER3: u1 = 0, - /// Software Interrupt on line 4 - SWIER4: u1 = 0, - /// Software Interrupt on line 5 - SWIER5: u1 = 0, - /// Software Interrupt on line 6 - SWIER6: u1 = 0, - /// Software Interrupt on line 7 - SWIER7: u1 = 0, - /// Software Interrupt on line 8 - SWIER8: u1 = 0, - /// Software Interrupt on line 9 - SWIER9: u1 = 0, - /// Software Interrupt on line 10 - SWIER10: u1 = 0, - /// Software Interrupt on line 11 - SWIER11: u1 = 0, - /// Software Interrupt on line 12 - SWIER12: u1 = 0, - /// Software Interrupt on line 13 - SWIER13: u1 = 0, - /// Software Interrupt on line 14 - SWIER14: u1 = 0, - /// Software Interrupt on line 15 - SWIER15: u1 = 0, - /// Software Interrupt on line 16 - SWIER16: u1 = 0, - /// Software Interrupt on line 17 - SWIER17: u1 = 0, - /// Software Interrupt on line 18 - SWIER18: u1 = 0, - /// Software Interrupt on line 19 - SWIER19: u1 = 0, - /// Software Interrupt on line 20 - SWIER20: u1 = 0, - /// Software Interrupt on line 21 - SWIER21: u1 = 0, - /// Software Interrupt on line 22 - SWIER22: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Software Interrupt on line 29 - SWIER29: u1 = 0, - /// Software Interrupt on line 309 - SWIER30: u1 = 0, - /// Software Interrupt on line 319 - SWIER31: u1 = 0, - }); - - /// Pending register - pub const PR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Pending bit 0 - PR0: u1 = 0, - /// Pending bit 1 - PR1: u1 = 0, - /// Pending bit 2 - PR2: u1 = 0, - /// Pending bit 3 - PR3: u1 = 0, - /// Pending bit 4 - PR4: u1 = 0, - /// Pending bit 5 - PR5: u1 = 0, - /// Pending bit 6 - PR6: u1 = 0, - /// Pending bit 7 - PR7: u1 = 0, - /// Pending bit 8 - PR8: u1 = 0, - /// Pending bit 9 - PR9: u1 = 0, - /// Pending bit 10 - PR10: u1 = 0, - /// Pending bit 11 - PR11: u1 = 0, - /// Pending bit 12 - PR12: u1 = 0, - /// Pending bit 13 - PR13: u1 = 0, - /// Pending bit 14 - PR14: u1 = 0, - /// Pending bit 15 - PR15: u1 = 0, - /// Pending bit 16 - PR16: u1 = 0, - /// Pending bit 17 - PR17: u1 = 0, - /// Pending bit 18 - PR18: u1 = 0, - /// Pending bit 19 - PR19: u1 = 0, - /// Pending bit 20 - PR20: u1 = 0, - /// Pending bit 21 - PR21: u1 = 0, - /// Pending bit 22 - PR22: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Pending bit 29 - PR29: u1 = 0, - /// Pending bit 30 - PR30: u1 = 0, - /// Pending bit 31 - PR31: u1 = 0, - }); - - /// Interrupt mask register - pub const IMR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Interrupt Mask on external/internal line 32 - MR32: u1 = 0, - /// Interrupt Mask on external/internal line 33 - MR33: u1 = 0, - /// Interrupt Mask on external/internal line 34 - MR34: u1 = 0, - /// Interrupt Mask on external/internal line 35 - MR35: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Event mask register - pub const EMR2 = mmio(Address + 0x0000001c, 32, packed struct { - /// Event mask on external/internal line 32 - MR32: u1 = 0, - /// Event mask on external/internal line 33 - MR33: u1 = 0, - /// Event mask on external/internal line 34 - MR34: u1 = 0, - /// Event mask on external/internal line 35 - MR35: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Rising Trigger selection register - pub const RTSR2 = mmio(Address + 0x00000020, 32, packed struct { - /// Rising trigger event configuration bit of line 32 - TR32: u1 = 0, - /// Rising trigger event configuration bit of line 33 - TR33: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Falling Trigger selection register - pub const FTSR2 = mmio(Address + 0x00000024, 32, packed struct { - /// Falling trigger event configuration bit of line 32 - TR32: u1 = 0, - /// Falling trigger event configuration bit of line 33 - TR33: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Software interrupt event register - pub const SWIER2 = mmio(Address + 0x00000028, 32, packed struct { - /// Software interrupt on line 32 - SWIER32: u1 = 0, - /// Software interrupt on line 33 - SWIER33: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pending register - pub const PR2 = mmio(Address + 0x0000002c, 32, packed struct { - /// Pending bit on line 32 - PR32: u1 = 0, - /// Pending bit on line 33 - PR33: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Power control -pub const PWR = extern struct { - pub const Address: u32 = 0x40007000; - - /// power control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// Low-power deep sleep - LPDS: u1 = 0, - /// Power down deepsleep - PDDS: u1 = 0, - /// Clear wakeup flag - CWUF: u1 = 0, - /// Clear standby flag - CSBF: u1 = 0, - /// Power voltage detector enable - PVDE: u1 = 0, - /// PVD level selection - PLS: u3 = 0, - /// Disable backup domain write protection - DBP: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// power control/status register - pub const CSR = mmio(Address + 0x00000004, 32, packed struct { - /// Wakeup flag - WUF: u1 = 0, - /// Standby flag - SBF: u1 = 0, - /// PVD output - PVDO: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable WKUP1 pin - EWUP1: u1 = 0, - /// Enable WKUP2 pin - EWUP2: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Controller area network -pub const CAN = extern struct { - pub const Address: u32 = 0x40006400; - - /// master control register - pub const MCR = mmio(Address + 0x00000000, 32, packed struct { - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// master status register - pub const MSR = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// transmit status register - pub const TSR = mmio(Address + 0x00000008, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Lowest priority flag for mailbox 0 - TME0: u1 = 0, - /// Lowest priority flag for mailbox 1 - TME1: u1 = 0, - /// Lowest priority flag for mailbox 2 - TME2: u1 = 0, - /// Lowest priority flag for mailbox 0 - LOW0: u1 = 0, - /// Lowest priority flag for mailbox 1 - LOW1: u1 = 0, - /// Lowest priority flag for mailbox 2 - LOW2: u1 = 0, - }); - - /// receive FIFO 0 register - pub const RF0R = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// receive FIFO 1 register - pub const RF1R = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000014, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// error status register - pub const ESR = mmio(Address + 0x00000018, 32, packed struct { - reserved1: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - }); - - /// bit timing register - pub const BTR = mmio(Address + 0x0000001c, 32, packed struct { - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved7: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - }); - - /// TX mailbox identifier register - pub const TI0R = mmio(Address + 0x00000180, 32, packed struct {}); - - /// mailbox data length control and time stamp register - pub const TDT0R = mmio(Address + 0x00000184, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// mailbox data low register - pub const TDL0R = mmio(Address + 0x00000188, 32, packed struct {}); - - /// mailbox data high register - pub const TDH0R = mmio(Address + 0x0000018c, 32, packed struct {}); - - /// TX mailbox identifier register - pub const TI1R = mmio(Address + 0x00000190, 32, packed struct {}); - - /// mailbox data length control and time stamp register - pub const TDT1R = mmio(Address + 0x00000194, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// mailbox data low register - pub const TDL1R = mmio(Address + 0x00000198, 32, packed struct {}); - - /// mailbox data high register - pub const TDH1R = mmio(Address + 0x0000019c, 32, packed struct {}); - - /// TX mailbox identifier register - pub const TI2R = mmio(Address + 0x000001a0, 32, packed struct {}); - - /// mailbox data length control and time stamp register - pub const TDT2R = mmio(Address + 0x000001a4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// mailbox data low register - pub const TDL2R = mmio(Address + 0x000001a8, 32, packed struct {}); - - /// mailbox data high register - pub const TDH2R = mmio(Address + 0x000001ac, 32, packed struct {}); - - /// receive FIFO mailbox identifier register - pub const RI0R = mmio(Address + 0x000001b0, 32, packed struct { - reserved1: u1 = 0, - }); - - /// receive FIFO mailbox data length control and time stamp register - pub const RDT0R = mmio(Address + 0x000001b4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// receive FIFO mailbox data low register - pub const RDL0R = mmio(Address + 0x000001b8, 32, packed struct {}); - - /// receive FIFO mailbox data high register - pub const RDH0R = mmio(Address + 0x000001bc, 32, packed struct {}); - - /// receive FIFO mailbox identifier register - pub const RI1R = mmio(Address + 0x000001c0, 32, packed struct { - reserved1: u1 = 0, - }); - - /// receive FIFO mailbox data length control and time stamp register - pub const RDT1R = mmio(Address + 0x000001c4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// receive FIFO mailbox data low register - pub const RDL1R = mmio(Address + 0x000001c8, 32, packed struct {}); - - /// receive FIFO mailbox data high register - pub const RDH1R = mmio(Address + 0x000001cc, 32, packed struct {}); - - /// filter master register - pub const FMR = mmio(Address + 0x00000200, 32, packed struct { - /// Filter init mode - FINIT: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// CAN2 start bank - CAN2SB: u6 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// filter mode register - pub const FM1R = mmio(Address + 0x00000204, 32, packed struct { - /// Filter mode - FBM0: u1 = 0, - /// Filter mode - FBM1: u1 = 0, - /// Filter mode - FBM2: u1 = 0, - /// Filter mode - FBM3: u1 = 0, - /// Filter mode - FBM4: u1 = 0, - /// Filter mode - FBM5: u1 = 0, - /// Filter mode - FBM6: u1 = 0, - /// Filter mode - FBM7: u1 = 0, - /// Filter mode - FBM8: u1 = 0, - /// Filter mode - FBM9: u1 = 0, - /// Filter mode - FBM10: u1 = 0, - /// Filter mode - FBM11: u1 = 0, - /// Filter mode - FBM12: u1 = 0, - /// Filter mode - FBM13: u1 = 0, - /// Filter mode - FBM14: u1 = 0, - /// Filter mode - FBM15: u1 = 0, - /// Filter mode - FBM16: u1 = 0, - /// Filter mode - FBM17: u1 = 0, - /// Filter mode - FBM18: u1 = 0, - /// Filter mode - FBM19: u1 = 0, - /// Filter mode - FBM20: u1 = 0, - /// Filter mode - FBM21: u1 = 0, - /// Filter mode - FBM22: u1 = 0, - /// Filter mode - FBM23: u1 = 0, - /// Filter mode - FBM24: u1 = 0, - /// Filter mode - FBM25: u1 = 0, - /// Filter mode - FBM26: u1 = 0, - /// Filter mode - FBM27: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// filter scale register - pub const FS1R = mmio(Address + 0x0000020c, 32, packed struct { - /// Filter scale configuration - FSC0: u1 = 0, - /// Filter scale configuration - FSC1: u1 = 0, - /// Filter scale configuration - FSC2: u1 = 0, - /// Filter scale configuration - FSC3: u1 = 0, - /// Filter scale configuration - FSC4: u1 = 0, - /// Filter scale configuration - FSC5: u1 = 0, - /// Filter scale configuration - FSC6: u1 = 0, - /// Filter scale configuration - FSC7: u1 = 0, - /// Filter scale configuration - FSC8: u1 = 0, - /// Filter scale configuration - FSC9: u1 = 0, - /// Filter scale configuration - FSC10: u1 = 0, - /// Filter scale configuration - FSC11: u1 = 0, - /// Filter scale configuration - FSC12: u1 = 0, - /// Filter scale configuration - FSC13: u1 = 0, - /// Filter scale configuration - FSC14: u1 = 0, - /// Filter scale configuration - FSC15: u1 = 0, - /// Filter scale configuration - FSC16: u1 = 0, - /// Filter scale configuration - FSC17: u1 = 0, - /// Filter scale configuration - FSC18: u1 = 0, - /// Filter scale configuration - FSC19: u1 = 0, - /// Filter scale configuration - FSC20: u1 = 0, - /// Filter scale configuration - FSC21: u1 = 0, - /// Filter scale configuration - FSC22: u1 = 0, - /// Filter scale configuration - FSC23: u1 = 0, - /// Filter scale configuration - FSC24: u1 = 0, - /// Filter scale configuration - FSC25: u1 = 0, - /// Filter scale configuration - FSC26: u1 = 0, - /// Filter scale configuration - FSC27: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// filter FIFO assignment register - pub const FFA1R = mmio(Address + 0x00000214, 32, packed struct { - /// Filter FIFO assignment for filter 0 - FFA0: u1 = 0, - /// Filter FIFO assignment for filter 1 - FFA1: u1 = 0, - /// Filter FIFO assignment for filter 2 - FFA2: u1 = 0, - /// Filter FIFO assignment for filter 3 - FFA3: u1 = 0, - /// Filter FIFO assignment for filter 4 - FFA4: u1 = 0, - /// Filter FIFO assignment for filter 5 - FFA5: u1 = 0, - /// Filter FIFO assignment for filter 6 - FFA6: u1 = 0, - /// Filter FIFO assignment for filter 7 - FFA7: u1 = 0, - /// Filter FIFO assignment for filter 8 - FFA8: u1 = 0, - /// Filter FIFO assignment for filter 9 - FFA9: u1 = 0, - /// Filter FIFO assignment for filter 10 - FFA10: u1 = 0, - /// Filter FIFO assignment for filter 11 - FFA11: u1 = 0, - /// Filter FIFO assignment for filter 12 - FFA12: u1 = 0, - /// Filter FIFO assignment for filter 13 - FFA13: u1 = 0, - /// Filter FIFO assignment for filter 14 - FFA14: u1 = 0, - /// Filter FIFO assignment for filter 15 - FFA15: u1 = 0, - /// Filter FIFO assignment for filter 16 - FFA16: u1 = 0, - /// Filter FIFO assignment for filter 17 - FFA17: u1 = 0, - /// Filter FIFO assignment for filter 18 - FFA18: u1 = 0, - /// Filter FIFO assignment for filter 19 - FFA19: u1 = 0, - /// Filter FIFO assignment for filter 20 - FFA20: u1 = 0, - /// Filter FIFO assignment for filter 21 - FFA21: u1 = 0, - /// Filter FIFO assignment for filter 22 - FFA22: u1 = 0, - /// Filter FIFO assignment for filter 23 - FFA23: u1 = 0, - /// Filter FIFO assignment for filter 24 - FFA24: u1 = 0, - /// Filter FIFO assignment for filter 25 - FFA25: u1 = 0, - /// Filter FIFO assignment for filter 26 - FFA26: u1 = 0, - /// Filter FIFO assignment for filter 27 - FFA27: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN filter activation register - pub const FA1R = mmio(Address + 0x0000021c, 32, packed struct { - /// Filter active - FACT0: u1 = 0, - /// Filter active - FACT1: u1 = 0, - /// Filter active - FACT2: u1 = 0, - /// Filter active - FACT3: u1 = 0, - /// Filter active - FACT4: u1 = 0, - /// Filter active - FACT5: u1 = 0, - /// Filter active - FACT6: u1 = 0, - /// Filter active - FACT7: u1 = 0, - /// Filter active - FACT8: u1 = 0, - /// Filter active - FACT9: u1 = 0, - /// Filter active - FACT10: u1 = 0, - /// Filter active - FACT11: u1 = 0, - /// Filter active - FACT12: u1 = 0, - /// Filter active - FACT13: u1 = 0, - /// Filter active - FACT14: u1 = 0, - /// Filter active - FACT15: u1 = 0, - /// Filter active - FACT16: u1 = 0, - /// Filter active - FACT17: u1 = 0, - /// Filter active - FACT18: u1 = 0, - /// Filter active - FACT19: u1 = 0, - /// Filter active - FACT20: u1 = 0, - /// Filter active - FACT21: u1 = 0, - /// Filter active - FACT22: u1 = 0, - /// Filter active - FACT23: u1 = 0, - /// Filter active - FACT24: u1 = 0, - /// Filter active - FACT25: u1 = 0, - /// Filter active - FACT26: u1 = 0, - /// Filter active - FACT27: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Filter bank 0 register 1 - pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 0 register 2 - pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 1 register 1 - pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 1 register 2 - pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 2 register 1 - pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 2 register 2 - pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 3 register 1 - pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 3 register 2 - pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 1 - pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 2 - pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 5 register 1 - pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 5 register 2 - pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 6 register 1 - pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 6 register 2 - pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 7 register 1 - pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 7 register 2 - pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 8 register 1 - pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 8 register 2 - pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 9 register 1 - pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 9 register 2 - pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 10 register 1 - pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 10 register 2 - pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 11 register 1 - pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 11 register 2 - pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 1 - pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 12 register 2 - pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 13 register 1 - pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 13 register 2 - pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 14 register 1 - pub const F14R1 = mmio(Address + 0x000002b0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 14 register 2 - pub const F14R2 = mmio(Address + 0x000002b4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 15 register 1 - pub const F15R1 = mmio(Address + 0x000002b8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 15 register 2 - pub const F15R2 = mmio(Address + 0x000002bc, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 16 register 1 - pub const F16R1 = mmio(Address + 0x000002c0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 16 register 2 - pub const F16R2 = mmio(Address + 0x000002c4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 17 register 1 - pub const F17R1 = mmio(Address + 0x000002c8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 17 register 2 - pub const F17R2 = mmio(Address + 0x000002cc, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 18 register 1 - pub const F18R1 = mmio(Address + 0x000002d0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 18 register 2 - pub const F18R2 = mmio(Address + 0x000002d4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 19 register 1 - pub const F19R1 = mmio(Address + 0x000002d8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 19 register 2 - pub const F19R2 = mmio(Address + 0x000002dc, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 20 register 1 - pub const F20R1 = mmio(Address + 0x000002e0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 20 register 2 - pub const F20R2 = mmio(Address + 0x000002e4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 21 register 1 - pub const F21R1 = mmio(Address + 0x000002e8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 21 register 2 - pub const F21R2 = mmio(Address + 0x000002ec, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 22 register 1 - pub const F22R1 = mmio(Address + 0x000002f0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 22 register 2 - pub const F22R2 = mmio(Address + 0x000002f4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 23 register 1 - pub const F23R1 = mmio(Address + 0x000002f8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 23 register 2 - pub const F23R2 = mmio(Address + 0x000002fc, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 24 register 1 - pub const F24R1 = mmio(Address + 0x00000300, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 24 register 2 - pub const F24R2 = mmio(Address + 0x00000304, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 25 register 1 - pub const F25R1 = mmio(Address + 0x00000308, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 25 register 2 - pub const F25R2 = mmio(Address + 0x0000030c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 26 register 1 - pub const F26R1 = mmio(Address + 0x00000310, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 26 register 2 - pub const F26R2 = mmio(Address + 0x00000314, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 27 register 1 - pub const F27R1 = mmio(Address + 0x00000318, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 27 register 2 - pub const F27R2 = mmio(Address + 0x0000031c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); -}; - -/// Universal serial bus full-speed device interface -pub const USB_FS = extern struct { - pub const Address: u32 = 0x40005c00; - - /// endpoint 0 register - pub const USB_EP0R = mmio(Address + 0x00000000, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 1 register - pub const USB_EP1R = mmio(Address + 0x00000004, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 2 register - pub const USB_EP2R = mmio(Address + 0x00000008, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 3 register - pub const USB_EP3R = mmio(Address + 0x0000000c, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 4 register - pub const USB_EP4R = mmio(Address + 0x00000010, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 5 register - pub const USB_EP5R = mmio(Address + 0x00000014, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 6 register - pub const USB_EP6R = mmio(Address + 0x00000018, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 7 register - pub const USB_EP7R = mmio(Address + 0x0000001c, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const USB_CNTR = mmio(Address + 0x00000040, 32, packed struct { - /// Force USB Reset - FRES: u1 = 0, - /// Power down - PDWN: u1 = 0, - /// Low-power mode - LPMODE: u1 = 0, - /// Force suspend - FSUSP: u1 = 0, - /// Resume request - RESUME: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Expected start of frame interrupt mask - ESOFM: u1 = 0, - /// Start of frame interrupt mask - SOFM: u1 = 0, - /// USB reset interrupt mask - RESETM: u1 = 0, - /// Suspend mode interrupt mask - SUSPM: u1 = 0, - /// Wakeup interrupt mask - WKUPM: u1 = 0, - /// Error interrupt mask - ERRM: u1 = 0, - /// Packet memory area over / underrun interrupt mask - PMAOVRM: u1 = 0, - /// Correct transfer interrupt mask - CTRM: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt status register - pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { - /// Endpoint Identifier - EP_ID: u4 = 0, - /// Direction of transaction - DIR: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Expected start frame - ESOF: u1 = 0, - /// start of frame - SOF: u1 = 0, - /// reset request - RESET: u1 = 0, - /// Suspend mode request - SUSP: u1 = 0, - /// Wakeup - WKUP: u1 = 0, - /// Error - ERR: u1 = 0, - /// Packet memory area over / underrun - PMAOVR: u1 = 0, - /// Correct transfer - CTR: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// frame number register - pub const FNR = mmio(Address + 0x00000048, 32, packed struct { - /// Frame number - FN: u11 = 0, - /// Lost SOF - LSOF: u2 = 0, - /// Locked - LCK: u1 = 0, - /// Receive data - line status - RXDM: u1 = 0, - /// Receive data + line status - RXDP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// device address - pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { - /// Device address - ADD: u1 = 0, - /// Device address - ADD1: u1 = 0, - /// Device address - ADD2: u1 = 0, - /// Device address - ADD3: u1 = 0, - /// Device address - ADD4: u1 = 0, - /// Device address - ADD5: u1 = 0, - /// Device address - ADD6: u1 = 0, - /// Enable function - EF: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Buffer table address - pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Buffer table - BTABLE: u13 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Inter-integrated circuit -pub const I2C1 = extern struct { - pub const Address: u32 = 0x40005400; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Peripheral enable - PE: u1 = 0, - /// TX Interrupt enable - TXIE: u1 = 0, - /// RX Interrupt enable - RXIE: u1 = 0, - /// Address match interrupt enable (slave only) - ADDRIE: u1 = 0, - /// Not acknowledge received interrupt enable - NACKIE: u1 = 0, - /// STOP detection Interrupt enable - STOPIE: u1 = 0, - /// Transfer Complete interrupt enable - TCIE: u1 = 0, - /// Error interrupts enable - ERRIE: u1 = 0, - /// Digital noise filter - DNF: u4 = 0, - /// Analog noise filter OFF - ANFOFF: u1 = 0, - /// Software reset - SWRST: u1 = 0, - /// DMA transmission requests enable - TXDMAEN: u1 = 0, - /// DMA reception requests enable - RXDMAEN: u1 = 0, - /// Slave byte control - SBC: u1 = 0, - /// Clock stretching disable - NOSTRETCH: u1 = 0, - /// Wakeup from STOP enable - WUPEN: u1 = 0, - /// General call enable - GCEN: u1 = 0, - /// SMBus Host address enable - SMBHEN: u1 = 0, - /// SMBus Device Default address enable - SMBDEN: u1 = 0, - /// SMBUS alert enable - ALERTEN: u1 = 0, - /// PEC enable - PECEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Slave address bit 0 (master mode) - SADD0: u1 = 0, - /// Slave address bit 7:1 (master mode) - SADD1: u7 = 0, - /// Slave address bit 9:8 (master mode) - SADD8: u2 = 0, - /// Transfer direction (master mode) - RD_WRN: u1 = 0, - /// 10-bit addressing mode (master mode) - ADD10: u1 = 0, - /// 10-bit address header only read direction (master receiver mode) - HEAD10R: u1 = 0, - /// Start generation - START: u1 = 0, - /// Stop generation (master mode) - STOP: u1 = 0, - /// NACK generation (slave mode) - NACK: u1 = 0, - /// Number of bytes - NBYTES: u8 = 0, - /// NBYTES reload mode - RELOAD: u1 = 0, - /// Automatic end mode (master mode) - AUTOEND: u1 = 0, - /// Packet error checking byte - PECBYTE: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Interface address - OA1_0: u1 = 0, - /// Interface address - OA1_1: u7 = 0, - /// Interface address - OA1_8: u2 = 0, - /// Own Address 1 10-bit mode - OA1MODE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Own Address 1 enable - OA1EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - /// Interface address - OA2: u7 = 0, - /// Own Address 2 masks - OA2MSK: u3 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Own Address 2 enable - OA2EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timing register - pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - /// SCL low period (master mode) - SCLL: u8 = 0, - /// SCL high period (master mode) - SCLH: u8 = 0, - /// Data hold time - SDADEL: u4 = 0, - /// Data setup time - SCLDEL: u4 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Timing prescaler - PRESC: u4 = 0, - }); - - /// Status register 1 - pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - /// Bus timeout A - TIMEOUTA: u12 = 0, - /// Idle clock timeout detection - TIDLE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Clock timeout enable - TIMOUTEN: u1 = 0, - /// Bus timeout B - TIMEOUTB: u12 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Extended clock timeout enable - TEXTEN: u1 = 0, - }); - - /// Interrupt and Status register - pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - /// Transmit data register empty (transmitters) - TXE: u1 = 0, - /// Transmit interrupt status (transmitters) - TXIS: u1 = 0, - /// Receive data register not empty (receivers) - RXNE: u1 = 0, - /// Address matched (slave mode) - ADDR: u1 = 0, - /// Not acknowledge received flag - NACKF: u1 = 0, - /// Stop detection flag - STOPF: u1 = 0, - /// Transfer Complete (master mode) - TC: u1 = 0, - /// Transfer Complete Reload - TCR: u1 = 0, - /// Bus error - BERR: u1 = 0, - /// Arbitration lost - ARLO: u1 = 0, - /// Overrun/Underrun (slave mode) - OVR: u1 = 0, - /// PEC Error in reception - PECERR: u1 = 0, - /// Timeout or t_low detection flag - TIMEOUT: u1 = 0, - /// SMBus alert - ALERT: u1 = 0, - reserved1: u1 = 0, - /// Bus busy - BUSY: u1 = 0, - /// Transfer direction (Slave mode) - DIR: u1 = 0, - /// Address match code (Slave mode) - ADDCODE: u7 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt clear register - pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Address Matched flag clear - ADDRCF: u1 = 0, - /// Not Acknowledge flag clear - NACKCF: u1 = 0, - /// Stop detection flag clear - STOPCF: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Bus error flag clear - BERRCF: u1 = 0, - /// Arbitration lost flag clear - ARLOCF: u1 = 0, - /// Overrun/Underrun flag clear - OVRCF: u1 = 0, - /// PEC Error flag clear - PECCF: u1 = 0, - /// Timeout detection flag clear - TIMOUTCF: u1 = 0, - /// Alert flag clear - ALERTCF: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PEC register - pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - /// Packet error checking register - PEC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - /// 8-bit receive data - RXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - /// 8-bit transmit data - TXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Inter-integrated circuit -pub const I2C2 = extern struct { - pub const Address: u32 = 0x40005800; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Peripheral enable - PE: u1 = 0, - /// TX Interrupt enable - TXIE: u1 = 0, - /// RX Interrupt enable - RXIE: u1 = 0, - /// Address match interrupt enable (slave only) - ADDRIE: u1 = 0, - /// Not acknowledge received interrupt enable - NACKIE: u1 = 0, - /// STOP detection Interrupt enable - STOPIE: u1 = 0, - /// Transfer Complete interrupt enable - TCIE: u1 = 0, - /// Error interrupts enable - ERRIE: u1 = 0, - /// Digital noise filter - DNF: u4 = 0, - /// Analog noise filter OFF - ANFOFF: u1 = 0, - /// Software reset - SWRST: u1 = 0, - /// DMA transmission requests enable - TXDMAEN: u1 = 0, - /// DMA reception requests enable - RXDMAEN: u1 = 0, - /// Slave byte control - SBC: u1 = 0, - /// Clock stretching disable - NOSTRETCH: u1 = 0, - /// Wakeup from STOP enable - WUPEN: u1 = 0, - /// General call enable - GCEN: u1 = 0, - /// SMBus Host address enable - SMBHEN: u1 = 0, - /// SMBus Device Default address enable - SMBDEN: u1 = 0, - /// SMBUS alert enable - ALERTEN: u1 = 0, - /// PEC enable - PECEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Slave address bit 0 (master mode) - SADD0: u1 = 0, - /// Slave address bit 7:1 (master mode) - SADD1: u7 = 0, - /// Slave address bit 9:8 (master mode) - SADD8: u2 = 0, - /// Transfer direction (master mode) - RD_WRN: u1 = 0, - /// 10-bit addressing mode (master mode) - ADD10: u1 = 0, - /// 10-bit address header only read direction (master receiver mode) - HEAD10R: u1 = 0, - /// Start generation - START: u1 = 0, - /// Stop generation (master mode) - STOP: u1 = 0, - /// NACK generation (slave mode) - NACK: u1 = 0, - /// Number of bytes - NBYTES: u8 = 0, - /// NBYTES reload mode - RELOAD: u1 = 0, - /// Automatic end mode (master mode) - AUTOEND: u1 = 0, - /// Packet error checking byte - PECBYTE: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Interface address - OA1_0: u1 = 0, - /// Interface address - OA1_1: u7 = 0, - /// Interface address - OA1_8: u2 = 0, - /// Own Address 1 10-bit mode - OA1MODE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Own Address 1 enable - OA1EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - /// Interface address - OA2: u7 = 0, - /// Own Address 2 masks - OA2MSK: u3 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Own Address 2 enable - OA2EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timing register - pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - /// SCL low period (master mode) - SCLL: u8 = 0, - /// SCL high period (master mode) - SCLH: u8 = 0, - /// Data hold time - SDADEL: u4 = 0, - /// Data setup time - SCLDEL: u4 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Timing prescaler - PRESC: u4 = 0, - }); - - /// Status register 1 - pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - /// Bus timeout A - TIMEOUTA: u12 = 0, - /// Idle clock timeout detection - TIDLE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Clock timeout enable - TIMOUTEN: u1 = 0, - /// Bus timeout B - TIMEOUTB: u12 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Extended clock timeout enable - TEXTEN: u1 = 0, - }); - - /// Interrupt and Status register - pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - /// Transmit data register empty (transmitters) - TXE: u1 = 0, - /// Transmit interrupt status (transmitters) - TXIS: u1 = 0, - /// Receive data register not empty (receivers) - RXNE: u1 = 0, - /// Address matched (slave mode) - ADDR: u1 = 0, - /// Not acknowledge received flag - NACKF: u1 = 0, - /// Stop detection flag - STOPF: u1 = 0, - /// Transfer Complete (master mode) - TC: u1 = 0, - /// Transfer Complete Reload - TCR: u1 = 0, - /// Bus error - BERR: u1 = 0, - /// Arbitration lost - ARLO: u1 = 0, - /// Overrun/Underrun (slave mode) - OVR: u1 = 0, - /// PEC Error in reception - PECERR: u1 = 0, - /// Timeout or t_low detection flag - TIMEOUT: u1 = 0, - /// SMBus alert - ALERT: u1 = 0, - reserved1: u1 = 0, - /// Bus busy - BUSY: u1 = 0, - /// Transfer direction (Slave mode) - DIR: u1 = 0, - /// Address match code (Slave mode) - ADDCODE: u7 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt clear register - pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Address Matched flag clear - ADDRCF: u1 = 0, - /// Not Acknowledge flag clear - NACKCF: u1 = 0, - /// Stop detection flag clear - STOPCF: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Bus error flag clear - BERRCF: u1 = 0, - /// Arbitration lost flag clear - ARLOCF: u1 = 0, - /// Overrun/Underrun flag clear - OVRCF: u1 = 0, - /// PEC Error flag clear - PECCF: u1 = 0, - /// Timeout detection flag clear - TIMOUTCF: u1 = 0, - /// Alert flag clear - ALERTCF: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PEC register - pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - /// Packet error checking register - PEC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - /// 8-bit receive data - RXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - /// 8-bit transmit data - TXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Inter-integrated circuit -pub const I2C3 = extern struct { - pub const Address: u32 = 0x40007800; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Peripheral enable - PE: u1 = 0, - /// TX Interrupt enable - TXIE: u1 = 0, - /// RX Interrupt enable - RXIE: u1 = 0, - /// Address match interrupt enable (slave only) - ADDRIE: u1 = 0, - /// Not acknowledge received interrupt enable - NACKIE: u1 = 0, - /// STOP detection Interrupt enable - STOPIE: u1 = 0, - /// Transfer Complete interrupt enable - TCIE: u1 = 0, - /// Error interrupts enable - ERRIE: u1 = 0, - /// Digital noise filter - DNF: u4 = 0, - /// Analog noise filter OFF - ANFOFF: u1 = 0, - /// Software reset - SWRST: u1 = 0, - /// DMA transmission requests enable - TXDMAEN: u1 = 0, - /// DMA reception requests enable - RXDMAEN: u1 = 0, - /// Slave byte control - SBC: u1 = 0, - /// Clock stretching disable - NOSTRETCH: u1 = 0, - /// Wakeup from STOP enable - WUPEN: u1 = 0, - /// General call enable - GCEN: u1 = 0, - /// SMBus Host address enable - SMBHEN: u1 = 0, - /// SMBus Device Default address enable - SMBDEN: u1 = 0, - /// SMBUS alert enable - ALERTEN: u1 = 0, - /// PEC enable - PECEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Slave address bit 0 (master mode) - SADD0: u1 = 0, - /// Slave address bit 7:1 (master mode) - SADD1: u7 = 0, - /// Slave address bit 9:8 (master mode) - SADD8: u2 = 0, - /// Transfer direction (master mode) - RD_WRN: u1 = 0, - /// 10-bit addressing mode (master mode) - ADD10: u1 = 0, - /// 10-bit address header only read direction (master receiver mode) - HEAD10R: u1 = 0, - /// Start generation - START: u1 = 0, - /// Stop generation (master mode) - STOP: u1 = 0, - /// NACK generation (slave mode) - NACK: u1 = 0, - /// Number of bytes - NBYTES: u8 = 0, - /// NBYTES reload mode - RELOAD: u1 = 0, - /// Automatic end mode (master mode) - AUTOEND: u1 = 0, - /// Packet error checking byte - PECBYTE: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Interface address - OA1_0: u1 = 0, - /// Interface address - OA1_1: u7 = 0, - /// Interface address - OA1_8: u2 = 0, - /// Own Address 1 10-bit mode - OA1MODE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Own Address 1 enable - OA1EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - /// Interface address - OA2: u7 = 0, - /// Own Address 2 masks - OA2MSK: u3 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Own Address 2 enable - OA2EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timing register - pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - /// SCL low period (master mode) - SCLL: u8 = 0, - /// SCL high period (master mode) - SCLH: u8 = 0, - /// Data hold time - SDADEL: u4 = 0, - /// Data setup time - SCLDEL: u4 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Timing prescaler - PRESC: u4 = 0, - }); - - /// Status register 1 - pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - /// Bus timeout A - TIMEOUTA: u12 = 0, - /// Idle clock timeout detection - TIDLE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Clock timeout enable - TIMOUTEN: u1 = 0, - /// Bus timeout B - TIMEOUTB: u12 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Extended clock timeout enable - TEXTEN: u1 = 0, - }); - - /// Interrupt and Status register - pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - /// Transmit data register empty (transmitters) - TXE: u1 = 0, - /// Transmit interrupt status (transmitters) - TXIS: u1 = 0, - /// Receive data register not empty (receivers) - RXNE: u1 = 0, - /// Address matched (slave mode) - ADDR: u1 = 0, - /// Not acknowledge received flag - NACKF: u1 = 0, - /// Stop detection flag - STOPF: u1 = 0, - /// Transfer Complete (master mode) - TC: u1 = 0, - /// Transfer Complete Reload - TCR: u1 = 0, - /// Bus error - BERR: u1 = 0, - /// Arbitration lost - ARLO: u1 = 0, - /// Overrun/Underrun (slave mode) - OVR: u1 = 0, - /// PEC Error in reception - PECERR: u1 = 0, - /// Timeout or t_low detection flag - TIMEOUT: u1 = 0, - /// SMBus alert - ALERT: u1 = 0, - reserved1: u1 = 0, - /// Bus busy - BUSY: u1 = 0, - /// Transfer direction (Slave mode) - DIR: u1 = 0, - /// Address match code (Slave mode) - ADDCODE: u7 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt clear register - pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Address Matched flag clear - ADDRCF: u1 = 0, - /// Not Acknowledge flag clear - NACKCF: u1 = 0, - /// Stop detection flag clear - STOPCF: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Bus error flag clear - BERRCF: u1 = 0, - /// Arbitration lost flag clear - ARLOCF: u1 = 0, - /// Overrun/Underrun flag clear - OVRCF: u1 = 0, - /// PEC Error flag clear - PECCF: u1 = 0, - /// Timeout detection flag clear - TIMOUTCF: u1 = 0, - /// Alert flag clear - ALERTCF: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PEC register - pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - /// Packet error checking register - PEC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - /// 8-bit receive data - RXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - /// 8-bit transmit data - TXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Independent watchdog -pub const IWDG = extern struct { - pub const Address: u32 = 0x40003000; - - /// Key register - pub const KR = mmio(Address + 0x00000000, 32, packed struct { - /// Key value - KEY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Prescaler register - pub const PR = mmio(Address + 0x00000004, 32, packed struct { - /// Prescaler divider - PR: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reload register - pub const RLR = mmio(Address + 0x00000008, 32, packed struct { - /// Watchdog counter reload value - RL: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - /// Watchdog prescaler value update - PVU: u1 = 0, - /// Watchdog counter reload value update - RVU: u1 = 0, - /// Watchdog counter window value update - WVU: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Window register - pub const WINR = mmio(Address + 0x00000010, 32, packed struct { - /// Watchdog counter window value - WIN: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Window watchdog -pub const WWDG = extern struct { - pub const Address: u32 = 0x40002c00; - - /// Control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// 7-bit counter - T: u7 = 0, - /// Activation bit - WDGA: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CFR = mmio(Address + 0x00000004, 32, packed struct { - /// 7-bit window value - W: u7 = 0, - /// Timer base - WDGTB: u2 = 0, - /// Early wakeup interrupt - EWI: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Early wakeup interrupt flag - EWIF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Real-time clock -pub const RTC = extern struct { - pub const Address: u32 = 0x40002800; - - /// time register - pub const TR = mmio(Address + 0x00000000, 32, packed struct { - /// Second units in BCD format - SU: u4 = 0, - /// Second tens in BCD format - ST: u3 = 0, - reserved1: u1 = 0, - /// Minute units in BCD format - MNU: u4 = 0, - /// Minute tens in BCD format - MNT: u3 = 0, - reserved2: u1 = 0, - /// Hour units in BCD format - HU: u4 = 0, - /// Hour tens in BCD format - HT: u2 = 0, - /// AM/PM notation - PM: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// date register - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - /// Date units in BCD format - DU: u4 = 0, - /// Date tens in BCD format - DT: u2 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Month units in BCD format - MU: u4 = 0, - /// Month tens in BCD format - MT: u1 = 0, - /// Week day units - WDU: u3 = 0, - /// Year units in BCD format - YU: u4 = 0, - /// Year tens in BCD format - YT: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - /// Wakeup clock selection - WCKSEL: u3 = 0, - /// Time-stamp event active edge - TSEDGE: u1 = 0, - /// Reference clock detection enable (50 or 60 Hz) - REFCKON: u1 = 0, - /// Bypass the shadow registers - BYPSHAD: u1 = 0, - /// Hour format - FMT: u1 = 0, - reserved1: u1 = 0, - /// Alarm A enable - ALRAE: u1 = 0, - /// Alarm B enable - ALRBE: u1 = 0, - /// Wakeup timer enable - WUTE: u1 = 0, - /// Time stamp enable - TSE: u1 = 0, - /// Alarm A interrupt enable - ALRAIE: u1 = 0, - /// Alarm B interrupt enable - ALRBIE: u1 = 0, - /// Wakeup timer interrupt enable - WUTIE: u1 = 0, - /// Time-stamp interrupt enable - TSIE: u1 = 0, - /// Add 1 hour (summer time change) - ADD1H: u1 = 0, - /// Subtract 1 hour (winter time change) - SUB1H: u1 = 0, - /// Backup - BKP: u1 = 0, - /// Calibration output selection - COSEL: u1 = 0, - /// Output polarity - POL: u1 = 0, - /// Output selection - OSEL: u2 = 0, - /// Calibration output enable - COE: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// initialization and status register - pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { - /// Alarm A write flag - ALRAWF: u1 = 0, - /// Alarm B write flag - ALRBWF: u1 = 0, - /// Wakeup timer write flag - WUTWF: u1 = 0, - /// Shift operation pending - SHPF: u1 = 0, - /// Initialization status flag - INITS: u1 = 0, - /// Registers synchronization flag - RSF: u1 = 0, - /// Initialization flag - INITF: u1 = 0, - /// Initialization mode - INIT: u1 = 0, - /// Alarm A flag - ALRAF: u1 = 0, - /// Alarm B flag - ALRBF: u1 = 0, - /// Wakeup timer flag - WUTF: u1 = 0, - /// Time-stamp flag - TSF: u1 = 0, - /// Time-stamp overflow flag - TSOVF: u1 = 0, - /// Tamper detection flag - TAMP1F: u1 = 0, - /// RTC_TAMP2 detection flag - TAMP2F: u1 = 0, - /// RTC_TAMP3 detection flag - TAMP3F: u1 = 0, - /// Recalibration pending Flag - RECALPF: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler register - pub const PRER = mmio(Address + 0x00000010, 32, packed struct { - /// Synchronous prescaler factor - PREDIV_S: u15 = 0, - reserved1: u1 = 0, - /// Asynchronous prescaler factor - PREDIV_A: u7 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// wakeup timer register - pub const WUTR = mmio(Address + 0x00000014, 32, packed struct { - /// Wakeup auto-reload value bits - WUT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// alarm A register - pub const ALRMAR = mmio(Address + 0x0000001c, 32, packed struct { - /// Second units in BCD format - SU: u4 = 0, - /// Second tens in BCD format - ST: u3 = 0, - /// Alarm A seconds mask - MSK1: u1 = 0, - /// Minute units in BCD format - MNU: u4 = 0, - /// Minute tens in BCD format - MNT: u3 = 0, - /// Alarm A minutes mask - MSK2: u1 = 0, - /// Hour units in BCD format - HU: u4 = 0, - /// Hour tens in BCD format - HT: u2 = 0, - /// AM/PM notation - PM: u1 = 0, - /// Alarm A hours mask - MSK3: u1 = 0, - /// Date units or day in BCD format - DU: u4 = 0, - /// Date tens in BCD format - DT: u2 = 0, - /// Week day selection - WDSEL: u1 = 0, - /// Alarm A date mask - MSK4: u1 = 0, - }); - - /// alarm B register - pub const ALRMBR = mmio(Address + 0x00000020, 32, packed struct { - /// Second units in BCD format - SU: u4 = 0, - /// Second tens in BCD format - ST: u3 = 0, - /// Alarm B seconds mask - MSK1: u1 = 0, - /// Minute units in BCD format - MNU: u4 = 0, - /// Minute tens in BCD format - MNT: u3 = 0, - /// Alarm B minutes mask - MSK2: u1 = 0, - /// Hour units in BCD format - HU: u4 = 0, - /// Hour tens in BCD format - HT: u2 = 0, - /// AM/PM notation - PM: u1 = 0, - /// Alarm B hours mask - MSK3: u1 = 0, - /// Date units or day in BCD format - DU: u4 = 0, - /// Date tens in BCD format - DT: u2 = 0, - /// Week day selection - WDSEL: u1 = 0, - /// Alarm B date mask - MSK4: u1 = 0, - }); - - /// write protection register - pub const WPR = mmio(Address + 0x00000024, 32, packed struct { - /// Write protection key - KEY: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sub second register - pub const SSR = mmio(Address + 0x00000028, 32, packed struct { - /// Sub second value - SS: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// shift control register - pub const SHIFTR = mmio(Address + 0x0000002c, 32, packed struct { - /// Subtract a fraction of a second - SUBFS: u15 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Add one second - ADD1S: u1 = 0, - }); - - /// time stamp time register - pub const TSTR = mmio(Address + 0x00000030, 32, packed struct { - /// Second units in BCD format - SU: u4 = 0, - /// Second tens in BCD format - ST: u3 = 0, - reserved1: u1 = 0, - /// Minute units in BCD format - MNU: u4 = 0, - /// Minute tens in BCD format - MNT: u3 = 0, - reserved2: u1 = 0, - /// Hour units in BCD format - HU: u4 = 0, - /// Hour tens in BCD format - HT: u2 = 0, - /// AM/PM notation - PM: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// time stamp date register - pub const TSDR = mmio(Address + 0x00000034, 32, packed struct { - /// Date units in BCD format - DU: u4 = 0, - /// Date tens in BCD format - DT: u2 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Month units in BCD format - MU: u4 = 0, - /// Month tens in BCD format - MT: u1 = 0, - /// Week day units - WDU: u3 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// timestamp sub second register - pub const TSSSR = mmio(Address + 0x00000038, 32, packed struct { - /// Sub second value - SS: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// calibration register - pub const CALR = mmio(Address + 0x0000003c, 32, packed struct { - /// Calibration minus - CALM: u9 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Use a 16-second calibration cycle period - CALW16: u1 = 0, - /// Use an 8-second calibration cycle period - CALW8: u1 = 0, - /// Increase frequency of RTC by 488.5 ppm - CALP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// tamper and alternate function configuration register - pub const TAFCR = mmio(Address + 0x00000040, 32, packed struct { - /// Tamper 1 detection enable - TAMP1E: u1 = 0, - /// Active level for tamper 1 - TAMP1TRG: u1 = 0, - /// Tamper interrupt enable - TAMPIE: u1 = 0, - /// Tamper 2 detection enable - TAMP2E: u1 = 0, - /// Active level for tamper 2 - TAMP2TRG: u1 = 0, - /// Tamper 3 detection enable - TAMP3E: u1 = 0, - /// Active level for tamper 3 - TAMP3TRG: u1 = 0, - /// Activate timestamp on tamper detection event - TAMPTS: u1 = 0, - /// Tamper sampling frequency - TAMPFREQ: u3 = 0, - /// Tamper filter count - TAMPFLT: u2 = 0, - /// Tamper precharge duration - TAMPPRCH: u2 = 0, - /// TAMPER pull-up disable - TAMPPUDIS: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// PC13 value - PC13VALUE: u1 = 0, - /// PC13 mode - PC13MODE: u1 = 0, - /// PC14 value - PC14VALUE: u1 = 0, - /// PC 14 mode - PC14MODE: u1 = 0, - /// PC15 value - PC15VALUE: u1 = 0, - /// PC15 mode - PC15MODE: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// alarm A sub second register - pub const ALRMASSR = mmio(Address + 0x00000044, 32, packed struct { - /// Sub seconds value - SS: u15 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Mask the most-significant bits starting at this bit - MASKSS: u4 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// alarm B sub second register - pub const ALRMBSSR = mmio(Address + 0x00000048, 32, packed struct { - /// Sub seconds value - SS: u15 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Mask the most-significant bits starting at this bit - MASKSS: u4 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// backup register - pub const BKP0R = mmio(Address + 0x00000050, 32, packed struct {}); - - /// backup register - pub const BKP1R = mmio(Address + 0x00000054, 32, packed struct {}); - - /// backup register - pub const BKP2R = mmio(Address + 0x00000058, 32, packed struct {}); - - /// backup register - pub const BKP3R = mmio(Address + 0x0000005c, 32, packed struct {}); - - /// backup register - pub const BKP4R = mmio(Address + 0x00000060, 32, packed struct {}); - - /// backup register - pub const BKP5R = mmio(Address + 0x00000064, 32, packed struct {}); - - /// backup register - pub const BKP6R = mmio(Address + 0x00000068, 32, packed struct {}); - - /// backup register - pub const BKP7R = mmio(Address + 0x0000006c, 32, packed struct {}); - - /// backup register - pub const BKP8R = mmio(Address + 0x00000070, 32, packed struct {}); - - /// backup register - pub const BKP9R = mmio(Address + 0x00000074, 32, packed struct {}); - - /// backup register - pub const BKP10R = mmio(Address + 0x00000078, 32, packed struct {}); - - /// backup register - pub const BKP11R = mmio(Address + 0x0000007c, 32, packed struct {}); - - /// backup register - pub const BKP12R = mmio(Address + 0x00000080, 32, packed struct {}); - - /// backup register - pub const BKP13R = mmio(Address + 0x00000084, 32, packed struct {}); - - /// backup register - pub const BKP14R = mmio(Address + 0x00000088, 32, packed struct {}); - - /// backup register - pub const BKP15R = mmio(Address + 0x0000008c, 32, packed struct {}); - - /// backup register - pub const BKP16R = mmio(Address + 0x00000090, 32, packed struct {}); - - /// backup register - pub const BKP17R = mmio(Address + 0x00000094, 32, packed struct {}); - - /// backup register - pub const BKP18R = mmio(Address + 0x00000098, 32, packed struct {}); - - /// backup register - pub const BKP19R = mmio(Address + 0x0000009c, 32, packed struct {}); - - /// backup register - pub const BKP20R = mmio(Address + 0x000000a0, 32, packed struct {}); - - /// backup register - pub const BKP21R = mmio(Address + 0x000000a4, 32, packed struct {}); - - /// backup register - pub const BKP22R = mmio(Address + 0x000000a8, 32, packed struct {}); - - /// backup register - pub const BKP23R = mmio(Address + 0x000000ac, 32, packed struct {}); - - /// backup register - pub const BKP24R = mmio(Address + 0x000000b0, 32, packed struct {}); - - /// backup register - pub const BKP25R = mmio(Address + 0x000000b4, 32, packed struct {}); - - /// backup register - pub const BKP26R = mmio(Address + 0x000000b8, 32, packed struct {}); - - /// backup register - pub const BKP27R = mmio(Address + 0x000000bc, 32, packed struct {}); - - /// backup register - pub const BKP28R = mmio(Address + 0x000000c0, 32, packed struct {}); - - /// backup register - pub const BKP29R = mmio(Address + 0x000000c4, 32, packed struct {}); - - /// backup register - pub const BKP30R = mmio(Address + 0x000000c8, 32, packed struct {}); - - /// backup register - pub const BKP31R = mmio(Address + 0x000000cc, 32, packed struct {}); -}; - -/// Basic timers -pub const TIM6 = extern struct { - pub const Address: u32 = 0x40001000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF Copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Basic timers -pub const TIM7 = extern struct { - pub const Address: u32 = 0x40001400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF Copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Digital-to-analog converter -pub const DAC = extern struct { - pub const Address: u32 = 0x40007400; - - /// control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// DAC channel1 enable - EN1: u1 = 0, - /// DAC channel1 output buffer disable - BOFF1: u1 = 0, - /// DAC channel1 trigger enable - TEN1: u1 = 0, - /// DAC channel1 trigger selection - TSEL1: u3 = 0, - /// DAC channel1 noise/triangle wave generation enable - WAVE1: u2 = 0, - /// DAC channel1 mask/amplitude selector - MAMP1: u4 = 0, - /// DAC channel1 DMA enable - DMAEN1: u1 = 0, - /// DAC channel1 DMA Underrun Interrupt enable - DMAUDRIE1: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 enable - EN2: u1 = 0, - /// DAC channel2 output buffer disable - BOFF2: u1 = 0, - /// DAC channel2 trigger enable - TEN2: u1 = 0, - /// DAC channel2 trigger selection - TSEL2: u3 = 0, - /// DAC channel2 noise/triangle wave generation enable - WAVE2: u2 = 0, - /// DAC channel2 mask/amplitude selector - MAMP2: u4 = 0, - /// DAC channel2 DMA enable - DMAEN2: u1 = 0, - /// DAC channel2 DMA underrun interrupt enable - DMAUDRIE2: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// software trigger register - pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { - /// DAC channel1 software trigger - SWTRIG1: u1 = 0, - /// DAC channel2 software trigger - SWTRIG2: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel1 12-bit right-aligned data holding register - pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { - /// DAC channel1 12-bit right-aligned data - DACC1DHR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel1 12-bit left aligned data holding register - pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel1 12-bit left-aligned data - DACC1DHR: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel1 8-bit right aligned data holding register - pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { - /// DAC channel1 8-bit right-aligned data - DACC1DHR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel2 12-bit right aligned data holding register - pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { - /// DAC channel2 12-bit right-aligned data - DACC2DHR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel2 12-bit left aligned data holding register - pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 12-bit left-aligned data - DACC2DHR: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel2 8-bit right-aligned data holding register - pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { - /// DAC channel2 8-bit right-aligned data - DACC2DHR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Dual DAC 12-bit right-aligned data holding register - pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { - /// DAC channel1 12-bit right-aligned data - DACC1DHR: u12 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 12-bit right-aligned data - DACC2DHR: u12 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DUAL DAC 12-bit left aligned data holding register - pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel1 12-bit left-aligned data - DACC1DHR: u12 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// DAC channel2 12-bit left-aligned data - DACC2DHR: u12 = 0, - }); - - /// DUAL DAC 8-bit right aligned data holding register - pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { - /// DAC channel1 8-bit right-aligned data - DACC1DHR: u8 = 0, - /// DAC channel2 8-bit right-aligned data - DACC2DHR: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel1 data output register - pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { - /// DAC channel1 data output - DACC1DOR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel2 data output register - pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { - /// DAC channel2 data output - DACC2DOR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000034, 32, packed struct { - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel1 DMA underrun flag - DMAUDR1: u1 = 0, - reserved28: u1 = 0, - reserved27: u1 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - /// DAC channel2 DMA underrun flag - DMAUDR2: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Debug support -pub const DBGMCU = extern struct { - pub const Address: u32 = 0xe0042000; - - /// MCU Device ID Code Register - pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { - /// Device Identifier - DEV_ID: u12 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Revision Identifier - REV_ID: u16 = 0, - }); - - /// Debug MCU Configuration Register - pub const CR = mmio(Address + 0x00000004, 32, packed struct { - /// Debug Sleep mode - DBG_SLEEP: u1 = 0, - /// Debug Stop Mode - DBG_STOP: u1 = 0, - /// Debug Standby Mode - DBG_STANDBY: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trace pin assignment control - TRACE_IOEN: u1 = 0, - /// Trace pin assignment control - TRACE_MODE: u2 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB Low Freeze Register - pub const APB1FZ = mmio(Address + 0x00000008, 32, packed struct { - /// Debug Timer 2 stopped when Core is halted - DBG_TIM2_STOP: u1 = 0, - /// Debug Timer 3 stopped when Core is halted - DBG_TIM3_STOP: u1 = 0, - /// Debug Timer 4 stopped when Core is halted - DBG_TIM4_STOP: u1 = 0, - /// Debug Timer 5 stopped when Core is halted - DBG_TIM5_STOP: u1 = 0, - /// Debug Timer 6 stopped when Core is halted - DBG_TIM6_STOP: u1 = 0, - /// Debug Timer 7 stopped when Core is halted - DBG_TIM7_STOP: u1 = 0, - /// Debug Timer 12 stopped when Core is halted - DBG_TIM12_STOP: u1 = 0, - /// Debug Timer 13 stopped when Core is halted - DBG_TIM13_STOP: u1 = 0, - /// Debug Timer 14 stopped when Core is halted - DBG_TIMER14_STOP: u1 = 0, - /// Debug Timer 18 stopped when Core is halted - DBG_TIM18_STOP: u1 = 0, - /// Debug RTC stopped when Core is halted - DBG_RTC_STOP: u1 = 0, - /// Debug Window Wachdog stopped when Core is halted - DBG_WWDG_STOP: u1 = 0, - /// Debug Independent Wachdog stopped when Core is halted - DBG_IWDG_STOP: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// SMBUS timeout mode stopped when Core is halted - I2C1_SMBUS_TIMEOUT: u1 = 0, - /// SMBUS timeout mode stopped when Core is halted - I2C2_SMBUS_TIMEOUT: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Debug CAN stopped when core is halted - DBG_CAN_STOP: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB High Freeze Register - pub const APB2FZ = mmio(Address + 0x0000000c, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Debug Timer 15 stopped when Core is halted - DBG_TIM15_STOP: u1 = 0, - /// Debug Timer 16 stopped when Core is halted - DBG_TIM16_STOP: u1 = 0, - /// Debug Timer 17 stopped when Core is halted - DBG_TIM17_STO: u1 = 0, - /// Debug Timer 19 stopped when Core is halted - DBG_TIM19_STOP: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Advanced timer -pub const TIM1 = extern struct { - pub const Address: u32 = 0x40012c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - /// Output Idle state 2 - OIS2N: u1 = 0, - /// Output Idle state 3 - OIS3: u1 = 0, - /// Output Idle state 3 - OIS3N: u1 = 0, - /// Output Idle state 4 - OIS4: u1 = 0, - reserved2: u1 = 0, - /// Output Idle state 5 - OIS5: u1 = 0, - reserved3: u1 = 0, - /// Output Idle state 6 - OIS6: u1 = 0, - reserved4: u1 = 0, - /// Master mode selection 2 - MMS2: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit 3 - SMS3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - /// Break 2 interrupt flag - B2IF: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 5 interrupt flag - C5IF: u1 = 0, - /// Capture/Compare 6 interrupt flag - C6IF: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - /// Break 2 generation - B2G: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - /// Output Compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - /// Output Compare 2 clear enable - OC2CE: u1 = 0, - /// Output Compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PCS: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PCS: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - OC4CE: u1 = 0, - /// Output Compare 3 mode bit 3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 4 mode bit 3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - /// Capture/Compare 2 complementary output enable - CC2NE: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - /// Capture/Compare 3 complementary output enable - CC3NE: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 4 output Polarity - CC4NP: u1 = 0, - /// Capture/Compare 5 output enable - CC5E: u1 = 0, - /// Capture/Compare 5 output Polarity - CC5P: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 6 output enable - CC6E: u1 = 0, - /// Capture/Compare 6 output Polarity - CC6P: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare 3 value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare 3 value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - /// Break 2 filter - BK2F: u4 = 0, - /// Break 2 enable - BK2E: u1 = 0, - /// Break 2 polarity - BK2P: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 3 (output mode) - pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 5 fast enable - OC5FE: u1 = 0, - /// Output compare 5 preload enable - OC5PE: u1 = 0, - /// Output compare 5 mode - OC5M: u3 = 0, - /// Output compare 5 clear enable - OC5CE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Output compare 6 fast enable - OC6FE: u1 = 0, - /// Output compare 6 preload enable - OC6PE: u1 = 0, - /// Output compare 6 mode - OC6M: u3 = 0, - /// Output compare 6 clear enable - OC6CE: u1 = 0, - /// Outout Compare 5 mode bit 3 - OC5M_3: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Outout Compare 6 mode bit 3 - OC6M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 5 - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Capture/Compare 5 value - CCR5: u16 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Group Channel 5 and Channel 1 - GC5C1: u1 = 0, - /// Group Channel 5 and Channel 2 - GC5C2: u1 = 0, - /// Group Channel 5 and Channel 3 - GC5C3: u1 = 0, - }); - - /// capture/compare register 6 - pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - /// Capture/Compare 6 value - CCR6: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// option registers - pub const OR = mmio(Address + 0x00000060, 32, packed struct { - /// TIM1_ETR_ADC1 remapping capability - TIM1_ETR_ADC1_RMP: u2 = 0, - /// TIM1_ETR_ADC4 remapping capability - TIM1_ETR_ADC4_RMP: u2 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Advanced timer -pub const TIM20 = extern struct { - pub const Address: u32 = 0x40015000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - /// Output Idle state 2 - OIS2N: u1 = 0, - /// Output Idle state 3 - OIS3: u1 = 0, - /// Output Idle state 3 - OIS3N: u1 = 0, - /// Output Idle state 4 - OIS4: u1 = 0, - reserved2: u1 = 0, - /// Output Idle state 5 - OIS5: u1 = 0, - reserved3: u1 = 0, - /// Output Idle state 6 - OIS6: u1 = 0, - reserved4: u1 = 0, - /// Master mode selection 2 - MMS2: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit 3 - SMS3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - /// Break 2 interrupt flag - B2IF: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 5 interrupt flag - C5IF: u1 = 0, - /// Capture/Compare 6 interrupt flag - C6IF: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - /// Break 2 generation - B2G: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - /// Output Compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - /// Output Compare 2 clear enable - OC2CE: u1 = 0, - /// Output Compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PCS: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PCS: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - OC4CE: u1 = 0, - /// Output Compare 3 mode bit 3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 4 mode bit 3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - /// Capture/Compare 2 complementary output enable - CC2NE: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - /// Capture/Compare 3 complementary output enable - CC3NE: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 4 output Polarity - CC4NP: u1 = 0, - /// Capture/Compare 5 output enable - CC5E: u1 = 0, - /// Capture/Compare 5 output Polarity - CC5P: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 6 output enable - CC6E: u1 = 0, - /// Capture/Compare 6 output Polarity - CC6P: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare 3 value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare 3 value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - /// Break 2 filter - BK2F: u4 = 0, - /// Break 2 enable - BK2E: u1 = 0, - /// Break 2 polarity - BK2P: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 3 (output mode) - pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 5 fast enable - OC5FE: u1 = 0, - /// Output compare 5 preload enable - OC5PE: u1 = 0, - /// Output compare 5 mode - OC5M: u3 = 0, - /// Output compare 5 clear enable - OC5CE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Output compare 6 fast enable - OC6FE: u1 = 0, - /// Output compare 6 preload enable - OC6PE: u1 = 0, - /// Output compare 6 mode - OC6M: u3 = 0, - /// Output compare 6 clear enable - OC6CE: u1 = 0, - /// Outout Compare 5 mode bit 3 - OC5M_3: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Outout Compare 6 mode bit 3 - OC6M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 5 - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Capture/Compare 5 value - CCR5: u16 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Group Channel 5 and Channel 1 - GC5C1: u1 = 0, - /// Group Channel 5 and Channel 2 - GC5C2: u1 = 0, - /// Group Channel 5 and Channel 3 - GC5C3: u1 = 0, - }); - - /// capture/compare register 6 - pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - /// Capture/Compare 6 value - CCR6: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// option registers - pub const OR = mmio(Address + 0x00000060, 32, packed struct { - /// TIM1_ETR_ADC1 remapping capability - TIM1_ETR_ADC1_RMP: u2 = 0, - /// TIM1_ETR_ADC4 remapping capability - TIM1_ETR_ADC4_RMP: u2 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Advanced-timers -pub const TIM8 = extern struct { - pub const Address: u32 = 0x40013400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - /// Output Idle state 2 - OIS2N: u1 = 0, - /// Output Idle state 3 - OIS3: u1 = 0, - /// Output Idle state 3 - OIS3N: u1 = 0, - /// Output Idle state 4 - OIS4: u1 = 0, - reserved2: u1 = 0, - /// Output Idle state 5 - OIS5: u1 = 0, - reserved3: u1 = 0, - /// Output Idle state 6 - OIS6: u1 = 0, - reserved4: u1 = 0, - /// Master mode selection 2 - MMS2: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit 3 - SMS3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - /// Break 2 interrupt flag - B2IF: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 5 interrupt flag - C5IF: u1 = 0, - /// Capture/Compare 6 interrupt flag - C6IF: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - /// Break 2 generation - B2G: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - /// Output Compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - /// Output Compare 2 clear enable - OC2CE: u1 = 0, - /// Output Compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PCS: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PCS: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - OC4CE: u1 = 0, - /// Output Compare 3 mode bit 3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 4 mode bit 3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - /// Capture/Compare 2 complementary output enable - CC2NE: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - /// Capture/Compare 3 complementary output enable - CC3NE: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 4 output Polarity - CC4NP: u1 = 0, - /// Capture/Compare 5 output enable - CC5E: u1 = 0, - /// Capture/Compare 5 output Polarity - CC5P: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 6 output enable - CC6E: u1 = 0, - /// Capture/Compare 6 output Polarity - CC6P: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare 3 value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare 3 value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - /// Break 2 filter - BK2F: u4 = 0, - /// Break 2 enable - BK2E: u1 = 0, - /// Break 2 polarity - BK2P: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 3 (output mode) - pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 5 fast enable - OC5FE: u1 = 0, - /// Output compare 5 preload enable - OC5PE: u1 = 0, - /// Output compare 5 mode - OC5M: u3 = 0, - /// Output compare 5 clear enable - OC5CE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Output compare 6 fast enable - OC6FE: u1 = 0, - /// Output compare 6 preload enable - OC6PE: u1 = 0, - /// Output compare 6 mode - OC6M: u3 = 0, - /// Output compare 6 clear enable - OC6CE: u1 = 0, - /// Outout Compare 5 mode bit 3 - OC5M_3: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Outout Compare 6 mode bit 3 - OC6M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 5 - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Capture/Compare 5 value - CCR5: u16 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Group Channel 5 and Channel 1 - GC5C1: u1 = 0, - /// Group Channel 5 and Channel 2 - GC5C2: u1 = 0, - /// Group Channel 5 and Channel 3 - GC5C3: u1 = 0, - }); - - /// capture/compare register 6 - pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - /// Capture/Compare 6 value - CCR6: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// option registers - pub const OR = mmio(Address + 0x00000060, 32, packed struct { - /// TIM8_ETR_ADC2 remapping capability - TIM8_ETR_ADC2_RMP: u2 = 0, - /// TIM8_ETR_ADC3 remapping capability - TIM8_ETR_ADC3_RMP: u2 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC1 = extern struct { - pub const Address: u32 = 0x50000000; - - /// interrupt and status register - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// configuration register - pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 1 - pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register - pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 3 - pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 4 - pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - reserved1: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular Data Register - pub const DR = mmio(Address + 0x00000040, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - padding1: u1 = 0, - }); - - /// offset register 1 - pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 2 - pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 3 - pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 4 - pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// injected data register 1 - pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 2 - pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 3 - pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 4 - pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 2 Configuration Register - pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 3 Configuration Register - pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Differential Mode Selection Register 2 - pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { - reserved1: u1 = 0, - /// Differential mode for channels 15 to 1 - DIFSEL_1_15: u15 = 0, - /// Differential mode for channels 18 to 16 - DIFSEL_16_18: u3 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Calibration Factors - pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC2 = extern struct { - pub const Address: u32 = 0x50000100; - - /// interrupt and status register - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// configuration register - pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 1 - pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register - pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 3 - pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 4 - pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - reserved1: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular Data Register - pub const DR = mmio(Address + 0x00000040, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - padding1: u1 = 0, - }); - - /// offset register 1 - pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 2 - pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 3 - pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 4 - pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// injected data register 1 - pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 2 - pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 3 - pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 4 - pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 2 Configuration Register - pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 3 Configuration Register - pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Differential Mode Selection Register 2 - pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { - reserved1: u1 = 0, - /// Differential mode for channels 15 to 1 - DIFSEL_1_15: u15 = 0, - /// Differential mode for channels 18 to 16 - DIFSEL_16_18: u3 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Calibration Factors - pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC3 = extern struct { - pub const Address: u32 = 0x50000400; - - /// interrupt and status register - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// configuration register - pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 1 - pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register - pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 3 - pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 4 - pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - reserved1: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular Data Register - pub const DR = mmio(Address + 0x00000040, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - padding1: u1 = 0, - }); - - /// offset register 1 - pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 2 - pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 3 - pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 4 - pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// injected data register 1 - pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 2 - pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 3 - pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 4 - pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 2 Configuration Register - pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 3 Configuration Register - pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Differential Mode Selection Register 2 - pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { - reserved1: u1 = 0, - /// Differential mode for channels 15 to 1 - DIFSEL_1_15: u15 = 0, - /// Differential mode for channels 18 to 16 - DIFSEL_16_18: u3 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Calibration Factors - pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC4 = extern struct { - pub const Address: u32 = 0x50000500; - - /// interrupt and status register - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// configuration register - pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 1 - pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register - pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 3 - pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 4 - pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - reserved1: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular Data Register - pub const DR = mmio(Address + 0x00000040, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - padding1: u1 = 0, - }); - - /// offset register 1 - pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 2 - pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 3 - pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 4 - pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// injected data register 1 - pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 2 - pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 3 - pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 4 - pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 2 Configuration Register - pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 3 Configuration Register - pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Differential Mode Selection Register 2 - pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { - reserved1: u1 = 0, - /// Differential mode for channels 15 to 1 - DIFSEL_1_15: u15 = 0, - /// Differential mode for channels 18 to 16 - DIFSEL_16_18: u3 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Calibration Factors - pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC1_2 = extern struct { - pub const Address: u32 = 0x50000300; - - /// ADC Common status register - pub const CSR = mmio(Address + 0x00000000, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// End of regular conversion of the slave ADC - EOC_SLV: u1 = 0, - /// End of regular sequence flag of the slave ADC - EOS_SLV: u1 = 0, - /// Overrun flag of the slave ADC - OVR_SLV: u1 = 0, - /// End of injected conversion flag of the slave ADC - JEOC_SLV: u1 = 0, - /// End of injected sequence flag of the slave ADC - JEOS_SLV: u1 = 0, - /// Analog watchdog 1 flag of the slave ADC - AWD1_SLV: u1 = 0, - /// Analog watchdog 2 flag of the slave ADC - AWD2_SLV: u1 = 0, - /// Analog watchdog 3 flag of the slave ADC - AWD3_SLV: u1 = 0, - /// Injected Context Queue Overflow flag of the slave ADC - JQOVF_SLV: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// ADC common control register - pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - /// Multi ADC mode selection - MULT: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Delay between 2 sampling phases - DELAY: u4 = 0, - reserved4: u1 = 0, - /// DMA configuration (for multi-ADC mode) - DMACFG: u1 = 0, - /// Direct memory access mode for multi ADC mode - MDMA: u2 = 0, - /// ADC clock mode - CKMODE: u2 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// VREFINT enable - VREFEN: u1 = 0, - /// Temperature sensor enable - TSEN: u1 = 0, - /// VBAT enable - VBATEN: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// ADC common regular data register for dual and triple modes - pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Regular data of the master ADC - RDATA_MST: u16 = 0, - /// Regular data of the slave ADC - RDATA_SLV: u16 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC3_4 = extern struct { - pub const Address: u32 = 0x50000700; - - /// ADC Common status register - pub const CSR = mmio(Address + 0x00000000, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// End of regular conversion of the slave ADC - EOC_SLV: u1 = 0, - /// End of regular sequence flag of the slave ADC - EOS_SLV: u1 = 0, - /// Overrun flag of the slave ADC - OVR_SLV: u1 = 0, - /// End of injected conversion flag of the slave ADC - JEOC_SLV: u1 = 0, - /// End of injected sequence flag of the slave ADC - JEOS_SLV: u1 = 0, - /// Analog watchdog 1 flag of the slave ADC - AWD1_SLV: u1 = 0, - /// Analog watchdog 2 flag of the slave ADC - AWD2_SLV: u1 = 0, - /// Analog watchdog 3 flag of the slave ADC - AWD3_SLV: u1 = 0, - /// Injected Context Queue Overflow flag of the slave ADC - JQOVF_SLV: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// ADC common control register - pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - /// Multi ADC mode selection - MULT: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Delay between 2 sampling phases - DELAY: u4 = 0, - reserved4: u1 = 0, - /// DMA configuration (for multi-ADC mode) - DMACFG: u1 = 0, - /// Direct memory access mode for multi ADC mode - MDMA: u2 = 0, - /// ADC clock mode - CKMODE: u2 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// VREFINT enable - VREFEN: u1 = 0, - /// Temperature sensor enable - TSEN: u1 = 0, - /// VBAT enable - VBATEN: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// ADC common regular data register for dual and triple modes - pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Regular data of the master ADC - RDATA_MST: u16 = 0, - /// Regular data of the slave ADC - RDATA_SLV: u16 = 0, - }); -}; - -/// System configuration controller _Comparator and Operational amplifier -pub const SYSCFG_COMP_OPAMP = extern struct { - pub const Address: u32 = 0x40010000; - - /// configuration register 1 - pub const SYSCFG_CFGR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Memory mapping selection bits - MEM_MODE: u2 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// USB interrupt remap - USB_IT_RMP: u1 = 0, - /// Timer 1 ITR3 selection - TIM1_ITR_RMP: u1 = 0, - /// DAC trigger remap (when TSEL = 001) - DAC_TRIG_RMP: u1 = 0, - /// ADC24 DMA remapping bit - ADC24_DMA_RMP: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// TIM16 DMA request remapping bit - TIM16_DMA_RMP: u1 = 0, - /// TIM17 DMA request remapping bit - TIM17_DMA_RMP: u1 = 0, - /// TIM6 and DAC1 DMA request remapping bit - TIM6_DAC1_DMA_RMP: u1 = 0, - /// TIM7 and DAC2 DMA request remapping bit - TIM7_DAC2_DMA_RMP: u1 = 0, - reserved6: u1 = 0, - /// Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB6_FM: u1 = 0, - /// Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB7_FM: u1 = 0, - /// Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB8_FM: u1 = 0, - /// Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB9_FM: u1 = 0, - /// I2C1 Fast Mode Plus - I2C1_FM: u1 = 0, - /// I2C2 Fast Mode Plus - I2C2_FM: u1 = 0, - /// Encoder mode - ENCODER_MODE: u2 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Interrupt enable bits from FPU - FPU_IT: u6 = 0, - }); - - /// CCM SRAM protection register - pub const SYSCFG_RCR = mmio(Address + 0x00000004, 32, packed struct { - /// CCM SRAM page write protection bit - PAGE0_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE1_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE2_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE3_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE4_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE5_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE6_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE7_WP: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// external interrupt configuration register 1 - pub const SYSCFG_EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { - /// EXTI 0 configuration bits - EXTI0: u4 = 0, - /// EXTI 1 configuration bits - EXTI1: u4 = 0, - /// EXTI 2 configuration bits - EXTI2: u4 = 0, - /// EXTI 3 configuration bits - EXTI3: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// external interrupt configuration register 2 - pub const SYSCFG_EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { - /// EXTI 4 configuration bits - EXTI4: u4 = 0, - /// EXTI 5 configuration bits - EXTI5: u4 = 0, - /// EXTI 6 configuration bits - EXTI6: u4 = 0, - /// EXTI 7 configuration bits - EXTI7: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// external interrupt configuration register 3 - pub const SYSCFG_EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { - /// EXTI 8 configuration bits - EXTI8: u4 = 0, - /// EXTI 9 configuration bits - EXTI9: u4 = 0, - /// EXTI 10 configuration bits - EXTI10: u4 = 0, - /// EXTI 11 configuration bits - EXTI11: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// external interrupt configuration register 4 - pub const SYSCFG_EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { - /// EXTI 12 configuration bits - EXTI12: u4 = 0, - /// EXTI 13 configuration bits - EXTI13: u4 = 0, - /// EXTI 14 configuration bits - EXTI14: u4 = 0, - /// EXTI 15 configuration bits - EXTI15: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// configuration register 2 - pub const SYSCFG_CFGR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Cortex-M0 LOCKUP bit enable bit - LOCUP_LOCK: u1 = 0, - /// SRAM parity lock bit - SRAM_PARITY_LOCK: u1 = 0, - /// PVD lock enable bit - PVD_LOCK: u1 = 0, - reserved1: u1 = 0, - /// Bypass address bit 29 in parity calculation - BYP_ADD_PAR: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// SRAM parity flag - SRAM_PEF: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control and status register - pub const COMP1_CSR = mmio(Address + 0x0000001c, 32, packed struct { - /// Comparator 1 enable - COMP1EN: u1 = 0, - /// Comparator 1 mode - COMP1MODE: u2 = 0, - /// Comparator 1 inverting input selection - COMP1INSEL: u3 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Comparator 1 output selection - COMP1_OUT_SEL: u4 = 0, - reserved4: u1 = 0, - /// Comparator 1 output polarity - COMP1POL: u1 = 0, - /// Comparator 1 hysteresis - COMP1HYST: u2 = 0, - /// Comparator 1 blanking source - COMP1_BLANKING: u3 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Comparator 1 output - COMP1OUT: u1 = 0, - /// Comparator 1 lock - COMP1LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP2_CSR = mmio(Address + 0x00000020, 32, packed struct { - /// Comparator 2 enable - COMP2EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 2 mode - COMP2MODE: u2 = 0, - /// Comparator 2 inverting input selection - COMP2INSEL: u3 = 0, - /// Comparator 2 non inverted input selection - COMP2INPSEL: u1 = 0, - reserved2: u1 = 0, - /// Comparator 1inverting input selection - COMP2INMSEL: u1 = 0, - /// Comparator 2 output selection - COMP2_OUT_SEL: u4 = 0, - reserved3: u1 = 0, - /// Comparator 2 output polarity - COMP2POL: u1 = 0, - /// Comparator 2 hysteresis - COMP2HYST: u2 = 0, - /// Comparator 2 blanking source - COMP2_BLANKING: u3 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Comparator 2 lock - COMP2LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP3_CSR = mmio(Address + 0x00000024, 32, packed struct { - /// Comparator 3 enable - COMP3EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 3 mode - COMP3MODE: u2 = 0, - /// Comparator 3 inverting input selection - COMP3INSEL: u3 = 0, - /// Comparator 3 non inverted input selection - COMP3INPSEL: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Comparator 3 output selection - COMP3_OUT_SEL: u4 = 0, - reserved4: u1 = 0, - /// Comparator 3 output polarity - COMP3POL: u1 = 0, - /// Comparator 3 hysteresis - COMP3HYST: u2 = 0, - /// Comparator 3 blanking source - COMP3_BLANKING: u3 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Comparator 3 output - COMP3OUT: u1 = 0, - /// Comparator 3 lock - COMP3LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP4_CSR = mmio(Address + 0x00000028, 32, packed struct { - /// Comparator 4 enable - COMP4EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 4 mode - COMP4MODE: u2 = 0, - /// Comparator 4 inverting input selection - COMP4INSEL: u3 = 0, - /// Comparator 4 non inverted input selection - COMP4INPSEL: u1 = 0, - reserved2: u1 = 0, - /// Comparator 4 window mode - COM4WINMODE: u1 = 0, - /// Comparator 4 output selection - COMP4_OUT_SEL: u4 = 0, - reserved3: u1 = 0, - /// Comparator 4 output polarity - COMP4POL: u1 = 0, - /// Comparator 4 hysteresis - COMP4HYST: u2 = 0, - /// Comparator 4 blanking source - COMP4_BLANKING: u3 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Comparator 4 output - COMP4OUT: u1 = 0, - /// Comparator 4 lock - COMP4LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP5_CSR = mmio(Address + 0x0000002c, 32, packed struct { - /// Comparator 5 enable - COMP5EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 5 mode - COMP5MODE: u2 = 0, - /// Comparator 5 inverting input selection - COMP5INSEL: u3 = 0, - /// Comparator 5 non inverted input selection - COMP5INPSEL: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Comparator 5 output selection - COMP5_OUT_SEL: u4 = 0, - reserved4: u1 = 0, - /// Comparator 5 output polarity - COMP5POL: u1 = 0, - /// Comparator 5 hysteresis - COMP5HYST: u2 = 0, - /// Comparator 5 blanking source - COMP5_BLANKING: u3 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Comparator51 output - COMP5OUT: u1 = 0, - /// Comparator 5 lock - COMP5LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP6_CSR = mmio(Address + 0x00000030, 32, packed struct { - /// Comparator 6 enable - COMP6EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 6 mode - COMP6MODE: u2 = 0, - /// Comparator 6 inverting input selection - COMP6INSEL: u3 = 0, - /// Comparator 6 non inverted input selection - COMP6INPSEL: u1 = 0, - reserved2: u1 = 0, - /// Comparator 6 window mode - COM6WINMODE: u1 = 0, - /// Comparator 6 output selection - COMP6_OUT_SEL: u4 = 0, - reserved3: u1 = 0, - /// Comparator 6 output polarity - COMP6POL: u1 = 0, - /// Comparator 6 hysteresis - COMP6HYST: u2 = 0, - /// Comparator 6 blanking source - COMP6_BLANKING: u3 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Comparator 6 output - COMP6OUT: u1 = 0, - /// Comparator 6 lock - COMP6LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP7_CSR = mmio(Address + 0x00000034, 32, packed struct { - /// Comparator 7 enable - COMP7EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 7 mode - COMP7MODE: u2 = 0, - /// Comparator 7 inverting input selection - COMP7INSEL: u3 = 0, - /// Comparator 7 non inverted input selection - COMP7INPSEL: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Comparator 7 output selection - COMP7_OUT_SEL: u4 = 0, - reserved4: u1 = 0, - /// Comparator 7 output polarity - COMP7POL: u1 = 0, - /// Comparator 7 hysteresis - COMP7HYST: u2 = 0, - /// Comparator 7 blanking source - COMP7_BLANKING: u3 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Comparator 7 output - COMP7OUT: u1 = 0, - /// Comparator 7 lock - COMP7LOCK: u1 = 0, - }); - - /// control register - pub const OPAMP1_CSR = mmio(Address + 0x00000038, 32, packed struct { - /// OPAMP1 enable - OPAMP1_EN: u1 = 0, - /// OPAMP1 Non inverting input selection - VP_SEL: u2 = 0, - reserved1: u1 = 0, - /// OPAMP1 inverting input selection - VM_SEL: u2 = 0, - /// Timer controlled Mux mode enable - TCM_EN: u1 = 0, - /// OPAMP1 inverting input secondary selection - VMS_SEL: u1 = 0, - /// OPAMP1 Non inverting input secondary selection - VPS_SEL: u2 = 0, - /// Calibration mode enable - CALON: u1 = 0, - /// Calibration selection - CALSEL: u2 = 0, - /// Gain in PGA mode - PGA_GAIN: u4 = 0, - /// User trimming enable - USER_TRIM: u1 = 0, - /// Offset trimming value (PMOS) - TRIMOFFSETP: u5 = 0, - /// Offset trimming value (NMOS) - TRIMOFFSETN: u5 = 0, - /// OPAMP 1 ouput status flag - OUTCAL: u1 = 0, - /// OPAMP 1 lock - LOCK: u1 = 0, - }); - - /// control register - pub const OPAMP2_CSR = mmio(Address + 0x0000003c, 32, packed struct { - /// OPAMP2 enable - OPAMP2EN: u1 = 0, - /// OPAMP2 Non inverting input selection - VP_SEL: u2 = 0, - reserved1: u1 = 0, - /// OPAMP2 inverting input selection - VM_SEL: u2 = 0, - /// Timer controlled Mux mode enable - TCM_EN: u1 = 0, - /// OPAMP2 inverting input secondary selection - VMS_SEL: u1 = 0, - /// OPAMP2 Non inverting input secondary selection - VPS_SEL: u2 = 0, - /// Calibration mode enable - CALON: u1 = 0, - /// Calibration selection - CAL_SEL: u2 = 0, - /// Gain in PGA mode - PGA_GAIN: u4 = 0, - /// User trimming enable - USER_TRIM: u1 = 0, - /// Offset trimming value (PMOS) - TRIMOFFSETP: u5 = 0, - /// Offset trimming value (NMOS) - TRIMOFFSETN: u5 = 0, - /// OPAMP 2 ouput status flag - OUTCAL: u1 = 0, - /// OPAMP 2 lock - LOCK: u1 = 0, - }); - - /// control register - pub const OPAMP3_CSR = mmio(Address + 0x00000040, 32, packed struct { - /// OPAMP3 enable - OPAMP3EN: u1 = 0, - /// OPAMP3 Non inverting input selection - VP_SEL: u2 = 0, - reserved1: u1 = 0, - /// OPAMP3 inverting input selection - VM_SEL: u2 = 0, - /// Timer controlled Mux mode enable - TCM_EN: u1 = 0, - /// OPAMP3 inverting input secondary selection - VMS_SEL: u1 = 0, - /// OPAMP3 Non inverting input secondary selection - VPS_SEL: u2 = 0, - /// Calibration mode enable - CALON: u1 = 0, - /// Calibration selection - CALSEL: u2 = 0, - /// Gain in PGA mode - PGA_GAIN: u4 = 0, - /// User trimming enable - USER_TRIM: u1 = 0, - /// Offset trimming value (PMOS) - TRIMOFFSETP: u5 = 0, - /// Offset trimming value (NMOS) - TRIMOFFSETN: u5 = 0, - /// OPAMP 3 ouput status flag - OUTCAL: u1 = 0, - /// OPAMP 3 lock - LOCK: u1 = 0, - }); - - /// control register - pub const OPAMP4_CSR = mmio(Address + 0x00000044, 32, packed struct { - /// OPAMP4 enable - OPAMP4EN: u1 = 0, - /// OPAMP4 Non inverting input selection - VP_SEL: u2 = 0, - reserved1: u1 = 0, - /// OPAMP4 inverting input selection - VM_SEL: u2 = 0, - /// Timer controlled Mux mode enable - TCM_EN: u1 = 0, - /// OPAMP4 inverting input secondary selection - VMS_SEL: u1 = 0, - /// OPAMP4 Non inverting input secondary selection - VPS_SEL: u2 = 0, - /// Calibration mode enable - CALON: u1 = 0, - /// Calibration selection - CALSEL: u2 = 0, - /// Gain in PGA mode - PGA_GAIN: u4 = 0, - /// User trimming enable - USER_TRIM: u1 = 0, - /// Offset trimming value (PMOS) - TRIMOFFSETP: u5 = 0, - /// Offset trimming value (NMOS) - TRIMOFFSETN: u5 = 0, - /// OPAMP 4 ouput status flag - OUTCAL: u1 = 0, - /// OPAMP 4 lock - LOCK: u1 = 0, - }); -}; - -/// Flexible memory controller -pub const FMC = extern struct { - pub const Address: u32 = 0xa0000400; - - /// SRAM/NOR-Flash chip-select control register 1 - pub const BCR1 = mmio(Address + 0x00000000, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 1 - pub const BTR1 = mmio(Address + 0x00000004, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 2 - pub const BCR2 = mmio(Address + 0x00000008, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 2 - pub const BTR2 = mmio(Address + 0x0000000c, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 3 - pub const BCR3 = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 3 - pub const BTR3 = mmio(Address + 0x00000014, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 4 - pub const BCR4 = mmio(Address + 0x00000018, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 4 - pub const BTR4 = mmio(Address + 0x0000001c, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PC Card/NAND Flash control register 2 - pub const PCR2 = mmio(Address + 0x00000060, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 2 - pub const SR2 = mmio(Address + 0x00000064, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 2 - pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct {}); - - /// Attribute memory space timing register 2 - pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct {}); - - /// ECC result register 2 - pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct {}); - - /// PC Card/NAND Flash control register 3 - pub const PCR3 = mmio(Address + 0x00000080, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 3 - pub const SR3 = mmio(Address + 0x00000084, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 3 - pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct {}); - - /// Attribute memory space timing register 3 - pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct {}); - - /// ECC result register 3 - pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct {}); - - /// PC Card/NAND Flash control register 4 - pub const PCR4 = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 4 - pub const SR4 = mmio(Address + 0x000000a4, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 4 - pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct {}); - - /// Attribute memory space timing register 4 - pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct {}); - - /// I/O space timing register 4 - pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct {}); - - /// SRAM/NOR-Flash write timing registers 1 - pub const BWTR1 = mmio(Address + 0x00000104, 32, packed struct { - /// Bus turnaround phase duration - BUSTURN: u4 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 2 - pub const BWTR2 = mmio(Address + 0x0000010c, 32, packed struct { - /// Bus turnaround phase duration - BUSTURN: u4 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 3 - pub const BWTR3 = mmio(Address + 0x00000114, 32, packed struct { - /// Bus turnaround phase duration - BUSTURN: u4 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 4 - pub const BWTR4 = mmio(Address + 0x0000011c, 32, packed struct { - /// Bus turnaround phase duration - BUSTURN: u4 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Nested Vectored Interrupt Controller -pub const NVIC = extern struct { - pub const Address: u32 = 0xe000e100; - - /// Interrupt Set-Enable Register - pub const ISER0 = mmio(Address + 0x00000000, 32, packed struct {}); - - /// Interrupt Set-Enable Register - pub const ISER1 = mmio(Address + 0x00000004, 32, packed struct {}); - - /// Interrupt Set-Enable Register - pub const ISER2 = mmio(Address + 0x00000008, 32, packed struct {}); - - /// Interrupt Clear-Enable Register - pub const ICER0 = mmio(Address + 0x00000080, 32, packed struct {}); - - /// Interrupt Clear-Enable Register - pub const ICER1 = mmio(Address + 0x00000084, 32, packed struct {}); - - /// Interrupt Clear-Enable Register - pub const ICER2 = mmio(Address + 0x00000088, 32, packed struct {}); - - /// Interrupt Set-Pending Register - pub const ISPR0 = mmio(Address + 0x00000100, 32, packed struct {}); - - /// Interrupt Set-Pending Register - pub const ISPR1 = mmio(Address + 0x00000104, 32, packed struct {}); - - /// Interrupt Set-Pending Register - pub const ISPR2 = mmio(Address + 0x00000108, 32, packed struct {}); - - /// Interrupt Clear-Pending Register - pub const ICPR0 = mmio(Address + 0x00000180, 32, packed struct {}); - - /// Interrupt Clear-Pending Register - pub const ICPR1 = mmio(Address + 0x00000184, 32, packed struct {}); - - /// Interrupt Clear-Pending Register - pub const ICPR2 = mmio(Address + 0x00000188, 32, packed struct {}); - - /// Interrupt Active Bit Register - pub const IABR0 = mmio(Address + 0x00000200, 32, packed struct {}); - - /// Interrupt Active Bit Register - pub const IABR1 = mmio(Address + 0x00000204, 32, packed struct {}); - - /// Interrupt Active Bit Register - pub const IABR2 = mmio(Address + 0x00000208, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR0 = mmio(Address + 0x00000300, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR1 = mmio(Address + 0x00000304, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR2 = mmio(Address + 0x00000308, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR3 = mmio(Address + 0x0000030c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR4 = mmio(Address + 0x00000310, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR5 = mmio(Address + 0x00000314, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR6 = mmio(Address + 0x00000318, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR7 = mmio(Address + 0x0000031c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR8 = mmio(Address + 0x00000320, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR9 = mmio(Address + 0x00000324, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR10 = mmio(Address + 0x00000328, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR11 = mmio(Address + 0x0000032c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR12 = mmio(Address + 0x00000330, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR13 = mmio(Address + 0x00000334, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR14 = mmio(Address + 0x00000338, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR15 = mmio(Address + 0x0000033c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR16 = mmio(Address + 0x00000340, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR17 = mmio(Address + 0x00000344, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR18 = mmio(Address + 0x00000348, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR19 = mmio(Address + 0x0000034c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR20 = mmio(Address + 0x00000350, 32, packed struct {}); -}; - -/// Floting point unit -pub const FPU = extern struct { - pub const Address: u32 = 0xe000ef34; - - /// Floating-point context control register - pub const FPCCR = mmio(Address + 0x00000000, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - }); - - /// Floating-point context address register - pub const FPCAR = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Location of unpopulated floating-point - ADDRESS: u29 = 0, - }); - - /// Floating-point status control register - pub const FPSCR = mmio(Address + 0x00000008, 32, packed struct { - /// Invalid operation cumulative exception bit - IOC: u1 = 0, - /// Division by zero cumulative exception bit. - DZC: u1 = 0, - /// Overflow cumulative exception bit - OFC: u1 = 0, - /// Underflow cumulative exception bit - UFC: u1 = 0, - /// Inexact cumulative exception bit - IXC: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Input denormal cumulative exception bit. - IDC: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Rounding Mode control field - RMode: u2 = 0, - /// Flush-to-zero mode control bit: - FZ: u1 = 0, - /// Default NaN mode control bit - DN: u1 = 0, - /// Alternative half-precision control bit - AHP: u1 = 0, - reserved17: u1 = 0, - /// Overflow condition code flag - V: u1 = 0, - /// Carry condition code flag - C: u1 = 0, - /// Zero condition code flag - Z: u1 = 0, - /// Negative condition code flag - N: u1 = 0, - }); -}; - -/// Memory protection unit -pub const MPU = extern struct { - pub const Address: u32 = 0xe000ed90; - - /// MPU type register - pub const MPU_TYPER = mmio(Address + 0x00000000, 32, packed struct { - /// Separate flag - SEPARATE: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Number of MPU data regions - DREGION: u8 = 0, - /// Number of MPU instruction regions - IREGION: u8 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// MPU control register - pub const MPU_CTRL = mmio(Address + 0x00000004, 32, packed struct { - /// Enables the MPU - ENABLE: u1 = 0, - /// Enables the operation of MPU during hard fault - HFNMIENA: u1 = 0, - /// Enable priviliged software access to default memory map - PRIVDEFENA: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// MPU region number register - pub const MPU_RNR = mmio(Address + 0x00000008, 32, packed struct { - /// MPU region - REGION: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// MPU region base address register - pub const MPU_RBAR = mmio(Address + 0x0000000c, 32, packed struct { - /// MPU region field - REGION: u4 = 0, - /// MPU region number valid - VALID: u1 = 0, - /// Region base address field - ADDR: u27 = 0, - }); - - /// MPU region attribute and size register - pub const MPU_RASR = mmio(Address + 0x00000010, 32, packed struct { - /// Region enable bit. - ENABLE: u1 = 0, - /// Size of the MPU protection region - SIZE: u5 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Subregion disable bits - SRD: u8 = 0, - /// memory attribute - B: u1 = 0, - /// memory attribute - C: u1 = 0, - /// Shareable memory attribute - S: u1 = 0, - /// memory attribute - TEX: u3 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Access permission - AP: u3 = 0, - reserved5: u1 = 0, - /// Instruction access disable bit - XN: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// SysTick timer -pub const STK = extern struct { - pub const Address: u32 = 0xe000e010; - - /// SysTick control and status register - pub const CTRL = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - ENABLE: u1 = 0, - /// SysTick exception request enable - TICKINT: u1 = 0, - /// Clock source selection - CLKSOURCE: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SysTick reload value register - pub const LOAD = mmio(Address + 0x00000004, 32, packed struct { - /// RELOAD value - RELOAD: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SysTick current value register - pub const VAL = mmio(Address + 0x00000008, 32, packed struct { - /// Current counter value - CURRENT: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SysTick calibration value register - pub const CALIB = mmio(Address + 0x0000000c, 32, packed struct { - /// Calibration value - TENMS: u24 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// SKEW flag: Indicates whether the TENMS value is exact - SKEW: u1 = 0, - /// NOREF flag. Reads as zero - NOREF: u1 = 0, - }); -}; - -/// System control block -pub const SCB = extern struct { - pub const Address: u32 = 0xe000ed00; - - /// CPUID base register - pub const CPUID = mmio(Address + 0x00000000, 32, packed struct { - /// Revision number - Revision: u4 = 0, - /// Part number of the processor - PartNo: u12 = 0, - /// Reads as 0xF - Constant: u4 = 0, - /// Variant number - Variant: u4 = 0, - /// Implementer code - Implementer: u8 = 0, - }); - - /// Interrupt control and state register - pub const ICSR = mmio(Address + 0x00000004, 32, packed struct { - /// Active vector - VECTACTIVE: u9 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Return to base level - RETTOBASE: u1 = 0, - /// Pending vector - VECTPENDING: u7 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Interrupt pending flag - ISRPENDING: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// SysTick exception clear-pending bit - PENDSTCLR: u1 = 0, - /// SysTick exception set-pending bit - PENDSTSET: u1 = 0, - /// PendSV clear-pending bit - PENDSVCLR: u1 = 0, - /// PendSV set-pending bit - PENDSVSET: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// NMI set-pending bit. - NMIPENDSET: u1 = 0, - }); - - /// Vector table offset register - pub const VTOR = mmio(Address + 0x00000008, 32, packed struct { - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Vector table base offset field - TBLOFF: u21 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Application interrupt and reset control register - pub const AIRCR = mmio(Address + 0x0000000c, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Register key - VECTKEYSTAT: u16 = 0, - }); - - /// System control register - pub const SCR = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - /// Send Event on Pending bit - SEVEONPEND: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration and control register - pub const CCR = mmio(Address + 0x00000014, 32, packed struct { - /// Configures how the processor enters Thread mode - NONBASETHRDENA: u1 = 0, - reserved1: u1 = 0, - /// UNALIGN_ TRP - UNALIGN__TRP: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// System handler priority registers - pub const SHPR1 = mmio(Address + 0x00000018, 32, packed struct { - /// Priority of system handler 4 - PRI_4: u8 = 0, - /// Priority of system handler 5 - PRI_5: u8 = 0, - /// Priority of system handler 6 - PRI_6: u8 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// System handler priority registers - pub const SHPR2 = mmio(Address + 0x0000001c, 32, packed struct { - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Priority of system handler 11 - PRI_11: u8 = 0, - }); - - /// System handler priority registers - pub const SHPR3 = mmio(Address + 0x00000020, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Priority of system handler 14 - PRI_14: u8 = 0, - /// Priority of system handler 15 - PRI_15: u8 = 0, - }); - - /// System handler control and state register - pub const SHCRS = mmio(Address + 0x00000024, 32, packed struct { - /// Memory management fault exception active bit - MEMFAULTACT: u1 = 0, - /// Bus fault exception active bit - BUSFAULTACT: u1 = 0, - reserved1: u1 = 0, - /// Usage fault exception active bit - USGFAULTACT: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// SVC call active bit - SVCALLACT: u1 = 0, - /// Debug monitor active bit - MONITORACT: u1 = 0, - reserved5: u1 = 0, - /// PendSV exception active bit - PENDSVACT: u1 = 0, - /// SysTick exception active bit - SYSTICKACT: u1 = 0, - /// Usage fault exception pending bit - USGFAULTPENDED: u1 = 0, - /// Memory management fault exception pending bit - MEMFAULTPENDED: u1 = 0, - /// Bus fault exception pending bit - BUSFAULTPENDED: u1 = 0, - /// SVC call pending bit - SVCALLPENDED: u1 = 0, - /// Memory management fault enable bit - MEMFAULTENA: u1 = 0, - /// Bus fault enable bit - BUSFAULTENA: u1 = 0, - /// Usage fault enable bit - USGFAULTENA: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configurable fault status register - pub const CFSR_UFSR_BFSR_MMFSR = mmio(Address + 0x00000028, 32, packed struct { - reserved1: u1 = 0, - /// Instruction access violation flag - IACCVIOL: u1 = 0, - reserved2: u1 = 0, - /// Memory manager fault on unstacking for a return from exception - MUNSTKERR: u1 = 0, - /// Memory manager fault on stacking for exception entry. - MSTKERR: u1 = 0, - reserved3: u1 = 0, - /// Memory Management Fault Address Register (MMAR) valid flag - MMARVALID: u1 = 0, - /// Instruction bus error - IBUSERR: u1 = 0, - /// Precise data bus error - PRECISERR: u1 = 0, - /// Imprecise data bus error - IMPRECISERR: u1 = 0, - /// Bus fault on unstacking for a return from exception - UNSTKERR: u1 = 0, - /// Bus fault on stacking for exception entry - STKERR: u1 = 0, - /// Bus fault on floating-point lazy state preservation - LSPERR: u1 = 0, - reserved4: u1 = 0, - /// Bus Fault Address Register (BFAR) valid flag - BFARVALID: u1 = 0, - /// Undefined instruction usage fault - UNDEFINSTR: u1 = 0, - /// Invalid state usage fault - INVSTATE: u1 = 0, - /// Invalid PC load usage fault - INVPC: u1 = 0, - /// No coprocessor usage fault. - NOCP: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Unaligned access usage fault - UNALIGNED: u1 = 0, - /// Divide by zero usage fault - DIVBYZERO: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Hard fault status register - pub const HFSR = mmio(Address + 0x0000002c, 32, packed struct { - reserved1: u1 = 0, - /// Vector table hard fault - VECTTBL: u1 = 0, - reserved29: u1 = 0, - reserved28: u1 = 0, - reserved27: u1 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Forced hard fault - FORCED: u1 = 0, - /// Reserved for Debug use - DEBUG_VT: u1 = 0, - }); - - /// Memory management fault address register - pub const MMFAR = @intToPtr(*volatile u32, Address + 0x00000034); - - /// Bus fault address register - pub const BFAR = @intToPtr(*volatile u32, Address + 0x00000038); - - /// Auxiliary fault status register - pub const AFSR = mmio(Address + 0x0000003c, 32, packed struct { - /// Implementation defined - IMPDEF: u32 = 0, - }); -}; - -/// Nested vectored interrupt controller -pub const NVIC_STIR = extern struct { - pub const Address: u32 = 0xe000ef00; - - /// Software trigger interrupt register - pub const STIR = mmio(Address + 0x00000000, 32, packed struct { - /// Software generated interrupt ID - INTID: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Floating point unit CPACR -pub const FPU_CPACR = extern struct { - pub const Address: u32 = 0xe000ed88; - - /// Coprocessor access control register - pub const CPACR = mmio(Address + 0x00000000, 32, packed struct { - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// System control block ACTLR -pub const SCB_ACTRL = extern struct { - pub const Address: u32 = 0xe000e008; - - /// Auxiliary control register - pub const ACTRL = mmio(Address + 0x00000000, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -const std = @import("std"); -const root = @import("root"); -const cpu = @import("cpu"); -const config = @import("microzig-config"); -const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { - return InterruptVector{ - .C = struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt: " ++ str); - } - }.unhandledInterrupt, - }; -} - -pub const VectorTable = extern struct { - initial_stack_pointer: u32 = config.end_of_stack, - Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, - NMI: InterruptVector = makeUnhandledHandler("NMI"), - HardFault: InterruptVector = makeUnhandledHandler("HardFault"), - MemManage: InterruptVector = makeUnhandledHandler("MemManage"), - BusFault: InterruptVector = makeUnhandledHandler("BusFault"), - UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), - - reserved: [4]u32 = .{ 0, 0, 0, 0 }, - SVCall: InterruptVector = makeUnhandledHandler("SVCall"), - DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), - reserved1: u32 = 0, - - PendSV: InterruptVector = makeUnhandledHandler("PendSV"), - SysTick: InterruptVector = makeUnhandledHandler("SysTick"), - +// this file is generated by regz +// +// device: STM32F303 +// cpu: CM4 + +pub const VectorTable = struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, /// Window Watchdog interrupt - WWDG: InterruptVector = makeUnhandledHandler("WWDG"), - /// PVD through EXTI line detection interrupt - PVD: InterruptVector = makeUnhandledHandler("PVD"), + WWDG: InterruptVector = unhandled, + /// PVD through EXTI line detection + /// interrupt + PVD: InterruptVector = unhandled, /// Tamper and TimeStamp interrupts - TAMP_STAMP: InterruptVector = makeUnhandledHandler("TAMP_STAMP"), - /// RTC Wakeup interrupt through the EXTI line - RTC_WKUP: InterruptVector = makeUnhandledHandler("RTC_WKUP"), + TAMP_STAMP: InterruptVector = unhandled, + /// RTC Wakeup interrupt through the EXTI + /// line + RTC_WKUP: InterruptVector = unhandled, /// Flash global interrupt - FLASH: InterruptVector = makeUnhandledHandler("FLASH"), + FLASH: InterruptVector = unhandled, /// RCC global interrupt - RCC: InterruptVector = makeUnhandledHandler("RCC"), + RCC: InterruptVector = unhandled, /// EXTI Line0 interrupt - EXTI0: InterruptVector = makeUnhandledHandler("EXTI0"), + EXTI0: InterruptVector = unhandled, /// EXTI Line3 interrupt - EXTI1: InterruptVector = makeUnhandledHandler("EXTI1"), - /// EXTI Line2 and Touch sensing interrupts - EXTI2_TSC: InterruptVector = makeUnhandledHandler("EXTI2_TSC"), + EXTI1: InterruptVector = unhandled, + /// EXTI Line2 and Touch sensing + /// interrupts + EXTI2_TSC: InterruptVector = unhandled, /// EXTI Line3 interrupt - EXTI3: InterruptVector = makeUnhandledHandler("EXTI3"), + EXTI3: InterruptVector = unhandled, /// EXTI Line4 interrupt - EXTI4: InterruptVector = makeUnhandledHandler("EXTI4"), + EXTI4: InterruptVector = unhandled, /// DMA1 channel 1 interrupt - DMA1_CH1: InterruptVector = makeUnhandledHandler("DMA1_CH1"), + DMA1_CH1: InterruptVector = unhandled, /// DMA1 channel 2 interrupt - DMA1_CH2: InterruptVector = makeUnhandledHandler("DMA1_CH2"), + DMA1_CH2: InterruptVector = unhandled, /// DMA1 channel 3 interrupt - DMA1_CH3: InterruptVector = makeUnhandledHandler("DMA1_CH3"), + DMA1_CH3: InterruptVector = unhandled, /// DMA1 channel 4 interrupt - DMA1_CH4: InterruptVector = makeUnhandledHandler("DMA1_CH4"), + DMA1_CH4: InterruptVector = unhandled, /// DMA1 channel 5 interrupt - DMA1_CH5: InterruptVector = makeUnhandledHandler("DMA1_CH5"), + DMA1_CH5: InterruptVector = unhandled, /// DMA1 channel 6 interrupt - DMA1_CH6: InterruptVector = makeUnhandledHandler("DMA1_CH6"), + DMA1_CH6: InterruptVector = unhandled, /// DMA1 channel 7interrupt - DMA1_CH7: InterruptVector = makeUnhandledHandler("DMA1_CH7"), + DMA1_CH7: InterruptVector = unhandled, /// ADC1 and ADC2 global interrupt - ADC1_2: InterruptVector = makeUnhandledHandler("ADC1_2"), - /// USB High Priority/CAN_TX interrupts - USB_HP_CAN_TX: InterruptVector = makeUnhandledHandler("USB_HP_CAN_TX"), - /// USB Low Priority/CAN_RX0 interrupts - USB_LP_CAN_RX0: InterruptVector = makeUnhandledHandler("USB_LP_CAN_RX0"), + ADC1_2: InterruptVector = unhandled, + /// USB High Priority/CAN_TX + /// interrupts + USB_HP_CAN_TX: InterruptVector = unhandled, + /// USB Low Priority/CAN_RX0 + /// interrupts + USB_LP_CAN_RX0: InterruptVector = unhandled, /// CAN_RX1 interrupt - CAN_RX1: InterruptVector = makeUnhandledHandler("CAN_RX1"), + CAN_RX1: InterruptVector = unhandled, /// CAN_SCE interrupt - CAN_SCE: InterruptVector = makeUnhandledHandler("CAN_SCE"), + CAN_SCE: InterruptVector = unhandled, /// EXTI Line5 to Line9 interrupts - EXTI9_5: InterruptVector = makeUnhandledHandler("EXTI9_5"), - /// TIM1 Break/TIM15 global interruts - TIM1_BRK_TIM15: InterruptVector = makeUnhandledHandler("TIM1_BRK_TIM15"), - /// TIM1 Update/TIM16 global interrupts - TIM1_UP_TIM16: InterruptVector = makeUnhandledHandler("TIM1_UP_TIM16"), - /// TIM1 trigger and commutation/TIM17 interrupts - TIM1_TRG_COM_TIM17: InterruptVector = makeUnhandledHandler("TIM1_TRG_COM_TIM17"), + EXTI9_5: InterruptVector = unhandled, + /// TIM1 Break/TIM15 global + /// interruts + TIM1_BRK_TIM15: InterruptVector = unhandled, + /// TIM1 Update/TIM16 global + /// interrupts + TIM1_UP_TIM16: InterruptVector = unhandled, + /// TIM1 trigger and commutation/TIM17 + /// interrupts + TIM1_TRG_COM_TIM17: InterruptVector = unhandled, /// TIM1 capture compare interrupt - TIM1_CC: InterruptVector = makeUnhandledHandler("TIM1_CC"), + TIM1_CC: InterruptVector = unhandled, /// TIM2 global interrupt - TIM2: InterruptVector = makeUnhandledHandler("TIM2"), + TIM2: InterruptVector = unhandled, /// TIM3 global interrupt - TIM3: InterruptVector = makeUnhandledHandler("TIM3"), + TIM3: InterruptVector = unhandled, /// TIM4 global interrupt - TIM4: InterruptVector = makeUnhandledHandler("TIM4"), - /// I2C1 event interrupt and EXTI Line23 interrupt - I2C1_EV_EXTI23: InterruptVector = makeUnhandledHandler("I2C1_EV_EXTI23"), + TIM4: InterruptVector = unhandled, + /// I2C1 event interrupt and EXTI Line23 + /// interrupt + I2C1_EV_EXTI23: InterruptVector = unhandled, /// I2C1 error interrupt - I2C1_ER: InterruptVector = makeUnhandledHandler("I2C1_ER"), - /// I2C2 event interrupt & EXTI Line24 interrupt - I2C2_EV_EXTI24: InterruptVector = makeUnhandledHandler("I2C2_EV_EXTI24"), + I2C1_ER: InterruptVector = unhandled, + /// I2C2 event interrupt & EXTI Line24 + /// interrupt + I2C2_EV_EXTI24: InterruptVector = unhandled, /// I2C2 error interrupt - I2C2_ER: InterruptVector = makeUnhandledHandler("I2C2_ER"), + I2C2_ER: InterruptVector = unhandled, /// SPI1 global interrupt - SPI1: InterruptVector = makeUnhandledHandler("SPI1"), + SPI1: InterruptVector = unhandled, /// SPI2 global interrupt - SPI2: InterruptVector = makeUnhandledHandler("SPI2"), - /// USART1 global interrupt and EXTI Line 25 interrupt - USART1_EXTI25: InterruptVector = makeUnhandledHandler("USART1_EXTI25"), - /// USART2 global interrupt and EXTI Line 26 interrupt - USART2_EXTI26: InterruptVector = makeUnhandledHandler("USART2_EXTI26"), - /// USART3 global interrupt and EXTI Line 28 interrupt - USART3_EXTI28: InterruptVector = makeUnhandledHandler("USART3_EXTI28"), + SPI2: InterruptVector = unhandled, + /// USART1 global interrupt and EXTI Line 25 + /// interrupt + USART1_EXTI25: InterruptVector = unhandled, + /// USART2 global interrupt and EXTI Line 26 + /// interrupt + USART2_EXTI26: InterruptVector = unhandled, + /// USART3 global interrupt and EXTI Line 28 + /// interrupt + USART3_EXTI28: InterruptVector = unhandled, /// EXTI Line15 to Line10 interrupts - EXTI15_10: InterruptVector = makeUnhandledHandler("EXTI15_10"), + EXTI15_10: InterruptVector = unhandled, /// RTC alarm interrupt - RTCAlarm: InterruptVector = makeUnhandledHandler("RTCAlarm"), + RTCAlarm: InterruptVector = unhandled, /// USB wakeup from Suspend - USB_WKUP: InterruptVector = makeUnhandledHandler("USB_WKUP"), + USB_WKUP: InterruptVector = unhandled, /// TIM8 break interrupt - TIM8_BRK: InterruptVector = makeUnhandledHandler("TIM8_BRK"), + TIM8_BRK: InterruptVector = unhandled, /// TIM8 update interrupt - TIM8_UP: InterruptVector = makeUnhandledHandler("TIM8_UP"), - /// TIM8 Trigger and commutation interrupts - TIM8_TRG_COM: InterruptVector = makeUnhandledHandler("TIM8_TRG_COM"), + TIM8_UP: InterruptVector = unhandled, + /// TIM8 Trigger and commutation + /// interrupts + TIM8_TRG_COM: InterruptVector = unhandled, /// TIM8 capture compare interrupt - TIM8_CC: InterruptVector = makeUnhandledHandler("TIM8_CC"), + TIM8_CC: InterruptVector = unhandled, /// ADC3 global interrupt - ADC3: InterruptVector = makeUnhandledHandler("ADC3"), + ADC3: InterruptVector = unhandled, /// FSMC global interrupt - FMC: InterruptVector = makeUnhandledHandler("FMC"), - reserved2: u32 = 0, - reserved3: u32 = 0, + FMC: InterruptVector = unhandled, + reserved2: u32 = undefined, + reserved3: u32 = undefined, /// SPI3 global interrupt - SPI3: InterruptVector = makeUnhandledHandler("SPI3"), - /// UART4 global and EXTI Line 34 interrupts - UART4_EXTI34: InterruptVector = makeUnhandledHandler("UART4_EXTI34"), - /// UART5 global and EXTI Line 35 interrupts - UART5_EXTI35: InterruptVector = makeUnhandledHandler("UART5_EXTI35"), - /// TIM6 global and DAC12 underrun interrupts - TIM6_DACUNDER: InterruptVector = makeUnhandledHandler("TIM6_DACUNDER"), + SPI3: InterruptVector = unhandled, + /// UART4 global and EXTI Line 34 + /// interrupts + UART4_EXTI34: InterruptVector = unhandled, + /// UART5 global and EXTI Line 35 + /// interrupts + UART5_EXTI35: InterruptVector = unhandled, + /// TIM6 global and DAC12 underrun + /// interrupts + TIM6_DACUNDER: InterruptVector = unhandled, /// TIM7 global interrupt - TIM7: InterruptVector = makeUnhandledHandler("TIM7"), + TIM7: InterruptVector = unhandled, /// DMA2 channel1 global interrupt - DMA2_CH1: InterruptVector = makeUnhandledHandler("DMA2_CH1"), + DMA2_CH1: InterruptVector = unhandled, /// DMA2 channel2 global interrupt - DMA2_CH2: InterruptVector = makeUnhandledHandler("DMA2_CH2"), + DMA2_CH2: InterruptVector = unhandled, /// DMA2 channel3 global interrupt - DMA2_CH3: InterruptVector = makeUnhandledHandler("DMA2_CH3"), + DMA2_CH3: InterruptVector = unhandled, /// DMA2 channel4 global interrupt - DMA2_CH4: InterruptVector = makeUnhandledHandler("DMA2_CH4"), + DMA2_CH4: InterruptVector = unhandled, /// DMA2 channel5 global interrupt - DMA2_CH5: InterruptVector = makeUnhandledHandler("DMA2_CH5"), + DMA2_CH5: InterruptVector = unhandled, /// ADC4 global interrupt - ADC4: InterruptVector = makeUnhandledHandler("ADC4"), - reserved4: u32 = 0, - reserved5: u32 = 0, - /// COMP1 & COMP2 & COMP3 interrupts combined with EXTI Lines 21, 22 and 29 + ADC4: InterruptVector = unhandled, + reserved4: u32 = undefined, + reserved5: u32 = undefined, + /// COMP1 & COMP2 & COMP3 interrupts + /// combined with EXTI Lines 21, 22 and 29 /// interrupts - COMP123: InterruptVector = makeUnhandledHandler("COMP123"), - /// COMP4 & COMP5 & COMP6 interrupts combined with EXTI Lines 30, 31 and 32 + COMP123: InterruptVector = unhandled, + /// COMP4 & COMP5 & COMP6 interrupts + /// combined with EXTI Lines 30, 31 and 32 /// interrupts - COMP456: InterruptVector = makeUnhandledHandler("COMP456"), - /// COMP7 interrupt combined with EXTI Line 33 interrupt - COMP7: InterruptVector = makeUnhandledHandler("COMP7"), - reserved6: u32 = 0, - reserved7: u32 = 0, - reserved8: u32 = 0, - reserved9: u32 = 0, - reserved10: u32 = 0, + COMP456: InterruptVector = unhandled, + /// COMP7 interrupt combined with EXTI Line 33 + /// interrupt + COMP7: InterruptVector = unhandled, + reserved6: u32 = undefined, + reserved7: u32 = undefined, + reserved8: u32 = undefined, + reserved9: u32 = undefined, + reserved10: u32 = undefined, /// I2C3 Event interrupt - I2C3_EV: InterruptVector = makeUnhandledHandler("I2C3_EV"), + I2C3_EV: InterruptVector = unhandled, /// I2C3 Error interrupt - I2C3_ER: InterruptVector = makeUnhandledHandler("I2C3_ER"), + I2C3_ER: InterruptVector = unhandled, /// USB High priority interrupt - USB_HP: InterruptVector = makeUnhandledHandler("USB_HP"), + USB_HP: InterruptVector = unhandled, /// USB Low priority interrupt - USB_LP: InterruptVector = makeUnhandledHandler("USB_LP"), - /// USB wakeup from Suspend and EXTI Line 18 - USB_WKUP_EXTI: InterruptVector = makeUnhandledHandler("USB_WKUP_EXTI"), + USB_LP: InterruptVector = unhandled, + /// USB wakeup from Suspend and EXTI Line + /// 18 + USB_WKUP_EXTI: InterruptVector = unhandled, /// TIM20 Break interrupt - TIM20_BRK: InterruptVector = makeUnhandledHandler("TIM20_BRK"), + TIM20_BRK: InterruptVector = unhandled, /// TIM20 Upgrade interrupt - TIM20_UP: InterruptVector = makeUnhandledHandler("TIM20_UP"), - /// TIM20 Trigger and Commutation interrupt - TIM20_TRG_COM: InterruptVector = makeUnhandledHandler("TIM20_TRG_COM"), + TIM20_UP: InterruptVector = unhandled, + /// TIM20 Trigger and Commutation + /// interrupt + TIM20_TRG_COM: InterruptVector = unhandled, /// TIM20 Capture Compare interrupt - TIM20_CC: InterruptVector = makeUnhandledHandler("TIM20_CC"), - /// Floating point unit interrupt; Floating point interrupt - FPU: InterruptVector = makeUnhandledHandler("FPU"), - reserved11: u32 = 0, - reserved12: u32 = 0, + TIM20_CC: InterruptVector = unhandled, + /// Floating point unit interrupt + FPU: InterruptVector = unhandled, + reserved11: u32 = undefined, + reserved12: u32 = undefined, /// SPI4 Global interrupt - SPI4: InterruptVector = makeUnhandledHandler("SPI4"), + SPI4: InterruptVector = unhandled, +}; + +pub const registers = struct { + /// General-purpose I/Os + pub const GPIOA = struct { + pub const base_address = 0x48000000; + + /// address: 0x48000000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48000004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48000008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800000c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48000010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48000014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48000018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800001c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48000020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48000024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48000028 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + /// General-purpose I/Os + pub const GPIOB = struct { + pub const base_address = 0x48000400; + + /// address: 0x48000400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48000404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48000408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800040c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48000410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48000414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48000418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800041c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48000420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48000424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48000428 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOC = struct { + pub const base_address = 0x48000800; + + /// address: 0x48000800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48000804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48000808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800080c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48000810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48000814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48000818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800081c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48000820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48000824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48000828 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOD = struct { + pub const base_address = 0x48000c00; + + /// address: 0x48000c00 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48000c04 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48000c08 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x48000c0c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48000c10 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48000c14 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48000c18 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x48000c1c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48000c20 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48000c24 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48000c28 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOE = struct { + pub const base_address = 0x48001000; + + /// address: 0x48001000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48001004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48001008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800100c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48001010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48001014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48001018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800101c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48001020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48001024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48001028 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOF = struct { + pub const base_address = 0x48001400; + + /// address: 0x48001400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48001404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48001408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800140c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48001410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48001414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48001418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800141c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48001420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48001424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48001428 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOG = struct { + pub const base_address = 0x48001800; + + /// address: 0x48001800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48001804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48001808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800180c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48001810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48001814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48001818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800181c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48001820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48001824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48001828 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOH = struct { + pub const base_address = 0x48001c00; + + /// address: 0x48001c00 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48001c04 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48001c08 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x48001c0c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48001c10 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48001c14 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48001c18 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x48001c1c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48001c20 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48001c24 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48001c28 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + /// Touch sensing controller + pub const TSC = struct { + pub const base_address = 0x40024000; + + /// address: 0x40024000 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Touch sensing controller + /// enable + TSCE: u1, + /// Start a new acquisition + START: u1, + /// Acquisition mode + AM: u1, + /// Synchronization pin + /// polarity + SYNCPOL: u1, + /// I/O Default mode + IODEF: u1, + /// Max count value + MCV: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// pulse generator prescaler + PGPSC: u3, + /// Spread spectrum prescaler + SSPSC: u1, + /// Spread spectrum enable + SSE: u1, + /// Spread spectrum deviation + SSD: u7, + /// Charge transfer pulse low + CTPL: u4, + /// Charge transfer pulse high + CTPH: u4, + }), base_address + 0x0); + + /// address: 0x40024004 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// End of acquisition interrupt + /// enable + EOAIE: u1, + /// Max count error interrupt + /// enable + MCEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40024008 + /// interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// End of acquisition interrupt + /// clear + EOAIC: u1, + /// Max count error interrupt + /// clear + MCEIC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x8); + + /// address: 0x4002400c + /// interrupt status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// End of acquisition flag + EOAF: u1, + /// Max count error flag + MCEF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40024010 + /// I/O hysteresis control + /// register + pub const IOHCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// G1_IO1 Schmitt trigger hysteresis + /// mode + G1_IO1: u1, + /// G1_IO2 Schmitt trigger hysteresis + /// mode + G1_IO2: u1, + /// G1_IO3 Schmitt trigger hysteresis + /// mode + G1_IO3: u1, + /// G1_IO4 Schmitt trigger hysteresis + /// mode + G1_IO4: u1, + /// G2_IO1 Schmitt trigger hysteresis + /// mode + G2_IO1: u1, + /// G2_IO2 Schmitt trigger hysteresis + /// mode + G2_IO2: u1, + /// G2_IO3 Schmitt trigger hysteresis + /// mode + G2_IO3: u1, + /// G2_IO4 Schmitt trigger hysteresis + /// mode + G2_IO4: u1, + /// G3_IO1 Schmitt trigger hysteresis + /// mode + G3_IO1: u1, + /// G3_IO2 Schmitt trigger hysteresis + /// mode + G3_IO2: u1, + /// G3_IO3 Schmitt trigger hysteresis + /// mode + G3_IO3: u1, + /// G3_IO4 Schmitt trigger hysteresis + /// mode + G3_IO4: u1, + /// G4_IO1 Schmitt trigger hysteresis + /// mode + G4_IO1: u1, + /// G4_IO2 Schmitt trigger hysteresis + /// mode + G4_IO2: u1, + /// G4_IO3 Schmitt trigger hysteresis + /// mode + G4_IO3: u1, + /// G4_IO4 Schmitt trigger hysteresis + /// mode + G4_IO4: u1, + /// G5_IO1 Schmitt trigger hysteresis + /// mode + G5_IO1: u1, + /// G5_IO2 Schmitt trigger hysteresis + /// mode + G5_IO2: u1, + /// G5_IO3 Schmitt trigger hysteresis + /// mode + G5_IO3: u1, + /// G5_IO4 Schmitt trigger hysteresis + /// mode + G5_IO4: u1, + /// G6_IO1 Schmitt trigger hysteresis + /// mode + G6_IO1: u1, + /// G6_IO2 Schmitt trigger hysteresis + /// mode + G6_IO2: u1, + /// G6_IO3 Schmitt trigger hysteresis + /// mode + G6_IO3: u1, + /// G6_IO4 Schmitt trigger hysteresis + /// mode + G6_IO4: u1, + /// G7_IO1 Schmitt trigger hysteresis + /// mode + G7_IO1: u1, + /// G7_IO2 Schmitt trigger hysteresis + /// mode + G7_IO2: u1, + /// G7_IO3 Schmitt trigger hysteresis + /// mode + G7_IO3: u1, + /// G7_IO4 Schmitt trigger hysteresis + /// mode + G7_IO4: u1, + /// G8_IO1 Schmitt trigger hysteresis + /// mode + G8_IO1: u1, + /// G8_IO2 Schmitt trigger hysteresis + /// mode + G8_IO2: u1, + /// G8_IO3 Schmitt trigger hysteresis + /// mode + G8_IO3: u1, + /// G8_IO4 Schmitt trigger hysteresis + /// mode + G8_IO4: u1, + }), base_address + 0x10); + + /// address: 0x40024018 + /// I/O analog switch control + /// register + pub const IOASCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// G1_IO1 analog switch + /// enable + G1_IO1: u1, + /// G1_IO2 analog switch + /// enable + G1_IO2: u1, + /// G1_IO3 analog switch + /// enable + G1_IO3: u1, + /// G1_IO4 analog switch + /// enable + G1_IO4: u1, + /// G2_IO1 analog switch + /// enable + G2_IO1: u1, + /// G2_IO2 analog switch + /// enable + G2_IO2: u1, + /// G2_IO3 analog switch + /// enable + G2_IO3: u1, + /// G2_IO4 analog switch + /// enable + G2_IO4: u1, + /// G3_IO1 analog switch + /// enable + G3_IO1: u1, + /// G3_IO2 analog switch + /// enable + G3_IO2: u1, + /// G3_IO3 analog switch + /// enable + G3_IO3: u1, + /// G3_IO4 analog switch + /// enable + G3_IO4: u1, + /// G4_IO1 analog switch + /// enable + G4_IO1: u1, + /// G4_IO2 analog switch + /// enable + G4_IO2: u1, + /// G4_IO3 analog switch + /// enable + G4_IO3: u1, + /// G4_IO4 analog switch + /// enable + G4_IO4: u1, + /// G5_IO1 analog switch + /// enable + G5_IO1: u1, + /// G5_IO2 analog switch + /// enable + G5_IO2: u1, + /// G5_IO3 analog switch + /// enable + G5_IO3: u1, + /// G5_IO4 analog switch + /// enable + G5_IO4: u1, + /// G6_IO1 analog switch + /// enable + G6_IO1: u1, + /// G6_IO2 analog switch + /// enable + G6_IO2: u1, + /// G6_IO3 analog switch + /// enable + G6_IO3: u1, + /// G6_IO4 analog switch + /// enable + G6_IO4: u1, + /// G7_IO1 analog switch + /// enable + G7_IO1: u1, + /// G7_IO2 analog switch + /// enable + G7_IO2: u1, + /// G7_IO3 analog switch + /// enable + G7_IO3: u1, + /// G7_IO4 analog switch + /// enable + G7_IO4: u1, + /// G8_IO1 analog switch + /// enable + G8_IO1: u1, + /// G8_IO2 analog switch + /// enable + G8_IO2: u1, + /// G8_IO3 analog switch + /// enable + G8_IO3: u1, + /// G8_IO4 analog switch + /// enable + G8_IO4: u1, + }), base_address + 0x18); + + /// address: 0x40024020 + /// I/O sampling control register + pub const IOSCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// G1_IO1 sampling mode + G1_IO1: u1, + /// G1_IO2 sampling mode + G1_IO2: u1, + /// G1_IO3 sampling mode + G1_IO3: u1, + /// G1_IO4 sampling mode + G1_IO4: u1, + /// G2_IO1 sampling mode + G2_IO1: u1, + /// G2_IO2 sampling mode + G2_IO2: u1, + /// G2_IO3 sampling mode + G2_IO3: u1, + /// G2_IO4 sampling mode + G2_IO4: u1, + /// G3_IO1 sampling mode + G3_IO1: u1, + /// G3_IO2 sampling mode + G3_IO2: u1, + /// G3_IO3 sampling mode + G3_IO3: u1, + /// G3_IO4 sampling mode + G3_IO4: u1, + /// G4_IO1 sampling mode + G4_IO1: u1, + /// G4_IO2 sampling mode + G4_IO2: u1, + /// G4_IO3 sampling mode + G4_IO3: u1, + /// G4_IO4 sampling mode + G4_IO4: u1, + /// G5_IO1 sampling mode + G5_IO1: u1, + /// G5_IO2 sampling mode + G5_IO2: u1, + /// G5_IO3 sampling mode + G5_IO3: u1, + /// G5_IO4 sampling mode + G5_IO4: u1, + /// G6_IO1 sampling mode + G6_IO1: u1, + /// G6_IO2 sampling mode + G6_IO2: u1, + /// G6_IO3 sampling mode + G6_IO3: u1, + /// G6_IO4 sampling mode + G6_IO4: u1, + /// G7_IO1 sampling mode + G7_IO1: u1, + /// G7_IO2 sampling mode + G7_IO2: u1, + /// G7_IO3 sampling mode + G7_IO3: u1, + /// G7_IO4 sampling mode + G7_IO4: u1, + /// G8_IO1 sampling mode + G8_IO1: u1, + /// G8_IO2 sampling mode + G8_IO2: u1, + /// G8_IO3 sampling mode + G8_IO3: u1, + /// G8_IO4 sampling mode + G8_IO4: u1, + }), base_address + 0x20); + + /// address: 0x40024028 + /// I/O channel control register + pub const IOCCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// G1_IO1 channel mode + G1_IO1: u1, + /// G1_IO2 channel mode + G1_IO2: u1, + /// G1_IO3 channel mode + G1_IO3: u1, + /// G1_IO4 channel mode + G1_IO4: u1, + /// G2_IO1 channel mode + G2_IO1: u1, + /// G2_IO2 channel mode + G2_IO2: u1, + /// G2_IO3 channel mode + G2_IO3: u1, + /// G2_IO4 channel mode + G2_IO4: u1, + /// G3_IO1 channel mode + G3_IO1: u1, + /// G3_IO2 channel mode + G3_IO2: u1, + /// G3_IO3 channel mode + G3_IO3: u1, + /// G3_IO4 channel mode + G3_IO4: u1, + /// G4_IO1 channel mode + G4_IO1: u1, + /// G4_IO2 channel mode + G4_IO2: u1, + /// G4_IO3 channel mode + G4_IO3: u1, + /// G4_IO4 channel mode + G4_IO4: u1, + /// G5_IO1 channel mode + G5_IO1: u1, + /// G5_IO2 channel mode + G5_IO2: u1, + /// G5_IO3 channel mode + G5_IO3: u1, + /// G5_IO4 channel mode + G5_IO4: u1, + /// G6_IO1 channel mode + G6_IO1: u1, + /// G6_IO2 channel mode + G6_IO2: u1, + /// G6_IO3 channel mode + G6_IO3: u1, + /// G6_IO4 channel mode + G6_IO4: u1, + /// G7_IO1 channel mode + G7_IO1: u1, + /// G7_IO2 channel mode + G7_IO2: u1, + /// G7_IO3 channel mode + G7_IO3: u1, + /// G7_IO4 channel mode + G7_IO4: u1, + /// G8_IO1 channel mode + G8_IO1: u1, + /// G8_IO2 channel mode + G8_IO2: u1, + /// G8_IO3 channel mode + G8_IO3: u1, + /// G8_IO4 channel mode + G8_IO4: u1, + }), base_address + 0x28); + + /// address: 0x40024030 + /// I/O group control status + /// register + pub const IOGCSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog I/O group x enable + G1E: u1, + /// Analog I/O group x enable + G2E: u1, + /// Analog I/O group x enable + G3E: u1, + /// Analog I/O group x enable + G4E: u1, + /// Analog I/O group x enable + G5E: u1, + /// Analog I/O group x enable + G6E: u1, + /// Analog I/O group x enable + G7E: u1, + /// Analog I/O group x enable + G8E: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Analog I/O group x status + G1S: u1, + /// Analog I/O group x status + G2S: u1, + /// Analog I/O group x status + G3S: u1, + /// Analog I/O group x status + G4S: u1, + /// Analog I/O group x status + G5S: u1, + /// Analog I/O group x status + G6S: u1, + /// Analog I/O group x status + G7S: u1, + /// Analog I/O group x status + G8S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x30); + + /// address: 0x40024034 + /// I/O group x counter register + pub const IOG1CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x34); + + /// address: 0x40024038 + /// I/O group x counter register + pub const IOG2CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x38); + + /// address: 0x4002403c + /// I/O group x counter register + pub const IOG3CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x3c); + + /// address: 0x40024040 + /// I/O group x counter register + pub const IOG4CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x40); + + /// address: 0x40024044 + /// I/O group x counter register + pub const IOG5CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x44); + + /// address: 0x40024048 + /// I/O group x counter register + pub const IOG6CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x48); + + /// address: 0x4002404c + /// I/O group x counter register + pub const IOG7CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x4c); + + /// address: 0x40024050 + /// I/O group x counter register + pub const IOG8CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x50); + }; + /// cyclic redundancy check calculation + /// unit + pub const CRC = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023000 + /// Data register + pub const DR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40023004 + /// Independent data register + pub const IDR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40023008 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// reset bit + RESET: u1, + reserved0: u1, + reserved1: u1, + /// Polynomial size + POLYSIZE: u2, + /// Reverse input data + REV_IN: u2, + /// Reverse output data + REV_OUT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x40023010 + /// Initial CRC value + pub const INIT = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40023014 + /// CRC polynomial + pub const POL = @intToPtr(*volatile u32, base_address + 0x14); + }; + /// Flash + pub const Flash = struct { + pub const base_address = 0x40022000; + + /// address: 0x40022000 + /// Flash access control register + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct{ + /// LATENCY + LATENCY: u3, + reserved0: u1, + /// PRFTBE + PRFTBE: u1, + /// PRFTBS + PRFTBS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40022004 + /// Flash key register + pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Flash Key + FKEYR: u32, + }), base_address + 0x4); + + /// address: 0x40022008 + /// Flash option key register + pub const OPTKEYR = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4002200c + /// Flash status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Busy + BSY: u1, + reserved0: u1, + /// Programming error + PGERR: u1, + reserved1: u1, + /// Write protection error + WRPRT: u1, + /// End of operation + EOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40022010 + /// Flash control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// Mass erase + MER: u1, + reserved0: u1, + /// Option byte programming + OPTPG: u1, + /// Option byte erase + OPTER: u1, + /// Start + STRT: u1, + /// Lock + LOCK: u1, + reserved1: u1, + /// Option bytes write enable + OPTWRE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved2: u1, + /// End of operation interrupt + /// enable + EOPIE: u1, + /// Force option byte loading + FORCE_OPTLOAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x10); + + /// address: 0x40022014 + /// Flash address register + pub const AR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Flash address + FAR: u32, + }), base_address + 0x14); + + /// address: 0x4002201c + /// Option byte register + pub const OBR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Option byte error + OPTERR: u1, + /// Level 1 protection status + LEVEL1_PROT: u1, + /// Level 2 protection status + LEVEL2_PROT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// WDG_SW + WDG_SW: u1, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + reserved5: u1, + /// BOOT1 + BOOT1: u1, + /// VDDA_MONITOR + VDDA_MONITOR: u1, + /// SRAM_PARITY_CHECK + SRAM_PARITY_CHECK: u1, + reserved6: u1, + /// Data0 + Data0: u8, + /// Data1 + Data1: u8, + }), base_address + 0x1c); + + /// address: 0x40022020 + /// Write protection register + pub const WRPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write protect + WRP: u32, + }), base_address + 0x20); + }; + /// Reset and clock control + pub const RCC = struct { + pub const base_address = 0x40021000; + + /// address: 0x40021000 + /// Clock control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Internal High Speed clock + /// enable + HSION: u1, + /// Internal High Speed clock ready + /// flag + HSIRDY: u1, + reserved0: u1, + /// Internal High Speed clock + /// trimming + HSITRIM: u5, + /// Internal High Speed clock + /// Calibration + HSICAL: u8, + /// External High Speed clock + /// enable + HSEON: u1, + /// External High Speed clock ready + /// flag + HSERDY: u1, + /// External High Speed clock + /// Bypass + HSEBYP: u1, + /// Clock Security System + /// enable + CSSON: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40021004 + /// Clock configuration register + /// (RCC_CFGR) + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// System clock Switch + SW: u2, + /// System Clock Switch Status + SWS: u2, + /// AHB prescaler + HPRE: u4, + /// APB Low speed prescaler + /// (APB1) + PPRE1: u3, + /// APB high speed prescaler + /// (APB2) + PPRE2: u3, + reserved0: u1, + /// PLL entry clock source + PLLSRC: u2, + /// HSE divider for PLL entry + PLLXTPRE: u1, + /// PLL Multiplication Factor + PLLMUL: u4, + /// USB prescaler + USBPRES: u1, + /// I2S external clock source + /// selection + I2SSRC: u1, + /// Microcontroller clock + /// output + MCO: u3, + reserved1: u1, + /// Microcontroller Clock Output + /// Flag + MCOF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x4); + + /// address: 0x40021008 + /// Clock interrupt register + /// (RCC_CIR) + pub const CIR = @intToPtr(*volatile Mmio(32, packed struct{ + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + reserved0: u1, + reserved1: u1, + /// Clock Security System Interrupt + /// flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + reserved5: u1, + reserved6: u1, + /// Clock security system interrupt + /// clear + CSSC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4002100c + /// APB2 peripheral reset register + /// (RCC_APB2RSTR) + pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SYSCFG and COMP reset + SYSCFGRST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + reserved10: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xc); + + /// address: 0x40021010 + /// APB1 peripheral reset register + /// (RCC_APB1RSTR) + pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 14 reset + TIM4RST: u1, + reserved0: u1, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Window watchdog reset + WWDGRST: u1, + reserved6: u1, + reserved7: u1, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved8: u1, + /// USART 2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// UART 4 reset + UART4RST: u1, + /// UART 5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved9: u1, + /// CAN reset + CANRST: u1, + reserved10: u1, + reserved11: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// I2C3 reset + I2C3RST: u1, + padding0: u1, + }), base_address + 0x10); + + /// address: 0x40021014 + /// AHB Peripheral Clock enable register + /// (RCC_AHBENR) + pub const AHBENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA1 clock enable + DMAEN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock + /// enable + SRAMEN: u1, + reserved0: u1, + /// FLITF clock enable + FLITFEN: u1, + /// FMC clock enable + FMCEN: u1, + /// CRC clock enable + CRCEN: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// IO port H clock enable + IOPHEN: u1, + /// I/O port A clock enable + IOPAEN: u1, + /// I/O port B clock enable + IOPBEN: u1, + /// I/O port C clock enable + IOPCEN: u1, + /// I/O port D clock enable + IOPDEN: u1, + /// I/O port E clock enable + IOPEEN: u1, + /// I/O port F clock enable + IOPFEN: u1, + /// I/O port G clock enable + IOPGEN: u1, + /// Touch sensing controller clock + /// enable + TSCEN: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// ADC1 and ADC2 clock enable + ADC12EN: u1, + /// ADC3 and ADC4 clock enable + ADC34EN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x40021018 + /// APB2 peripheral clock enable register + /// (RCC_APB2ENR) + pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + /// TIM8 Timer clock enable + TIM8EN: u1, + /// USART1 clock enable + USART1EN: u1, + reserved10: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x18); + + /// address: 0x4002101c + /// APB1 peripheral clock enable register + /// (RCC_APB1ENR) + pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + reserved0: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Window watchdog clock + /// enable + WWDGEN: u1, + reserved6: u1, + reserved7: u1, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved8: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// USART 4 clock enable + USART4EN: u1, + /// USART 5 clock enable + USART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved9: u1, + /// CAN clock enable + CANEN: u1, + /// DAC2 interface clock + /// enable + DAC2EN: u1, + reserved10: u1, + /// Power interface clock + /// enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// I2C3 clock enable + I2C3EN: u1, + padding0: u1, + }), base_address + 0x1c); + + /// address: 0x40021020 + /// Backup domain control register + /// (RCC_BDCR) + pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// External Low Speed oscillator + /// enable + LSEON: u1, + /// External Low Speed oscillator + /// ready + LSERDY: u1, + /// External Low Speed oscillator + /// bypass + LSEBYP: u1, + /// LSE oscillator drive + /// capability + LSEDRV: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// RTC clock source selection + RTCSEL: u2, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software + /// reset + BDRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x20); + + /// address: 0x40021024 + /// Control/status register + /// (RCC_CSR) + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Internal low speed oscillator + /// enable + LSION: u1, + /// Internal low speed oscillator + /// ready + LSIRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Remove reset flag + RMVF: u1, + /// Option byte loader reset + /// flag + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset + /// flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), base_address + 0x24); + + /// address: 0x40021028 + /// AHB peripheral reset register + pub const AHBRSTR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// FMC reset + FMCRST: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// I/O port H reset + IOPHRST: u1, + /// I/O port A reset + IOPARST: u1, + /// I/O port B reset + IOPBRST: u1, + /// I/O port C reset + IOPCRST: u1, + /// I/O port D reset + IOPDRST: u1, + /// I/O port E reset + IOPERST: u1, + /// I/O port F reset + IOPFRST: u1, + /// Touch sensing controller + /// reset + IOPGRST: u1, + /// Touch sensing controller + /// reset + TSCRST: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// ADC1 and ADC2 reset + ADC12RST: u1, + /// ADC3 and ADC4 reset + ADC34RST: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x28); + + /// address: 0x4002102c + /// Clock configuration register 2 + pub const CFGR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// PREDIV division factor + PREDIV: u4, + /// ADC1 and ADC2 prescaler + ADC12PRES: u5, + /// ADC3 and ADC4 prescaler + ADC34PRES: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x2c); + + /// address: 0x40021030 + /// Clock configuration register 3 + pub const CFGR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART1 clock source + /// selection + USART1SW: u2, + reserved0: u1, + reserved1: u1, + /// I2C1 clock source + /// selection + I2C1SW: u1, + /// I2C2 clock source + /// selection + I2C2SW: u1, + /// I2C3 clock source + /// selection + I2C3SW: u1, + reserved2: u1, + /// Timer1 clock source + /// selection + TIM1SW: u1, + /// Timer8 clock source + /// selection + TIM8SW: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// USART2 clock source + /// selection + USART2SW: u2, + /// USART3 clock source + /// selection + USART3SW: u2, + /// UART4 clock source + /// selection + UART4SW: u2, + /// UART5 clock source + /// selection + UART5SW: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x30); + }; + /// DMA controller 1 + pub const DMA1 = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020000 + /// DMA interrupt status register + /// (DMA_ISR) + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// flag + GIF1: u1, + /// Channel 1 Transfer Complete + /// flag + TCIF1: u1, + /// Channel 1 Half Transfer Complete + /// flag + HTIF1: u1, + /// Channel 1 Transfer Error + /// flag + TEIF1: u1, + /// Channel 2 Global interrupt + /// flag + GIF2: u1, + /// Channel 2 Transfer Complete + /// flag + TCIF2: u1, + /// Channel 2 Half Transfer Complete + /// flag + HTIF2: u1, + /// Channel 2 Transfer Error + /// flag + TEIF2: u1, + /// Channel 3 Global interrupt + /// flag + GIF3: u1, + /// Channel 3 Transfer Complete + /// flag + TCIF3: u1, + /// Channel 3 Half Transfer Complete + /// flag + HTIF3: u1, + /// Channel 3 Transfer Error + /// flag + TEIF3: u1, + /// Channel 4 Global interrupt + /// flag + GIF4: u1, + /// Channel 4 Transfer Complete + /// flag + TCIF4: u1, + /// Channel 4 Half Transfer Complete + /// flag + HTIF4: u1, + /// Channel 4 Transfer Error + /// flag + TEIF4: u1, + /// Channel 5 Global interrupt + /// flag + GIF5: u1, + /// Channel 5 Transfer Complete + /// flag + TCIF5: u1, + /// Channel 5 Half Transfer Complete + /// flag + HTIF5: u1, + /// Channel 5 Transfer Error + /// flag + TEIF5: u1, + /// Channel 6 Global interrupt + /// flag + GIF6: u1, + /// Channel 6 Transfer Complete + /// flag + TCIF6: u1, + /// Channel 6 Half Transfer Complete + /// flag + HTIF6: u1, + /// Channel 6 Transfer Error + /// flag + TEIF6: u1, + /// Channel 7 Global interrupt + /// flag + GIF7: u1, + /// Channel 7 Transfer Complete + /// flag + TCIF7: u1, + /// Channel 7 Half Transfer Complete + /// flag + HTIF7: u1, + /// Channel 7 Transfer Error + /// flag + TEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40020004 + /// DMA interrupt flag clear register + /// (DMA_IFCR) + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// clear + CGIF1: u1, + /// Channel 1 Transfer Complete + /// clear + CTCIF1: u1, + /// Channel 1 Half Transfer + /// clear + CHTIF1: u1, + /// Channel 1 Transfer Error + /// clear + CTEIF1: u1, + /// Channel 2 Global interrupt + /// clear + CGIF2: u1, + /// Channel 2 Transfer Complete + /// clear + CTCIF2: u1, + /// Channel 2 Half Transfer + /// clear + CHTIF2: u1, + /// Channel 2 Transfer Error + /// clear + CTEIF2: u1, + /// Channel 3 Global interrupt + /// clear + CGIF3: u1, + /// Channel 3 Transfer Complete + /// clear + CTCIF3: u1, + /// Channel 3 Half Transfer + /// clear + CHTIF3: u1, + /// Channel 3 Transfer Error + /// clear + CTEIF3: u1, + /// Channel 4 Global interrupt + /// clear + CGIF4: u1, + /// Channel 4 Transfer Complete + /// clear + CTCIF4: u1, + /// Channel 4 Half Transfer + /// clear + CHTIF4: u1, + /// Channel 4 Transfer Error + /// clear + CTEIF4: u1, + /// Channel 5 Global interrupt + /// clear + CGIF5: u1, + /// Channel 5 Transfer Complete + /// clear + CTCIF5: u1, + /// Channel 5 Half Transfer + /// clear + CHTIF5: u1, + /// Channel 5 Transfer Error + /// clear + CTEIF5: u1, + /// Channel 6 Global interrupt + /// clear + CGIF6: u1, + /// Channel 6 Transfer Complete + /// clear + CTCIF6: u1, + /// Channel 6 Half Transfer + /// clear + CHTIF6: u1, + /// Channel 6 Transfer Error + /// clear + CTEIF6: u1, + /// Channel 7 Global interrupt + /// clear + CGIF7: u1, + /// Channel 7 Transfer Complete + /// clear + CTCIF7: u1, + /// Channel 7 Half Transfer + /// clear + CHTIF7: u1, + /// Channel 7 Transfer Error + /// clear + CTEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40020008 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x8); + + /// address: 0x4002000c + /// DMA channel 1 number of data + /// register + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40020010 + /// DMA channel 1 peripheral address + /// register + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x10); + + /// address: 0x40020014 + /// DMA channel 1 memory address + /// register + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x14); + + /// address: 0x4002001c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40020020 + /// DMA channel 2 number of data + /// register + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40020024 + /// DMA channel 2 peripheral address + /// register + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x24); + + /// address: 0x40020028 + /// DMA channel 2 memory address + /// register + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x28); + + /// address: 0x40020030 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x30); + + /// address: 0x40020034 + /// DMA channel 3 number of data + /// register + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40020038 + /// DMA channel 3 peripheral address + /// register + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x38); + + /// address: 0x4002003c + /// DMA channel 3 memory address + /// register + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x3c); + + /// address: 0x40020044 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x44); + + /// address: 0x40020048 + /// DMA channel 4 number of data + /// register + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002004c + /// DMA channel 4 peripheral address + /// register + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x4c); + + /// address: 0x40020050 + /// DMA channel 4 memory address + /// register + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x50); + + /// address: 0x40020058 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x58); + + /// address: 0x4002005c + /// DMA channel 5 number of data + /// register + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40020060 + /// DMA channel 5 peripheral address + /// register + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40020064 + /// DMA channel 5 memory address + /// register + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x64); + + /// address: 0x4002006c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x6c); + + /// address: 0x40020070 + /// DMA channel 6 number of data + /// register + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x70); + + /// address: 0x40020074 + /// DMA channel 6 peripheral address + /// register + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x74); + + /// address: 0x40020078 + /// DMA channel 6 memory address + /// register + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x78); + + /// address: 0x40020080 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40020084 + /// DMA channel 7 number of data + /// register + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x40020088 + /// DMA channel 7 peripheral address + /// register + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x88); + + /// address: 0x4002008c + /// DMA channel 7 memory address + /// register + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x8c); + }; + pub const DMA2 = struct { + pub const base_address = 0x40020400; + + /// address: 0x40020400 + /// DMA interrupt status register + /// (DMA_ISR) + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// flag + GIF1: u1, + /// Channel 1 Transfer Complete + /// flag + TCIF1: u1, + /// Channel 1 Half Transfer Complete + /// flag + HTIF1: u1, + /// Channel 1 Transfer Error + /// flag + TEIF1: u1, + /// Channel 2 Global interrupt + /// flag + GIF2: u1, + /// Channel 2 Transfer Complete + /// flag + TCIF2: u1, + /// Channel 2 Half Transfer Complete + /// flag + HTIF2: u1, + /// Channel 2 Transfer Error + /// flag + TEIF2: u1, + /// Channel 3 Global interrupt + /// flag + GIF3: u1, + /// Channel 3 Transfer Complete + /// flag + TCIF3: u1, + /// Channel 3 Half Transfer Complete + /// flag + HTIF3: u1, + /// Channel 3 Transfer Error + /// flag + TEIF3: u1, + /// Channel 4 Global interrupt + /// flag + GIF4: u1, + /// Channel 4 Transfer Complete + /// flag + TCIF4: u1, + /// Channel 4 Half Transfer Complete + /// flag + HTIF4: u1, + /// Channel 4 Transfer Error + /// flag + TEIF4: u1, + /// Channel 5 Global interrupt + /// flag + GIF5: u1, + /// Channel 5 Transfer Complete + /// flag + TCIF5: u1, + /// Channel 5 Half Transfer Complete + /// flag + HTIF5: u1, + /// Channel 5 Transfer Error + /// flag + TEIF5: u1, + /// Channel 6 Global interrupt + /// flag + GIF6: u1, + /// Channel 6 Transfer Complete + /// flag + TCIF6: u1, + /// Channel 6 Half Transfer Complete + /// flag + HTIF6: u1, + /// Channel 6 Transfer Error + /// flag + TEIF6: u1, + /// Channel 7 Global interrupt + /// flag + GIF7: u1, + /// Channel 7 Transfer Complete + /// flag + TCIF7: u1, + /// Channel 7 Half Transfer Complete + /// flag + HTIF7: u1, + /// Channel 7 Transfer Error + /// flag + TEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40020404 + /// DMA interrupt flag clear register + /// (DMA_IFCR) + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// clear + CGIF1: u1, + /// Channel 1 Transfer Complete + /// clear + CTCIF1: u1, + /// Channel 1 Half Transfer + /// clear + CHTIF1: u1, + /// Channel 1 Transfer Error + /// clear + CTEIF1: u1, + /// Channel 2 Global interrupt + /// clear + CGIF2: u1, + /// Channel 2 Transfer Complete + /// clear + CTCIF2: u1, + /// Channel 2 Half Transfer + /// clear + CHTIF2: u1, + /// Channel 2 Transfer Error + /// clear + CTEIF2: u1, + /// Channel 3 Global interrupt + /// clear + CGIF3: u1, + /// Channel 3 Transfer Complete + /// clear + CTCIF3: u1, + /// Channel 3 Half Transfer + /// clear + CHTIF3: u1, + /// Channel 3 Transfer Error + /// clear + CTEIF3: u1, + /// Channel 4 Global interrupt + /// clear + CGIF4: u1, + /// Channel 4 Transfer Complete + /// clear + CTCIF4: u1, + /// Channel 4 Half Transfer + /// clear + CHTIF4: u1, + /// Channel 4 Transfer Error + /// clear + CTEIF4: u1, + /// Channel 5 Global interrupt + /// clear + CGIF5: u1, + /// Channel 5 Transfer Complete + /// clear + CTCIF5: u1, + /// Channel 5 Half Transfer + /// clear + CHTIF5: u1, + /// Channel 5 Transfer Error + /// clear + CTEIF5: u1, + /// Channel 6 Global interrupt + /// clear + CGIF6: u1, + /// Channel 6 Transfer Complete + /// clear + CTCIF6: u1, + /// Channel 6 Half Transfer + /// clear + CHTIF6: u1, + /// Channel 6 Transfer Error + /// clear + CTEIF6: u1, + /// Channel 7 Global interrupt + /// clear + CGIF7: u1, + /// Channel 7 Transfer Complete + /// clear + CTCIF7: u1, + /// Channel 7 Half Transfer + /// clear + CHTIF7: u1, + /// Channel 7 Transfer Error + /// clear + CTEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40020408 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x8); + + /// address: 0x4002040c + /// DMA channel 1 number of data + /// register + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40020410 + /// DMA channel 1 peripheral address + /// register + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x10); + + /// address: 0x40020414 + /// DMA channel 1 memory address + /// register + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x14); + + /// address: 0x4002041c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40020420 + /// DMA channel 2 number of data + /// register + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40020424 + /// DMA channel 2 peripheral address + /// register + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x24); + + /// address: 0x40020428 + /// DMA channel 2 memory address + /// register + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x28); + + /// address: 0x40020430 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x30); + + /// address: 0x40020434 + /// DMA channel 3 number of data + /// register + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40020438 + /// DMA channel 3 peripheral address + /// register + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x38); + + /// address: 0x4002043c + /// DMA channel 3 memory address + /// register + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x3c); + + /// address: 0x40020444 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x44); + + /// address: 0x40020448 + /// DMA channel 4 number of data + /// register + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002044c + /// DMA channel 4 peripheral address + /// register + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x4c); + + /// address: 0x40020450 + /// DMA channel 4 memory address + /// register + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x50); + + /// address: 0x40020458 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x58); + + /// address: 0x4002045c + /// DMA channel 5 number of data + /// register + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40020460 + /// DMA channel 5 peripheral address + /// register + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40020464 + /// DMA channel 5 memory address + /// register + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x64); + + /// address: 0x4002046c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x6c); + + /// address: 0x40020470 + /// DMA channel 6 number of data + /// register + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x70); + + /// address: 0x40020474 + /// DMA channel 6 peripheral address + /// register + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x74); + + /// address: 0x40020478 + /// DMA channel 6 memory address + /// register + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x78); + + /// address: 0x40020480 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40020484 + /// DMA channel 7 number of data + /// register + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x40020488 + /// DMA channel 7 peripheral address + /// register + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x88); + + /// address: 0x4002048c + /// DMA channel 7 memory address + /// register + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x8c); + }; + /// General purpose timer + pub const TIM2 = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40000004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit3 + SMS_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4000000c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + /// Output compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40000018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000001c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + /// Output compare 3 mode bit3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 4 mode bit3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x4000001c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000024 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low counter value + CNTL: u16, + /// High counter value + CNTH: u15, + /// if IUFREMAP=0 than CNT with read write + /// access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40000028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000002c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Auto-reload value + ARRL: u16, + /// High Auto-reload value + ARRH: u16, + }), base_address + 0x2c); + + /// address: 0x40000034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 1 + /// value + CCR1L: u16, + /// High Capture/Compare 1 value (on + /// TIM2) + CCR1H: u16, + }), base_address + 0x34); + + /// address: 0x40000038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 2 + /// value + CCR2L: u16, + /// High Capture/Compare 2 value (on + /// TIM2) + CCR2H: u16, + }), base_address + 0x38); + + /// address: 0x4000003c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR3L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR3H: u16, + }), base_address + 0x3c); + + /// address: 0x40000040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR4L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR4H: u16, + }), base_address + 0x40); + + /// address: 0x40000048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000004c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM3 = struct { + pub const base_address = 0x40000400; + + /// address: 0x40000400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40000404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit3 + SMS_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4000040c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + /// Output compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40000418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000041c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + /// Output compare 3 mode bit3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 4 mode bit3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x4000041c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000424 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low counter value + CNTL: u16, + /// High counter value + CNTH: u15, + /// if IUFREMAP=0 than CNT with read write + /// access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40000428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000042c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Auto-reload value + ARRL: u16, + /// High Auto-reload value + ARRH: u16, + }), base_address + 0x2c); + + /// address: 0x40000434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 1 + /// value + CCR1L: u16, + /// High Capture/Compare 1 value (on + /// TIM2) + CCR1H: u16, + }), base_address + 0x34); + + /// address: 0x40000438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 2 + /// value + CCR2L: u16, + /// High Capture/Compare 2 value (on + /// TIM2) + CCR2H: u16, + }), base_address + 0x38); + + /// address: 0x4000043c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR3L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR3H: u16, + }), base_address + 0x3c); + + /// address: 0x40000440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR4L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR4H: u16, + }), base_address + 0x40); + + /// address: 0x40000448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000044c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM4 = struct { + pub const base_address = 0x40000800; + + /// address: 0x40000800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40000804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit3 + SMS_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4000080c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + /// Output compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40000818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000081c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + /// Output compare 3 mode bit3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 4 mode bit3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x4000081c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000824 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low counter value + CNTL: u16, + /// High counter value + CNTH: u15, + /// if IUFREMAP=0 than CNT with read write + /// access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40000828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000082c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Auto-reload value + ARRL: u16, + /// High Auto-reload value + ARRH: u16, + }), base_address + 0x2c); + + /// address: 0x40000834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 1 + /// value + CCR1L: u16, + /// High Capture/Compare 1 value (on + /// TIM2) + CCR1H: u16, + }), base_address + 0x34); + + /// address: 0x40000838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 2 + /// value + CCR2L: u16, + /// High Capture/Compare 2 value (on + /// TIM2) + CCR2H: u16, + }), base_address + 0x38); + + /// address: 0x4000083c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR3L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR3H: u16, + }), base_address + 0x3c); + + /// address: 0x40000840 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR4L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR4H: u16, + }), base_address + 0x40); + + /// address: 0x40000848 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000084c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + /// General purpose timers + pub const TIM15 = struct { + pub const base_address = 0x40014000; + + /// address: 0x40014000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved3: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40014004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x40014008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Slave mode selection bit 3 + SMS_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4001400c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + reserved2: u1, + reserved3: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40014010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40014014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40014018 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + reserved1: u1, + /// Output Compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Output Compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40014018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40014020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved0: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40014024 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40014028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001402c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014030 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40014034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x40014044 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x44); + + /// address: 0x40014048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001404c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + /// General-purpose-timers + pub const TIM16 = struct { + pub const base_address = 0x40014400; + + /// address: 0x40014400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved3: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40014404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x4001440c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40014410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved3: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40014414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40014418 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Output Compare 1 mode + OC1M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + + /// address: 0x40014418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40014420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40014424 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF Copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40014428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001442c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014430 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40014434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014444 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x44); + + /// address: 0x40014448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001444c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40014450 + /// option register + pub const OR = @intToPtr(*volatile u32, base_address + 0x50); + }; + /// General purpose timer + pub const TIM17 = struct { + pub const base_address = 0x40014800; + + /// address: 0x40014800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved3: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40014804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x4001480c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40014810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved3: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40014814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40014818 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Output Compare 1 mode + OC1M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + + /// address: 0x40014818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40014820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40014824 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF Copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40014828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001482c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014830 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40014834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014844 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x44); + + /// address: 0x40014848 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001484c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + /// Universal synchronous asynchronous receiver + /// transmitter + pub const USART1 = struct { + pub const base_address = 0x40013800; + + /// address: 0x40013800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: u1, + /// Word length + M: u1, + /// Mute mode enable + MME: u1, + /// Character match interrupt + /// enable + CMIE: u1, + /// Oversampling mode + OVER8: u1, + /// Driver Enable deassertion + /// time + DEDT: u5, + /// Driver Enable assertion + /// time + DEAT: u5, + /// Receiver timeout interrupt + /// enable + RTOIE: u1, + /// End of Block interrupt + /// enable + EOBIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40013804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// 7-bit Address Detection/4-bit Address + /// Detection + ADDM7: u1, + /// LIN break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved4: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level + /// inversion + RXINV: u1, + /// TX pin active level + /// inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: u1, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: u2, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD0: u4, + /// Address of the USART node + ADD4: u4, + }), base_address + 0x4); + + /// address: 0x40013808 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception + /// Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity + /// selection + DEP: u1, + reserved0: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag + /// selection + WUS: u2, + /// Wakeup from Stop mode interrupt + /// enable + WUFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x4001380c + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40013810 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013814 + /// Receiver timeout register + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), base_address + 0x14); + + /// address: 0x40013818 + /// Request register + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Auto baud rate request + ABRRQ: u1, + /// Send break request + SBKRQ: u1, + /// Mute mode request + MMRQ: u1, + /// Receive data flush request + RXFRQ: u1, + /// Transmit data flush + /// request + TXFRQ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x18); + + /// address: 0x4001381c + /// Interrupt & status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved0: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute + /// mode + RWU: u1, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge + /// flag + TEACK: u1, + /// Receive enable acknowledge + /// flag + REACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x1c); + + /// address: 0x40013820 + /// Interrupt flag clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error clear flag + PECF: u1, + /// Framing error clear flag + FECF: u1, + /// Noise detected clear flag + NCF: u1, + /// Overrun error clear flag + ORECF: u1, + /// Idle line detected clear + /// flag + IDLECF: u1, + reserved0: u1, + /// Transmission complete clear + /// flag + TCCF: u1, + reserved1: u1, + /// LIN break detection clear + /// flag + LBDCF: u1, + /// CTS clear flag + CTSCF: u1, + reserved2: u1, + /// Receiver timeout clear + /// flag + RTOCF: u1, + /// End of timeout clear flag + EOBCF: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Character match clear flag + CMCF: u1, + reserved7: u1, + reserved8: u1, + /// Wakeup from Stop mode clear + /// flag + WUCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40013824 + /// Receive data register + pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); + + /// address: 0x40013828 + /// Transmit data register + pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); + }; + pub const USART2 = struct { + pub const base_address = 0x40004400; + + /// address: 0x40004400 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: u1, + /// Word length + M: u1, + /// Mute mode enable + MME: u1, + /// Character match interrupt + /// enable + CMIE: u1, + /// Oversampling mode + OVER8: u1, + /// Driver Enable deassertion + /// time + DEDT: u5, + /// Driver Enable assertion + /// time + DEAT: u5, + /// Receiver timeout interrupt + /// enable + RTOIE: u1, + /// End of Block interrupt + /// enable + EOBIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40004404 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// 7-bit Address Detection/4-bit Address + /// Detection + ADDM7: u1, + /// LIN break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved4: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level + /// inversion + RXINV: u1, + /// TX pin active level + /// inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: u1, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: u2, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD0: u4, + /// Address of the USART node + ADD4: u4, + }), base_address + 0x4); + + /// address: 0x40004408 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception + /// Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity + /// selection + DEP: u1, + reserved0: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag + /// selection + WUS: u2, + /// Wakeup from Stop mode interrupt + /// enable + WUFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x4000440c + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004410 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40004414 + /// Receiver timeout register + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), base_address + 0x14); + + /// address: 0x40004418 + /// Request register + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Auto baud rate request + ABRRQ: u1, + /// Send break request + SBKRQ: u1, + /// Mute mode request + MMRQ: u1, + /// Receive data flush request + RXFRQ: u1, + /// Transmit data flush + /// request + TXFRQ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x18); + + /// address: 0x4000441c + /// Interrupt & status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved0: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute + /// mode + RWU: u1, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge + /// flag + TEACK: u1, + /// Receive enable acknowledge + /// flag + REACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x1c); + + /// address: 0x40004420 + /// Interrupt flag clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error clear flag + PECF: u1, + /// Framing error clear flag + FECF: u1, + /// Noise detected clear flag + NCF: u1, + /// Overrun error clear flag + ORECF: u1, + /// Idle line detected clear + /// flag + IDLECF: u1, + reserved0: u1, + /// Transmission complete clear + /// flag + TCCF: u1, + reserved1: u1, + /// LIN break detection clear + /// flag + LBDCF: u1, + /// CTS clear flag + CTSCF: u1, + reserved2: u1, + /// Receiver timeout clear + /// flag + RTOCF: u1, + /// End of timeout clear flag + EOBCF: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Character match clear flag + CMCF: u1, + reserved7: u1, + reserved8: u1, + /// Wakeup from Stop mode clear + /// flag + WUCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40004424 + /// Receive data register + pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); + + /// address: 0x40004428 + /// Transmit data register + pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); + }; + pub const USART3 = struct { + pub const base_address = 0x40004800; + + /// address: 0x40004800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: u1, + /// Word length + M: u1, + /// Mute mode enable + MME: u1, + /// Character match interrupt + /// enable + CMIE: u1, + /// Oversampling mode + OVER8: u1, + /// Driver Enable deassertion + /// time + DEDT: u5, + /// Driver Enable assertion + /// time + DEAT: u5, + /// Receiver timeout interrupt + /// enable + RTOIE: u1, + /// End of Block interrupt + /// enable + EOBIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40004804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// 7-bit Address Detection/4-bit Address + /// Detection + ADDM7: u1, + /// LIN break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved4: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level + /// inversion + RXINV: u1, + /// TX pin active level + /// inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: u1, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: u2, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD0: u4, + /// Address of the USART node + ADD4: u4, + }), base_address + 0x4); + + /// address: 0x40004808 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception + /// Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity + /// selection + DEP: u1, + reserved0: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag + /// selection + WUS: u2, + /// Wakeup from Stop mode interrupt + /// enable + WUFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x4000480c + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004810 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40004814 + /// Receiver timeout register + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), base_address + 0x14); + + /// address: 0x40004818 + /// Request register + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Auto baud rate request + ABRRQ: u1, + /// Send break request + SBKRQ: u1, + /// Mute mode request + MMRQ: u1, + /// Receive data flush request + RXFRQ: u1, + /// Transmit data flush + /// request + TXFRQ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x18); + + /// address: 0x4000481c + /// Interrupt & status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved0: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute + /// mode + RWU: u1, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge + /// flag + TEACK: u1, + /// Receive enable acknowledge + /// flag + REACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x1c); + + /// address: 0x40004820 + /// Interrupt flag clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error clear flag + PECF: u1, + /// Framing error clear flag + FECF: u1, + /// Noise detected clear flag + NCF: u1, + /// Overrun error clear flag + ORECF: u1, + /// Idle line detected clear + /// flag + IDLECF: u1, + reserved0: u1, + /// Transmission complete clear + /// flag + TCCF: u1, + reserved1: u1, + /// LIN break detection clear + /// flag + LBDCF: u1, + /// CTS clear flag + CTSCF: u1, + reserved2: u1, + /// Receiver timeout clear + /// flag + RTOCF: u1, + /// End of timeout clear flag + EOBCF: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Character match clear flag + CMCF: u1, + reserved7: u1, + reserved8: u1, + /// Wakeup from Stop mode clear + /// flag + WUCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40004824 + /// Receive data register + pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); + + /// address: 0x40004828 + /// Transmit data register + pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); + }; + pub const UART4 = struct { + pub const base_address = 0x40004c00; + + /// address: 0x40004c00 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: u1, + /// Word length + M: u1, + /// Mute mode enable + MME: u1, + /// Character match interrupt + /// enable + CMIE: u1, + /// Oversampling mode + OVER8: u1, + /// Driver Enable deassertion + /// time + DEDT: u5, + /// Driver Enable assertion + /// time + DEAT: u5, + /// Receiver timeout interrupt + /// enable + RTOIE: u1, + /// End of Block interrupt + /// enable + EOBIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40004c04 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// 7-bit Address Detection/4-bit Address + /// Detection + ADDM7: u1, + /// LIN break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved4: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level + /// inversion + RXINV: u1, + /// TX pin active level + /// inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: u1, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: u2, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD0: u4, + /// Address of the USART node + ADD4: u4, + }), base_address + 0x4); + + /// address: 0x40004c08 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception + /// Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity + /// selection + DEP: u1, + reserved0: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag + /// selection + WUS: u2, + /// Wakeup from Stop mode interrupt + /// enable + WUFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x40004c0c + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004c10 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40004c14 + /// Receiver timeout register + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), base_address + 0x14); + + /// address: 0x40004c18 + /// Request register + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Auto baud rate request + ABRRQ: u1, + /// Send break request + SBKRQ: u1, + /// Mute mode request + MMRQ: u1, + /// Receive data flush request + RXFRQ: u1, + /// Transmit data flush + /// request + TXFRQ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x18); + + /// address: 0x40004c1c + /// Interrupt & status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved0: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute + /// mode + RWU: u1, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge + /// flag + TEACK: u1, + /// Receive enable acknowledge + /// flag + REACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x1c); + + /// address: 0x40004c20 + /// Interrupt flag clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error clear flag + PECF: u1, + /// Framing error clear flag + FECF: u1, + /// Noise detected clear flag + NCF: u1, + /// Overrun error clear flag + ORECF: u1, + /// Idle line detected clear + /// flag + IDLECF: u1, + reserved0: u1, + /// Transmission complete clear + /// flag + TCCF: u1, + reserved1: u1, + /// LIN break detection clear + /// flag + LBDCF: u1, + /// CTS clear flag + CTSCF: u1, + reserved2: u1, + /// Receiver timeout clear + /// flag + RTOCF: u1, + /// End of timeout clear flag + EOBCF: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Character match clear flag + CMCF: u1, + reserved7: u1, + reserved8: u1, + /// Wakeup from Stop mode clear + /// flag + WUCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40004c24 + /// Receive data register + pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); + + /// address: 0x40004c28 + /// Transmit data register + pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); + }; + pub const UART5 = struct { + pub const base_address = 0x40005000; + + /// address: 0x40005000 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: u1, + /// Word length + M: u1, + /// Mute mode enable + MME: u1, + /// Character match interrupt + /// enable + CMIE: u1, + /// Oversampling mode + OVER8: u1, + /// Driver Enable deassertion + /// time + DEDT: u5, + /// Driver Enable assertion + /// time + DEAT: u5, + /// Receiver timeout interrupt + /// enable + RTOIE: u1, + /// End of Block interrupt + /// enable + EOBIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// 7-bit Address Detection/4-bit Address + /// Detection + ADDM7: u1, + /// LIN break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved4: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level + /// inversion + RXINV: u1, + /// TX pin active level + /// inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: u1, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: u2, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD0: u4, + /// Address of the USART node + ADD4: u4, + }), base_address + 0x4); + + /// address: 0x40005008 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception + /// Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity + /// selection + DEP: u1, + reserved0: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag + /// selection + WUS: u2, + /// Wakeup from Stop mode interrupt + /// enable + WUFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x4000500c + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005010 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40005014 + /// Receiver timeout register + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), base_address + 0x14); + + /// address: 0x40005018 + /// Request register + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Auto baud rate request + ABRRQ: u1, + /// Send break request + SBKRQ: u1, + /// Mute mode request + MMRQ: u1, + /// Receive data flush request + RXFRQ: u1, + /// Transmit data flush + /// request + TXFRQ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x18); + + /// address: 0x4000501c + /// Interrupt & status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved0: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute + /// mode + RWU: u1, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge + /// flag + TEACK: u1, + /// Receive enable acknowledge + /// flag + REACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x1c); + + /// address: 0x40005020 + /// Interrupt flag clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error clear flag + PECF: u1, + /// Framing error clear flag + FECF: u1, + /// Noise detected clear flag + NCF: u1, + /// Overrun error clear flag + ORECF: u1, + /// Idle line detected clear + /// flag + IDLECF: u1, + reserved0: u1, + /// Transmission complete clear + /// flag + TCCF: u1, + reserved1: u1, + /// LIN break detection clear + /// flag + LBDCF: u1, + /// CTS clear flag + CTSCF: u1, + reserved2: u1, + /// Receiver timeout clear + /// flag + RTOCF: u1, + /// End of timeout clear flag + EOBCF: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Character match clear flag + CMCF: u1, + reserved7: u1, + reserved8: u1, + /// Wakeup from Stop mode clear + /// flag + WUCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40005024 + /// Receive data register + pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); + + /// address: 0x40005028 + /// Transmit data register + pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); + }; + /// Serial peripheral interface/Inter-IC + /// sound + pub const SPI1 = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40013008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x4001300c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001301c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI2 = struct { + pub const base_address = 0x40003800; + + /// address: 0x40003800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40003808 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x4000380c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003810 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003818 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000381c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003820 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI3 = struct { + pub const base_address = 0x40003c00; + + /// address: 0x40003c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40003c08 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x40003c0c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003c10 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003c14 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003c18 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40003c1c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003c20 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const I2S2ext = struct { + pub const base_address = 0x40003400; + + /// address: 0x40003400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40003408 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x4000340c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003410 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003414 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003418 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000341c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003420 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const I2S3ext = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40004004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40004008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x4000400c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40004010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40004014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40004018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000401c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40004020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI4 = struct { + pub const base_address = 0x40013c00; + + /// address: 0x40013c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40013c08 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x40013c0c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013c10 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013c14 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013c18 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40013c1c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013c20 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + /// External interrupt/event + /// controller + pub const EXTI = struct { + pub const base_address = 0x40010400; + + /// address: 0x40010400 + /// Interrupt mask register + pub const IMR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interrupt Mask on line 0 + MR0: u1, + /// Interrupt Mask on line 1 + MR1: u1, + /// Interrupt Mask on line 2 + MR2: u1, + /// Interrupt Mask on line 3 + MR3: u1, + /// Interrupt Mask on line 4 + MR4: u1, + /// Interrupt Mask on line 5 + MR5: u1, + /// Interrupt Mask on line 6 + MR6: u1, + /// Interrupt Mask on line 7 + MR7: u1, + /// Interrupt Mask on line 8 + MR8: u1, + /// Interrupt Mask on line 9 + MR9: u1, + /// Interrupt Mask on line 10 + MR10: u1, + /// Interrupt Mask on line 11 + MR11: u1, + /// Interrupt Mask on line 12 + MR12: u1, + /// Interrupt Mask on line 13 + MR13: u1, + /// Interrupt Mask on line 14 + MR14: u1, + /// Interrupt Mask on line 15 + MR15: u1, + /// Interrupt Mask on line 16 + MR16: u1, + /// Interrupt Mask on line 17 + MR17: u1, + /// Interrupt Mask on line 18 + MR18: u1, + /// Interrupt Mask on line 19 + MR19: u1, + /// Interrupt Mask on line 20 + MR20: u1, + /// Interrupt Mask on line 21 + MR21: u1, + /// Interrupt Mask on line 22 + MR22: u1, + /// Interrupt Mask on line 23 + MR23: u1, + /// Interrupt Mask on line 24 + MR24: u1, + /// Interrupt Mask on line 25 + MR25: u1, + /// Interrupt Mask on line 26 + MR26: u1, + /// Interrupt Mask on line 27 + MR27: u1, + /// Interrupt Mask on line 28 + MR28: u1, + /// Interrupt Mask on line 29 + MR29: u1, + /// Interrupt Mask on line 30 + MR30: u1, + /// Interrupt Mask on line 31 + MR31: u1, + }), base_address + 0x0); + + /// address: 0x40010404 + /// Event mask register + pub const EMR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Event Mask on line 0 + MR0: u1, + /// Event Mask on line 1 + MR1: u1, + /// Event Mask on line 2 + MR2: u1, + /// Event Mask on line 3 + MR3: u1, + /// Event Mask on line 4 + MR4: u1, + /// Event Mask on line 5 + MR5: u1, + /// Event Mask on line 6 + MR6: u1, + /// Event Mask on line 7 + MR7: u1, + /// Event Mask on line 8 + MR8: u1, + /// Event Mask on line 9 + MR9: u1, + /// Event Mask on line 10 + MR10: u1, + /// Event Mask on line 11 + MR11: u1, + /// Event Mask on line 12 + MR12: u1, + /// Event Mask on line 13 + MR13: u1, + /// Event Mask on line 14 + MR14: u1, + /// Event Mask on line 15 + MR15: u1, + /// Event Mask on line 16 + MR16: u1, + /// Event Mask on line 17 + MR17: u1, + /// Event Mask on line 18 + MR18: u1, + /// Event Mask on line 19 + MR19: u1, + /// Event Mask on line 20 + MR20: u1, + /// Event Mask on line 21 + MR21: u1, + /// Event Mask on line 22 + MR22: u1, + /// Event Mask on line 23 + MR23: u1, + /// Event Mask on line 24 + MR24: u1, + /// Event Mask on line 25 + MR25: u1, + /// Event Mask on line 26 + MR26: u1, + /// Event Mask on line 27 + MR27: u1, + /// Event Mask on line 28 + MR28: u1, + /// Event Mask on line 29 + MR29: u1, + /// Event Mask on line 30 + MR30: u1, + /// Event Mask on line 31 + MR31: u1, + }), base_address + 0x4); + + /// address: 0x40010408 + /// Rising Trigger selection + /// register + pub const RTSR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rising trigger event configuration of + /// line 0 + TR0: u1, + /// Rising trigger event configuration of + /// line 1 + TR1: u1, + /// Rising trigger event configuration of + /// line 2 + TR2: u1, + /// Rising trigger event configuration of + /// line 3 + TR3: u1, + /// Rising trigger event configuration of + /// line 4 + TR4: u1, + /// Rising trigger event configuration of + /// line 5 + TR5: u1, + /// Rising trigger event configuration of + /// line 6 + TR6: u1, + /// Rising trigger event configuration of + /// line 7 + TR7: u1, + /// Rising trigger event configuration of + /// line 8 + TR8: u1, + /// Rising trigger event configuration of + /// line 9 + TR9: u1, + /// Rising trigger event configuration of + /// line 10 + TR10: u1, + /// Rising trigger event configuration of + /// line 11 + TR11: u1, + /// Rising trigger event configuration of + /// line 12 + TR12: u1, + /// Rising trigger event configuration of + /// line 13 + TR13: u1, + /// Rising trigger event configuration of + /// line 14 + TR14: u1, + /// Rising trigger event configuration of + /// line 15 + TR15: u1, + /// Rising trigger event configuration of + /// line 16 + TR16: u1, + /// Rising trigger event configuration of + /// line 17 + TR17: u1, + /// Rising trigger event configuration of + /// line 18 + TR18: u1, + /// Rising trigger event configuration of + /// line 19 + TR19: u1, + /// Rising trigger event configuration of + /// line 20 + TR20: u1, + /// Rising trigger event configuration of + /// line 21 + TR21: u1, + /// Rising trigger event configuration of + /// line 22 + TR22: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Rising trigger event configuration of + /// line 29 + TR29: u1, + /// Rising trigger event configuration of + /// line 30 + TR30: u1, + /// Rising trigger event configuration of + /// line 31 + TR31: u1, + }), base_address + 0x8); + + /// address: 0x4001040c + /// Falling Trigger selection + /// register + pub const FTSR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Falling trigger event configuration of + /// line 0 + TR0: u1, + /// Falling trigger event configuration of + /// line 1 + TR1: u1, + /// Falling trigger event configuration of + /// line 2 + TR2: u1, + /// Falling trigger event configuration of + /// line 3 + TR3: u1, + /// Falling trigger event configuration of + /// line 4 + TR4: u1, + /// Falling trigger event configuration of + /// line 5 + TR5: u1, + /// Falling trigger event configuration of + /// line 6 + TR6: u1, + /// Falling trigger event configuration of + /// line 7 + TR7: u1, + /// Falling trigger event configuration of + /// line 8 + TR8: u1, + /// Falling trigger event configuration of + /// line 9 + TR9: u1, + /// Falling trigger event configuration of + /// line 10 + TR10: u1, + /// Falling trigger event configuration of + /// line 11 + TR11: u1, + /// Falling trigger event configuration of + /// line 12 + TR12: u1, + /// Falling trigger event configuration of + /// line 13 + TR13: u1, + /// Falling trigger event configuration of + /// line 14 + TR14: u1, + /// Falling trigger event configuration of + /// line 15 + TR15: u1, + /// Falling trigger event configuration of + /// line 16 + TR16: u1, + /// Falling trigger event configuration of + /// line 17 + TR17: u1, + /// Falling trigger event configuration of + /// line 18 + TR18: u1, + /// Falling trigger event configuration of + /// line 19 + TR19: u1, + /// Falling trigger event configuration of + /// line 20 + TR20: u1, + /// Falling trigger event configuration of + /// line 21 + TR21: u1, + /// Falling trigger event configuration of + /// line 22 + TR22: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Falling trigger event configuration of + /// line 29 + TR29: u1, + /// Falling trigger event configuration of + /// line 30. + TR30: u1, + /// Falling trigger event configuration of + /// line 31 + TR31: u1, + }), base_address + 0xc); + + /// address: 0x40010410 + /// Software interrupt event + /// register + pub const SWIER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Software Interrupt on line + /// 0 + SWIER0: u1, + /// Software Interrupt on line + /// 1 + SWIER1: u1, + /// Software Interrupt on line + /// 2 + SWIER2: u1, + /// Software Interrupt on line + /// 3 + SWIER3: u1, + /// Software Interrupt on line + /// 4 + SWIER4: u1, + /// Software Interrupt on line + /// 5 + SWIER5: u1, + /// Software Interrupt on line + /// 6 + SWIER6: u1, + /// Software Interrupt on line + /// 7 + SWIER7: u1, + /// Software Interrupt on line + /// 8 + SWIER8: u1, + /// Software Interrupt on line + /// 9 + SWIER9: u1, + /// Software Interrupt on line + /// 10 + SWIER10: u1, + /// Software Interrupt on line + /// 11 + SWIER11: u1, + /// Software Interrupt on line + /// 12 + SWIER12: u1, + /// Software Interrupt on line + /// 13 + SWIER13: u1, + /// Software Interrupt on line + /// 14 + SWIER14: u1, + /// Software Interrupt on line + /// 15 + SWIER15: u1, + /// Software Interrupt on line + /// 16 + SWIER16: u1, + /// Software Interrupt on line + /// 17 + SWIER17: u1, + /// Software Interrupt on line + /// 18 + SWIER18: u1, + /// Software Interrupt on line + /// 19 + SWIER19: u1, + /// Software Interrupt on line + /// 20 + SWIER20: u1, + /// Software Interrupt on line + /// 21 + SWIER21: u1, + /// Software Interrupt on line + /// 22 + SWIER22: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Software Interrupt on line + /// 29 + SWIER29: u1, + /// Software Interrupt on line + /// 309 + SWIER30: u1, + /// Software Interrupt on line + /// 319 + SWIER31: u1, + }), base_address + 0x10); + + /// address: 0x40010414 + /// Pending register + pub const PR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pending bit 0 + PR0: u1, + /// Pending bit 1 + PR1: u1, + /// Pending bit 2 + PR2: u1, + /// Pending bit 3 + PR3: u1, + /// Pending bit 4 + PR4: u1, + /// Pending bit 5 + PR5: u1, + /// Pending bit 6 + PR6: u1, + /// Pending bit 7 + PR7: u1, + /// Pending bit 8 + PR8: u1, + /// Pending bit 9 + PR9: u1, + /// Pending bit 10 + PR10: u1, + /// Pending bit 11 + PR11: u1, + /// Pending bit 12 + PR12: u1, + /// Pending bit 13 + PR13: u1, + /// Pending bit 14 + PR14: u1, + /// Pending bit 15 + PR15: u1, + /// Pending bit 16 + PR16: u1, + /// Pending bit 17 + PR17: u1, + /// Pending bit 18 + PR18: u1, + /// Pending bit 19 + PR19: u1, + /// Pending bit 20 + PR20: u1, + /// Pending bit 21 + PR21: u1, + /// Pending bit 22 + PR22: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Pending bit 29 + PR29: u1, + /// Pending bit 30 + PR30: u1, + /// Pending bit 31 + PR31: u1, + }), base_address + 0x14); + + /// address: 0x40010418 + /// Interrupt mask register + pub const IMR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interrupt Mask on external/internal line + /// 32 + MR32: u1, + /// Interrupt Mask on external/internal line + /// 33 + MR33: u1, + /// Interrupt Mask on external/internal line + /// 34 + MR34: u1, + /// Interrupt Mask on external/internal line + /// 35 + MR35: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x18); + + /// address: 0x4001041c + /// Event mask register + pub const EMR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Event mask on external/internal line + /// 32 + MR32: u1, + /// Event mask on external/internal line + /// 33 + MR33: u1, + /// Event mask on external/internal line + /// 34 + MR34: u1, + /// Event mask on external/internal line + /// 35 + MR35: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x1c); + + /// address: 0x40010420 + /// Rising Trigger selection + /// register + pub const RTSR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rising trigger event configuration bit + /// of line 32 + TR32: u1, + /// Rising trigger event configuration bit + /// of line 33 + TR33: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x20); + + /// address: 0x40010424 + /// Falling Trigger selection + /// register + pub const FTSR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Falling trigger event configuration bit + /// of line 32 + TR32: u1, + /// Falling trigger event configuration bit + /// of line 33 + TR33: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x24); + + /// address: 0x40010428 + /// Software interrupt event + /// register + pub const SWIER2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Software interrupt on line + /// 32 + SWIER32: u1, + /// Software interrupt on line + /// 33 + SWIER33: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x28); + + /// address: 0x4001042c + /// Pending register + pub const PR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pending bit on line 32 + PR32: u1, + /// Pending bit on line 33 + PR33: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x2c); + }; + /// Power control + pub const PWR = struct { + pub const base_address = 0x40007000; + + /// address: 0x40007000 + /// power control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: u1, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector + /// enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write + /// protection + DBP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40007004 + /// power control/status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Enable WKUP1 pin + EWUP1: u1, + /// Enable WKUP2 pin + EWUP2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + }; + /// Controller area network + pub const CAN = struct { + pub const base_address = 0x40006400; + + /// address: 0x40006400 + /// master control register + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006404 + /// master status register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006408 + /// transmit status register + pub const TSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox + /// 0 + TME0: u1, + /// Lowest priority flag for mailbox + /// 1 + TME1: u1, + /// Lowest priority flag for mailbox + /// 2 + TME2: u1, + /// Lowest priority flag for mailbox + /// 0 + LOW0: u1, + /// Lowest priority flag for mailbox + /// 1 + LOW1: u1, + /// Lowest priority flag for mailbox + /// 2 + LOW2: u1, + }), base_address + 0x8); + + /// address: 0x4000640c + /// receive FIFO 0 register + pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// FMP0 + FMP0: u2, + reserved0: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006410 + /// receive FIFO 1 register + pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// FMP1 + FMP1: u2, + reserved0: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006414 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved0: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006418 + /// error status register + pub const ESR = @intToPtr(*volatile Mmio(32, packed struct{ + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved0: u1, + /// LEC + LEC: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), base_address + 0x18); + + /// address: 0x4000641c + /// bit timing register + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// BRP + BRP: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved6: u1, + /// SJW + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), base_address + 0x1c); + + /// address: 0x40006580 + /// TX mailbox identifier register + pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x180); + + /// address: 0x40006584 + /// mailbox data length control and time stamp + /// register + pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x184); + + /// address: 0x40006588 + /// mailbox data low register + pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x188); + + /// address: 0x4000658c + /// mailbox data high register + pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x18c); + + /// address: 0x40006590 + /// TX mailbox identifier register + pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x190); + + /// address: 0x40006594 + /// mailbox data length control and time stamp + /// register + pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x194); + + /// address: 0x40006598 + /// mailbox data low register + pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x198); + + /// address: 0x4000659c + /// mailbox data high register + pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x19c); + + /// address: 0x400065a0 + /// TX mailbox identifier register + pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1a0); + + /// address: 0x400065a4 + /// mailbox data length control and time stamp + /// register + pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x1a4); + + /// address: 0x400065a8 + /// mailbox data low register + pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1a8); + + /// address: 0x400065ac + /// mailbox data high register + pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1ac); + + /// address: 0x400065b0 + /// receive FIFO mailbox identifier + /// register + pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1b0); + + /// address: 0x400065b4 + /// receive FIFO mailbox data length control and + /// time stamp register + pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1b4); + + /// address: 0x400065b8 + /// receive FIFO mailbox data low + /// register + pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1b8); + + /// address: 0x400065bc + /// receive FIFO mailbox data high + /// register + pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1bc); + + /// address: 0x400065c0 + /// receive FIFO mailbox identifier + /// register + pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1c0); + + /// address: 0x400065c4 + /// receive FIFO mailbox data length control and + /// time stamp register + pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1c4); + + /// address: 0x400065c8 + /// receive FIFO mailbox data low + /// register + pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1c8); + + /// address: 0x400065cc + /// receive FIFO mailbox data high + /// register + pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006600 + /// filter master register + pub const FMR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter init mode + FINIT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// CAN2 start bank + CAN2SB: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40006604 + /// filter mode register + pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + /// Filter mode + FBM14: u1, + /// Filter mode + FBM15: u1, + /// Filter mode + FBM16: u1, + /// Filter mode + FBM17: u1, + /// Filter mode + FBM18: u1, + /// Filter mode + FBM19: u1, + /// Filter mode + FBM20: u1, + /// Filter mode + FBM21: u1, + /// Filter mode + FBM22: u1, + /// Filter mode + FBM23: u1, + /// Filter mode + FBM24: u1, + /// Filter mode + FBM25: u1, + /// Filter mode + FBM26: u1, + /// Filter mode + FBM27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x204); + + /// address: 0x4000660c + /// filter scale register + pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + /// Filter scale configuration + FSC14: u1, + /// Filter scale configuration + FSC15: u1, + /// Filter scale configuration + FSC16: u1, + /// Filter scale configuration + FSC17: u1, + /// Filter scale configuration + FSC18: u1, + /// Filter scale configuration + FSC19: u1, + /// Filter scale configuration + FSC20: u1, + /// Filter scale configuration + FSC21: u1, + /// Filter scale configuration + FSC22: u1, + /// Filter scale configuration + FSC23: u1, + /// Filter scale configuration + FSC24: u1, + /// Filter scale configuration + FSC25: u1, + /// Filter scale configuration + FSC26: u1, + /// Filter scale configuration + FSC27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20c); + + /// address: 0x40006614 + /// filter FIFO assignment + /// register + pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter FIFO assignment for filter + /// 0 + FFA0: u1, + /// Filter FIFO assignment for filter + /// 1 + FFA1: u1, + /// Filter FIFO assignment for filter + /// 2 + FFA2: u1, + /// Filter FIFO assignment for filter + /// 3 + FFA3: u1, + /// Filter FIFO assignment for filter + /// 4 + FFA4: u1, + /// Filter FIFO assignment for filter + /// 5 + FFA5: u1, + /// Filter FIFO assignment for filter + /// 6 + FFA6: u1, + /// Filter FIFO assignment for filter + /// 7 + FFA7: u1, + /// Filter FIFO assignment for filter + /// 8 + FFA8: u1, + /// Filter FIFO assignment for filter + /// 9 + FFA9: u1, + /// Filter FIFO assignment for filter + /// 10 + FFA10: u1, + /// Filter FIFO assignment for filter + /// 11 + FFA11: u1, + /// Filter FIFO assignment for filter + /// 12 + FFA12: u1, + /// Filter FIFO assignment for filter + /// 13 + FFA13: u1, + /// Filter FIFO assignment for filter + /// 14 + FFA14: u1, + /// Filter FIFO assignment for filter + /// 15 + FFA15: u1, + /// Filter FIFO assignment for filter + /// 16 + FFA16: u1, + /// Filter FIFO assignment for filter + /// 17 + FFA17: u1, + /// Filter FIFO assignment for filter + /// 18 + FFA18: u1, + /// Filter FIFO assignment for filter + /// 19 + FFA19: u1, + /// Filter FIFO assignment for filter + /// 20 + FFA20: u1, + /// Filter FIFO assignment for filter + /// 21 + FFA21: u1, + /// Filter FIFO assignment for filter + /// 22 + FFA22: u1, + /// Filter FIFO assignment for filter + /// 23 + FFA23: u1, + /// Filter FIFO assignment for filter + /// 24 + FFA24: u1, + /// Filter FIFO assignment for filter + /// 25 + FFA25: u1, + /// Filter FIFO assignment for filter + /// 26 + FFA26: u1, + /// Filter FIFO assignment for filter + /// 27 + FFA27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x214); + + /// address: 0x4000661c + /// CAN filter activation register + pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + /// Filter active + FACT14: u1, + /// Filter active + FACT15: u1, + /// Filter active + FACT16: u1, + /// Filter active + FACT17: u1, + /// Filter active + FACT18: u1, + /// Filter active + FACT19: u1, + /// Filter active + FACT20: u1, + /// Filter active + FACT21: u1, + /// Filter active + FACT22: u1, + /// Filter active + FACT23: u1, + /// Filter active + FACT24: u1, + /// Filter active + FACT25: u1, + /// Filter active + FACT26: u1, + /// Filter active + FACT27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x21c); + + /// address: 0x40006640 + /// Filter bank 0 register 1 + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x240); + + /// address: 0x40006644 + /// Filter bank 0 register 2 + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x244); + + /// address: 0x40006648 + /// Filter bank 1 register 1 + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x248); + + /// address: 0x4000664c + /// Filter bank 1 register 2 + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x24c); + + /// address: 0x40006650 + /// Filter bank 2 register 1 + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x250); + + /// address: 0x40006654 + /// Filter bank 2 register 2 + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x254); + + /// address: 0x40006658 + /// Filter bank 3 register 1 + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x258); + + /// address: 0x4000665c + /// Filter bank 3 register 2 + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x25c); + + /// address: 0x40006660 + /// Filter bank 4 register 1 + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x260); + + /// address: 0x40006664 + /// Filter bank 4 register 2 + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x264); + + /// address: 0x40006668 + /// Filter bank 5 register 1 + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x268); + + /// address: 0x4000666c + /// Filter bank 5 register 2 + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x26c); + + /// address: 0x40006670 + /// Filter bank 6 register 1 + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x270); + + /// address: 0x40006674 + /// Filter bank 6 register 2 + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x274); + + /// address: 0x40006678 + /// Filter bank 7 register 1 + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x278); + + /// address: 0x4000667c + /// Filter bank 7 register 2 + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x27c); + + /// address: 0x40006680 + /// Filter bank 8 register 1 + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x280); + + /// address: 0x40006684 + /// Filter bank 8 register 2 + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x284); + + /// address: 0x40006688 + /// Filter bank 9 register 1 + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x288); + + /// address: 0x4000668c + /// Filter bank 9 register 2 + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x28c); + + /// address: 0x40006690 + /// Filter bank 10 register 1 + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x290); + + /// address: 0x40006694 + /// Filter bank 10 register 2 + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x294); + + /// address: 0x40006698 + /// Filter bank 11 register 1 + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x298); + + /// address: 0x4000669c + /// Filter bank 11 register 2 + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x29c); + + /// address: 0x400066a0 + /// Filter bank 4 register 1 + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a0); + + /// address: 0x400066a4 + /// Filter bank 12 register 2 + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a4); + + /// address: 0x400066a8 + /// Filter bank 13 register 1 + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a8); + + /// address: 0x400066ac + /// Filter bank 13 register 2 + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ac); + + /// address: 0x400066b0 + /// Filter bank 14 register 1 + pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b0); + + /// address: 0x400066b4 + /// Filter bank 14 register 2 + pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b4); + + /// address: 0x400066b8 + /// Filter bank 15 register 1 + pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b8); + + /// address: 0x400066bc + /// Filter bank 15 register 2 + pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2bc); + + /// address: 0x400066c0 + /// Filter bank 16 register 1 + pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c0); + + /// address: 0x400066c4 + /// Filter bank 16 register 2 + pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c4); + + /// address: 0x400066c8 + /// Filter bank 17 register 1 + pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c8); + + /// address: 0x400066cc + /// Filter bank 17 register 2 + pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2cc); + + /// address: 0x400066d0 + /// Filter bank 18 register 1 + pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d0); + + /// address: 0x400066d4 + /// Filter bank 18 register 2 + pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d4); + + /// address: 0x400066d8 + /// Filter bank 19 register 1 + pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d8); + + /// address: 0x400066dc + /// Filter bank 19 register 2 + pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2dc); + + /// address: 0x400066e0 + /// Filter bank 20 register 1 + pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e0); + + /// address: 0x400066e4 + /// Filter bank 20 register 2 + pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e4); + + /// address: 0x400066e8 + /// Filter bank 21 register 1 + pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e8); + + /// address: 0x400066ec + /// Filter bank 21 register 2 + pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ec); + + /// address: 0x400066f0 + /// Filter bank 22 register 1 + pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f0); + + /// address: 0x400066f4 + /// Filter bank 22 register 2 + pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f4); + + /// address: 0x400066f8 + /// Filter bank 23 register 1 + pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f8); + + /// address: 0x400066fc + /// Filter bank 23 register 2 + pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2fc); + + /// address: 0x40006700 + /// Filter bank 24 register 1 + pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x300); + + /// address: 0x40006704 + /// Filter bank 24 register 2 + pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x304); + + /// address: 0x40006708 + /// Filter bank 25 register 1 + pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x308); + + /// address: 0x4000670c + /// Filter bank 25 register 2 + pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x30c); + + /// address: 0x40006710 + /// Filter bank 26 register 1 + pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x310); + + /// address: 0x40006714 + /// Filter bank 26 register 2 + pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x314); + + /// address: 0x40006718 + /// Filter bank 27 register 1 + pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x318); + + /// address: 0x4000671c + /// Filter bank 27 register 2 + pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x31c); + }; + /// Universal serial bus full-speed device + /// interface + pub const USB_FS = struct { + pub const base_address = 0x40005c00; + + /// address: 0x40005c00 + /// endpoint 0 register + pub const USB_EP0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005c04 + /// endpoint 1 register + pub const USB_EP1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40005c08 + /// endpoint 2 register + pub const USB_EP2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40005c0c + /// endpoint 3 register + pub const USB_EP3R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005c10 + /// endpoint 4 register + pub const USB_EP4R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40005c14 + /// endpoint 5 register + pub const USB_EP5R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005c18 + /// endpoint 6 register + pub const USB_EP6R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40005c1c + /// endpoint 7 register + pub const USB_EP7R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005c40 + /// control register + pub const USB_CNTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Force USB Reset + FRES: u1, + /// Power down + PDWN: u1, + /// Low-power mode + LPMODE: u1, + /// Force suspend + FSUSP: u1, + /// Resume request + RESUME: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Expected start of frame interrupt + /// mask + ESOFM: u1, + /// Start of frame interrupt + /// mask + SOFM: u1, + /// USB reset interrupt mask + RESETM: u1, + /// Suspend mode interrupt + /// mask + SUSPM: u1, + /// Wakeup interrupt mask + WKUPM: u1, + /// Error interrupt mask + ERRM: u1, + /// Packet memory area over / underrun + /// interrupt mask + PMAOVRM: u1, + /// Correct transfer interrupt + /// mask + CTRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40005c44 + /// interrupt status register + pub const ISTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint Identifier + EP_ID: u4, + /// Direction of transaction + DIR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Expected start frame + ESOF: u1, + /// start of frame + SOF: u1, + /// reset request + RESET: u1, + /// Suspend mode request + SUSP: u1, + /// Wakeup + WKUP: u1, + /// Error + ERR: u1, + /// Packet memory area over / + /// underrun + PMAOVR: u1, + /// Correct transfer + CTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40005c48 + /// frame number register + pub const FNR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Frame number + FN: u11, + /// Lost SOF + LSOF: u2, + /// Locked + LCK: u1, + /// Receive data - line status + RXDM: u1, + /// Receive data + line status + RXDP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x40005c4c + /// device address + pub const DADDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Device address + ADD: u1, + /// Device address + ADD1: u1, + /// Device address + ADD2: u1, + /// Device address + ADD3: u1, + /// Device address + ADD4: u1, + /// Device address + ADD5: u1, + /// Device address + ADD6: u1, + /// Enable function + EF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4c); + + /// address: 0x40005c50 + /// Buffer table address + pub const BTABLE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x50); + }; + /// Inter-integrated circuit + pub const I2C1 = struct { + pub const base_address = 0x40005400; + + /// address: 0x40005400 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral enable + PE: u1, + /// TX Interrupt enable + TXIE: u1, + /// RX Interrupt enable + RXIE: u1, + /// Address match interrupt enable (slave + /// only) + ADDRIE: u1, + /// Not acknowledge received interrupt + /// enable + NACKIE: u1, + /// STOP detection Interrupt + /// enable + STOPIE: u1, + /// Transfer Complete interrupt + /// enable + TCIE: u1, + /// Error interrupts enable + ERRIE: u1, + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANFOFF: u1, + /// Software reset + SWRST: u1, + /// DMA transmission requests + /// enable + TXDMAEN: u1, + /// DMA reception requests + /// enable + RXDMAEN: u1, + /// Slave byte control + SBC: u1, + /// Clock stretching disable + NOSTRETCH: u1, + /// Wakeup from STOP enable + WUPEN: u1, + /// General call enable + GCEN: u1, + /// SMBus Host address enable + SMBHEN: u1, + /// SMBus Device Default address + /// enable + SMBDEN: u1, + /// SMBUS alert enable + ALERTEN: u1, + /// PEC enable + PECEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0x40005404 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave address bit 0 (master + /// mode) + SADD0: u1, + /// Slave address bit 7:1 (master + /// mode) + SADD1: u7, + /// Slave address bit 9:8 (master + /// mode) + SADD8: u2, + /// Transfer direction (master + /// mode) + RD_WRN: u1, + /// 10-bit addressing mode (master + /// mode) + ADD10: u1, + /// 10-bit address header only read + /// direction (master receiver mode) + HEAD10R: u1, + /// Start generation + START: u1, + /// Stop generation (master + /// mode) + STOP: u1, + /// NACK generation (slave + /// mode) + NACK: u1, + /// Number of bytes + NBYTES: u8, + /// NBYTES reload mode + RELOAD: u1, + /// Automatic end mode (master + /// mode) + AUTOEND: u1, + /// Packet error checking byte + PECBYTE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40005408 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interface address + OA1_0: u1, + /// Interface address + OA1_1: u7, + /// Interface address + OA1_8: u2, + /// Own Address 1 10-bit mode + OA1MODE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Own Address 1 enable + OA1EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000540c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Interface address + OA2: u7, + /// Own Address 2 masks + OA2MSK: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Own Address 2 enable + OA2EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005410 + /// Timing register + pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SCL low period (master + /// mode) + SCLL: u8, + /// SCL high period (master + /// mode) + SCLH: u8, + /// Data hold time + SDADEL: u4, + /// Data setup time + SCLDEL: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Timing prescaler + PRESC: u4, + }), base_address + 0x10); + + /// address: 0x40005414 + /// Status register 1 + pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bus timeout A + TIMEOUTA: u12, + /// Idle clock timeout + /// detection + TIDLE: u1, + reserved0: u1, + reserved1: u1, + /// Clock timeout enable + TIMOUTEN: u1, + /// Bus timeout B + TIMEOUTB: u12, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Extended clock timeout + /// enable + TEXTEN: u1, + }), base_address + 0x14); + + /// address: 0x40005418 + /// Interrupt and Status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Transmit data register empty + /// (transmitters) + TXE: u1, + /// Transmit interrupt status + /// (transmitters) + TXIS: u1, + /// Receive data register not empty + /// (receivers) + RXNE: u1, + /// Address matched (slave + /// mode) + ADDR: u1, + /// Not acknowledge received + /// flag + NACKF: u1, + /// Stop detection flag + STOPF: u1, + /// Transfer Complete (master + /// mode) + TC: u1, + /// Transfer Complete Reload + TCR: u1, + /// Bus error + BERR: u1, + /// Arbitration lost + ARLO: u1, + /// Overrun/Underrun (slave + /// mode) + OVR: u1, + /// PEC Error in reception + PECERR: u1, + /// Timeout or t_low detection + /// flag + TIMEOUT: u1, + /// SMBus alert + ALERT: u1, + reserved0: u1, + /// Bus busy + BUSY: u1, + /// Transfer direction (Slave + /// mode) + DIR: u1, + /// Address match code (Slave + /// mode) + ADDCODE: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0x4000541c + /// Interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Address Matched flag clear + ADDRCF: u1, + /// Not Acknowledge flag clear + NACKCF: u1, + /// Stop detection flag clear + STOPCF: u1, + reserved3: u1, + reserved4: u1, + /// Bus error flag clear + BERRCF: u1, + /// Arbitration lost flag + /// clear + ARLOCF: u1, + /// Overrun/Underrun flag + /// clear + OVRCF: u1, + /// PEC Error flag clear + PECCF: u1, + /// Timeout detection flag + /// clear + TIMOUTCF: u1, + /// Alert flag clear + ALERTCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1c); + + /// address: 0x40005420 + /// PEC register + pub const PECR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Packet error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40005424 + /// Receive data register + pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit receive data + RXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40005428 + /// Transmit data register + pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit transmit data + TXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x28); + }; + pub const I2C2 = struct { + pub const base_address = 0x40005800; + + /// address: 0x40005800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral enable + PE: u1, + /// TX Interrupt enable + TXIE: u1, + /// RX Interrupt enable + RXIE: u1, + /// Address match interrupt enable (slave + /// only) + ADDRIE: u1, + /// Not acknowledge received interrupt + /// enable + NACKIE: u1, + /// STOP detection Interrupt + /// enable + STOPIE: u1, + /// Transfer Complete interrupt + /// enable + TCIE: u1, + /// Error interrupts enable + ERRIE: u1, + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANFOFF: u1, + /// Software reset + SWRST: u1, + /// DMA transmission requests + /// enable + TXDMAEN: u1, + /// DMA reception requests + /// enable + RXDMAEN: u1, + /// Slave byte control + SBC: u1, + /// Clock stretching disable + NOSTRETCH: u1, + /// Wakeup from STOP enable + WUPEN: u1, + /// General call enable + GCEN: u1, + /// SMBus Host address enable + SMBHEN: u1, + /// SMBus Device Default address + /// enable + SMBDEN: u1, + /// SMBUS alert enable + ALERTEN: u1, + /// PEC enable + PECEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0x40005804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave address bit 0 (master + /// mode) + SADD0: u1, + /// Slave address bit 7:1 (master + /// mode) + SADD1: u7, + /// Slave address bit 9:8 (master + /// mode) + SADD8: u2, + /// Transfer direction (master + /// mode) + RD_WRN: u1, + /// 10-bit addressing mode (master + /// mode) + ADD10: u1, + /// 10-bit address header only read + /// direction (master receiver mode) + HEAD10R: u1, + /// Start generation + START: u1, + /// Stop generation (master + /// mode) + STOP: u1, + /// NACK generation (slave + /// mode) + NACK: u1, + /// Number of bytes + NBYTES: u8, + /// NBYTES reload mode + RELOAD: u1, + /// Automatic end mode (master + /// mode) + AUTOEND: u1, + /// Packet error checking byte + PECBYTE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40005808 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interface address + OA1_0: u1, + /// Interface address + OA1_1: u7, + /// Interface address + OA1_8: u2, + /// Own Address 1 10-bit mode + OA1MODE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Own Address 1 enable + OA1EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000580c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Interface address + OA2: u7, + /// Own Address 2 masks + OA2MSK: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Own Address 2 enable + OA2EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005810 + /// Timing register + pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SCL low period (master + /// mode) + SCLL: u8, + /// SCL high period (master + /// mode) + SCLH: u8, + /// Data hold time + SDADEL: u4, + /// Data setup time + SCLDEL: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Timing prescaler + PRESC: u4, + }), base_address + 0x10); + + /// address: 0x40005814 + /// Status register 1 + pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bus timeout A + TIMEOUTA: u12, + /// Idle clock timeout + /// detection + TIDLE: u1, + reserved0: u1, + reserved1: u1, + /// Clock timeout enable + TIMOUTEN: u1, + /// Bus timeout B + TIMEOUTB: u12, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Extended clock timeout + /// enable + TEXTEN: u1, + }), base_address + 0x14); + + /// address: 0x40005818 + /// Interrupt and Status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Transmit data register empty + /// (transmitters) + TXE: u1, + /// Transmit interrupt status + /// (transmitters) + TXIS: u1, + /// Receive data register not empty + /// (receivers) + RXNE: u1, + /// Address matched (slave + /// mode) + ADDR: u1, + /// Not acknowledge received + /// flag + NACKF: u1, + /// Stop detection flag + STOPF: u1, + /// Transfer Complete (master + /// mode) + TC: u1, + /// Transfer Complete Reload + TCR: u1, + /// Bus error + BERR: u1, + /// Arbitration lost + ARLO: u1, + /// Overrun/Underrun (slave + /// mode) + OVR: u1, + /// PEC Error in reception + PECERR: u1, + /// Timeout or t_low detection + /// flag + TIMEOUT: u1, + /// SMBus alert + ALERT: u1, + reserved0: u1, + /// Bus busy + BUSY: u1, + /// Transfer direction (Slave + /// mode) + DIR: u1, + /// Address match code (Slave + /// mode) + ADDCODE: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0x4000581c + /// Interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Address Matched flag clear + ADDRCF: u1, + /// Not Acknowledge flag clear + NACKCF: u1, + /// Stop detection flag clear + STOPCF: u1, + reserved3: u1, + reserved4: u1, + /// Bus error flag clear + BERRCF: u1, + /// Arbitration lost flag + /// clear + ARLOCF: u1, + /// Overrun/Underrun flag + /// clear + OVRCF: u1, + /// PEC Error flag clear + PECCF: u1, + /// Timeout detection flag + /// clear + TIMOUTCF: u1, + /// Alert flag clear + ALERTCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1c); + + /// address: 0x40005820 + /// PEC register + pub const PECR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Packet error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40005824 + /// Receive data register + pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit receive data + RXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40005828 + /// Transmit data register + pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit transmit data + TXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x28); + }; + pub const I2C3 = struct { + pub const base_address = 0x40007800; + + /// address: 0x40007800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral enable + PE: u1, + /// TX Interrupt enable + TXIE: u1, + /// RX Interrupt enable + RXIE: u1, + /// Address match interrupt enable (slave + /// only) + ADDRIE: u1, + /// Not acknowledge received interrupt + /// enable + NACKIE: u1, + /// STOP detection Interrupt + /// enable + STOPIE: u1, + /// Transfer Complete interrupt + /// enable + TCIE: u1, + /// Error interrupts enable + ERRIE: u1, + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANFOFF: u1, + /// Software reset + SWRST: u1, + /// DMA transmission requests + /// enable + TXDMAEN: u1, + /// DMA reception requests + /// enable + RXDMAEN: u1, + /// Slave byte control + SBC: u1, + /// Clock stretching disable + NOSTRETCH: u1, + /// Wakeup from STOP enable + WUPEN: u1, + /// General call enable + GCEN: u1, + /// SMBus Host address enable + SMBHEN: u1, + /// SMBus Device Default address + /// enable + SMBDEN: u1, + /// SMBUS alert enable + ALERTEN: u1, + /// PEC enable + PECEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0x40007804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave address bit 0 (master + /// mode) + SADD0: u1, + /// Slave address bit 7:1 (master + /// mode) + SADD1: u7, + /// Slave address bit 9:8 (master + /// mode) + SADD8: u2, + /// Transfer direction (master + /// mode) + RD_WRN: u1, + /// 10-bit addressing mode (master + /// mode) + ADD10: u1, + /// 10-bit address header only read + /// direction (master receiver mode) + HEAD10R: u1, + /// Start generation + START: u1, + /// Stop generation (master + /// mode) + STOP: u1, + /// NACK generation (slave + /// mode) + NACK: u1, + /// Number of bytes + NBYTES: u8, + /// NBYTES reload mode + RELOAD: u1, + /// Automatic end mode (master + /// mode) + AUTOEND: u1, + /// Packet error checking byte + PECBYTE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40007808 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interface address + OA1_0: u1, + /// Interface address + OA1_1: u7, + /// Interface address + OA1_8: u2, + /// Own Address 1 10-bit mode + OA1MODE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Own Address 1 enable + OA1EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000780c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Interface address + OA2: u7, + /// Own Address 2 masks + OA2MSK: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Own Address 2 enable + OA2EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007810 + /// Timing register + pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SCL low period (master + /// mode) + SCLL: u8, + /// SCL high period (master + /// mode) + SCLH: u8, + /// Data hold time + SDADEL: u4, + /// Data setup time + SCLDEL: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Timing prescaler + PRESC: u4, + }), base_address + 0x10); + + /// address: 0x40007814 + /// Status register 1 + pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bus timeout A + TIMEOUTA: u12, + /// Idle clock timeout + /// detection + TIDLE: u1, + reserved0: u1, + reserved1: u1, + /// Clock timeout enable + TIMOUTEN: u1, + /// Bus timeout B + TIMEOUTB: u12, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Extended clock timeout + /// enable + TEXTEN: u1, + }), base_address + 0x14); + + /// address: 0x40007818 + /// Interrupt and Status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Transmit data register empty + /// (transmitters) + TXE: u1, + /// Transmit interrupt status + /// (transmitters) + TXIS: u1, + /// Receive data register not empty + /// (receivers) + RXNE: u1, + /// Address matched (slave + /// mode) + ADDR: u1, + /// Not acknowledge received + /// flag + NACKF: u1, + /// Stop detection flag + STOPF: u1, + /// Transfer Complete (master + /// mode) + TC: u1, + /// Transfer Complete Reload + TCR: u1, + /// Bus error + BERR: u1, + /// Arbitration lost + ARLO: u1, + /// Overrun/Underrun (slave + /// mode) + OVR: u1, + /// PEC Error in reception + PECERR: u1, + /// Timeout or t_low detection + /// flag + TIMEOUT: u1, + /// SMBus alert + ALERT: u1, + reserved0: u1, + /// Bus busy + BUSY: u1, + /// Transfer direction (Slave + /// mode) + DIR: u1, + /// Address match code (Slave + /// mode) + ADDCODE: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0x4000781c + /// Interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Address Matched flag clear + ADDRCF: u1, + /// Not Acknowledge flag clear + NACKCF: u1, + /// Stop detection flag clear + STOPCF: u1, + reserved3: u1, + reserved4: u1, + /// Bus error flag clear + BERRCF: u1, + /// Arbitration lost flag + /// clear + ARLOCF: u1, + /// Overrun/Underrun flag + /// clear + OVRCF: u1, + /// PEC Error flag clear + PECCF: u1, + /// Timeout detection flag + /// clear + TIMOUTCF: u1, + /// Alert flag clear + ALERTCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1c); + + /// address: 0x40007820 + /// PEC register + pub const PECR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Packet error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40007824 + /// Receive data register + pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit receive data + RXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40007828 + /// Transmit data register + pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit transmit data + TXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x28); + }; + /// Independent watchdog + pub const IWDG = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Key register + pub const KR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Key value + KEY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Prescaler register + pub const PR = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); + + /// address: 0x40003008 + /// Reload register + pub const RLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Watchdog counter reload + /// value + RL: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Watchdog prescaler value + /// update + PVU: u1, + /// Watchdog counter reload value + /// update + RVU: u1, + /// Watchdog counter window value + /// update + WVU: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0xc); + + /// address: 0x40003010 + /// Window register + pub const WINR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Watchdog counter window + /// value + WIN: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x10); + }; + /// Window watchdog + pub const WWDG = struct { + pub const base_address = 0x40002c00; + + /// address: 0x40002c00 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7-bit counter + T: u7, + /// Activation bit + WDGA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40002c04 + /// Configuration register + pub const CFR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7-bit window value + W: u7, + /// Timer base + WDGTB: u2, + /// Early wakeup interrupt + EWI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x40002c08 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Early wakeup interrupt + /// flag + EWIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + }; + /// Real-time clock + pub const RTC = struct { + pub const base_address = 0x40002800; + + /// address: 0x40002800 + /// time register + pub const TR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved0: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved1: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x0); + + /// address: 0x40002804 + /// date register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved0: u1, + reserved1: u1, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40002808 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Wakeup clock selection + WCKSEL: u3, + /// Time-stamp event active + /// edge + TSEDGE: u1, + /// Reference clock detection enable (50 or + /// 60 Hz) + REFCKON: u1, + /// Bypass the shadow + /// registers + BYPSHAD: u1, + /// Hour format + FMT: u1, + reserved0: u1, + /// Alarm A enable + ALRAE: u1, + /// Alarm B enable + ALRBE: u1, + /// Wakeup timer enable + WUTE: u1, + /// Time stamp enable + TSE: u1, + /// Alarm A interrupt enable + ALRAIE: u1, + /// Alarm B interrupt enable + ALRBIE: u1, + /// Wakeup timer interrupt + /// enable + WUTIE: u1, + /// Time-stamp interrupt + /// enable + TSIE: u1, + /// Add 1 hour (summer time + /// change) + ADD1H: u1, + /// Subtract 1 hour (winter time + /// change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output + /// selection + COSEL: u1, + /// Output polarity + POL: u1, + /// Output selection + OSEL: u2, + /// Calibration output enable + COE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4000280c + /// initialization and status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alarm A write flag + ALRAWF: u1, + /// Alarm B write flag + ALRBWF: u1, + /// Wakeup timer write flag + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization + /// flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Initialization mode + INIT: u1, + /// Alarm A flag + ALRAF: u1, + /// Alarm B flag + ALRBF: u1, + /// Wakeup timer flag + WUTF: u1, + /// Time-stamp flag + TSF: u1, + /// Time-stamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMP1F: u1, + /// RTC_TAMP2 detection flag + TAMP2F: u1, + /// RTC_TAMP3 detection flag + TAMP3F: u1, + /// Recalibration pending Flag + RECALPF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0xc); + + /// address: 0x40002810 + /// prescaler register + pub const PRER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Synchronous prescaler + /// factor + PREDIV_S: u15, + reserved0: u1, + /// Asynchronous prescaler + /// factor + PREDIV_A: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x10); + + /// address: 0x40002814 + /// wakeup timer register + pub const WUTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Wakeup auto-reload value + /// bits + WUT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x4000281c + /// alarm A register + pub const ALRMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm A seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm A minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm A hours mask + MSK3: u1, + /// Date units or day in BCD + /// format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm A date mask + MSK4: u1, + }), base_address + 0x1c); + + /// address: 0x40002820 + /// alarm B register + pub const ALRMBR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm B seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm B minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm B hours mask + MSK3: u1, + /// Date units or day in BCD + /// format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm B date mask + MSK4: u1, + }), base_address + 0x20); + + /// address: 0x40002824 + /// write protection register + pub const WPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write protection key + KEY: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40002828 + /// sub second register + pub const SSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Sub second value + SS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000282c + /// shift control register + pub const SHIFTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Subtract a fraction of a + /// second + SUBFS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Add one second + ADD1S: u1, + }), base_address + 0x2c); + + /// address: 0x40002830 + /// time stamp time register + pub const TSTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved0: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved1: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x30); + + /// address: 0x40002834 + /// time stamp date register + pub const TSDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved0: u1, + reserved1: u1, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40002838 + /// timestamp sub second register + pub const TSSSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Sub second value + SS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x38); + + /// address: 0x4000283c + /// calibration register + pub const CALR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Calibration minus + CALM: u9, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Use a 16-second calibration cycle + /// period + CALW16: u1, + /// Use an 8-second calibration cycle + /// period + CALW8: u1, + /// Increase frequency of RTC by 488.5 + /// ppm + CALP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40002840 + /// tamper and alternate function configuration + /// register + pub const TAFCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + /// Tamper 2 detection enable + TAMP2E: u1, + /// Active level for tamper 2 + TAMP2TRG: u1, + /// Tamper 3 detection enable + TAMP3E: u1, + /// Active level for tamper 3 + TAMP3TRG: u1, + /// Activate timestamp on tamper detection + /// event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: u3, + /// Tamper filter count + TAMPFLT: u2, + /// Tamper precharge duration + TAMPPRCH: u2, + /// TAMPER pull-up disable + TAMPPUDIS: u1, + reserved0: u1, + reserved1: u1, + /// PC13 value + PC13VALUE: u1, + /// PC13 mode + PC13MODE: u1, + /// PC14 value + PC14VALUE: u1, + /// PC 14 mode + PC14MODE: u1, + /// PC15 value + PC15VALUE: u1, + /// PC15 mode + PC15MODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x40002844 + /// alarm A sub second register + pub const ALRMASSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Sub seconds value + SS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mask the most-significant bits starting + /// at this bit + MASKSS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x44); + + /// address: 0x40002848 + /// alarm B sub second register + pub const ALRMBSSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Sub seconds value + SS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mask the most-significant bits starting + /// at this bit + MASKSS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x48); + + /// address: 0x40002850 + /// backup register + pub const BKP0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x50); + + /// address: 0x40002854 + /// backup register + pub const BKP1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x54); + + /// address: 0x40002858 + /// backup register + pub const BKP2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x58); + + /// address: 0x4000285c + /// backup register + pub const BKP3R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x5c); + + /// address: 0x40002860 + /// backup register + pub const BKP4R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x60); + + /// address: 0x40002864 + /// backup register + pub const BKP5R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x64); + + /// address: 0x40002868 + /// backup register + pub const BKP6R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x68); + + /// address: 0x4000286c + /// backup register + pub const BKP7R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x6c); + + /// address: 0x40002870 + /// backup register + pub const BKP8R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x70); + + /// address: 0x40002874 + /// backup register + pub const BKP9R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x74); + + /// address: 0x40002878 + /// backup register + pub const BKP10R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x78); + + /// address: 0x4000287c + /// backup register + pub const BKP11R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x7c); + + /// address: 0x40002880 + /// backup register + pub const BKP12R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x80); + + /// address: 0x40002884 + /// backup register + pub const BKP13R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x84); + + /// address: 0x40002888 + /// backup register + pub const BKP14R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x88); + + /// address: 0x4000288c + /// backup register + pub const BKP15R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x8c); + + /// address: 0x40002890 + /// backup register + pub const BKP16R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x90); + + /// address: 0x40002894 + /// backup register + pub const BKP17R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x94); + + /// address: 0x40002898 + /// backup register + pub const BKP18R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x98); + + /// address: 0x4000289c + /// backup register + pub const BKP19R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x9c); + + /// address: 0x400028a0 + /// backup register + pub const BKP20R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xa0); + + /// address: 0x400028a4 + /// backup register + pub const BKP21R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xa4); + + /// address: 0x400028a8 + /// backup register + pub const BKP22R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xa8); + + /// address: 0x400028ac + /// backup register + pub const BKP23R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xac); + + /// address: 0x400028b0 + /// backup register + pub const BKP24R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xb0); + + /// address: 0x400028b4 + /// backup register + pub const BKP25R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xb4); + + /// address: 0x400028b8 + /// backup register + pub const BKP26R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xb8); + + /// address: 0x400028bc + /// backup register + pub const BKP27R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xbc); + + /// address: 0x400028c0 + /// backup register + pub const BKP28R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xc0); + + /// address: 0x400028c4 + /// backup register + pub const BKP29R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xc4); + + /// address: 0x400028c8 + /// backup register + pub const BKP30R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xc8); + + /// address: 0x400028cc + /// backup register + pub const BKP31R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xcc); + }; + /// Basic timers + pub const TIM6 = struct { + pub const base_address = 0x40001000; + + /// address: 0x40001000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40001004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000100c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001024 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF Copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40001028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000102c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + pub const TIM7 = struct { + pub const base_address = 0x40001400; + + /// address: 0x40001400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40001404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000140c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001424 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF Copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40001428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000142c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + /// Digital-to-analog converter + pub const DAC = struct { + pub const base_address = 0x40007400; + + /// address: 0x40007400 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 enable + EN1: u1, + /// DAC channel1 output buffer + /// disable + BOFF1: u1, + /// DAC channel1 trigger + /// enable + TEN1: u1, + /// DAC channel1 trigger + /// selection + TSEL1: u3, + /// DAC channel1 noise/triangle wave + /// generation enable + WAVE1: u2, + /// DAC channel1 mask/amplitude + /// selector + MAMP1: u4, + /// DAC channel1 DMA enable + DMAEN1: u1, + /// DAC channel1 DMA Underrun Interrupt + /// enable + DMAUDRIE1: u1, + reserved0: u1, + reserved1: u1, + /// DAC channel2 enable + EN2: u1, + /// DAC channel2 output buffer + /// disable + BOFF2: u1, + /// DAC channel2 trigger + /// enable + TEN2: u1, + /// DAC channel2 trigger + /// selection + TSEL2: u3, + /// DAC channel2 noise/triangle wave + /// generation enable + WAVE2: u2, + /// DAC channel2 mask/amplitude + /// selector + MAMP2: u4, + /// DAC channel2 DMA enable + DMAEN2: u1, + /// DAC channel2 DMA underrun interrupt + /// enable + DMAUDRIE2: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x40007404 + /// software trigger register + pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 software + /// trigger + SWTRIG1: u1, + /// DAC channel2 software + /// trigger + SWTRIG2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40007408 + /// channel1 12-bit right-aligned data holding + /// register + pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000740c + /// channel1 12-bit left aligned data holding + /// register + pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007410 + /// channel1 8-bit right aligned data holding + /// register + pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40007414 + /// channel2 12-bit right aligned data holding + /// register + pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007418 + /// channel2 12-bit left aligned data holding + /// register + pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000741c + /// channel2 8-bit right-aligned data holding + /// register + pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1c); + + /// address: 0x40007420 + /// Dual DAC 12-bit right-aligned data holding + /// register + pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x40007424 + /// DUAL DAC 12-bit left aligned data holding + /// register + pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + }), base_address + 0x24); + + /// address: 0x40007428 + /// DUAL DAC 8-bit right aligned data holding + /// register + pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000742c + /// channel1 data output register + pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 data output + DACC1DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40007430 + /// channel2 data output register + pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 data output + DACC2DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x30); + + /// address: 0x40007434 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// DAC channel1 DMA underrun + /// flag + DMAUDR1: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + /// DAC channel2 DMA underrun + /// flag + DMAUDR2: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + }; + /// Debug support + pub const DBGMCU = struct { + pub const base_address = 0xe0042000; + + /// address: 0xe0042000 + /// MCU Device ID Code Register + pub const IDCODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Device Identifier + DEV_ID: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Revision Identifier + REV_ID: u16, + }), base_address + 0x0); + + /// address: 0xe0042004 + /// Debug MCU Configuration + /// Register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Debug Sleep mode + DBG_SLEEP: u1, + /// Debug Stop Mode + DBG_STOP: u1, + /// Debug Standby Mode + DBG_STANDBY: u1, + reserved0: u1, + reserved1: u1, + /// Trace pin assignment + /// control + TRACE_IOEN: u1, + /// Trace pin assignment + /// control + TRACE_MODE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0xe0042008 + /// APB Low Freeze Register + pub const APB1FZ = @intToPtr(*volatile Mmio(32, packed struct{ + /// Debug Timer 2 stopped when Core is + /// halted + DBG_TIM2_STOP: u1, + /// Debug Timer 3 stopped when Core is + /// halted + DBG_TIM3_STOP: u1, + /// Debug Timer 4 stopped when Core is + /// halted + DBG_TIM4_STOP: u1, + /// Debug Timer 5 stopped when Core is + /// halted + DBG_TIM5_STOP: u1, + /// Debug Timer 6 stopped when Core is + /// halted + DBG_TIM6_STOP: u1, + /// Debug Timer 7 stopped when Core is + /// halted + DBG_TIM7_STOP: u1, + /// Debug Timer 12 stopped when Core is + /// halted + DBG_TIM12_STOP: u1, + /// Debug Timer 13 stopped when Core is + /// halted + DBG_TIM13_STOP: u1, + /// Debug Timer 14 stopped when Core is + /// halted + DBG_TIMER14_STOP: u1, + /// Debug Timer 18 stopped when Core is + /// halted + DBG_TIM18_STOP: u1, + /// Debug RTC stopped when Core is + /// halted + DBG_RTC_STOP: u1, + /// Debug Window Wachdog stopped when Core + /// is halted + DBG_WWDG_STOP: u1, + /// Debug Independent Wachdog stopped when + /// Core is halted + DBG_IWDG_STOP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// SMBUS timeout mode stopped when Core is + /// halted + I2C1_SMBUS_TIMEOUT: u1, + /// SMBUS timeout mode stopped when Core is + /// halted + I2C2_SMBUS_TIMEOUT: u1, + reserved8: u1, + reserved9: u1, + /// Debug CAN stopped when core is + /// halted + DBG_CAN_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0xe004200c + /// APB High Freeze Register + pub const APB2FZ = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Debug Timer 15 stopped when Core is + /// halted + DBG_TIM15_STOP: u1, + /// Debug Timer 16 stopped when Core is + /// halted + DBG_TIM16_STOP: u1, + /// Debug Timer 17 stopped when Core is + /// halted + DBG_TIM17_STO: u1, + /// Debug Timer 19 stopped when Core is + /// halted + DBG_TIM19_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + }; + /// Advanced timer + pub const TIM1 = struct { + pub const base_address = 0x40012c00; + + /// address: 0x40012c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40012c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + reserved1: u1, + /// Output Idle state 5 + OIS5: u1, + reserved2: u1, + /// Output Idle state 6 + OIS6: u1, + reserved3: u1, + /// Master mode selection 2 + MMS2: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40012c08 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit 3 + SMS3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x40012c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40012c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + /// Break 2 interrupt flag + B2IF: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 5 interrupt + /// flag + C5IF: u1, + /// Capture/Compare 6 interrupt + /// flag + C6IF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x10); + + /// address: 0x40012c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + /// Break 2 generation + B2G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x14); + + /// address: 0x40012c18 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + /// Output Compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40012c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40012c1c + /// capture/compare mode register (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + /// Output Compare 3 mode bit + /// 3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 4 mode bit + /// 3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x40012c1c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40012c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved0: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + /// Capture/Compare 5 output + /// enable + CC5E: u1, + /// Capture/Compare 5 output + /// Polarity + CC5P: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 6 output + /// enable + CC6E: u1, + /// Capture/Compare 6 output + /// Polarity + CC6P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x20); + + /// address: 0x40012c24 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40012c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40012c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40012c30 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x30); + + /// address: 0x40012c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40012c38 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x40012c3c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40012c40 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40012c44 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + /// Break 2 filter + BK2F: u4, + /// Break 2 enable + BK2E: u1, + /// Break 2 polarity + BK2P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x44); + + /// address: 0x40012c48 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x40012c4c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40012c54 + /// capture/compare mode register 3 (output + /// mode) + pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Output compare 5 fast + /// enable + OC5FE: u1, + /// Output compare 5 preload + /// enable + OC5PE: u1, + /// Output compare 5 mode + OC5M: u3, + /// Output compare 5 clear + /// enable + OC5CE: u1, + reserved2: u1, + reserved3: u1, + /// Output compare 6 fast + /// enable + OC6FE: u1, + /// Output compare 6 preload + /// enable + OC6PE: u1, + /// Output compare 6 mode + OC6M: u3, + /// Output compare 6 clear + /// enable + OC6CE: u1, + /// Outout Compare 5 mode bit + /// 3 + OC5M_3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Outout Compare 6 mode bit + /// 3 + OC6M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x54); + + /// address: 0x40012c58 + /// capture/compare register 5 + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 5 value + CCR5: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Group Channel 5 and Channel + /// 1 + GC5C1: u1, + /// Group Channel 5 and Channel + /// 2 + GC5C2: u1, + /// Group Channel 5 and Channel + /// 3 + GC5C3: u1, + }), base_address + 0x58); + + /// address: 0x40012c5c + /// capture/compare register 6 + pub const CCR6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c); + + /// address: 0x40012c60 + /// option registers + pub const OR = @intToPtr(*volatile Mmio(32, packed struct{ + /// TIM1_ETR_ADC1 remapping + /// capability + TIM1_ETR_ADC1_RMP: u2, + /// TIM1_ETR_ADC4 remapping + /// capability + TIM1_ETR_ADC4_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x60); + }; + pub const TIM20 = struct { + pub const base_address = 0x40015000; + + /// address: 0x40015000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40015004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + reserved1: u1, + /// Output Idle state 5 + OIS5: u1, + reserved2: u1, + /// Output Idle state 6 + OIS6: u1, + reserved3: u1, + /// Master mode selection 2 + MMS2: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40015008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit 3 + SMS3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4001500c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40015010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + /// Break 2 interrupt flag + B2IF: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 5 interrupt + /// flag + C5IF: u1, + /// Capture/Compare 6 interrupt + /// flag + C6IF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x10); + + /// address: 0x40015014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + /// Break 2 generation + B2G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x14); + + /// address: 0x40015018 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + /// Output Compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40015018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001501c + /// capture/compare mode register (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + /// Output Compare 3 mode bit + /// 3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 4 mode bit + /// 3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x4001501c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40015020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved0: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + /// Capture/Compare 5 output + /// enable + CC5E: u1, + /// Capture/Compare 5 output + /// Polarity + CC5P: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 6 output + /// enable + CC6E: u1, + /// Capture/Compare 6 output + /// Polarity + CC6P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x20); + + /// address: 0x40015024 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40015028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001502c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40015030 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x30); + + /// address: 0x40015034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40015038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001503c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40015040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40015044 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + /// Break 2 filter + BK2F: u4, + /// Break 2 enable + BK2E: u1, + /// Break 2 polarity + BK2P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x44); + + /// address: 0x40015048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001504c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40015054 + /// capture/compare mode register 3 (output + /// mode) + pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Output compare 5 fast + /// enable + OC5FE: u1, + /// Output compare 5 preload + /// enable + OC5PE: u1, + /// Output compare 5 mode + OC5M: u3, + /// Output compare 5 clear + /// enable + OC5CE: u1, + reserved2: u1, + reserved3: u1, + /// Output compare 6 fast + /// enable + OC6FE: u1, + /// Output compare 6 preload + /// enable + OC6PE: u1, + /// Output compare 6 mode + OC6M: u3, + /// Output compare 6 clear + /// enable + OC6CE: u1, + /// Outout Compare 5 mode bit + /// 3 + OC5M_3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Outout Compare 6 mode bit + /// 3 + OC6M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x54); + + /// address: 0x40015058 + /// capture/compare register 5 + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 5 value + CCR5: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Group Channel 5 and Channel + /// 1 + GC5C1: u1, + /// Group Channel 5 and Channel + /// 2 + GC5C2: u1, + /// Group Channel 5 and Channel + /// 3 + GC5C3: u1, + }), base_address + 0x58); + + /// address: 0x4001505c + /// capture/compare register 6 + pub const CCR6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c); + + /// address: 0x40015060 + /// option registers + pub const OR = @intToPtr(*volatile Mmio(32, packed struct{ + /// TIM1_ETR_ADC1 remapping + /// capability + TIM1_ETR_ADC1_RMP: u2, + /// TIM1_ETR_ADC4 remapping + /// capability + TIM1_ETR_ADC4_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x60); + }; + /// Advanced-timers + pub const TIM8 = struct { + pub const base_address = 0x40013400; + + /// address: 0x40013400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40013404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + reserved1: u1, + /// Output Idle state 5 + OIS5: u1, + reserved2: u1, + /// Output Idle state 6 + OIS6: u1, + reserved3: u1, + /// Master mode selection 2 + MMS2: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40013408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit 3 + SMS3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4001340c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40013410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + /// Break 2 interrupt flag + B2IF: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 5 interrupt + /// flag + C5IF: u1, + /// Capture/Compare 6 interrupt + /// flag + C6IF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x10); + + /// address: 0x40013414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + /// Break 2 generation + B2G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x14); + + /// address: 0x40013418 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + /// Output Compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40013418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001341c + /// capture/compare mode register (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + /// Output Compare 3 mode bit + /// 3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 4 mode bit + /// 3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x4001341c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40013420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved0: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + /// Capture/Compare 5 output + /// enable + CC5E: u1, + /// Capture/Compare 5 output + /// Polarity + CC5P: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 6 output + /// enable + CC6E: u1, + /// Capture/Compare 6 output + /// Polarity + CC6P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x20); + + /// address: 0x40013424 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40013428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001342c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40013430 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x30); + + /// address: 0x40013434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40013438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001343c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40013440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40013444 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + /// Break 2 filter + BK2F: u4, + /// Break 2 enable + BK2E: u1, + /// Break 2 polarity + BK2P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x44); + + /// address: 0x40013448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001344c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40013454 + /// capture/compare mode register 3 (output + /// mode) + pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Output compare 5 fast + /// enable + OC5FE: u1, + /// Output compare 5 preload + /// enable + OC5PE: u1, + /// Output compare 5 mode + OC5M: u3, + /// Output compare 5 clear + /// enable + OC5CE: u1, + reserved2: u1, + reserved3: u1, + /// Output compare 6 fast + /// enable + OC6FE: u1, + /// Output compare 6 preload + /// enable + OC6PE: u1, + /// Output compare 6 mode + OC6M: u3, + /// Output compare 6 clear + /// enable + OC6CE: u1, + /// Outout Compare 5 mode bit + /// 3 + OC5M_3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Outout Compare 6 mode bit + /// 3 + OC6M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x54); + + /// address: 0x40013458 + /// capture/compare register 5 + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 5 value + CCR5: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Group Channel 5 and Channel + /// 1 + GC5C1: u1, + /// Group Channel 5 and Channel + /// 2 + GC5C2: u1, + /// Group Channel 5 and Channel + /// 3 + GC5C3: u1, + }), base_address + 0x58); + + /// address: 0x4001345c + /// capture/compare register 6 + pub const CCR6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c); + + /// address: 0x40013460 + /// option registers + pub const OR = @intToPtr(*volatile Mmio(32, packed struct{ + /// TIM8_ETR_ADC2 remapping + /// capability + TIM8_ETR_ADC2_RMP: u2, + /// TIM8_ETR_ADC3 remapping + /// capability + TIM8_ETR_ADC3_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x60); + }; + /// Analog-to-Digital Converter + pub const ADC1 = struct { + pub const base_address = 0x50000000; + + /// address: 0x50000000 + /// interrupt and status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDY + ADRDY: u1, + /// EOSMP + EOSMP: u1, + /// EOC + EOC: u1, + /// EOS + EOS: u1, + /// OVR + OVR: u1, + /// JEOC + JEOC: u1, + /// JEOS + JEOS: u1, + /// AWD1 + AWD1: u1, + /// AWD2 + AWD2: u1, + /// AWD3 + AWD3: u1, + /// JQOVF + JQOVF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x0); + + /// address: 0x50000004 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDYIE + ADRDYIE: u1, + /// EOSMPIE + EOSMPIE: u1, + /// EOCIE + EOCIE: u1, + /// EOSIE + EOSIE: u1, + /// OVRIE + OVRIE: u1, + /// JEOCIE + JEOCIE: u1, + /// JEOSIE + JEOSIE: u1, + /// AWD1IE + AWD1IE: u1, + /// AWD2IE + AWD2IE: u1, + /// AWD3IE + AWD3IE: u1, + /// JQOVFIE + JQOVFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x50000008 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADEN + ADEN: u1, + /// ADDIS + ADDIS: u1, + /// ADSTART + ADSTART: u1, + /// JADSTART + JADSTART: u1, + /// ADSTP + ADSTP: u1, + /// JADSTP + JADSTP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADVREGEN + ADVREGEN: u1, + /// DEEPPWD + DEEPPWD: u1, + /// ADCALDIF + ADCALDIF: u1, + /// ADCAL + ADCAL: u1, + }), base_address + 0x8); + + /// address: 0x5000000c + /// configuration register + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMAEN + DMAEN: u1, + /// DMACFG + DMACFG: u1, + reserved0: u1, + /// RES + RES: u2, + /// ALIGN + ALIGN: u1, + /// EXTSEL + EXTSEL: u4, + /// EXTEN + EXTEN: u2, + /// OVRMOD + OVRMOD: u1, + /// CONT + CONT: u1, + /// AUTDLY + AUTDLY: u1, + /// AUTOFF + AUTOFF: u1, + /// DISCEN + DISCEN: u1, + /// DISCNUM + DISCNUM: u3, + /// JDISCEN + JDISCEN: u1, + /// JQM + JQM: u1, + /// AWD1SGL + AWD1SGL: u1, + /// AWD1EN + AWD1EN: u1, + /// JAWD1EN + JAWD1EN: u1, + /// JAUTO + JAUTO: u1, + /// AWDCH1CH + AWDCH1CH: u5, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x50000014 + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// SMP1 + SMP1: u3, + /// SMP2 + SMP2: u3, + /// SMP3 + SMP3: u3, + /// SMP4 + SMP4: u3, + /// SMP5 + SMP5: u3, + /// SMP6 + SMP6: u3, + /// SMP7 + SMP7: u3, + /// SMP8 + SMP8: u3, + /// SMP9 + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x50000018 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SMP10 + SMP10: u3, + /// SMP11 + SMP11: u3, + /// SMP12 + SMP12: u3, + /// SMP13 + SMP13: u3, + /// SMP14 + SMP14: u3, + /// SMP15 + SMP15: u3, + /// SMP16 + SMP16: u3, + /// SMP17 + SMP17: u3, + /// SMP18 + SMP18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x50000020 + /// watchdog threshold register 1 + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT1 + LT1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// HT1 + HT1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x50000024 + /// watchdog threshold register + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT2 + LT2: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT2 + HT2: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x50000028 + /// watchdog threshold register 3 + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT3 + LT3: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT3 + HT3: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x28); + + /// address: 0x50000030 + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// L3 + L3: u4, + reserved0: u1, + reserved1: u1, + /// SQ1 + SQ1: u5, + reserved2: u1, + /// SQ2 + SQ2: u5, + reserved3: u1, + /// SQ3 + SQ3: u5, + reserved4: u1, + /// SQ4 + SQ4: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x30); + + /// address: 0x50000034 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ5 + SQ5: u5, + reserved0: u1, + /// SQ6 + SQ6: u5, + reserved1: u1, + /// SQ7 + SQ7: u5, + reserved2: u1, + /// SQ8 + SQ8: u5, + reserved3: u1, + /// SQ9 + SQ9: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x34); + + /// address: 0x50000038 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ10 + SQ10: u5, + reserved0: u1, + /// SQ11 + SQ11: u5, + reserved1: u1, + /// SQ12 + SQ12: u5, + reserved2: u1, + /// SQ13 + SQ13: u5, + reserved3: u1, + /// SQ14 + SQ14: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x38); + + /// address: 0x5000003c + /// regular sequence register 4 + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ15 + SQ15: u5, + reserved0: u1, + /// SQ16 + SQ16: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x3c); + + /// address: 0x50000040 + /// regular Data Register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// regularDATA + regularDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x5000004c + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// JL + JL: u2, + /// JEXTSEL + JEXTSEL: u4, + /// JEXTEN + JEXTEN: u2, + /// JSQ1 + JSQ1: u5, + reserved0: u1, + /// JSQ2 + JSQ2: u5, + reserved1: u1, + /// JSQ3 + JSQ3: u5, + reserved2: u1, + /// JSQ4 + JSQ4: u5, + padding0: u1, + }), base_address + 0x4c); + + /// address: 0x50000060 + /// offset register 1 + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET1 + OFFSET1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET1_CH + OFFSET1_CH: u5, + /// OFFSET1_EN + OFFSET1_EN: u1, + }), base_address + 0x60); + + /// address: 0x50000064 + /// offset register 2 + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET2 + OFFSET2: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET2_CH + OFFSET2_CH: u5, + /// OFFSET2_EN + OFFSET2_EN: u1, + }), base_address + 0x64); + + /// address: 0x50000068 + /// offset register 3 + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET3 + OFFSET3: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET3_CH + OFFSET3_CH: u5, + /// OFFSET3_EN + OFFSET3_EN: u1, + }), base_address + 0x68); + + /// address: 0x5000006c + /// offset register 4 + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET4 + OFFSET4: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET4_CH + OFFSET4_CH: u5, + /// OFFSET4_EN + OFFSET4_EN: u1, + }), base_address + 0x6c); + + /// address: 0x50000080 + /// injected data register 1 + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA1 + JDATA1: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x80); + + /// address: 0x50000084 + /// injected data register 2 + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA2 + JDATA2: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x50000088 + /// injected data register 3 + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA3 + JDATA3: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x88); + + /// address: 0x5000008c + /// injected data register 4 + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA4 + JDATA4: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x500000a0 + /// Analog Watchdog 2 Configuration + /// Register + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD2CH + AWD2CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa0); + + /// address: 0x500000a4 + /// Analog Watchdog 3 Configuration + /// Register + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD3CH + AWD3CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa4); + + /// address: 0x500000b0 + /// Differential Mode Selection Register + /// 2 + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Differential mode for channels 15 to + /// 1 + DIFSEL_1_15: u15, + /// Differential mode for channels 18 to + /// 16 + DIFSEL_16_18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xb0); + + /// address: 0x500000b4 + /// Calibration Factors + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + /// CALFACT_S + CALFACT_S: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// CALFACT_D + CALFACT_D: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0xb4); + }; + pub const ADC2 = struct { + pub const base_address = 0x50000100; + + /// address: 0x50000100 + /// interrupt and status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDY + ADRDY: u1, + /// EOSMP + EOSMP: u1, + /// EOC + EOC: u1, + /// EOS + EOS: u1, + /// OVR + OVR: u1, + /// JEOC + JEOC: u1, + /// JEOS + JEOS: u1, + /// AWD1 + AWD1: u1, + /// AWD2 + AWD2: u1, + /// AWD3 + AWD3: u1, + /// JQOVF + JQOVF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x0); + + /// address: 0x50000104 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDYIE + ADRDYIE: u1, + /// EOSMPIE + EOSMPIE: u1, + /// EOCIE + EOCIE: u1, + /// EOSIE + EOSIE: u1, + /// OVRIE + OVRIE: u1, + /// JEOCIE + JEOCIE: u1, + /// JEOSIE + JEOSIE: u1, + /// AWD1IE + AWD1IE: u1, + /// AWD2IE + AWD2IE: u1, + /// AWD3IE + AWD3IE: u1, + /// JQOVFIE + JQOVFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x50000108 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADEN + ADEN: u1, + /// ADDIS + ADDIS: u1, + /// ADSTART + ADSTART: u1, + /// JADSTART + JADSTART: u1, + /// ADSTP + ADSTP: u1, + /// JADSTP + JADSTP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADVREGEN + ADVREGEN: u1, + /// DEEPPWD + DEEPPWD: u1, + /// ADCALDIF + ADCALDIF: u1, + /// ADCAL + ADCAL: u1, + }), base_address + 0x8); + + /// address: 0x5000010c + /// configuration register + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMAEN + DMAEN: u1, + /// DMACFG + DMACFG: u1, + reserved0: u1, + /// RES + RES: u2, + /// ALIGN + ALIGN: u1, + /// EXTSEL + EXTSEL: u4, + /// EXTEN + EXTEN: u2, + /// OVRMOD + OVRMOD: u1, + /// CONT + CONT: u1, + /// AUTDLY + AUTDLY: u1, + /// AUTOFF + AUTOFF: u1, + /// DISCEN + DISCEN: u1, + /// DISCNUM + DISCNUM: u3, + /// JDISCEN + JDISCEN: u1, + /// JQM + JQM: u1, + /// AWD1SGL + AWD1SGL: u1, + /// AWD1EN + AWD1EN: u1, + /// JAWD1EN + JAWD1EN: u1, + /// JAUTO + JAUTO: u1, + /// AWDCH1CH + AWDCH1CH: u5, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x50000114 + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// SMP1 + SMP1: u3, + /// SMP2 + SMP2: u3, + /// SMP3 + SMP3: u3, + /// SMP4 + SMP4: u3, + /// SMP5 + SMP5: u3, + /// SMP6 + SMP6: u3, + /// SMP7 + SMP7: u3, + /// SMP8 + SMP8: u3, + /// SMP9 + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x50000118 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SMP10 + SMP10: u3, + /// SMP11 + SMP11: u3, + /// SMP12 + SMP12: u3, + /// SMP13 + SMP13: u3, + /// SMP14 + SMP14: u3, + /// SMP15 + SMP15: u3, + /// SMP16 + SMP16: u3, + /// SMP17 + SMP17: u3, + /// SMP18 + SMP18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x50000120 + /// watchdog threshold register 1 + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT1 + LT1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// HT1 + HT1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x50000124 + /// watchdog threshold register + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT2 + LT2: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT2 + HT2: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x50000128 + /// watchdog threshold register 3 + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT3 + LT3: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT3 + HT3: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x28); + + /// address: 0x50000130 + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// L3 + L3: u4, + reserved0: u1, + reserved1: u1, + /// SQ1 + SQ1: u5, + reserved2: u1, + /// SQ2 + SQ2: u5, + reserved3: u1, + /// SQ3 + SQ3: u5, + reserved4: u1, + /// SQ4 + SQ4: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x30); + + /// address: 0x50000134 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ5 + SQ5: u5, + reserved0: u1, + /// SQ6 + SQ6: u5, + reserved1: u1, + /// SQ7 + SQ7: u5, + reserved2: u1, + /// SQ8 + SQ8: u5, + reserved3: u1, + /// SQ9 + SQ9: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x34); + + /// address: 0x50000138 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ10 + SQ10: u5, + reserved0: u1, + /// SQ11 + SQ11: u5, + reserved1: u1, + /// SQ12 + SQ12: u5, + reserved2: u1, + /// SQ13 + SQ13: u5, + reserved3: u1, + /// SQ14 + SQ14: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x38); + + /// address: 0x5000013c + /// regular sequence register 4 + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ15 + SQ15: u5, + reserved0: u1, + /// SQ16 + SQ16: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x3c); + + /// address: 0x50000140 + /// regular Data Register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// regularDATA + regularDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x5000014c + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// JL + JL: u2, + /// JEXTSEL + JEXTSEL: u4, + /// JEXTEN + JEXTEN: u2, + /// JSQ1 + JSQ1: u5, + reserved0: u1, + /// JSQ2 + JSQ2: u5, + reserved1: u1, + /// JSQ3 + JSQ3: u5, + reserved2: u1, + /// JSQ4 + JSQ4: u5, + padding0: u1, + }), base_address + 0x4c); + + /// address: 0x50000160 + /// offset register 1 + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET1 + OFFSET1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET1_CH + OFFSET1_CH: u5, + /// OFFSET1_EN + OFFSET1_EN: u1, + }), base_address + 0x60); + + /// address: 0x50000164 + /// offset register 2 + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET2 + OFFSET2: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET2_CH + OFFSET2_CH: u5, + /// OFFSET2_EN + OFFSET2_EN: u1, + }), base_address + 0x64); + + /// address: 0x50000168 + /// offset register 3 + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET3 + OFFSET3: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET3_CH + OFFSET3_CH: u5, + /// OFFSET3_EN + OFFSET3_EN: u1, + }), base_address + 0x68); + + /// address: 0x5000016c + /// offset register 4 + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET4 + OFFSET4: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET4_CH + OFFSET4_CH: u5, + /// OFFSET4_EN + OFFSET4_EN: u1, + }), base_address + 0x6c); + + /// address: 0x50000180 + /// injected data register 1 + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA1 + JDATA1: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x80); + + /// address: 0x50000184 + /// injected data register 2 + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA2 + JDATA2: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x50000188 + /// injected data register 3 + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA3 + JDATA3: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x88); + + /// address: 0x5000018c + /// injected data register 4 + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA4 + JDATA4: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x500001a0 + /// Analog Watchdog 2 Configuration + /// Register + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD2CH + AWD2CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa0); + + /// address: 0x500001a4 + /// Analog Watchdog 3 Configuration + /// Register + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD3CH + AWD3CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa4); + + /// address: 0x500001b0 + /// Differential Mode Selection Register + /// 2 + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Differential mode for channels 15 to + /// 1 + DIFSEL_1_15: u15, + /// Differential mode for channels 18 to + /// 16 + DIFSEL_16_18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xb0); + + /// address: 0x500001b4 + /// Calibration Factors + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + /// CALFACT_S + CALFACT_S: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// CALFACT_D + CALFACT_D: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0xb4); + }; + pub const ADC3 = struct { + pub const base_address = 0x50000400; + + /// address: 0x50000400 + /// interrupt and status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDY + ADRDY: u1, + /// EOSMP + EOSMP: u1, + /// EOC + EOC: u1, + /// EOS + EOS: u1, + /// OVR + OVR: u1, + /// JEOC + JEOC: u1, + /// JEOS + JEOS: u1, + /// AWD1 + AWD1: u1, + /// AWD2 + AWD2: u1, + /// AWD3 + AWD3: u1, + /// JQOVF + JQOVF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x0); + + /// address: 0x50000404 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDYIE + ADRDYIE: u1, + /// EOSMPIE + EOSMPIE: u1, + /// EOCIE + EOCIE: u1, + /// EOSIE + EOSIE: u1, + /// OVRIE + OVRIE: u1, + /// JEOCIE + JEOCIE: u1, + /// JEOSIE + JEOSIE: u1, + /// AWD1IE + AWD1IE: u1, + /// AWD2IE + AWD2IE: u1, + /// AWD3IE + AWD3IE: u1, + /// JQOVFIE + JQOVFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x50000408 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADEN + ADEN: u1, + /// ADDIS + ADDIS: u1, + /// ADSTART + ADSTART: u1, + /// JADSTART + JADSTART: u1, + /// ADSTP + ADSTP: u1, + /// JADSTP + JADSTP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADVREGEN + ADVREGEN: u1, + /// DEEPPWD + DEEPPWD: u1, + /// ADCALDIF + ADCALDIF: u1, + /// ADCAL + ADCAL: u1, + }), base_address + 0x8); + + /// address: 0x5000040c + /// configuration register + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMAEN + DMAEN: u1, + /// DMACFG + DMACFG: u1, + reserved0: u1, + /// RES + RES: u2, + /// ALIGN + ALIGN: u1, + /// EXTSEL + EXTSEL: u4, + /// EXTEN + EXTEN: u2, + /// OVRMOD + OVRMOD: u1, + /// CONT + CONT: u1, + /// AUTDLY + AUTDLY: u1, + /// AUTOFF + AUTOFF: u1, + /// DISCEN + DISCEN: u1, + /// DISCNUM + DISCNUM: u3, + /// JDISCEN + JDISCEN: u1, + /// JQM + JQM: u1, + /// AWD1SGL + AWD1SGL: u1, + /// AWD1EN + AWD1EN: u1, + /// JAWD1EN + JAWD1EN: u1, + /// JAUTO + JAUTO: u1, + /// AWDCH1CH + AWDCH1CH: u5, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x50000414 + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// SMP1 + SMP1: u3, + /// SMP2 + SMP2: u3, + /// SMP3 + SMP3: u3, + /// SMP4 + SMP4: u3, + /// SMP5 + SMP5: u3, + /// SMP6 + SMP6: u3, + /// SMP7 + SMP7: u3, + /// SMP8 + SMP8: u3, + /// SMP9 + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x50000418 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SMP10 + SMP10: u3, + /// SMP11 + SMP11: u3, + /// SMP12 + SMP12: u3, + /// SMP13 + SMP13: u3, + /// SMP14 + SMP14: u3, + /// SMP15 + SMP15: u3, + /// SMP16 + SMP16: u3, + /// SMP17 + SMP17: u3, + /// SMP18 + SMP18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x50000420 + /// watchdog threshold register 1 + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT1 + LT1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// HT1 + HT1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x50000424 + /// watchdog threshold register + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT2 + LT2: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT2 + HT2: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x50000428 + /// watchdog threshold register 3 + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT3 + LT3: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT3 + HT3: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x28); + + /// address: 0x50000430 + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// L3 + L3: u4, + reserved0: u1, + reserved1: u1, + /// SQ1 + SQ1: u5, + reserved2: u1, + /// SQ2 + SQ2: u5, + reserved3: u1, + /// SQ3 + SQ3: u5, + reserved4: u1, + /// SQ4 + SQ4: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x30); + + /// address: 0x50000434 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ5 + SQ5: u5, + reserved0: u1, + /// SQ6 + SQ6: u5, + reserved1: u1, + /// SQ7 + SQ7: u5, + reserved2: u1, + /// SQ8 + SQ8: u5, + reserved3: u1, + /// SQ9 + SQ9: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x34); + + /// address: 0x50000438 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ10 + SQ10: u5, + reserved0: u1, + /// SQ11 + SQ11: u5, + reserved1: u1, + /// SQ12 + SQ12: u5, + reserved2: u1, + /// SQ13 + SQ13: u5, + reserved3: u1, + /// SQ14 + SQ14: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x38); + + /// address: 0x5000043c + /// regular sequence register 4 + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ15 + SQ15: u5, + reserved0: u1, + /// SQ16 + SQ16: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x3c); + + /// address: 0x50000440 + /// regular Data Register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// regularDATA + regularDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x5000044c + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// JL + JL: u2, + /// JEXTSEL + JEXTSEL: u4, + /// JEXTEN + JEXTEN: u2, + /// JSQ1 + JSQ1: u5, + reserved0: u1, + /// JSQ2 + JSQ2: u5, + reserved1: u1, + /// JSQ3 + JSQ3: u5, + reserved2: u1, + /// JSQ4 + JSQ4: u5, + padding0: u1, + }), base_address + 0x4c); + + /// address: 0x50000460 + /// offset register 1 + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET1 + OFFSET1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET1_CH + OFFSET1_CH: u5, + /// OFFSET1_EN + OFFSET1_EN: u1, + }), base_address + 0x60); + + /// address: 0x50000464 + /// offset register 2 + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET2 + OFFSET2: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET2_CH + OFFSET2_CH: u5, + /// OFFSET2_EN + OFFSET2_EN: u1, + }), base_address + 0x64); + + /// address: 0x50000468 + /// offset register 3 + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET3 + OFFSET3: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET3_CH + OFFSET3_CH: u5, + /// OFFSET3_EN + OFFSET3_EN: u1, + }), base_address + 0x68); + + /// address: 0x5000046c + /// offset register 4 + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET4 + OFFSET4: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET4_CH + OFFSET4_CH: u5, + /// OFFSET4_EN + OFFSET4_EN: u1, + }), base_address + 0x6c); + + /// address: 0x50000480 + /// injected data register 1 + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA1 + JDATA1: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x80); + + /// address: 0x50000484 + /// injected data register 2 + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA2 + JDATA2: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x50000488 + /// injected data register 3 + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA3 + JDATA3: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x88); + + /// address: 0x5000048c + /// injected data register 4 + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA4 + JDATA4: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x500004a0 + /// Analog Watchdog 2 Configuration + /// Register + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD2CH + AWD2CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa0); + + /// address: 0x500004a4 + /// Analog Watchdog 3 Configuration + /// Register + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD3CH + AWD3CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa4); + + /// address: 0x500004b0 + /// Differential Mode Selection Register + /// 2 + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Differential mode for channels 15 to + /// 1 + DIFSEL_1_15: u15, + /// Differential mode for channels 18 to + /// 16 + DIFSEL_16_18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xb0); + + /// address: 0x500004b4 + /// Calibration Factors + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + /// CALFACT_S + CALFACT_S: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// CALFACT_D + CALFACT_D: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0xb4); + }; + pub const ADC4 = struct { + pub const base_address = 0x50000500; + + /// address: 0x50000500 + /// interrupt and status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDY + ADRDY: u1, + /// EOSMP + EOSMP: u1, + /// EOC + EOC: u1, + /// EOS + EOS: u1, + /// OVR + OVR: u1, + /// JEOC + JEOC: u1, + /// JEOS + JEOS: u1, + /// AWD1 + AWD1: u1, + /// AWD2 + AWD2: u1, + /// AWD3 + AWD3: u1, + /// JQOVF + JQOVF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x0); + + /// address: 0x50000504 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDYIE + ADRDYIE: u1, + /// EOSMPIE + EOSMPIE: u1, + /// EOCIE + EOCIE: u1, + /// EOSIE + EOSIE: u1, + /// OVRIE + OVRIE: u1, + /// JEOCIE + JEOCIE: u1, + /// JEOSIE + JEOSIE: u1, + /// AWD1IE + AWD1IE: u1, + /// AWD2IE + AWD2IE: u1, + /// AWD3IE + AWD3IE: u1, + /// JQOVFIE + JQOVFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x50000508 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADEN + ADEN: u1, + /// ADDIS + ADDIS: u1, + /// ADSTART + ADSTART: u1, + /// JADSTART + JADSTART: u1, + /// ADSTP + ADSTP: u1, + /// JADSTP + JADSTP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADVREGEN + ADVREGEN: u1, + /// DEEPPWD + DEEPPWD: u1, + /// ADCALDIF + ADCALDIF: u1, + /// ADCAL + ADCAL: u1, + }), base_address + 0x8); + + /// address: 0x5000050c + /// configuration register + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMAEN + DMAEN: u1, + /// DMACFG + DMACFG: u1, + reserved0: u1, + /// RES + RES: u2, + /// ALIGN + ALIGN: u1, + /// EXTSEL + EXTSEL: u4, + /// EXTEN + EXTEN: u2, + /// OVRMOD + OVRMOD: u1, + /// CONT + CONT: u1, + /// AUTDLY + AUTDLY: u1, + /// AUTOFF + AUTOFF: u1, + /// DISCEN + DISCEN: u1, + /// DISCNUM + DISCNUM: u3, + /// JDISCEN + JDISCEN: u1, + /// JQM + JQM: u1, + /// AWD1SGL + AWD1SGL: u1, + /// AWD1EN + AWD1EN: u1, + /// JAWD1EN + JAWD1EN: u1, + /// JAUTO + JAUTO: u1, + /// AWDCH1CH + AWDCH1CH: u5, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x50000514 + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// SMP1 + SMP1: u3, + /// SMP2 + SMP2: u3, + /// SMP3 + SMP3: u3, + /// SMP4 + SMP4: u3, + /// SMP5 + SMP5: u3, + /// SMP6 + SMP6: u3, + /// SMP7 + SMP7: u3, + /// SMP8 + SMP8: u3, + /// SMP9 + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x50000518 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SMP10 + SMP10: u3, + /// SMP11 + SMP11: u3, + /// SMP12 + SMP12: u3, + /// SMP13 + SMP13: u3, + /// SMP14 + SMP14: u3, + /// SMP15 + SMP15: u3, + /// SMP16 + SMP16: u3, + /// SMP17 + SMP17: u3, + /// SMP18 + SMP18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x50000520 + /// watchdog threshold register 1 + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT1 + LT1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// HT1 + HT1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x50000524 + /// watchdog threshold register + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT2 + LT2: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT2 + HT2: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x50000528 + /// watchdog threshold register 3 + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT3 + LT3: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT3 + HT3: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x28); + + /// address: 0x50000530 + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// L3 + L3: u4, + reserved0: u1, + reserved1: u1, + /// SQ1 + SQ1: u5, + reserved2: u1, + /// SQ2 + SQ2: u5, + reserved3: u1, + /// SQ3 + SQ3: u5, + reserved4: u1, + /// SQ4 + SQ4: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x30); + + /// address: 0x50000534 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ5 + SQ5: u5, + reserved0: u1, + /// SQ6 + SQ6: u5, + reserved1: u1, + /// SQ7 + SQ7: u5, + reserved2: u1, + /// SQ8 + SQ8: u5, + reserved3: u1, + /// SQ9 + SQ9: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x34); + + /// address: 0x50000538 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ10 + SQ10: u5, + reserved0: u1, + /// SQ11 + SQ11: u5, + reserved1: u1, + /// SQ12 + SQ12: u5, + reserved2: u1, + /// SQ13 + SQ13: u5, + reserved3: u1, + /// SQ14 + SQ14: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x38); + + /// address: 0x5000053c + /// regular sequence register 4 + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ15 + SQ15: u5, + reserved0: u1, + /// SQ16 + SQ16: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x3c); + + /// address: 0x50000540 + /// regular Data Register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// regularDATA + regularDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x5000054c + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// JL + JL: u2, + /// JEXTSEL + JEXTSEL: u4, + /// JEXTEN + JEXTEN: u2, + /// JSQ1 + JSQ1: u5, + reserved0: u1, + /// JSQ2 + JSQ2: u5, + reserved1: u1, + /// JSQ3 + JSQ3: u5, + reserved2: u1, + /// JSQ4 + JSQ4: u5, + padding0: u1, + }), base_address + 0x4c); + + /// address: 0x50000560 + /// offset register 1 + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET1 + OFFSET1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET1_CH + OFFSET1_CH: u5, + /// OFFSET1_EN + OFFSET1_EN: u1, + }), base_address + 0x60); + + /// address: 0x50000564 + /// offset register 2 + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET2 + OFFSET2: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET2_CH + OFFSET2_CH: u5, + /// OFFSET2_EN + OFFSET2_EN: u1, + }), base_address + 0x64); + + /// address: 0x50000568 + /// offset register 3 + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET3 + OFFSET3: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET3_CH + OFFSET3_CH: u5, + /// OFFSET3_EN + OFFSET3_EN: u1, + }), base_address + 0x68); + + /// address: 0x5000056c + /// offset register 4 + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET4 + OFFSET4: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET4_CH + OFFSET4_CH: u5, + /// OFFSET4_EN + OFFSET4_EN: u1, + }), base_address + 0x6c); + + /// address: 0x50000580 + /// injected data register 1 + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA1 + JDATA1: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x80); + + /// address: 0x50000584 + /// injected data register 2 + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA2 + JDATA2: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x50000588 + /// injected data register 3 + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA3 + JDATA3: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x88); + + /// address: 0x5000058c + /// injected data register 4 + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA4 + JDATA4: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x500005a0 + /// Analog Watchdog 2 Configuration + /// Register + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD2CH + AWD2CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa0); + + /// address: 0x500005a4 + /// Analog Watchdog 3 Configuration + /// Register + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD3CH + AWD3CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa4); + + /// address: 0x500005b0 + /// Differential Mode Selection Register + /// 2 + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Differential mode for channels 15 to + /// 1 + DIFSEL_1_15: u15, + /// Differential mode for channels 18 to + /// 16 + DIFSEL_16_18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xb0); + + /// address: 0x500005b4 + /// Calibration Factors + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + /// CALFACT_S + CALFACT_S: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// CALFACT_D + CALFACT_D: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0xb4); + }; + /// Analog-to-Digital Converter + pub const ADC1_2 = struct { + pub const base_address = 0x50000300; + + /// address: 0x50000300 + /// ADC Common status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDRDY_MST + ADDRDY_MST: u1, + /// EOSMP_MST + EOSMP_MST: u1, + /// EOC_MST + EOC_MST: u1, + /// EOS_MST + EOS_MST: u1, + /// OVR_MST + OVR_MST: u1, + /// JEOC_MST + JEOC_MST: u1, + /// JEOS_MST + JEOS_MST: u1, + /// AWD1_MST + AWD1_MST: u1, + /// AWD2_MST + AWD2_MST: u1, + /// AWD3_MST + AWD3_MST: u1, + /// JQOVF_MST + JQOVF_MST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// ADRDY_SLV + ADRDY_SLV: u1, + /// EOSMP_SLV + EOSMP_SLV: u1, + /// End of regular conversion of the slave + /// ADC + EOC_SLV: u1, + /// End of regular sequence flag of the + /// slave ADC + EOS_SLV: u1, + /// Overrun flag of the slave + /// ADC + OVR_SLV: u1, + /// End of injected conversion flag of the + /// slave ADC + JEOC_SLV: u1, + /// End of injected sequence flag of the + /// slave ADC + JEOS_SLV: u1, + /// Analog watchdog 1 flag of the slave + /// ADC + AWD1_SLV: u1, + /// Analog watchdog 2 flag of the slave + /// ADC + AWD2_SLV: u1, + /// Analog watchdog 3 flag of the slave + /// ADC + AWD3_SLV: u1, + /// Injected Context Queue Overflow flag of + /// the slave ADC + JQOVF_SLV: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x0); + + /// address: 0x50000308 + /// ADC common control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Multi ADC mode selection + MULT: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Delay between 2 sampling + /// phases + DELAY: u4, + reserved3: u1, + /// DMA configuration (for multi-ADC + /// mode) + DMACFG: u1, + /// Direct memory access mode for multi ADC + /// mode + MDMA: u2, + /// ADC clock mode + CKMODE: u2, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// VREFINT enable + VREFEN: u1, + /// Temperature sensor enable + TSEN: u1, + /// VBAT enable + VBATEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x5000030c + /// ADC common regular data register for dual + /// and triple modes + pub const CDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Regular data of the master + /// ADC + RDATA_MST: u16, + /// Regular data of the slave + /// ADC + RDATA_SLV: u16, + }), base_address + 0xc); + }; + pub const ADC3_4 = struct { + pub const base_address = 0x50000700; + + /// address: 0x50000700 + /// ADC Common status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDRDY_MST + ADDRDY_MST: u1, + /// EOSMP_MST + EOSMP_MST: u1, + /// EOC_MST + EOC_MST: u1, + /// EOS_MST + EOS_MST: u1, + /// OVR_MST + OVR_MST: u1, + /// JEOC_MST + JEOC_MST: u1, + /// JEOS_MST + JEOS_MST: u1, + /// AWD1_MST + AWD1_MST: u1, + /// AWD2_MST + AWD2_MST: u1, + /// AWD3_MST + AWD3_MST: u1, + /// JQOVF_MST + JQOVF_MST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// ADRDY_SLV + ADRDY_SLV: u1, + /// EOSMP_SLV + EOSMP_SLV: u1, + /// End of regular conversion of the slave + /// ADC + EOC_SLV: u1, + /// End of regular sequence flag of the + /// slave ADC + EOS_SLV: u1, + /// Overrun flag of the slave + /// ADC + OVR_SLV: u1, + /// End of injected conversion flag of the + /// slave ADC + JEOC_SLV: u1, + /// End of injected sequence flag of the + /// slave ADC + JEOS_SLV: u1, + /// Analog watchdog 1 flag of the slave + /// ADC + AWD1_SLV: u1, + /// Analog watchdog 2 flag of the slave + /// ADC + AWD2_SLV: u1, + /// Analog watchdog 3 flag of the slave + /// ADC + AWD3_SLV: u1, + /// Injected Context Queue Overflow flag of + /// the slave ADC + JQOVF_SLV: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x0); + + /// address: 0x50000708 + /// ADC common control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Multi ADC mode selection + MULT: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Delay between 2 sampling + /// phases + DELAY: u4, + reserved3: u1, + /// DMA configuration (for multi-ADC + /// mode) + DMACFG: u1, + /// Direct memory access mode for multi ADC + /// mode + MDMA: u2, + /// ADC clock mode + CKMODE: u2, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// VREFINT enable + VREFEN: u1, + /// Temperature sensor enable + TSEN: u1, + /// VBAT enable + VBATEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x5000070c + /// ADC common regular data register for dual + /// and triple modes + pub const CDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Regular data of the master + /// ADC + RDATA_MST: u16, + /// Regular data of the slave + /// ADC + RDATA_SLV: u16, + }), base_address + 0xc); + }; + /// System configuration controller _Comparator and + /// Operational amplifier + pub const SYSCFG_COMP_OPAMP = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// configuration register 1 + pub const SYSCFG_CFGR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory mapping selection + /// bits + MEM_MODE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// USB interrupt remap + USB_IT_RMP: u1, + /// Timer 1 ITR3 selection + TIM1_ITR_RMP: u1, + /// DAC trigger remap (when TSEL = + /// 001) + DAC_TRIG_RMP: u1, + /// ADC24 DMA remapping bit + ADC24_DMA_RMP: u1, + reserved3: u1, + reserved4: u1, + /// TIM16 DMA request remapping + /// bit + TIM16_DMA_RMP: u1, + /// TIM17 DMA request remapping + /// bit + TIM17_DMA_RMP: u1, + /// TIM6 and DAC1 DMA request remapping + /// bit + TIM6_DAC1_DMA_RMP: u1, + /// TIM7 and DAC2 DMA request remapping + /// bit + TIM7_DAC2_DMA_RMP: u1, + reserved5: u1, + /// Fast Mode Plus (FM+) driving capability + /// activation bits. + I2C_PB6_FM: u1, + /// Fast Mode Plus (FM+) driving capability + /// activation bits. + I2C_PB7_FM: u1, + /// Fast Mode Plus (FM+) driving capability + /// activation bits. + I2C_PB8_FM: u1, + /// Fast Mode Plus (FM+) driving capability + /// activation bits. + I2C_PB9_FM: u1, + /// I2C1 Fast Mode Plus + I2C1_FM: u1, + /// I2C2 Fast Mode Plus + I2C2_FM: u1, + /// Encoder mode + ENCODER_MODE: u2, + reserved6: u1, + reserved7: u1, + /// Interrupt enable bits from + /// FPU + FPU_IT: u6, + }), base_address + 0x0); + + /// address: 0x40010008 + /// external interrupt configuration register + /// 1 + pub const SYSCFG_EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI 0 configuration bits + EXTI0: u4, + /// EXTI 1 configuration bits + EXTI1: u4, + /// EXTI 2 configuration bits + EXTI2: u4, + /// EXTI 3 configuration bits + EXTI3: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001000c + /// external interrupt configuration register + /// 2 + pub const SYSCFG_EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI 4 configuration bits + EXTI4: u4, + /// EXTI 5 configuration bits + EXTI5: u4, + /// EXTI 6 configuration bits + EXTI6: u4, + /// EXTI 7 configuration bits + EXTI7: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40010010 + /// external interrupt configuration register + /// 3 + pub const SYSCFG_EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI 8 configuration bits + EXTI8: u4, + /// EXTI 9 configuration bits + EXTI9: u4, + /// EXTI 10 configuration bits + EXTI10: u4, + /// EXTI 11 configuration bits + EXTI11: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40010014 + /// external interrupt configuration register + /// 4 + pub const SYSCFG_EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI 12 configuration bits + EXTI12: u4, + /// EXTI 13 configuration bits + EXTI13: u4, + /// EXTI 14 configuration bits + EXTI14: u4, + /// EXTI 15 configuration bits + EXTI15: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40010018 + /// configuration register 2 + pub const SYSCFG_CFGR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Cortex-M0 LOCKUP bit enable + /// bit + LOCUP_LOCK: u1, + /// SRAM parity lock bit + SRAM_PARITY_LOCK: u1, + /// PVD lock enable bit + PVD_LOCK: u1, + reserved0: u1, + /// Bypass address bit 29 in parity + /// calculation + BYP_ADD_PAR: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// SRAM parity flag + SRAM_PEF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x18); + + /// address: 0x40010004 + /// CCM SRAM protection register + pub const SYSCFG_RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CCM SRAM page write protection + /// bit + PAGE0_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE1_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE2_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE3_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE4_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE5_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE6_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE7_WP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x4001001c + /// control and status register + pub const COMP1_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 1 enable + COMP1EN: u1, + /// COMP1_INP_DAC + COMP1_INP_DAC: u1, + /// Comparator 1 mode + COMP1MODE: u2, + /// Comparator 1 inverting input + /// selection + COMP1INSEL: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Comparator 1 output + /// selection + COMP1_OUT_SEL: u4, + reserved3: u1, + /// Comparator 1 output + /// polarity + COMP1POL: u1, + /// Comparator 1 hysteresis + COMP1HYST: u2, + /// Comparator 1 blanking + /// source + COMP1_BLANKING: u3, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Comparator 1 output + COMP1OUT: u1, + /// Comparator 1 lock + COMP1LOCK: u1, + }), base_address + 0x1c); + + /// address: 0x40010020 + /// control and status register + pub const COMP2_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 2 enable + COMP2EN: u1, + reserved0: u1, + /// Comparator 2 mode + COMP2MODE: u2, + /// Comparator 2 inverting input + /// selection + COMP2INSEL: u3, + /// Comparator 2 non inverted input + /// selection + COMP2INPSEL: u1, + reserved1: u1, + /// Comparator 1inverting input + /// selection + COMP2INMSEL: u1, + /// Comparator 2 output + /// selection + COMP2_OUT_SEL: u4, + reserved2: u1, + /// Comparator 2 output + /// polarity + COMP2POL: u1, + /// Comparator 2 hysteresis + COMP2HYST: u2, + /// Comparator 2 blanking + /// source + COMP2_BLANKING: u3, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Comparator 2 lock + COMP2LOCK: u1, + }), base_address + 0x20); + + /// address: 0x40010024 + /// control and status register + pub const COMP3_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 3 enable + COMP3EN: u1, + reserved0: u1, + /// Comparator 3 mode + COMP3MODE: u2, + /// Comparator 3 inverting input + /// selection + COMP3INSEL: u3, + /// Comparator 3 non inverted input + /// selection + COMP3INPSEL: u1, + reserved1: u1, + reserved2: u1, + /// Comparator 3 output + /// selection + COMP3_OUT_SEL: u4, + reserved3: u1, + /// Comparator 3 output + /// polarity + COMP3POL: u1, + /// Comparator 3 hysteresis + COMP3HYST: u2, + /// Comparator 3 blanking + /// source + COMP3_BLANKING: u3, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Comparator 3 output + COMP3OUT: u1, + /// Comparator 3 lock + COMP3LOCK: u1, + }), base_address + 0x24); + + /// address: 0x40010028 + /// control and status register + pub const COMP4_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 4 enable + COMP4EN: u1, + reserved0: u1, + /// Comparator 4 mode + COMP4MODE: u2, + /// Comparator 4 inverting input + /// selection + COMP4INSEL: u3, + /// Comparator 4 non inverted input + /// selection + COMP4INPSEL: u1, + reserved1: u1, + /// Comparator 4 window mode + COM4WINMODE: u1, + /// Comparator 4 output + /// selection + COMP4_OUT_SEL: u4, + reserved2: u1, + /// Comparator 4 output + /// polarity + COMP4POL: u1, + /// Comparator 4 hysteresis + COMP4HYST: u2, + /// Comparator 4 blanking + /// source + COMP4_BLANKING: u3, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Comparator 4 output + COMP4OUT: u1, + /// Comparator 4 lock + COMP4LOCK: u1, + }), base_address + 0x28); + + /// address: 0x4001002c + /// control and status register + pub const COMP5_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 5 enable + COMP5EN: u1, + reserved0: u1, + /// Comparator 5 mode + COMP5MODE: u2, + /// Comparator 5 inverting input + /// selection + COMP5INSEL: u3, + /// Comparator 5 non inverted input + /// selection + COMP5INPSEL: u1, + reserved1: u1, + reserved2: u1, + /// Comparator 5 output + /// selection + COMP5_OUT_SEL: u4, + reserved3: u1, + /// Comparator 5 output + /// polarity + COMP5POL: u1, + /// Comparator 5 hysteresis + COMP5HYST: u2, + /// Comparator 5 blanking + /// source + COMP5_BLANKING: u3, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Comparator51 output + COMP5OUT: u1, + /// Comparator 5 lock + COMP5LOCK: u1, + }), base_address + 0x2c); + + /// address: 0x40010030 + /// control and status register + pub const COMP6_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 6 enable + COMP6EN: u1, + reserved0: u1, + /// Comparator 6 mode + COMP6MODE: u2, + /// Comparator 6 inverting input + /// selection + COMP6INSEL: u3, + /// Comparator 6 non inverted input + /// selection + COMP6INPSEL: u1, + reserved1: u1, + /// Comparator 6 window mode + COM6WINMODE: u1, + /// Comparator 6 output + /// selection + COMP6_OUT_SEL: u4, + reserved2: u1, + /// Comparator 6 output + /// polarity + COMP6POL: u1, + /// Comparator 6 hysteresis + COMP6HYST: u2, + /// Comparator 6 blanking + /// source + COMP6_BLANKING: u3, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Comparator 6 output + COMP6OUT: u1, + /// Comparator 6 lock + COMP6LOCK: u1, + }), base_address + 0x30); + + /// address: 0x40010034 + /// control and status register + pub const COMP7_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 7 enable + COMP7EN: u1, + reserved0: u1, + /// Comparator 7 mode + COMP7MODE: u2, + /// Comparator 7 inverting input + /// selection + COMP7INSEL: u3, + /// Comparator 7 non inverted input + /// selection + COMP7INPSEL: u1, + reserved1: u1, + reserved2: u1, + /// Comparator 7 output + /// selection + COMP7_OUT_SEL: u4, + reserved3: u1, + /// Comparator 7 output + /// polarity + COMP7POL: u1, + /// Comparator 7 hysteresis + COMP7HYST: u2, + /// Comparator 7 blanking + /// source + COMP7_BLANKING: u3, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Comparator 7 output + COMP7OUT: u1, + /// Comparator 7 lock + COMP7LOCK: u1, + }), base_address + 0x34); + + /// address: 0x40010038 + /// control register + pub const OPAMP1_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// OPAMP1 enable + OPAMP1_EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP1 Non inverting input + /// selection + VP_SEL: u2, + reserved0: u1, + /// OPAMP1 inverting input + /// selection + VM_SEL: u2, + /// Timer controlled Mux mode + /// enable + TCM_EN: u1, + /// OPAMP1 inverting input secondary + /// selection + VMS_SEL: u1, + /// OPAMP1 Non inverting input secondary + /// selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CALSEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value + /// (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value + /// (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 1 ouput status flag + OUTCAL: u1, + /// OPAMP 1 lock + LOCK: u1, + }), base_address + 0x38); + + /// address: 0x4001003c + /// control register + pub const OPAMP2_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// OPAMP2 enable + OPAMP2EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP2 Non inverting input + /// selection + VP_SEL: u2, + reserved0: u1, + /// OPAMP2 inverting input + /// selection + VM_SEL: u2, + /// Timer controlled Mux mode + /// enable + TCM_EN: u1, + /// OPAMP2 inverting input secondary + /// selection + VMS_SEL: u1, + /// OPAMP2 Non inverting input secondary + /// selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CAL_SEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value + /// (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value + /// (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 2 ouput status flag + OUTCAL: u1, + /// OPAMP 2 lock + LOCK: u1, + }), base_address + 0x3c); + + /// address: 0x40010040 + /// control register + pub const OPAMP3_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// OPAMP3 enable + OPAMP3EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP3 Non inverting input + /// selection + VP_SEL: u2, + reserved0: u1, + /// OPAMP3 inverting input + /// selection + VM_SEL: u2, + /// Timer controlled Mux mode + /// enable + TCM_EN: u1, + /// OPAMP3 inverting input secondary + /// selection + VMS_SEL: u1, + /// OPAMP3 Non inverting input secondary + /// selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CALSEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value + /// (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value + /// (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 3 ouput status flag + OUTCAL: u1, + /// OPAMP 3 lock + LOCK: u1, + }), base_address + 0x40); + + /// address: 0x40010044 + /// control register + pub const OPAMP4_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// OPAMP4 enable + OPAMP4EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP4 Non inverting input + /// selection + VP_SEL: u2, + reserved0: u1, + /// OPAMP4 inverting input + /// selection + VM_SEL: u2, + /// Timer controlled Mux mode + /// enable + TCM_EN: u1, + /// OPAMP4 inverting input secondary + /// selection + VMS_SEL: u1, + /// OPAMP4 Non inverting input secondary + /// selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CALSEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value + /// (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value + /// (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 4 ouput status flag + OUTCAL: u1, + /// OPAMP 4 lock + LOCK: u1, + }), base_address + 0x44); + }; + /// Flexible memory controller + pub const FMC = struct { + pub const base_address = 0xa0000400; + + /// address: 0xa0000400 + /// SRAM/NOR-Flash chip-select control register + /// 1 + pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + reserved1: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// CBURSTRW + CBURSTRW: u1, + /// CCLKEN + CCLKEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x0); + + /// address: 0xa0000404 + /// SRAM/NOR-Flash chip-select timing register + /// 1 + pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x4); + + /// address: 0xa0000408 + /// SRAM/NOR-Flash chip-select control register + /// 2 + pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x8); + + /// address: 0xa000040c + /// SRAM/NOR-Flash chip-select timing register + /// 2 + pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0xa0000410 + /// SRAM/NOR-Flash chip-select control register + /// 3 + pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0xa0000414 + /// SRAM/NOR-Flash chip-select timing register + /// 3 + pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0xa0000418 + /// SRAM/NOR-Flash chip-select control register + /// 4 + pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x18); + + /// address: 0xa000041c + /// SRAM/NOR-Flash chip-select timing register + /// 4 + pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x1c); + + /// address: 0xa0000460 + /// PC Card/NAND Flash control register + /// 2 + pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x60); + + /// address: 0xa0000464 + /// FIFO status and interrupt register + /// 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x64); + + /// address: 0xa0000468 + /// Common memory space timing register + /// 2 + pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x68); + + /// address: 0xa000046c + /// Attribute memory space timing register + /// 2 + pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x6c); + + /// address: 0xa0000474 + /// ECC result register 2 + pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ECCx + ECCx: u32, + }), base_address + 0x74); + + /// address: 0xa0000480 + /// PC Card/NAND Flash control register + /// 3 + pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x80); + + /// address: 0xa0000484 + /// FIFO status and interrupt register + /// 3 + pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x84); + + /// address: 0xa0000488 + /// Common memory space timing register + /// 3 + pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x88); + + /// address: 0xa000048c + /// Attribute memory space timing register + /// 3 + pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x8c); + + /// address: 0xa0000494 + /// ECC result register 3 + pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ECCx + ECCx: u32, + }), base_address + 0x94); + + /// address: 0xa00004a0 + /// PC Card/NAND Flash control register + /// 4 + pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0xa0); + + /// address: 0xa00004a4 + /// FIFO status and interrupt register + /// 4 + pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xa4); + + /// address: 0xa00004a8 + /// Common memory space timing register + /// 4 + pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0xa8); + + /// address: 0xa00004ac + /// Attribute memory space timing register + /// 4 + pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0xac); + + /// address: 0xa00004b0 + /// I/O space timing register 4 + pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), base_address + 0xb0); + + /// address: 0xa0000504 + /// SRAM/NOR-Flash write timing registers + /// 1 + pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase + /// duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x104); + + /// address: 0xa000050c + /// SRAM/NOR-Flash write timing registers + /// 2 + pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase + /// duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x10c); + + /// address: 0xa0000514 + /// SRAM/NOR-Flash write timing registers + /// 3 + pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase + /// duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x114); + + /// address: 0xa000051c + /// SRAM/NOR-Flash write timing registers + /// 4 + pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase + /// duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x11c); + }; + /// Nested Vectored Interrupt + /// Controller + pub const NVIC = struct { + pub const base_address = 0xe000e100; + + /// address: 0xe000e100 + /// Interrupt Set-Enable Register + pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETENA + SETENA: u32, + }), base_address + 0x0); + + /// address: 0xe000e104 + /// Interrupt Set-Enable Register + pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETENA + SETENA: u32, + }), base_address + 0x4); + + /// address: 0xe000e108 + /// Interrupt Set-Enable Register + pub const ISER2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETENA + SETENA: u32, + }), base_address + 0x8); + + /// address: 0xe000e180 + /// Interrupt Clear-Enable + /// Register + pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRENA + CLRENA: u32, + }), base_address + 0x80); + + /// address: 0xe000e184 + /// Interrupt Clear-Enable + /// Register + pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRENA + CLRENA: u32, + }), base_address + 0x84); + + /// address: 0xe000e188 + /// Interrupt Clear-Enable + /// Register + pub const ICER2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRENA + CLRENA: u32, + }), base_address + 0x88); + + /// address: 0xe000e200 + /// Interrupt Set-Pending Register + pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETPEND + SETPEND: u32, + }), base_address + 0x100); + + /// address: 0xe000e204 + /// Interrupt Set-Pending Register + pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETPEND + SETPEND: u32, + }), base_address + 0x104); + + /// address: 0xe000e208 + /// Interrupt Set-Pending Register + pub const ISPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETPEND + SETPEND: u32, + }), base_address + 0x108); + + /// address: 0xe000e280 + /// Interrupt Clear-Pending + /// Register + pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x180); + + /// address: 0xe000e284 + /// Interrupt Clear-Pending + /// Register + pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x184); + + /// address: 0xe000e288 + /// Interrupt Clear-Pending + /// Register + pub const ICPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x188); + + /// address: 0xe000e300 + /// Interrupt Active Bit Register + pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x200); + + /// address: 0xe000e304 + /// Interrupt Active Bit Register + pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x204); + + /// address: 0xe000e308 + /// Interrupt Active Bit Register + pub const IABR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x208); + + /// address: 0xe000e400 + /// Interrupt Priority Register + pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x300); + + /// address: 0xe000e404 + /// Interrupt Priority Register + pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x304); + + /// address: 0xe000e408 + /// Interrupt Priority Register + pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x308); + + /// address: 0xe000e40c + /// Interrupt Priority Register + pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x30c); + + /// address: 0xe000e410 + /// Interrupt Priority Register + pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x310); + + /// address: 0xe000e414 + /// Interrupt Priority Register + pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x314); + + /// address: 0xe000e418 + /// Interrupt Priority Register + pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x318); + + /// address: 0xe000e41c + /// Interrupt Priority Register + pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x31c); + + /// address: 0xe000e420 + /// Interrupt Priority Register + pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x320); + + /// address: 0xe000e424 + /// Interrupt Priority Register + pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x324); + + /// address: 0xe000e428 + /// Interrupt Priority Register + pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x328); + + /// address: 0xe000e42c + /// Interrupt Priority Register + pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x32c); + + /// address: 0xe000e430 + /// Interrupt Priority Register + pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x330); + + /// address: 0xe000e434 + /// Interrupt Priority Register + pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x334); + + /// address: 0xe000e438 + /// Interrupt Priority Register + pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x338); + + /// address: 0xe000e43c + /// Interrupt Priority Register + pub const IPR15 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x33c); + + /// address: 0xe000e440 + /// Interrupt Priority Register + pub const IPR16 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x340); + + /// address: 0xe000e444 + /// Interrupt Priority Register + pub const IPR17 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x344); + + /// address: 0xe000e448 + /// Interrupt Priority Register + pub const IPR18 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x348); + + /// address: 0xe000e44c + /// Interrupt Priority Register + pub const IPR19 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x34c); + + /// address: 0xe000e450 + /// Interrupt Priority Register + pub const IPR20 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x350); + }; + /// Floting point unit + pub const FPU = struct { + pub const base_address = 0xe000ef34; + + /// address: 0xe000ef34 + /// Floating-point context control + /// register + pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// LSPACT + LSPACT: u1, + /// USER + USER: u1, + reserved0: u1, + /// THREAD + THREAD: u1, + /// HFRDY + HFRDY: u1, + /// MMRDY + MMRDY: u1, + /// BFRDY + BFRDY: u1, + reserved1: u1, + /// MONRDY + MONRDY: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + /// LSPEN + LSPEN: u1, + /// ASPEN + ASPEN: u1, + }), base_address + 0x0); + + /// address: 0xe000ef38 + /// Floating-point context address + /// register + pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Location of unpopulated + /// floating-point + ADDRESS: u29, + }), base_address + 0x4); + + /// address: 0xe000ef3c + /// Floating-point status control + /// register + pub const FPSCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Invalid operation cumulative exception + /// bit + IOC: u1, + /// Division by zero cumulative exception + /// bit. + DZC: u1, + /// Overflow cumulative exception + /// bit + OFC: u1, + /// Underflow cumulative exception + /// bit + UFC: u1, + /// Inexact cumulative exception + /// bit + IXC: u1, + reserved0: u1, + reserved1: u1, + /// Input denormal cumulative exception + /// bit. + IDC: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Rounding Mode control + /// field + RMode: u2, + /// Flush-to-zero mode control + /// bit: + FZ: u1, + /// Default NaN mode control + /// bit + DN: u1, + /// Alternative half-precision control + /// bit + AHP: u1, + reserved16: u1, + /// Overflow condition code + /// flag + V: u1, + /// Carry condition code flag + C: u1, + /// Zero condition code flag + Z: u1, + /// Negative condition code + /// flag + N: u1, + }), base_address + 0x8); + }; + /// Memory protection unit + pub const MPU = struct { + pub const base_address = 0xe000ed90; + + /// address: 0xe000ed90 + /// MPU type register + pub const MPU_TYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Separate flag + SEPARATE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Number of MPU data regions + DREGION: u8, + /// Number of MPU instruction + /// regions + IREGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0xe000ed94 + /// MPU control register + pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enables the MPU + ENABLE: u1, + /// Enables the operation of MPU during hard + /// fault + HFNMIENA: u1, + /// Enable priviliged software access to + /// default memory map + PRIVDEFENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0xe000ed98 + /// MPU region number register + pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct{ + /// MPU region + REGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0xe000ed9c + /// MPU region base address + /// register + pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// MPU region field + REGION: u4, + /// MPU region number valid + VALID: u1, + /// Region base address field + ADDR: u27, + }), base_address + 0xc); + + /// address: 0xe000eda0 + /// MPU region attribute and size + /// register + pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Region enable bit. + ENABLE: u1, + /// Size of the MPU protection + /// region + SIZE: u5, + reserved0: u1, + reserved1: u1, + /// Subregion disable bits + SRD: u8, + /// memory attribute + B: u1, + /// memory attribute + C: u1, + /// Shareable memory attribute + S: u1, + /// memory attribute + TEX: u3, + reserved2: u1, + reserved3: u1, + /// Access permission + AP: u3, + reserved4: u1, + /// Instruction access disable + /// bit + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + }; + /// SysTick timer + pub const STK = struct { + pub const base_address = 0xe000e010; + + /// address: 0xe000e010 + /// SysTick control and status + /// register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + ENABLE: u1, + /// SysTick exception request + /// enable + TICKINT: u1, + /// Clock source selection + CLKSOURCE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// COUNTFLAG + COUNTFLAG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0xe000e014 + /// SysTick reload value register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct{ + /// RELOAD value + RELOAD: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0xe000e018 + /// SysTick current value register + pub const VAL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Current counter value + CURRENT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0xe000e01c + /// SysTick calibration value + /// register + pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct{ + /// Calibration value + TENMS: u24, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// SKEW flag: Indicates whether the TENMS + /// value is exact + SKEW: u1, + /// NOREF flag. Reads as zero + NOREF: u1, + }), base_address + 0xc); + }; + /// System control block + pub const SCB = struct { + pub const base_address = 0xe000ed00; + + /// address: 0xe000ed00 + /// CPUID base register + pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct{ + /// Revision number + Revision: u4, + /// Part number of the + /// processor + PartNo: u12, + /// Reads as 0xF + Constant: u4, + /// Variant number + Variant: u4, + /// Implementer code + Implementer: u8, + }), base_address + 0x0); + + /// address: 0xe000ed04 + /// Interrupt control and state + /// register + pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Active vector + VECTACTIVE: u9, + reserved0: u1, + reserved1: u1, + /// Return to base level + RETTOBASE: u1, + /// Pending vector + VECTPENDING: u7, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Interrupt pending flag + ISRPENDING: u1, + reserved5: u1, + reserved6: u1, + /// SysTick exception clear-pending + /// bit + PENDSTCLR: u1, + /// SysTick exception set-pending + /// bit + PENDSTSET: u1, + /// PendSV clear-pending bit + PENDSVCLR: u1, + /// PendSV set-pending bit + PENDSVSET: u1, + reserved7: u1, + reserved8: u1, + /// NMI set-pending bit. + NMIPENDSET: u1, + }), base_address + 0x4); + + /// address: 0xe000ed08 + /// Vector table offset register + pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Vector table base offset + /// field + TBLOFF: u21, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0xe000ed0c + /// Application interrupt and reset control + /// register + pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// VECTRESET + VECTRESET: u1, + /// VECTCLRACTIVE + VECTCLRACTIVE: u1, + /// SYSRESETREQ + SYSRESETREQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// PRIGROUP + PRIGROUP: u3, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ENDIANESS + ENDIANESS: u1, + /// Register key + VECTKEYSTAT: u16, + }), base_address + 0xc); + + /// address: 0xe000ed10 + /// System control register + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// SLEEPONEXIT + SLEEPONEXIT: u1, + /// SLEEPDEEP + SLEEPDEEP: u1, + reserved1: u1, + /// Send Event on Pending bit + SEVEONPEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x10); + + /// address: 0xe000ed14 + /// Configuration and control + /// register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Configures how the processor enters + /// Thread mode + NONBASETHRDENA: u1, + /// USERSETMPEND + USERSETMPEND: u1, + reserved0: u1, + /// UNALIGN_ TRP + UNALIGN__TRP: u1, + /// DIV_0_TRP + DIV_0_TRP: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// BFHFNMIGN + BFHFNMIGN: u1, + /// STKALIGN + STKALIGN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x14); + + /// address: 0xe000ed18 + /// System handler priority + /// registers + pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Priority of system handler + /// 4 + PRI_4: u8, + /// Priority of system handler + /// 5 + PRI_5: u8, + /// Priority of system handler + /// 6 + PRI_6: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0xe000ed1c + /// System handler priority + /// registers + pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + /// Priority of system handler + /// 11 + PRI_11: u8, + }), base_address + 0x1c); + + /// address: 0xe000ed20 + /// System handler priority + /// registers + pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Priority of system handler + /// 14 + PRI_14: u8, + /// Priority of system handler + /// 15 + PRI_15: u8, + }), base_address + 0x20); + + /// address: 0xe000ed24 + /// System handler control and state + /// register + pub const SHCRS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory management fault exception active + /// bit + MEMFAULTACT: u1, + /// Bus fault exception active + /// bit + BUSFAULTACT: u1, + reserved0: u1, + /// Usage fault exception active + /// bit + USGFAULTACT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// SVC call active bit + SVCALLACT: u1, + /// Debug monitor active bit + MONITORACT: u1, + reserved4: u1, + /// PendSV exception active + /// bit + PENDSVACT: u1, + /// SysTick exception active + /// bit + SYSTICKACT: u1, + /// Usage fault exception pending + /// bit + USGFAULTPENDED: u1, + /// Memory management fault exception + /// pending bit + MEMFAULTPENDED: u1, + /// Bus fault exception pending + /// bit + BUSFAULTPENDED: u1, + /// SVC call pending bit + SVCALLPENDED: u1, + /// Memory management fault enable + /// bit + MEMFAULTENA: u1, + /// Bus fault enable bit + BUSFAULTENA: u1, + /// Usage fault enable bit + USGFAULTENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x24); + + /// address: 0xe000ed28 + /// Configurable fault status + /// register + pub const CFSR_UFSR_BFSR_MMFSR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Instruction access violation + /// flag + IACCVIOL: u1, + reserved1: u1, + /// Memory manager fault on unstacking for a + /// return from exception + MUNSTKERR: u1, + /// Memory manager fault on stacking for + /// exception entry. + MSTKERR: u1, + /// MLSPERR + MLSPERR: u1, + reserved2: u1, + /// Memory Management Fault Address Register + /// (MMAR) valid flag + MMARVALID: u1, + /// Instruction bus error + IBUSERR: u1, + /// Precise data bus error + PRECISERR: u1, + /// Imprecise data bus error + IMPRECISERR: u1, + /// Bus fault on unstacking for a return + /// from exception + UNSTKERR: u1, + /// Bus fault on stacking for exception + /// entry + STKERR: u1, + /// Bus fault on floating-point lazy state + /// preservation + LSPERR: u1, + reserved3: u1, + /// Bus Fault Address Register (BFAR) valid + /// flag + BFARVALID: u1, + /// Undefined instruction usage + /// fault + UNDEFINSTR: u1, + /// Invalid state usage fault + INVSTATE: u1, + /// Invalid PC load usage + /// fault + INVPC: u1, + /// No coprocessor usage + /// fault. + NOCP: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Unaligned access usage + /// fault + UNALIGNED: u1, + /// Divide by zero usage fault + DIVBYZERO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x28); + + /// address: 0xe000ed2c + /// Hard fault status register + pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Vector table hard fault + VECTTBL: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + reserved28: u1, + /// Forced hard fault + FORCED: u1, + /// Reserved for Debug use + DEBUG_VT: u1, + }), base_address + 0x2c); + + /// address: 0xe000ed34 + /// Memory management fault address + /// register + pub const MMFAR = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0xe000ed38 + /// Bus fault address register + pub const BFAR = @intToPtr(*volatile u32, base_address + 0x38); + + /// address: 0xe000ed3c + /// Auxiliary fault status + /// register + pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Implementation defined + IMPDEF: u32, + }), base_address + 0x3c); + }; + /// Nested vectored interrupt + /// controller + pub const NVIC_STIR = struct { + pub const base_address = 0xe000ef00; + + /// address: 0xe000ef00 + /// Software trigger interrupt + /// register + pub const STIR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Software generated interrupt + /// ID + INTID: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + }; + /// Floating point unit CPACR + pub const FPU_CPACR = struct { + pub const base_address = 0xe000ed88; + + /// address: 0xe000ed88 + /// Coprocessor access control + /// register + pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// CP + CP: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + }; + /// System control block ACTLR + pub const SCB_ACTRL = struct { + pub const base_address = 0xe000e008; + + /// address: 0xe000e008 + /// Auxiliary control register + pub const ACTRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// DISMCYCINT + DISMCYCINT: u1, + /// DISDEFWBUF + DISDEFWBUF: u1, + /// DISFOLD + DISFOLD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// DISFPCA + DISFPCA: u1, + /// DISOOFP + DISOOFP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + }; }; -fn isValidField(field_name: []const u8) bool { - return !std.mem.startsWith(u8, field_name, "reserved") and - !std.mem.eql(u8, field_name, "initial_stack_pointer") and - !std.mem.eql(u8, field_name, "reset"); +const std = @import("std"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); } -export const vectors: VectorTable linksection("microzig_flash_start") = blk: { - var temp: VectorTable = .{}; - if (@hasDecl(root, "vector_table")) { - const vector_table = root.vector_table; - if (@typeInfo(vector_table) != .Struct) - @compileLog("root.vector_table must be a struct"); - - inline for (@typeInfo(vector_table).Struct.decls) |decl| { - const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; - const handler = @field(vector_table, decl.name); - - if (!@hasField(VectorTable, decl.name)) { - var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; - inline for (std.meta.fields(VectorTable)) |field| { - if (isValidField(field.name)) { - msg = msg ++ " " ++ field.name ++ "\n"; - } - } - - @compileError(msg); +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; - if (!isValidField(decl.name)) - @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); - - @field(temp, decl.name) = switch (calling_convention) { - .C => .{ .C = handler }, - .Naked => .{ .Naked = handler }, - // for unspecified calling convention we are going to generate small wrapper - .Unspecified => .{ - .C = struct { - fn wrapper() callconv(.C) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - }, - - else => @compileError("unsupported calling convention for function " ++ decl.name), - }; +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); } - } - break :blk temp; + }.tmp, }; diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig index 4fb8ca0..91f25cd 100644 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ b/src/modules/chips/stm32f303/stm32f303.zig @@ -1,10 +1,11 @@ const std = @import("std"); const micro = @import("microzig"); +const chip = @import("registers.zig"); +const regs = chip.registers; -pub const cpu = @import("cpu"); -pub const registers = @import("registers.zig"); -pub const VectorTable = registers.VectorTable; +pub usingnamespace chip; +pub const cpu = @import("cpu"); pub fn parsePin(comptime spec: []const u8) type { const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; @@ -18,7 +19,7 @@ pub fn parsePin(comptime spec: []const u8) type { return struct { /// 'A'...'H' const gpio_port_name = spec[1..2]; - const gpio_port = @field(registers, "GPIO" ++ gpio_port_name); + const gpio_port = @field(regs, "GPIO" ++ gpio_port_name); const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); }; } @@ -31,12 +32,12 @@ fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void pub const gpio = struct { pub fn setOutput(comptime pin: type) void { - setRegField(registers.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(regs.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); } pub fn setInput(comptime pin: type) void { - setRegField(registers.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(regs.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); } diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index 8c97d4f..a1713b2 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -26,32 +26,32 @@ const PLL = struct { overclock_pll(3); // 100 MHz } - fn overclock_flash(timing: u5) void { - micro.chip.registers.SYSCON.FLASHCFG.write(.{ - .FLASHTIM = @intToEnum(@TypeOf(micro.chip.registers.SYSCON.FLASHCFG.read().FLASHTIM), @intCast(u4, timing - 1)), + fn overclock_flash(timing: u4) void { + micro.chip.registers.SYSCON.FLASHCFG.modify(.{ + .FLASHTIM = timing - 1, }); } inline fn feed_pll() void { - micro.chip.registers.SYSCON.PLL0FEED.write(.{ .PLL0FEED = 0xAA }); - micro.chip.registers.SYSCON.PLL0FEED.write(.{ .PLL0FEED = 0x55 }); + micro.chip.registers.SYSCON.PLL0FEED.modify(.{ .PLL0FEED = 0xAA }); + micro.chip.registers.SYSCON.PLL0FEED.modify(.{ .PLL0FEED = 0x55 }); } fn overclock_pll(divider: u8) void { // PLL einrichten für RC - micro.chip.registers.SYSCON.PLL0CON.write(.{ + micro.chip.registers.SYSCON.PLL0CON.modify(.{ .PLLE0 = 0, .PLLC0 = 0, }); feed_pll(); - micro.chip.registers.SYSCON.CLKSRCSEL.write(.{ .CLKSRC = .SELECTS_THE_INTERNAL }); // RC-Oszillator als Quelle - micro.chip.registers.SYSCON.PLL0CFG.write(.{ + micro.chip.registers.SYSCON.CLKSRCSEL.modify(.{ .CLKSRC = 0 }); // RC-Oszillator als Quelle + micro.chip.registers.SYSCON.PLL0CFG.modify(.{ // SysClk = (4MHz / 2) * (2 * 75) = 300 MHz .MSEL0 = 74, .NSEL0 = 1, }); // CPU Takt = SysClk / divider - micro.chip.registers.SYSCON.CCLKCFG.write(.{ .CCLKSEL = divider - 1 }); + micro.chip.registers.SYSCON.CCLKCFG.modify(.{ .CCLKSEL = divider - 1 }); feed_pll();