From 5fb80ada81470de26b3cdb99707d62fd5c68c027 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 18 Feb 2023 17:48:31 -0500 Subject: [PATCH] add chips and boards (#1) --- .buildkite/pipeline.yml | 2 +- LICENSE | 2 +- README.adoc | 22 +- deps/microzig | 2 +- src/boards.zig | 17 +- src/boards/arduino_nano.zig | 33 + src/boards/arduino_uno.zig | 32 + src/chips.zig | 13 +- src/chips/ATmega328P.json | 2947 +++++++++++++++++++++++++++++++++++ src/chips/ATmega328P.zig | 1388 +++++++++++++++++ src/hals/ATmega328P.zig | 191 +++ 11 files changed, 4638 insertions(+), 11 deletions(-) create mode 100644 src/boards/arduino_nano.zig create mode 100644 src/boards/arduino_uno.zig create mode 100644 src/chips/ATmega328P.json create mode 100644 src/chips/ATmega328P.zig create mode 100644 src/hals/ATmega328P.zig diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml index 7767bbb..24d9646 100644 --- a/.buildkite/pipeline.yml +++ b/.buildkite/pipeline.yml @@ -1,4 +1,4 @@ steps: - group: Build steps: - - command: zig build + - command: zig build -Doptimize=ReleaseSmall diff --git a/LICENSE b/LICENSE index c1cc5ec..bcb425d 100644 --- a/LICENSE +++ b/LICENSE @@ -1,4 +1,4 @@ -Copyright (c) 2022 +Copyright (c) 2022 Zig Embedded Group Contributors This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use diff --git a/README.adoc b/README.adoc index 46ca057..f4214f4 100644 --- a/README.adoc +++ b/README.adoc @@ -1,6 +1,18 @@ -= Hardware Support Package Template += Microchip ATmega Hardware Support Package -1. Update LICENSE file -2. Update `microzig` submodule under `deps/` -3. Add chips/boards/hals -4. Set up buildkite pipeline +Note: for testing, renode supports arduino nano 33 BLE + +Currently LLVM is having trouble lowering AVR when this is built in debug mode: + +[source] +---- +LLVM Emit Object... Don't know how to custom lower this! +UNREACHABLE executed at /Users/mattnite/code/llvm-project-15/llvm/lib/Target/AVR/AVRISelLowering.cpp:842! +---- + +for now always build in release small: + +[source] +---- +zig build -Doptimize=ReleaseSmall +---- diff --git a/deps/microzig b/deps/microzig index 97ca549..2d0ee5c 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 97ca5497da0f22d025e18bced9311efed088d893 +Subproject commit 2d0ee5c4731de1d81afb9c8e08ba4e8c2c2cfbf3 diff --git a/src/boards.zig b/src/boards.zig index 2cb647a..9288770 100644 --- a/src/boards.zig +++ b/src/boards.zig @@ -1,6 +1,19 @@ const std = @import("std"); -const microzig = @import("../deps/microzig/src/main.zig"); +const micro = @import("../deps/microzig/src/main.zig"); +const chips = @import("chips.zig"); fn root_dir() []const u8 { - return std.fs.path.dirname(@src().file) orelse "."; + return std.fs.path.dirname(@src().file) orelse unreachable; } + +pub const arduino_nano = micro.Board{ + .name = "Arduino Nano", + .source = .{ .path = root_dir() ++ "/boards/arduino_nano.zig" }, + .chip = chips.atmega328p, +}; + +pub const arduino_uno = micro.Board{ + .name = "Arduino Uno", + .source = .{ .path = root_dir() ++ "/boards/arduino_uno.zig" }, + .chip = chips.atmega328p, +}; diff --git a/src/boards/arduino_nano.zig b/src/boards/arduino_nano.zig new file mode 100644 index 0000000..96490f8 --- /dev/null +++ b/src/boards/arduino_nano.zig @@ -0,0 +1,33 @@ +pub const chip = @import("chip"); + +pub const clock_frequencies = .{ + .cpu = 16_000_000, +}; + +pub const pin_map = .{ + // Port A + .D0 = "PD0", + .D1 = "PD1", + .D2 = "PD2", + .D3 = "PD3", + .D4 = "PD4", + .D5 = "PD5", + .D6 = "PD6", + .D7 = "PD7", + // Port B + .D8 = "PB0", + .D9 = "PB1", + .D10 = "PB2", + .D11 = "PB3", + .D12 = "PB4", + .D13 = "PB5", + // Port C (Analog) + .A0 = "PC0", + .A1 = "PC1", + .A2 = "PC2", + .A3 = "PC3", + .A4 = "PC4", + .A5 = "PC5", + .A6 = "ADC6", + .A7 = "ADC7", +}; diff --git a/src/boards/arduino_uno.zig b/src/boards/arduino_uno.zig new file mode 100644 index 0000000..9dd729c --- /dev/null +++ b/src/boards/arduino_uno.zig @@ -0,0 +1,32 @@ +pub const chip = @import("chip"); + +pub const clock_frequencies = .{ + .cpu = 16_000_000, +}; + +pub const pin_map = .{ + // Port D + .D0 = "PD0", + .D1 = "PD1", + .D2 = "PD2", + .D3 = "PD3", + .D4 = "PD4", + .D5 = "PD5", + .D6 = "PD6", + .D7 = "PD7", + // Port B + .D8 = "PB0", + .D9 = "PB1", + .D10 = "PB2", + .D11 = "PB3", + .D12 = "PB4", + // LED_BUILTIN + .D13 = "PB5", + // Port C (Analog) + .A0 = "PC0", + .A1 = "PC1", + .A2 = "PC2", + .A3 = "PC3", + .A4 = "PC4", + .A5 = "PC5", +}; diff --git a/src/chips.zig b/src/chips.zig index 2cb647a..b47fe15 100644 --- a/src/chips.zig +++ b/src/chips.zig @@ -1,6 +1,17 @@ const std = @import("std"); -const microzig = @import("../deps/microzig/src/main.zig"); +const micro = @import("../deps/microzig/src/main.zig"); +const Chip = micro.Chip; +const MemoryRegion = micro.MemoryRegion; fn root_dir() []const u8 { return std.fs.path.dirname(@src().file) orelse "."; } + +pub const atmega328p = Chip.from_standard_paths(root_dir(), .{ + .name = "ATmega328P", + .cpu = micro.cpus.avr5, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x800100, .length = 2048, .kind = .ram }, + }, +}); diff --git a/src/chips/ATmega328P.json b/src/chips/ATmega328P.json new file mode 100644 index 0000000..7baa55c --- /dev/null +++ b/src/chips/ATmega328P.json @@ -0,0 +1,2947 @@ +{ + "version": "0.1.0", + "types": { + "peripherals": { + "FUSE": { + "description": "Fuses", + "children": { + "registers": { + "EXTENDED": { + "offset": 2, + "size": 8, + "reset_value": 255, + "children": { + "fields": { + "BODLEVEL": { + "description": "Brown-out Detector trigger level", + "offset": 0, + "size": 3, + "enum": "types.peripherals.FUSE.children.enums.ENUM_BODLEVEL" + } + } + } + }, + "HIGH": { + "offset": 1, + "size": 8, + "reset_value": 217, + "children": { + "fields": { + "RSTDISBL": { + "description": "Reset Disabled (Enable PC6 as i/o pin)", + "offset": 7, + "size": 1 + }, + "DWEN": { + "description": "Debug Wire enable", + "offset": 6, + "size": 1 + }, + "SPIEN": { + "description": "Serial program downloading (SPI) enabled", + "offset": 5, + "size": 1 + }, + "WDTON": { + "description": "Watch-dog Timer always on", + "offset": 4, + "size": 1 + }, + "EESAVE": { + "description": "Preserve EEPROM through the Chip Erase cycle", + "offset": 3, + "size": 1 + }, + "BOOTSZ": { + "description": "Select boot size", + "offset": 1, + "size": 2, + "enum": "types.peripherals.FUSE.children.enums.ENUM_BOOTSZ" + }, + "BOOTRST": { + "description": "Boot Reset vector Enabled", + "offset": 0, + "size": 1 + } + } + } + }, + "LOW": { + "offset": 0, + "size": 8, + "reset_value": 98, + "children": { + "fields": { + "CKDIV8": { + "description": "Divide clock by 8 internally", + "offset": 7, + "size": 1 + }, + "CKOUT": { + "description": "Clock output on PORTB0", + "offset": 6, + "size": 1 + }, + "SUT_CKSEL": { + "description": "Select Clock Source", + "offset": 0, + "size": 6, + "enum": "types.peripherals.FUSE.children.enums.ENUM_SUT_CKSEL" + } + } + } + } + }, + "enums": { + "ENUM_SUT_CKSEL": { + "size": 6, + "children": { + "enum_fields": { + "EXTCLK_6CK_14CK_0MS": { + "description": "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms", + "value": 0 + }, + "EXTCLK_6CK_14CK_4MS1": { + "description": "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms", + "value": 16 + }, + "EXTCLK_6CK_14CK_65MS": { + "description": "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms", + "value": 32 + }, + "INTRCOSC_8MHZ_6CK_14CK_0MS": { + "description": "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms", + "value": 2 + }, + "INTRCOSC_8MHZ_6CK_14CK_4MS1": { + "description": "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms", + "value": 18 + }, + "INTRCOSC_8MHZ_6CK_14CK_65MS": { + "description": "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms", + "value": 34 + }, + "INTRCOSC_128KHZ_6CK_14CK_0MS": { + "description": "Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms", + "value": 3 + }, + "INTRCOSC_128KHZ_6CK_14CK_4MS1": { + "description": "Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms", + "value": 19 + }, + "INTRCOSC_128KHZ_6CK_14CK_65MS": { + "description": "Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms", + "value": 35 + }, + "EXTLOFXTAL_1KCK_14CK_0MS": { + "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms", + "value": 4 + }, + "EXTLOFXTAL_1KCK_14CK_4MS1": { + "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms", + "value": 20 + }, + "EXTLOFXTAL_1KCK_14CK_65MS": { + "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms", + "value": 36 + }, + "EXTLOFXTAL_32KCK_14CK_0MS": { + "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms", + "value": 5 + }, + "EXTLOFXTAL_32KCK_14CK_4MS1": { + "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms", + "value": 21 + }, + "EXTLOFXTAL_32KCK_14CK_65MS": { + "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms", + "value": 37 + }, + "EXTFSXTAL_258CK_14CK_4MS1": { + "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms", + "value": 6 + }, + "EXTFSXTAL_258CK_14CK_65MS": { + "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms", + "value": 22 + }, + "EXTFSXTAL_1KCK_14CK_0MS": { + "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms", + "value": 38 + }, + "EXTFSXTAL_1KCK_14CK_4MS1": { + "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms", + "value": 54 + }, + "EXTFSXTAL_1KCK_14CK_65MS": { + "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms", + "value": 7 + }, + "EXTFSXTAL_16KCK_14CK_0MS": { + "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms", + "value": 23 + }, + "EXTFSXTAL_16KCK_14CK_4MS1": { + "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms", + "value": 39 + }, + "EXTFSXTAL_16KCK_14CK_65MS": { + "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms", + "value": 55 + }, + "EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms", + "value": 8 + }, + "EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms", + "value": 24 + }, + "EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms", + "value": 40 + }, + "EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms", + "value": 56 + }, + "EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms", + "value": 9 + }, + "EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms", + "value": 25 + }, + "EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms", + "value": 41 + }, + "EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms", + "value": 57 + }, + "EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms", + "value": 10 + }, + "EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms", + "value": 26 + }, + "EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms", + "value": 42 + }, + "EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms", + "value": 58 + }, + "EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms", + "value": 11 + }, + "EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms", + "value": 27 + }, + "EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms", + "value": 43 + }, + "EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms", + "value": 59 + }, + "EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms", + "value": 12 + }, + "EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms", + "value": 28 + }, + "EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms", + "value": 44 + }, + "EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms", + "value": 60 + }, + "EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms", + "value": 13 + }, + "EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms", + "value": 29 + }, + "EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms", + "value": 45 + }, + "EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms", + "value": 61 + }, + "EXTXOSC_8MHZ_XX_258CK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms", + "value": 14 + }, + "EXTXOSC_8MHZ_XX_258CK_14CK_65MS": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms", + "value": 30 + }, + "EXTXOSC_8MHZ_XX_1KCK_14CK_0MS": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms", + "value": 46 + }, + "EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms", + "value": 62 + }, + "EXTXOSC_8MHZ_XX_1KCK_14CK_65MS": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms", + "value": 15 + }, + "EXTXOSC_8MHZ_XX_16KCK_14CK_0MS": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms", + "value": 31 + }, + "EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms", + "value": 47 + }, + "EXTXOSC_8MHZ_XX_16KCK_14CK_65MS": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms", + "value": 63 + } + } + } + }, + "ENUM_BODLEVEL": { + "size": 3, + "children": { + "enum_fields": { + "4V3": { + "description": "Brown-out detection at VCC=4.3 V", + "value": 4 + }, + "2V7": { + "description": "Brown-out detection at VCC=2.7 V", + "value": 5 + }, + "1V8": { + "description": "Brown-out detection at VCC=1.8 V", + "value": 6 + }, + "DISABLED": { + "description": "Brown-out detection disabled", + "value": 7 + } + } + } + }, + "ENUM_BOOTSZ": { + "size": 2, + "children": { + "enum_fields": { + "256W_3F00": { + "description": "Boot Flash size=256 words start address=$3F00", + "value": 3 + }, + "512W_3E00": { + "description": "Boot Flash size=512 words start address=$3E00", + "value": 2 + }, + "1024W_3C00": { + "description": "Boot Flash size=1024 words start address=$3C00", + "value": 1 + }, + "2048W_3800": { + "description": "Boot Flash size=2048 words start address=$3800", + "value": 0 + } + } + } + } + } + } + }, + "LOCKBIT": { + "description": "Lockbits", + "children": { + "registers": { + "LOCKBIT": { + "offset": 0, + "size": 8, + "reset_value": 255, + "children": { + "fields": { + "LB": { + "description": "Memory Lock", + "offset": 0, + "size": 2, + "enum": "types.peripherals.LOCKBIT.children.enums.ENUM_LB" + }, + "BLB0": { + "description": "Boot Loader Protection Mode", + "offset": 2, + "size": 2, + "enum": "types.peripherals.LOCKBIT.children.enums.ENUM_BLB" + }, + "BLB1": { + "description": "Boot Loader Protection Mode", + "offset": 4, + "size": 2, + "enum": "types.peripherals.LOCKBIT.children.enums.ENUM_BLB2" + } + } + } + } + }, + "enums": { + "ENUM_LB": { + "size": 2, + "children": { + "enum_fields": { + "PROG_VER_DISABLED": { + "description": "Further programming and verification disabled", + "value": 0 + }, + "PROG_DISABLED": { + "description": "Further programming disabled", + "value": 2 + }, + "NO_LOCK": { + "description": "No memory lock features enabled", + "value": 3 + } + } + } + }, + "ENUM_BLB": { + "size": 2, + "children": { + "enum_fields": { + "LPM_SPM_DISABLE": { + "description": "LPM and SPM prohibited in Application Section", + "value": 0 + }, + "LPM_DISABLE": { + "description": "LPM prohibited in Application Section", + "value": 1 + }, + "SPM_DISABLE": { + "description": "SPM prohibited in Application Section", + "value": 2 + }, + "NO_LOCK": { + "description": "No lock on SPM and LPM in Application Section", + "value": 3 + } + } + } + }, + "ENUM_BLB2": { + "size": 2, + "children": { + "enum_fields": { + "LPM_SPM_DISABLE": { + "description": "LPM and SPM prohibited in Boot Section", + "value": 0 + }, + "LPM_DISABLE": { + "description": "LPM prohibited in Boot Section", + "value": 1 + }, + "SPM_DISABLE": { + "description": "SPM prohibited in Boot Section", + "value": 2 + }, + "NO_LOCK": { + "description": "No lock on SPM and LPM in Boot Section", + "value": 3 + } + } + } + } + } + } + }, + "USART": { + "description": "USART", + "children": { + "register_groups": { + "USART0": { + "description": "USART", + "children": { + "registers": { + "UDR0": { + "description": "USART I/O Data Register", + "offset": 6, + "size": 8 + }, + "UCSR0A": { + "description": "USART Control and Status Register A", + "offset": 0, + "size": 8, + "children": { + "fields": { + "RXC0": { + "description": "USART Receive Complete", + "offset": 7, + "size": 1 + }, + "TXC0": { + "description": "USART Transmitt Complete", + "offset": 6, + "size": 1 + }, + "UDRE0": { + "description": "USART Data Register Empty", + "offset": 5, + "size": 1 + }, + "FE0": { + "description": "Framing Error", + "offset": 4, + "size": 1 + }, + "DOR0": { + "description": "Data overRun", + "offset": 3, + "size": 1 + }, + "UPE0": { + "description": "Parity Error", + "offset": 2, + "size": 1 + }, + "U2X0": { + "description": "Double the USART transmission speed", + "offset": 1, + "size": 1 + }, + "MPCM0": { + "description": "Multi-processor Communication Mode", + "offset": 0, + "size": 1 + } + } + } + }, + "UCSR0B": { + "description": "USART Control and Status Register B", + "offset": 1, + "size": 8, + "children": { + "fields": { + "RXCIE0": { + "description": "RX Complete Interrupt Enable", + "offset": 7, + "size": 1 + }, + "TXCIE0": { + "description": "TX Complete Interrupt Enable", + "offset": 6, + "size": 1 + }, + "UDRIE0": { + "description": "USART Data register Empty Interrupt Enable", + "offset": 5, + "size": 1 + }, + "RXEN0": { + "description": "Receiver Enable", + "offset": 4, + "size": 1 + }, + "TXEN0": { + "description": "Transmitter Enable", + "offset": 3, + "size": 1 + }, + "UCSZ02": { + "description": "Character Size - together with UCSZ0 in UCSR0C", + "offset": 2, + "size": 1 + }, + "RXB80": { + "description": "Receive Data Bit 8", + "offset": 1, + "size": 1 + }, + "TXB80": { + "description": "Transmit Data Bit 8", + "offset": 0, + "size": 1 + } + } + } + }, + "UCSR0C": { + "description": "USART Control and Status Register C", + "offset": 2, + "size": 8, + "children": { + "fields": { + "UMSEL0": { + "description": "USART Mode Select", + "offset": 6, + "size": 2, + "enum": "types.peripherals.USART.children.enums.COMM_USART_MODE_2BIT" + }, + "UPM0": { + "description": "Parity Mode Bits", + "offset": 4, + "size": 2, + "enum": "types.peripherals.USART.children.enums.COMM_UPM_PARITY_MODE" + }, + "USBS0": { + "description": "Stop Bit Select", + "offset": 3, + "size": 1, + "enum": "types.peripherals.USART.children.enums.COMM_STOP_BIT_SEL" + }, + "UCSZ0": { + "description": "Character Size - together with UCSZ2 in UCSR0B", + "offset": 1, + "size": 2 + }, + "UCPOL0": { + "description": "Clock Polarity", + "offset": 0, + "size": 1 + } + } + } + }, + "UBRR0": { + "description": "USART Baud Rate Register Bytes", + "offset": 4, + "size": 16 + } + } + } + } + }, + "enums": { + "COMM_USART_MODE_2BIT": { + "size": 2, + "children": { + "enum_fields": { + "ASYNCHRONOUS_USART": { + "description": "Asynchronous USART", + "value": 0 + }, + "SYNCHRONOUS_USART": { + "description": "Synchronous USART", + "value": 1 + }, + "MASTER_SPI": { + "description": "Master SPI", + "value": 3 + } + } + } + }, + "COMM_UPM_PARITY_MODE": { + "size": 2, + "children": { + "enum_fields": { + "DISABLED": { + "description": "Disabled", + "value": 0 + }, + "RESERVED": { + "description": "Reserved", + "value": 1 + }, + "ENABLED_EVEN_PARITY": { + "description": "Enabled, Even Parity", + "value": 2 + }, + "ENABLED_ODD_PARITY": { + "description": "Enabled, Odd Parity", + "value": 3 + } + } + } + }, + "COMM_STOP_BIT_SEL": { + "size": 1, + "children": { + "enum_fields": { + "1_BIT": { + "description": "1-bit", + "value": 0 + }, + "2_BIT": { + "description": "2-bit", + "value": 1 + } + } + } + } + } + } + }, + "TWI": { + "description": "Two Wire Serial Interface", + "children": { + "registers": { + "TWAMR": { + "description": "TWI (Slave) Address Mask Register", + "offset": 5, + "size": 8, + "children": { + "fields": { + "TWAM": { + "offset": 1, + "size": 7 + } + } + } + }, + "TWBR": { + "description": "TWI Bit Rate register", + "offset": 0, + "size": 8 + }, + "TWCR": { + "description": "TWI Control Register", + "offset": 4, + "size": 8, + "children": { + "fields": { + "TWINT": { + "description": "TWI Interrupt Flag", + "offset": 7, + "size": 1 + }, + "TWEA": { + "description": "TWI Enable Acknowledge Bit", + "offset": 6, + "size": 1 + }, + "TWSTA": { + "description": "TWI Start Condition Bit", + "offset": 5, + "size": 1 + }, + "TWSTO": { + "description": "TWI Stop Condition Bit", + "offset": 4, + "size": 1 + }, + "TWWC": { + "description": "TWI Write Collition Flag", + "offset": 3, + "size": 1 + }, + "TWEN": { + "description": "TWI Enable Bit", + "offset": 2, + "size": 1 + }, + "TWIE": { + "description": "TWI Interrupt Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TWSR": { + "description": "TWI Status Register", + "offset": 1, + "size": 8, + "children": { + "fields": { + "TWS": { + "description": "TWI Status", + "offset": 3, + "size": 5 + }, + "TWPS": { + "description": "TWI Prescaler", + "offset": 0, + "size": 2, + "enum": "types.peripherals.TWI.children.enums.COMM_TWI_PRESACLE" + } + } + } + }, + "TWDR": { + "description": "TWI Data register", + "offset": 3, + "size": 8 + }, + "TWAR": { + "description": "TWI (Slave) Address register", + "offset": 2, + "size": 8, + "children": { + "fields": { + "TWA": { + "description": "TWI (Slave) Address register Bits", + "offset": 1, + "size": 7 + }, + "TWGCE": { + "description": "TWI General Call Recognition Enable Bit", + "offset": 0, + "size": 1 + } + } + } + } + }, + "enums": { + "COMM_TWI_PRESACLE": { + "size": 2, + "children": { + "enum_fields": { + "1": { + "description": "1", + "value": 0 + }, + "4": { + "description": "4", + "value": 1 + }, + "16": { + "description": "16", + "value": 2 + }, + "64": { + "description": "64", + "value": 3 + } + } + } + } + } + } + }, + "TC16": { + "description": "Timer/Counter, 16-bit", + "children": { + "register_groups": { + "TC1": { + "description": "Timer/Counter, 16-bit", + "children": { + "registers": { + "TIMSK1": { + "description": "Timer/Counter Interrupt Mask Register", + "offset": 57, + "size": 8, + "children": { + "fields": { + "ICIE1": { + "description": "Timer/Counter1 Input Capture Interrupt Enable", + "offset": 5, + "size": 1 + }, + "OCIE1B": { + "description": "Timer/Counter1 Output CompareB Match Interrupt Enable", + "offset": 2, + "size": 1 + }, + "OCIE1A": { + "description": "Timer/Counter1 Output CompareA Match Interrupt Enable", + "offset": 1, + "size": 1 + }, + "TOIE1": { + "description": "Timer/Counter1 Overflow Interrupt Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TIFR1": { + "description": "Timer/Counter Interrupt Flag register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "ICF1": { + "description": "Input Capture Flag 1", + "offset": 5, + "size": 1 + }, + "OCF1B": { + "description": "Output Compare Flag 1B", + "offset": 2, + "size": 1 + }, + "OCF1A": { + "description": "Output Compare Flag 1A", + "offset": 1, + "size": 1 + }, + "TOV1": { + "description": "Timer/Counter1 Overflow Flag", + "offset": 0, + "size": 1 + } + } + } + }, + "TCCR1A": { + "description": "Timer/Counter1 Control Register A", + "offset": 74, + "size": 8, + "children": { + "fields": { + "COM1A": { + "description": "Compare Output Mode 1A, bits", + "offset": 6, + "size": 2 + }, + "COM1B": { + "description": "Compare Output Mode 1B, bits", + "offset": 4, + "size": 2 + }, + "WGM1": { + "description": "Waveform Generation Mode", + "offset": 0, + "size": 2 + } + } + } + }, + "TCCR1B": { + "description": "Timer/Counter1 Control Register B", + "offset": 75, + "size": 8, + "children": { + "fields": { + "ICNC1": { + "description": "Input Capture 1 Noise Canceler", + "offset": 7, + "size": 1 + }, + "ICES1": { + "description": "Input Capture 1 Edge Select", + "offset": 6, + "size": 1 + }, + "WGM1": { + "description": "Waveform Generation Mode", + "offset": 3, + "size": 2 + }, + "CS1": { + "description": "Prescaler source of Timer/Counter 1", + "offset": 0, + "size": 3, + "enum": "types.peripherals.TC16.children.enums.CLK_SEL_3BIT_EXT" + } + } + } + }, + "TCCR1C": { + "description": "Timer/Counter1 Control Register C", + "offset": 76, + "size": 8, + "children": { + "fields": { + "FOC1A": { + "offset": 7, + "size": 1 + }, + "FOC1B": { + "offset": 6, + "size": 1 + } + } + } + }, + "TCNT1": { + "description": "Timer/Counter1 Bytes", + "offset": 78, + "size": 16 + }, + "OCR1A": { + "description": "Timer/Counter1 Output Compare Register Bytes", + "offset": 82, + "size": 16 + }, + "OCR1B": { + "description": "Timer/Counter1 Output Compare Register Bytes", + "offset": 84, + "size": 16 + }, + "ICR1": { + "description": "Timer/Counter1 Input Capture Register Bytes", + "offset": 80, + "size": 16 + }, + "GTCCR": { + "description": "General Timer/Counter Control Register", + "offset": 13, + "size": 8, + "children": { + "fields": { + "TSM": { + "description": "Timer/Counter Synchronization Mode", + "offset": 7, + "size": 1 + }, + "PSRSYNC": { + "description": "Prescaler Reset Timer/Counter1 and Timer/Counter0", + "offset": 0, + "size": 1 + } + } + } + } + } + } + } + }, + "enums": { + "CLK_SEL_3BIT_EXT": { + "size": 3, + "children": { + "enum_fields": { + "NO_CLOCK_SOURCE_STOPPED": { + "description": "No Clock Source (Stopped)", + "value": 0 + }, + "RUNNING_NO_PRESCALING": { + "description": "Running, No Prescaling", + "value": 1 + }, + "RUNNING_CLK_8": { + "description": "Running, CLK/8", + "value": 2 + }, + "RUNNING_CLK_64": { + "description": "Running, CLK/64", + "value": 3 + }, + "RUNNING_CLK_256": { + "description": "Running, CLK/256", + "value": 4 + }, + "RUNNING_CLK_1024": { + "description": "Running, CLK/1024", + "value": 5 + }, + "RUNNING_EXTCLK_TN_FALLING_EDGE": { + "description": "Running, ExtClk Tn Falling Edge", + "value": 6 + }, + "RUNNING_EXTCLK_TN_RISING_EDGE": { + "description": "Running, ExtClk Tn Rising Edge", + "value": 7 + } + } + } + } + } + } + }, + "TC8_ASYNC": { + "description": "Timer/Counter, 8-bit Async", + "children": { + "register_groups": { + "TC2": { + "description": "Timer/Counter, 8-bit Async", + "children": { + "registers": { + "TIMSK2": { + "description": "Timer/Counter Interrupt Mask register", + "offset": 57, + "size": 8, + "children": { + "fields": { + "OCIE2B": { + "description": "Timer/Counter2 Output Compare Match B Interrupt Enable", + "offset": 2, + "size": 1 + }, + "OCIE2A": { + "description": "Timer/Counter2 Output Compare Match A Interrupt Enable", + "offset": 1, + "size": 1 + }, + "TOIE2": { + "description": "Timer/Counter2 Overflow Interrupt Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TIFR2": { + "description": "Timer/Counter Interrupt Flag Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "OCF2B": { + "description": "Output Compare Flag 2B", + "offset": 2, + "size": 1 + }, + "OCF2A": { + "description": "Output Compare Flag 2A", + "offset": 1, + "size": 1 + }, + "TOV2": { + "description": "Timer/Counter2 Overflow Flag", + "offset": 0, + "size": 1 + } + } + } + }, + "TCCR2A": { + "description": "Timer/Counter2 Control Register A", + "offset": 121, + "size": 8, + "children": { + "fields": { + "COM2A": { + "description": "Compare Output Mode bits", + "offset": 6, + "size": 2 + }, + "COM2B": { + "description": "Compare Output Mode bits", + "offset": 4, + "size": 2 + }, + "WGM2": { + "description": "Waveform Genration Mode", + "offset": 0, + "size": 2 + } + } + } + }, + "TCCR2B": { + "description": "Timer/Counter2 Control Register B", + "offset": 122, + "size": 8, + "children": { + "fields": { + "FOC2A": { + "description": "Force Output Compare A", + "offset": 7, + "size": 1 + }, + "FOC2B": { + "description": "Force Output Compare B", + "offset": 6, + "size": 1 + }, + "WGM22": { + "description": "Waveform Generation Mode", + "offset": 3, + "size": 1 + }, + "CS2": { + "description": "Clock Select bits", + "offset": 0, + "size": 3, + "enum": "types.peripherals.TC8_ASYNC.children.enums.CLK_SEL_3BIT" + } + } + } + }, + "TCNT2": { + "description": "Timer/Counter2", + "offset": 123, + "size": 8 + }, + "OCR2B": { + "description": "Timer/Counter2 Output Compare Register B", + "offset": 125, + "size": 8 + }, + "OCR2A": { + "description": "Timer/Counter2 Output Compare Register A", + "offset": 124, + "size": 8 + }, + "ASSR": { + "description": "Asynchronous Status Register", + "offset": 127, + "size": 8, + "children": { + "fields": { + "EXCLK": { + "description": "Enable External Clock Input", + "offset": 6, + "size": 1 + }, + "AS2": { + "description": "Asynchronous Timer/Counter2", + "offset": 5, + "size": 1 + }, + "TCN2UB": { + "description": "Timer/Counter2 Update Busy", + "offset": 4, + "size": 1 + }, + "OCR2AUB": { + "description": "Output Compare Register2 Update Busy", + "offset": 3, + "size": 1 + }, + "OCR2BUB": { + "description": "Output Compare Register 2 Update Busy", + "offset": 2, + "size": 1 + }, + "TCR2AUB": { + "description": "Timer/Counter Control Register2 Update Busy", + "offset": 1, + "size": 1 + }, + "TCR2BUB": { + "description": "Timer/Counter Control Register2 Update Busy", + "offset": 0, + "size": 1 + } + } + } + }, + "GTCCR": { + "description": "General Timer Counter Control register", + "offset": 12, + "size": 8, + "children": { + "fields": { + "TSM": { + "description": "Timer/Counter Synchronization Mode", + "offset": 7, + "size": 1 + }, + "PSRASY": { + "description": "Prescaler Reset Timer/Counter2", + "offset": 1, + "size": 1 + } + } + } + } + } + } + } + }, + "enums": { + "CLK_SEL_3BIT": { + "size": 3, + "children": { + "enum_fields": { + "NO_CLOCK_SOURCE_STOPPED": { + "description": "No Clock Source (Stopped)", + "value": 0 + }, + "RUNNING_NO_PRESCALING": { + "description": "Running, No Prescaling", + "value": 1 + }, + "RUNNING_CLK_8": { + "description": "Running, CLK/8", + "value": 2 + }, + "RUNNING_CLK_32": { + "description": "Running, CLK/32", + "value": 3 + }, + "RUNNING_CLK_64": { + "description": "Running, CLK/64", + "value": 4 + }, + "RUNNING_CLK_128": { + "description": "Running, CLK/128", + "value": 5 + }, + "RUNNING_CLK_256": { + "description": "Running, CLK/256", + "value": 6 + }, + "RUNNING_CLK_1024": { + "description": "Running, CLK/1024", + "value": 7 + } + } + } + } + } + } + }, + "ADC": { + "description": "Analog-to-Digital Converter", + "children": { + "registers": { + "ADMUX": { + "description": "The ADC multiplexer Selection Register", + "offset": 4, + "size": 8, + "children": { + "fields": { + "REFS": { + "description": "Reference Selection Bits", + "offset": 6, + "size": 2, + "enum": "types.peripherals.ADC.children.enums.ANALOG_ADC_V_REF3" + }, + "ADLAR": { + "description": "Left Adjust Result", + "offset": 5, + "size": 1 + }, + "MUX": { + "description": "Analog Channel Selection Bits", + "offset": 0, + "size": 4, + "enum": "types.peripherals.ADC.children.enums.ADC_MUX_SINGLE" + } + } + } + }, + "ADC": { + "description": "ADC Data Register Bytes", + "offset": 0, + "size": 16 + }, + "ADCSRA": { + "description": "The ADC Control and Status register A", + "offset": 2, + "size": 8, + "children": { + "fields": { + "ADEN": { + "description": "ADC Enable", + "offset": 7, + "size": 1 + }, + "ADSC": { + "description": "ADC Start Conversion", + "offset": 6, + "size": 1 + }, + "ADATE": { + "description": "ADC Auto Trigger Enable", + "offset": 5, + "size": 1 + }, + "ADIF": { + "description": "ADC Interrupt Flag", + "offset": 4, + "size": 1 + }, + "ADIE": { + "description": "ADC Interrupt Enable", + "offset": 3, + "size": 1 + }, + "ADPS": { + "description": "ADC Prescaler Select Bits", + "offset": 0, + "size": 3, + "enum": "types.peripherals.ADC.children.enums.ANALOG_ADC_PRESCALER" + } + } + } + }, + "ADCSRB": { + "description": "The ADC Control and Status register B", + "offset": 3, + "size": 8, + "children": { + "fields": { + "ACME": { + "offset": 6, + "size": 1 + }, + "ADTS": { + "description": "ADC Auto Trigger Source bits", + "offset": 0, + "size": 3, + "enum": "types.peripherals.ADC.children.enums.ANALOG_ADC_AUTO_TRIGGER" + } + } + } + }, + "DIDR0": { + "description": "Digital Input Disable Register", + "offset": 6, + "size": 8, + "children": { + "fields": { + "ADC5D": { + "offset": 5, + "size": 1 + }, + "ADC4D": { + "offset": 4, + "size": 1 + }, + "ADC3D": { + "offset": 3, + "size": 1 + }, + "ADC2D": { + "offset": 2, + "size": 1 + }, + "ADC1D": { + "offset": 1, + "size": 1 + }, + "ADC0D": { + "offset": 0, + "size": 1 + } + } + } + } + }, + "enums": { + "ANALOG_ADC_V_REF3": { + "size": 2, + "children": { + "enum_fields": { + "AREF_INTERNAL_VREF_TURNED_OFF": { + "description": "AREF, Internal Vref turned off", + "value": 0 + }, + "AVCC_WITH_EXTERNAL_CAPACITOR_AT_AREF_PIN": { + "description": "AVCC with external capacitor at AREF pin", + "value": 1 + }, + "RESERVED": { + "description": "Reserved", + "value": 2 + }, + "INTERNAL_1_1V_VOLTAGE_REFERENCE_WITH_EXTERNAL_CAPACITOR_AT_AREF_PIN": { + "description": "Internal 1.1V Voltage Reference with external capacitor at AREF pin", + "value": 3 + } + } + } + }, + "ADC_MUX_SINGLE": { + "size": 4, + "children": { + "enum_fields": { + "ADC0": { + "description": "ADC Single Ended Input pin 0", + "value": 0 + }, + "ADC1": { + "description": "ADC Single Ended Input pin 1", + "value": 1 + }, + "ADC2": { + "description": "ADC Single Ended Input pin 2", + "value": 2 + }, + "ADC3": { + "description": "ADC Single Ended Input pin 3", + "value": 3 + }, + "ADC4": { + "description": "ADC Single Ended Input pin 4", + "value": 4 + }, + "ADC5": { + "description": "ADC Single Ended Input pin 5", + "value": 5 + }, + "ADC6": { + "description": "ADC Single Ended Input pin 6", + "value": 6 + }, + "ADC7": { + "description": "ADC Single Ended Input pin 7", + "value": 7 + }, + "TEMPSENS": { + "description": "Temperature sensor", + "value": 8 + }, + "ADC_VBG": { + "description": "Internal Reference (VBG)", + "value": 14 + }, + "ADC_GND": { + "description": "0V (GND)", + "value": 15 + } + } + } + }, + "ANALOG_ADC_PRESCALER": { + "size": 3, + "children": { + "enum_fields": { + "2": { + "description": "2", + "value": 1 + }, + "4": { + "description": "4", + "value": 2 + }, + "8": { + "description": "8", + "value": 3 + }, + "16": { + "description": "16", + "value": 4 + }, + "32": { + "description": "32", + "value": 5 + }, + "64": { + "description": "64", + "value": 6 + }, + "128": { + "description": "128", + "value": 7 + } + } + } + }, + "ANALOG_ADC_AUTO_TRIGGER": { + "size": 3, + "children": { + "enum_fields": { + "FREE_RUNNING_MODE": { + "description": "Free Running mode", + "value": 0 + }, + "ANALOG_COMPARATOR": { + "description": "Analog Comparator", + "value": 1 + }, + "EXTERNAL_INTERRUPT_REQUEST_0": { + "description": "External Interrupt Request 0", + "value": 2 + }, + "TIMER_COUNTER0_COMPARE_MATCH_A": { + "description": "Timer/Counter0 Compare Match A", + "value": 3 + }, + "TIMER_COUNTER0_OVERFLOW": { + "description": "Timer/Counter0 Overflow", + "value": 4 + }, + "TIMER_COUNTER1_COMPARE_MATCH_B": { + "description": "Timer/Counter1 Compare Match B", + "value": 5 + }, + "TIMER_COUNTER1_OVERFLOW": { + "description": "Timer/Counter1 Overflow", + "value": 6 + }, + "TIMER_COUNTER1_CAPTURE_EVENT": { + "description": "Timer/Counter1 Capture Event", + "value": 7 + } + } + } + } + } + } + }, + "AC": { + "description": "Analog Comparator", + "children": { + "registers": { + "ACSR": { + "description": "Analog Comparator Control And Status Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "ACD": { + "description": "Analog Comparator Disable", + "offset": 7, + "size": 1 + }, + "ACBG": { + "description": "Analog Comparator Bandgap Select", + "offset": 6, + "size": 1 + }, + "ACO": { + "description": "Analog Compare Output", + "offset": 5, + "size": 1 + }, + "ACI": { + "description": "Analog Comparator Interrupt Flag", + "offset": 4, + "size": 1 + }, + "ACIE": { + "description": "Analog Comparator Interrupt Enable", + "offset": 3, + "size": 1 + }, + "ACIC": { + "description": "Analog Comparator Input Capture Enable", + "offset": 2, + "size": 1 + }, + "ACIS": { + "description": "Analog Comparator Interrupt Mode Select bits", + "offset": 0, + "size": 2, + "enum": "types.peripherals.AC.children.enums.ANALOG_COMP_INTERRUPT" + } + } + } + }, + "DIDR1": { + "description": "Digital Input Disable Register 1", + "offset": 47, + "size": 8, + "children": { + "fields": { + "AIN1D": { + "description": "AIN1 Digital Input Disable", + "offset": 1, + "size": 1 + }, + "AIN0D": { + "description": "AIN0 Digital Input Disable", + "offset": 0, + "size": 1 + } + } + } + } + }, + "enums": { + "ANALOG_COMP_INTERRUPT": { + "size": 2, + "children": { + "enum_fields": { + "INTERRUPT_ON_TOGGLE": { + "description": "Interrupt on Toggle", + "value": 0 + }, + "RESERVED": { + "description": "Reserved", + "value": 1 + }, + "INTERRUPT_ON_FALLING_EDGE": { + "description": "Interrupt on Falling Edge", + "value": 2 + }, + "INTERRUPT_ON_RISING_EDGE": { + "description": "Interrupt on Rising Edge", + "value": 3 + } + } + } + } + } + } + }, + "PORT": { + "description": "I/O Port", + "children": { + "register_groups": { + "PORTB": { + "description": "I/O Port", + "children": { + "registers": { + "PORTB": { + "description": "Port B Data Register", + "offset": 2, + "size": 8 + }, + "DDRB": { + "description": "Port B Data Direction Register", + "offset": 1, + "size": 8 + }, + "PINB": { + "description": "Port B Input Pins", + "offset": 0, + "size": 8 + } + } + } + }, + "PORTC": { + "description": "I/O Port", + "children": { + "registers": { + "PORTC": { + "description": "Port C Data Register", + "offset": 2, + "size": 8 + }, + "DDRC": { + "description": "Port C Data Direction Register", + "offset": 1, + "size": 8 + }, + "PINC": { + "description": "Port C Input Pins", + "offset": 0, + "size": 8 + } + } + } + }, + "PORTD": { + "description": "I/O Port", + "children": { + "registers": { + "PORTD": { + "description": "Port D Data Register", + "offset": 2, + "size": 8 + }, + "DDRD": { + "description": "Port D Data Direction Register", + "offset": 1, + "size": 8 + }, + "PIND": { + "description": "Port D Input Pins", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "TC8": { + "description": "Timer/Counter, 8-bit", + "children": { + "register_groups": { + "TC0": { + "description": "Timer/Counter, 8-bit", + "children": { + "registers": { + "OCR0B": { + "description": "Timer/Counter0 Output Compare Register", + "offset": 19, + "size": 8 + }, + "OCR0A": { + "description": "Timer/Counter0 Output Compare Register", + "offset": 18, + "size": 8 + }, + "TCNT0": { + "description": "Timer/Counter0", + "offset": 17, + "size": 8 + }, + "TCCR0B": { + "description": "Timer/Counter Control Register B", + "offset": 16, + "size": 8, + "children": { + "fields": { + "FOC0A": { + "description": "Force Output Compare A", + "offset": 7, + "size": 1 + }, + "FOC0B": { + "description": "Force Output Compare B", + "offset": 6, + "size": 1 + }, + "WGM02": { + "offset": 3, + "size": 1 + }, + "CS0": { + "description": "Clock Select", + "offset": 0, + "size": 3, + "enum": "types.peripherals.TC16.children.enums.CLK_SEL_3BIT_EXT" + } + } + } + }, + "TCCR0A": { + "description": "Timer/Counter Control Register A", + "offset": 15, + "size": 8, + "children": { + "fields": { + "COM0A": { + "description": "Compare Output Mode, Phase Correct PWM Mode", + "offset": 6, + "size": 2 + }, + "COM0B": { + "description": "Compare Output Mode, Fast PWm", + "offset": 4, + "size": 2 + }, + "WGM0": { + "description": "Waveform Generation Mode", + "offset": 0, + "size": 2 + } + } + } + }, + "TIMSK0": { + "description": "Timer/Counter0 Interrupt Mask Register", + "offset": 57, + "size": 8, + "children": { + "fields": { + "OCIE0B": { + "description": "Timer/Counter0 Output Compare Match B Interrupt Enable", + "offset": 2, + "size": 1 + }, + "OCIE0A": { + "description": "Timer/Counter0 Output Compare Match A Interrupt Enable", + "offset": 1, + "size": 1 + }, + "TOIE0": { + "description": "Timer/Counter0 Overflow Interrupt Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TIFR0": { + "description": "Timer/Counter0 Interrupt Flag register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "OCF0B": { + "description": "Timer/Counter0 Output Compare Flag 0B", + "offset": 2, + "size": 1 + }, + "OCF0A": { + "description": "Timer/Counter0 Output Compare Flag 0A", + "offset": 1, + "size": 1 + }, + "TOV0": { + "description": "Timer/Counter0 Overflow Flag", + "offset": 0, + "size": 1 + } + } + } + }, + "GTCCR": { + "description": "General Timer/Counter Control Register", + "offset": 14, + "size": 8, + "children": { + "fields": { + "TSM": { + "description": "Timer/Counter Synchronization Mode", + "offset": 7, + "size": 1 + }, + "PSRSYNC": { + "description": "Prescaler Reset Timer/Counter1 and Timer/Counter0", + "offset": 0, + "size": 1 + } + } + } + } + } + } + } + }, + "enums": { + "CLK_SEL_3BIT_EXT": { + "size": 3, + "children": { + "enum_fields": { + "NO_CLOCK_SOURCE_STOPPED": { + "description": "No Clock Source (Stopped)", + "value": 0 + }, + "RUNNING_NO_PRESCALING": { + "description": "Running, No Prescaling", + "value": 1 + }, + "RUNNING_CLK_8": { + "description": "Running, CLK/8", + "value": 2 + }, + "RUNNING_CLK_64": { + "description": "Running, CLK/64", + "value": 3 + }, + "RUNNING_CLK_256": { + "description": "Running, CLK/256", + "value": 4 + }, + "RUNNING_CLK_1024": { + "description": "Running, CLK/1024", + "value": 5 + }, + "RUNNING_EXTCLK_TN_FALLING_EDGE": { + "description": "Running, ExtClk Tn Falling Edge", + "value": 6 + }, + "RUNNING_EXTCLK_TN_RISING_EDGE": { + "description": "Running, ExtClk Tn Rising Edge", + "value": 7 + } + } + } + } + } + } + }, + "EXINT": { + "description": "External Interrupts", + "children": { + "registers": { + "EICRA": { + "description": "External Interrupt Control Register", + "offset": 46, + "size": 8, + "children": { + "fields": { + "ISC1": { + "description": "External Interrupt Sense Control 1 Bits", + "offset": 2, + "size": 2, + "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL" + }, + "ISC0": { + "description": "External Interrupt Sense Control 0 Bits", + "offset": 0, + "size": 2, + "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL" + } + } + } + }, + "EIMSK": { + "description": "External Interrupt Mask Register", + "offset": 2, + "size": 8, + "children": { + "fields": { + "INT": { + "description": "External Interrupt Request 1 Enable", + "offset": 0, + "size": 2 + } + } + } + }, + "EIFR": { + "description": "External Interrupt Flag Register", + "offset": 1, + "size": 8, + "children": { + "fields": { + "INTF": { + "description": "External Interrupt Flags", + "offset": 0, + "size": 2 + } + } + } + }, + "PCICR": { + "description": "Pin Change Interrupt Control Register", + "offset": 45, + "size": 8, + "children": { + "fields": { + "PCIE": { + "description": "Pin Change Interrupt Enables", + "offset": 0, + "size": 3 + } + } + } + }, + "PCMSK2": { + "description": "Pin Change Mask Register 2", + "offset": 50, + "size": 8, + "children": { + "fields": { + "PCINT": { + "description": "Pin Change Enable Masks", + "offset": 0, + "size": 8 + } + } + } + }, + "PCMSK1": { + "description": "Pin Change Mask Register 1", + "offset": 49, + "size": 8, + "children": { + "fields": { + "PCINT": { + "description": "Pin Change Enable Masks", + "offset": 0, + "size": 7 + } + } + } + }, + "PCMSK0": { + "description": "Pin Change Mask Register 0", + "offset": 48, + "size": 8, + "children": { + "fields": { + "PCINT": { + "description": "Pin Change Enable Masks", + "offset": 0, + "size": 8 + } + } + } + }, + "PCIFR": { + "description": "Pin Change Interrupt Flag Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "PCIF": { + "description": "Pin Change Interrupt Flags", + "offset": 0, + "size": 3 + } + } + } + } + }, + "enums": { + "INTERRUPT_SENSE_CONTROL": { + "description": "Interrupt Sense Control", + "size": 2, + "children": { + "enum_fields": { + "LOW_LEVEL_OF_INTX": { + "description": "Low Level of INTX", + "value": 0 + }, + "ANY_LOGICAL_CHANGE_OF_INTX": { + "description": "Any Logical Change of INTX", + "value": 1 + }, + "FALLING_EDGE_OF_INTX": { + "description": "Falling Edge of INTX", + "value": 2 + }, + "RISING_EDGE_OF_INTX": { + "description": "Rising Edge of INTX", + "value": 3 + } + } + } + } + } + } + }, + "SPI": { + "description": "Serial Peripheral Interface", + "children": { + "registers": { + "SPDR": { + "description": "SPI Data Register", + "offset": 2, + "size": 8 + }, + "SPSR": { + "description": "SPI Status Register", + "offset": 1, + "size": 8, + "children": { + "fields": { + "SPIF": { + "description": "SPI Interrupt Flag", + "offset": 7, + "size": 1 + }, + "WCOL": { + "description": "Write Collision Flag", + "offset": 6, + "size": 1 + }, + "SPI2X": { + "description": "Double SPI Speed Bit", + "offset": 0, + "size": 1 + } + } + } + }, + "SPCR": { + "description": "SPI Control Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "SPIE": { + "description": "SPI Interrupt Enable", + "offset": 7, + "size": 1 + }, + "SPE": { + "description": "SPI Enable", + "offset": 6, + "size": 1 + }, + "DORD": { + "description": "Data Order", + "offset": 5, + "size": 1 + }, + "MSTR": { + "description": "Master/Slave Select", + "offset": 4, + "size": 1 + }, + "CPOL": { + "description": "Clock polarity", + "offset": 3, + "size": 1 + }, + "CPHA": { + "description": "Clock Phase", + "offset": 2, + "size": 1 + }, + "SPR": { + "description": "SPI Clock Rate Selects", + "offset": 0, + "size": 2, + "enum": "types.peripherals.SPI.children.enums.COMM_SCK_RATE_3BIT" + } + } + } + } + }, + "enums": { + "COMM_SCK_RATE_3BIT": { + "size": 2, + "children": { + "enum_fields": { + "FOSC_2_OR_FOSC_4": { + "description": "fosc/2 or fosc/4", + "value": 0 + }, + "FOSC_8_OR_FOSC_16": { + "description": "fosc/8 or fosc/16", + "value": 1 + }, + "FOSC_32_OR_FOSC_64": { + "description": "fosc/32 or fosc/64", + "value": 2 + }, + "FOSC_64_OR_FOSC_128": { + "description": "fosc/64 or fosc/128", + "value": 3 + } + } + } + } + } + } + }, + "WDT": { + "description": "Watchdog Timer", + "children": { + "registers": { + "WDTCSR": { + "description": "Watchdog Timer Control Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "WDIF": { + "description": "Watchdog Timeout Interrupt Flag", + "offset": 7, + "size": 1 + }, + "WDIE": { + "description": "Watchdog Timeout Interrupt Enable", + "offset": 6, + "size": 1 + }, + "WDP_bit0": { + "description": "Watchdog Timer Prescaler Bits", + "offset": 0, + "size": 1 + }, + "WDP_bit1": { + "description": "Watchdog Timer Prescaler Bits", + "offset": 1, + "size": 1 + }, + "WDP_bit2": { + "description": "Watchdog Timer Prescaler Bits", + "offset": 2, + "size": 1 + }, + "WDP_bit3": { + "description": "Watchdog Timer Prescaler Bits", + "offset": 5, + "size": 1 + }, + "WDCE": { + "description": "Watchdog Change Enable", + "offset": 4, + "size": 1 + }, + "WDE": { + "description": "Watch Dog Enable", + "offset": 3, + "size": 1 + } + } + } + } + }, + "enums": { + "WDOG_TIMER_PRESCALE_4BITS": { + "size": 4, + "children": { + "enum_fields": { + "OSCILLATOR_CYCLES_2K": { + "description": "Oscillator Cycles 2K", + "value": 0 + }, + "OSCILLATOR_CYCLES_4K": { + "description": "Oscillator Cycles 4K", + "value": 1 + }, + "OSCILLATOR_CYCLES_8K": { + "description": "Oscillator Cycles 8K", + "value": 2 + }, + "OSCILLATOR_CYCLES_16K": { + "description": "Oscillator Cycles 16K", + "value": 3 + }, + "OSCILLATOR_CYCLES_32K": { + "description": "Oscillator Cycles 32K", + "value": 4 + }, + "OSCILLATOR_CYCLES_64K": { + "description": "Oscillator Cycles 64K", + "value": 5 + }, + "OSCILLATOR_CYCLES_128K": { + "description": "Oscillator Cycles 128K", + "value": 6 + }, + "OSCILLATOR_CYCLES_256K": { + "description": "Oscillator Cycles 256K", + "value": 7 + }, + "OSCILLATOR_CYCLES_512K": { + "description": "Oscillator Cycles 512K", + "value": 8 + }, + "OSCILLATOR_CYCLES_1024K": { + "description": "Oscillator Cycles 1024K", + "value": 9 + } + } + } + } + } + } + }, + "CPU": { + "description": "CPU Registers", + "children": { + "registers": { + "PRR": { + "description": "Power Reduction Register", + "offset": 38, + "size": 8, + "children": { + "fields": { + "PRTWI": { + "description": "Power Reduction TWI", + "offset": 7, + "size": 1 + }, + "PRTIM2": { + "description": "Power Reduction Timer/Counter2", + "offset": 6, + "size": 1 + }, + "PRTIM0": { + "description": "Power Reduction Timer/Counter0", + "offset": 5, + "size": 1 + }, + "PRTIM1": { + "description": "Power Reduction Timer/Counter1", + "offset": 3, + "size": 1 + }, + "PRSPI": { + "description": "Power Reduction Serial Peripheral Interface", + "offset": 2, + "size": 1 + }, + "PRUSART0": { + "description": "Power Reduction USART", + "offset": 1, + "size": 1 + }, + "PRADC": { + "description": "Power Reduction ADC", + "offset": 0, + "size": 1 + } + } + } + }, + "OSCCAL": { + "description": "Oscillator Calibration Value", + "offset": 40, + "size": 8, + "children": { + "fields": { + "OSCCAL": { + "description": "Oscillator Calibration ", + "offset": 0, + "size": 8 + } + } + } + }, + "CLKPR": { + "description": "Clock Prescale Register", + "offset": 35, + "size": 8, + "children": { + "fields": { + "CLKPCE": { + "description": "Clock Prescaler Change Enable", + "offset": 7, + "size": 1 + }, + "CLKPS": { + "description": "Clock Prescaler Select Bits", + "offset": 0, + "size": 4, + "enum": "types.peripherals.CPU.children.enums.CPU_CLK_PRESCALE_4_BITS_SMALL" + } + } + } + }, + "SREG": { + "description": "Status Register", + "offset": 33, + "size": 8, + "children": { + "fields": { + "I": { + "description": "Global Interrupt Enable", + "offset": 7, + "size": 1 + }, + "T": { + "description": "Bit Copy Storage", + "offset": 6, + "size": 1 + }, + "H": { + "description": "Half Carry Flag", + "offset": 5, + "size": 1 + }, + "S": { + "description": "Sign Bit", + "offset": 4, + "size": 1 + }, + "V": { + "description": "Two's Complement Overflow Flag", + "offset": 3, + "size": 1 + }, + "N": { + "description": "Negative Flag", + "offset": 2, + "size": 1 + }, + "Z": { + "description": "Zero Flag", + "offset": 1, + "size": 1 + }, + "C": { + "description": "Carry Flag", + "offset": 0, + "size": 1 + } + } + } + }, + "SP": { + "description": "Stack Pointer ", + "offset": 31, + "size": 16 + }, + "SPMCSR": { + "description": "Store Program Memory Control and Status Register", + "offset": 25, + "size": 8, + "children": { + "fields": { + "SPMIE": { + "description": "SPM Interrupt Enable", + "offset": 7, + "size": 1 + }, + "RWWSB": { + "description": "Read-While-Write Section Busy", + "offset": 6, + "size": 1 + }, + "SIGRD": { + "description": "Signature Row Read", + "offset": 5, + "size": 1 + }, + "RWWSRE": { + "description": "Read-While-Write section read enable", + "offset": 4, + "size": 1 + }, + "BLBSET": { + "description": "Boot Lock Bit Set", + "offset": 3, + "size": 1 + }, + "PGWRT": { + "description": "Page Write", + "offset": 2, + "size": 1 + }, + "PGERS": { + "description": "Page Erase", + "offset": 1, + "size": 1 + }, + "SPMEN": { + "description": "Store Program Memory", + "offset": 0, + "size": 1 + } + } + } + }, + "MCUCR": { + "description": "MCU Control Register", + "offset": 23, + "size": 8, + "children": { + "fields": { + "BODS": { + "description": "BOD Sleep", + "offset": 6, + "size": 1 + }, + "BODSE": { + "description": "BOD Sleep Enable", + "offset": 5, + "size": 1 + }, + "PUD": { + "offset": 4, + "size": 1 + }, + "IVSEL": { + "offset": 1, + "size": 1 + }, + "IVCE": { + "offset": 0, + "size": 1 + } + } + } + }, + "MCUSR": { + "description": "MCU Status Register", + "offset": 22, + "size": 8, + "children": { + "fields": { + "WDRF": { + "description": "Watchdog Reset Flag", + "offset": 3, + "size": 1 + }, + "BORF": { + "description": "Brown-out Reset Flag", + "offset": 2, + "size": 1 + }, + "EXTRF": { + "description": "External Reset Flag", + "offset": 1, + "size": 1 + }, + "PORF": { + "description": "Power-on reset flag", + "offset": 0, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "Sleep Mode Control Register", + "offset": 21, + "size": 8, + "children": { + "fields": { + "SM": { + "description": "Sleep Mode Select Bits", + "offset": 1, + "size": 3, + "enum": "types.peripherals.CPU.children.enums.CPU_SLEEP_MODE_3BITS2" + }, + "SE": { + "description": "Sleep Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "GPIOR2": { + "description": "General Purpose I/O Register 2", + "offset": 13, + "size": 8 + }, + "GPIOR1": { + "description": "General Purpose I/O Register 1", + "offset": 12, + "size": 8 + }, + "GPIOR0": { + "description": "General Purpose I/O Register 0", + "offset": 0, + "size": 8 + } + }, + "enums": { + "CPU_CLK_PRESCALE_4_BITS_SMALL": { + "size": 4, + "children": { + "enum_fields": { + "1": { + "description": "1", + "value": 0 + }, + "2": { + "description": "2", + "value": 1 + }, + "4": { + "description": "4", + "value": 2 + }, + "8": { + "description": "8", + "value": 3 + }, + "16": { + "description": "16", + "value": 4 + }, + "32": { + "description": "32", + "value": 5 + }, + "64": { + "description": "64", + "value": 6 + }, + "128": { + "description": "128", + "value": 7 + }, + "256": { + "description": "256", + "value": 8 + } + } + } + }, + "CPU_SLEEP_MODE_3BITS2": { + "size": 3, + "children": { + "enum_fields": { + "IDLE": { + "description": "Idle", + "value": 0 + }, + "ADC": { + "description": "ADC Noise Reduction (If Available)", + "value": 1 + }, + "PDOWN": { + "description": "Power Down", + "value": 2 + }, + "PSAVE": { + "description": "Power Save", + "value": 3 + }, + "VAL_0x04": { + "description": "Reserved", + "value": 4 + }, + "VAL_0x05": { + "description": "Reserved", + "value": 5 + }, + "STDBY": { + "description": "Standby", + "value": 6 + }, + "ESTDBY": { + "description": "Extended Standby", + "value": 7 + } + } + } + }, + "OSCCAL_VALUE_ADDRESSES": { + "description": "Oscillator Calibration Values", + "size": 1, + "children": { + "enum_fields": { + "8_0_MHz": { + "description": "8.0 MHz", + "value": 0 + } + } + } + } + } + } + }, + "EEPROM": { + "description": "EEPROM", + "children": { + "registers": { + "EEAR": { + "description": "EEPROM Address Register Bytes", + "offset": 2, + "size": 16 + }, + "EEDR": { + "description": "EEPROM Data Register", + "offset": 1, + "size": 8 + }, + "EECR": { + "description": "EEPROM Control Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "EEPM": { + "description": "EEPROM Programming Mode Bits", + "offset": 4, + "size": 2, + "enum": "types.peripherals.EEPROM.children.enums.EEP_MODE" + }, + "EERIE": { + "description": "EEPROM Ready Interrupt Enable", + "offset": 3, + "size": 1 + }, + "EEMPE": { + "description": "EEPROM Master Write Enable", + "offset": 2, + "size": 1 + }, + "EEPE": { + "description": "EEPROM Write Enable", + "offset": 1, + "size": 1 + }, + "EERE": { + "description": "EEPROM Read Enable", + "offset": 0, + "size": 1 + } + } + } + } + }, + "enums": { + "EEP_MODE": { + "size": 2, + "children": { + "enum_fields": { + "ERASE_AND_WRITE_IN_ONE_OPERATION": { + "description": "Erase and Write in one operation", + "value": 0 + }, + "ERASE_ONLY": { + "description": "Erase Only", + "value": 1 + }, + "WRITE_ONLY": { + "description": "Write Only", + "value": 2 + } + } + } + } + } + } + } + } + }, + "devices": { + "ATmega328P": { + "arch": "avr8", + "properties": { + "family": "megaAVR", + "arch": "AVR8" + }, + "children": { + "interrupts": { + "RESET": { + "index": 0, + "description": "External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset" + }, + "INT0": { + "index": 1, + "description": "External Interrupt Request 0" + }, + "INT1": { + "index": 2, + "description": "External Interrupt Request 1" + }, + "PCINT0": { + "index": 3, + "description": "Pin Change Interrupt Request 0" + }, + "PCINT1": { + "index": 4, + "description": "Pin Change Interrupt Request 1" + }, + "PCINT2": { + "index": 5, + "description": "Pin Change Interrupt Request 2" + }, + "WDT": { + "index": 6, + "description": "Watchdog Time-out Interrupt" + }, + "TIMER2_COMPA": { + "index": 7, + "description": "Timer/Counter2 Compare Match A" + }, + "TIMER2_COMPB": { + "index": 8, + "description": "Timer/Counter2 Compare Match B" + }, + "TIMER2_OVF": { + "index": 9, + "description": "Timer/Counter2 Overflow" + }, + "TIMER1_CAPT": { + "index": 10, + "description": "Timer/Counter1 Capture Event" + }, + "TIMER1_COMPA": { + "index": 11, + "description": "Timer/Counter1 Compare Match A" + }, + "TIMER1_COMPB": { + "index": 12, + "description": "Timer/Counter1 Compare Match B" + }, + "TIMER1_OVF": { + "index": 13, + "description": "Timer/Counter1 Overflow" + }, + "TIMER0_COMPA": { + "index": 14, + "description": "TimerCounter0 Compare Match A" + }, + "TIMER0_COMPB": { + "index": 15, + "description": "TimerCounter0 Compare Match B" + }, + "TIMER0_OVF": { + "index": 16, + "description": "Timer/Couner0 Overflow" + }, + "SPI_STC": { + "index": 17, + "description": "SPI Serial Transfer Complete" + }, + "USART_RX": { + "index": 18, + "description": "USART Rx Complete" + }, + "USART_UDRE": { + "index": 19, + "description": "USART, Data Register Empty" + }, + "USART_TX": { + "index": 20, + "description": "USART Tx Complete" + }, + "ADC": { + "index": 21, + "description": "ADC Conversion Complete" + }, + "EE_READY": { + "index": 22, + "description": "EEPROM Ready" + }, + "ANALOG_COMP": { + "index": 23, + "description": "Analog Comparator" + }, + "TWI": { + "index": 24, + "description": "Two-wire Serial Interface" + }, + "SPM_Ready": { + "index": 25, + "description": "Store Program Memory Read" + } + }, + "peripheral_instances": { + "USART0": { + "description": "USART", + "offset": 192, + "type": "types.peripherals.USART.children.register_groups.USART0" + }, + "TWI": { + "description": "Two Wire Serial Interface", + "offset": 184, + "type": "types.peripherals.TWI" + }, + "TC1": { + "description": "Timer/Counter, 16-bit", + "offset": 54, + "type": "types.peripherals.TC16.children.register_groups.TC1" + }, + "TC2": { + "description": "Timer/Counter, 8-bit Async", + "offset": 55, + "type": "types.peripherals.TC8_ASYNC.children.register_groups.TC2" + }, + "ADC": { + "description": "Analog-to-Digital Converter", + "offset": 120, + "type": "types.peripherals.ADC" + }, + "AC": { + "description": "Analog Comparator", + "offset": 80, + "type": "types.peripherals.AC" + }, + "PORTB": { + "description": "I/O Port", + "offset": 35, + "type": "types.peripherals.PORT.children.register_groups.PORTB" + }, + "PORTC": { + "description": "I/O Port", + "offset": 38, + "type": "types.peripherals.PORT.children.register_groups.PORTC" + }, + "PORTD": { + "description": "I/O Port", + "offset": 41, + "type": "types.peripherals.PORT.children.register_groups.PORTD" + }, + "TC0": { + "description": "Timer/Counter, 8-bit", + "offset": 53, + "type": "types.peripherals.TC8.children.register_groups.TC0" + }, + "EXINT": { + "description": "External Interrupts", + "offset": 59, + "type": "types.peripherals.EXINT" + }, + "SPI": { + "description": "Serial Peripheral Interface", + "offset": 76, + "type": "types.peripherals.SPI" + }, + "WDT": { + "description": "Watchdog Timer", + "offset": 96, + "type": "types.peripherals.WDT" + }, + "EEPROM": { + "description": "EEPROM", + "offset": 63, + "type": "types.peripherals.EEPROM" + }, + "CPU": { + "description": "CPU Registers", + "offset": 62, + "type": "types.peripherals.CPU" + }, + "FUSE": { + "description": "Fuses", + "offset": 0, + "type": "types.peripherals.FUSE" + }, + "LOCKBIT": { + "description": "Lockbits", + "offset": 0, + "type": "types.peripherals.LOCKBIT" + } + } + } + } + } +} \ No newline at end of file diff --git a/src/chips/ATmega328P.zig b/src/chips/ATmega328P.zig new file mode 100644 index 0000000..604b37f --- /dev/null +++ b/src/chips/ATmega328P.zig @@ -0,0 +1,1388 @@ +const micro = @import("microzig"); +const mmio = micro.mmio; + +pub const devices = struct { + pub const ATmega328P = struct { + pub const properties = struct { + pub const family = "megaAVR"; + pub const arch = "AVR8"; + }; + + pub const VectorTable = extern struct { + const Handler = micro.interrupt.Handler; + const unhandled = micro.interrupt.unhandled; + + RESET: Handler = unhandled, + /// External Interrupt Request 0 + INT0: Handler = unhandled, + /// External Interrupt Request 1 + INT1: Handler = unhandled, + /// Pin Change Interrupt Request 0 + PCINT0: Handler = unhandled, + /// Pin Change Interrupt Request 1 + PCINT1: Handler = unhandled, + /// Pin Change Interrupt Request 2 + PCINT2: Handler = unhandled, + /// Watchdog Time-out Interrupt + WDT: Handler = unhandled, + /// Timer/Counter2 Compare Match A + TIMER2_COMPA: Handler = unhandled, + /// Timer/Counter2 Compare Match B + TIMER2_COMPB: Handler = unhandled, + /// Timer/Counter2 Overflow + TIMER2_OVF: Handler = unhandled, + /// Timer/Counter1 Capture Event + TIMER1_CAPT: Handler = unhandled, + /// Timer/Counter1 Compare Match A + TIMER1_COMPA: Handler = unhandled, + /// Timer/Counter1 Compare Match B + TIMER1_COMPB: Handler = unhandled, + /// Timer/Counter1 Overflow + TIMER1_OVF: Handler = unhandled, + /// TimerCounter0 Compare Match A + TIMER0_COMPA: Handler = unhandled, + /// TimerCounter0 Compare Match B + TIMER0_COMPB: Handler = unhandled, + /// Timer/Couner0 Overflow + TIMER0_OVF: Handler = unhandled, + /// SPI Serial Transfer Complete + SPI_STC: Handler = unhandled, + /// USART Rx Complete + USART_RX: Handler = unhandled, + /// USART, Data Register Empty + USART_UDRE: Handler = unhandled, + /// USART Tx Complete + USART_TX: Handler = unhandled, + /// ADC Conversion Complete + ADC: Handler = unhandled, + /// EEPROM Ready + EE_READY: Handler = unhandled, + /// Analog Comparator + ANALOG_COMP: Handler = unhandled, + /// Two-wire Serial Interface + TWI: Handler = unhandled, + /// Store Program Memory Read + SPM_Ready: Handler = unhandled, + }; + + pub const peripherals = struct { + /// Fuses + pub const FUSE = @intToPtr(*volatile types.peripherals.FUSE, 0x0); + /// Lockbits + pub const LOCKBIT = @intToPtr(*volatile types.peripherals.LOCKBIT, 0x0); + /// I/O Port + pub const PORTB = @intToPtr(*volatile types.peripherals.PORT.PORTB, 0x23); + /// I/O Port + pub const PORTC = @intToPtr(*volatile types.peripherals.PORT.PORTC, 0x26); + /// I/O Port + pub const PORTD = @intToPtr(*volatile types.peripherals.PORT.PORTD, 0x29); + /// Timer/Counter, 8-bit + pub const TC0 = @intToPtr(*volatile types.peripherals.TC8.TC0, 0x35); + /// Timer/Counter, 16-bit + pub const TC1 = @intToPtr(*volatile types.peripherals.TC16.TC1, 0x36); + /// Timer/Counter, 8-bit Async + pub const TC2 = @intToPtr(*volatile types.peripherals.TC8_ASYNC.TC2, 0x37); + /// External Interrupts + pub const EXINT = @intToPtr(*volatile types.peripherals.EXINT, 0x3b); + /// CPU Registers + pub const CPU = @intToPtr(*volatile types.peripherals.CPU, 0x3e); + /// EEPROM + pub const EEPROM = @intToPtr(*volatile types.peripherals.EEPROM, 0x3f); + /// Serial Peripheral Interface + pub const SPI = @intToPtr(*volatile types.peripherals.SPI, 0x4c); + /// Analog Comparator + pub const AC = @intToPtr(*volatile types.peripherals.AC, 0x50); + /// Watchdog Timer + pub const WDT = @intToPtr(*volatile types.peripherals.WDT, 0x60); + /// Analog-to-Digital Converter + pub const ADC = @intToPtr(*volatile types.peripherals.ADC, 0x78); + /// Two Wire Serial Interface + pub const TWI = @intToPtr(*volatile types.peripherals.TWI, 0xb8); + /// USART + pub const USART0 = @intToPtr(*volatile types.peripherals.USART.USART0, 0xc0); + }; + }; +}; + +pub const types = struct { + pub const peripherals = struct { + /// Fuses + pub const FUSE = extern struct { + pub const ENUM_SUT_CKSEL = enum(u6) { + /// Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + EXTCLK_6CK_14CK_0MS = 0x0, + /// Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + EXTCLK_6CK_14CK_4MS1 = 0x10, + /// Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + EXTCLK_6CK_14CK_65MS = 0x20, + /// Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + INTRCOSC_8MHZ_6CK_14CK_0MS = 0x2, + /// Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + INTRCOSC_8MHZ_6CK_14CK_4MS1 = 0x12, + /// Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + INTRCOSC_8MHZ_6CK_14CK_65MS = 0x22, + /// Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + INTRCOSC_128KHZ_6CK_14CK_0MS = 0x3, + /// Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + INTRCOSC_128KHZ_6CK_14CK_4MS1 = 0x13, + /// Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + INTRCOSC_128KHZ_6CK_14CK_65MS = 0x23, + /// Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms + EXTLOFXTAL_1KCK_14CK_0MS = 0x4, + /// Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms + EXTLOFXTAL_1KCK_14CK_4MS1 = 0x14, + /// Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms + EXTLOFXTAL_1KCK_14CK_65MS = 0x24, + /// Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms + EXTLOFXTAL_32KCK_14CK_0MS = 0x5, + /// Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms + EXTLOFXTAL_32KCK_14CK_4MS1 = 0x15, + /// Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms + EXTLOFXTAL_32KCK_14CK_65MS = 0x25, + /// Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + EXTFSXTAL_258CK_14CK_4MS1 = 0x6, + /// Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + EXTFSXTAL_258CK_14CK_65MS = 0x16, + /// Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + EXTFSXTAL_1KCK_14CK_0MS = 0x26, + /// Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + EXTFSXTAL_1KCK_14CK_4MS1 = 0x36, + /// Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + EXTFSXTAL_1KCK_14CK_65MS = 0x7, + /// Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + EXTFSXTAL_16KCK_14CK_0MS = 0x17, + /// Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + EXTFSXTAL_16KCK_14CK_4MS1 = 0x27, + /// Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + EXTFSXTAL_16KCK_14CK_65MS = 0x37, + /// Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 = 0x8, + /// Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS = 0x18, + /// Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS = 0x28, + /// Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 = 0x38, + /// Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS = 0x9, + /// Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS = 0x19, + /// Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 = 0x29, + /// Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS = 0x39, + /// Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 = 0xa, + /// Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS = 0x1a, + /// Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS = 0x2a, + /// Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 = 0x3a, + /// Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS = 0xb, + /// Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS = 0x1b, + /// Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 = 0x2b, + /// Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS = 0x3b, + /// Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 = 0xc, + /// Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS = 0x1c, + /// Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS = 0x2c, + /// Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 = 0x3c, + /// Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS = 0xd, + /// Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS = 0x1d, + /// Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 = 0x2d, + /// Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS = 0x3d, + /// Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 = 0xe, + /// Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + EXTXOSC_8MHZ_XX_258CK_14CK_65MS = 0x1e, + /// Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + EXTXOSC_8MHZ_XX_1KCK_14CK_0MS = 0x2e, + /// Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 = 0x3e, + /// Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + EXTXOSC_8MHZ_XX_1KCK_14CK_65MS = 0xf, + /// Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + EXTXOSC_8MHZ_XX_16KCK_14CK_0MS = 0x1f, + /// Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 = 0x2f, + /// Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + EXTXOSC_8MHZ_XX_16KCK_14CK_65MS = 0x3f, + _, + }; + + pub const ENUM_BODLEVEL = enum(u3) { + /// Brown-out detection at VCC=4.3 V + @"4V3" = 0x4, + /// Brown-out detection at VCC=2.7 V + @"2V7" = 0x5, + /// Brown-out detection at VCC=1.8 V + @"1V8" = 0x6, + /// Brown-out detection disabled + DISABLED = 0x7, + _, + }; + + pub const ENUM_BOOTSZ = enum(u2) { + /// Boot Flash size=256 words start address=$3F00 + @"256W_3F00" = 0x3, + /// Boot Flash size=512 words start address=$3E00 + @"512W_3E00" = 0x2, + /// Boot Flash size=1024 words start address=$3C00 + @"1024W_3C00" = 0x1, + /// Boot Flash size=2048 words start address=$3800 + @"2048W_3800" = 0x0, + }; + + LOW: mmio.Mmio(packed struct(u8) { + /// Select Clock Source + SUT_CKSEL: packed union { + raw: u6, + value: ENUM_SUT_CKSEL, + }, + /// Clock output on PORTB0 + CKOUT: u1, + /// Divide clock by 8 internally + CKDIV8: u1, + }), + HIGH: mmio.Mmio(packed struct(u8) { + /// Boot Reset vector Enabled + BOOTRST: u1, + /// Select boot size + BOOTSZ: packed union { + raw: u2, + value: ENUM_BOOTSZ, + }, + /// Preserve EEPROM through the Chip Erase cycle + EESAVE: u1, + /// Watch-dog Timer always on + WDTON: u1, + /// Serial program downloading (SPI) enabled + SPIEN: u1, + /// Debug Wire enable + DWEN: u1, + /// Reset Disabled (Enable PC6 as i/o pin) + RSTDISBL: u1, + }), + EXTENDED: mmio.Mmio(packed struct(u8) { + /// Brown-out Detector trigger level + BODLEVEL: packed union { + raw: u3, + value: ENUM_BODLEVEL, + }, + padding: u5, + }), + }; + + /// Lockbits + pub const LOCKBIT = extern struct { + pub const ENUM_LB = enum(u2) { + /// Further programming and verification disabled + PROG_VER_DISABLED = 0x0, + /// Further programming disabled + PROG_DISABLED = 0x2, + /// No memory lock features enabled + NO_LOCK = 0x3, + _, + }; + + pub const ENUM_BLB = enum(u2) { + /// LPM and SPM prohibited in Application Section + LPM_SPM_DISABLE = 0x0, + /// LPM prohibited in Application Section + LPM_DISABLE = 0x1, + /// SPM prohibited in Application Section + SPM_DISABLE = 0x2, + /// No lock on SPM and LPM in Application Section + NO_LOCK = 0x3, + }; + + pub const ENUM_BLB2 = enum(u2) { + /// LPM and SPM prohibited in Boot Section + LPM_SPM_DISABLE = 0x0, + /// LPM prohibited in Boot Section + LPM_DISABLE = 0x1, + /// SPM prohibited in Boot Section + SPM_DISABLE = 0x2, + /// No lock on SPM and LPM in Boot Section + NO_LOCK = 0x3, + }; + + LOCKBIT: mmio.Mmio(packed struct(u8) { + /// Memory Lock + LB: packed union { + raw: u2, + value: ENUM_LB, + }, + /// Boot Loader Protection Mode + BLB0: packed union { + raw: u2, + value: ENUM_BLB, + }, + /// Boot Loader Protection Mode + BLB1: packed union { + raw: u2, + value: ENUM_BLB2, + }, + padding: u2, + }), + }; + + /// USART + pub const USART = struct { + pub const COMM_USART_MODE_2BIT = enum(u2) { + /// Asynchronous USART + ASYNCHRONOUS_USART = 0x0, + /// Synchronous USART + SYNCHRONOUS_USART = 0x1, + /// Master SPI + MASTER_SPI = 0x3, + _, + }; + + pub const COMM_UPM_PARITY_MODE = enum(u2) { + /// Disabled + DISABLED = 0x0, + /// Reserved + RESERVED = 0x1, + /// Enabled, Even Parity + ENABLED_EVEN_PARITY = 0x2, + /// Enabled, Odd Parity + ENABLED_ODD_PARITY = 0x3, + }; + + pub const COMM_STOP_BIT_SEL = enum(u1) { + /// 1-bit + @"1_BIT" = 0x0, + /// 2-bit + @"2_BIT" = 0x1, + }; + + /// USART + pub const USART0 = extern struct { + /// USART Control and Status Register A + UCSR0A: mmio.Mmio(packed struct(u8) { + /// Multi-processor Communication Mode + MPCM0: u1, + /// Double the USART transmission speed + U2X0: u1, + /// Parity Error + UPE0: u1, + /// Data overRun + DOR0: u1, + /// Framing Error + FE0: u1, + /// USART Data Register Empty + UDRE0: u1, + /// USART Transmitt Complete + TXC0: u1, + /// USART Receive Complete + RXC0: u1, + }), + /// USART Control and Status Register B + UCSR0B: mmio.Mmio(packed struct(u8) { + /// Transmit Data Bit 8 + TXB80: u1, + /// Receive Data Bit 8 + RXB80: u1, + /// Character Size - together with UCSZ0 in UCSR0C + UCSZ02: u1, + /// Transmitter Enable + TXEN0: u1, + /// Receiver Enable + RXEN0: u1, + /// USART Data register Empty Interrupt Enable + UDRIE0: u1, + /// TX Complete Interrupt Enable + TXCIE0: u1, + /// RX Complete Interrupt Enable + RXCIE0: u1, + }), + /// USART Control and Status Register C + UCSR0C: mmio.Mmio(packed struct(u8) { + /// Clock Polarity + UCPOL0: u1, + /// Character Size - together with UCSZ2 in UCSR0B + UCSZ0: u2, + /// Stop Bit Select + USBS0: packed union { + raw: u1, + value: COMM_STOP_BIT_SEL, + }, + /// Parity Mode Bits + UPM0: packed union { + raw: u2, + value: COMM_UPM_PARITY_MODE, + }, + /// USART Mode Select + UMSEL0: packed union { + raw: u2, + value: COMM_USART_MODE_2BIT, + }, + }), + reserved4: [1]u8, + /// USART Baud Rate Register Bytes + UBRR0: u16, + /// USART I/O Data Register + UDR0: u8, + }; + }; + + /// Two Wire Serial Interface + pub const TWI = extern struct { + pub const COMM_TWI_PRESACLE = enum(u2) { + /// 1 + @"1" = 0x0, + /// 4 + @"4" = 0x1, + /// 16 + @"16" = 0x2, + /// 64 + @"64" = 0x3, + }; + + /// TWI Bit Rate register + TWBR: u8, + /// TWI Status Register + TWSR: mmio.Mmio(packed struct(u8) { + /// TWI Prescaler + TWPS: packed union { + raw: u2, + value: COMM_TWI_PRESACLE, + }, + reserved3: u1, + /// TWI Status + TWS: u5, + }), + /// TWI (Slave) Address register + TWAR: mmio.Mmio(packed struct(u8) { + /// TWI General Call Recognition Enable Bit + TWGCE: u1, + /// TWI (Slave) Address register Bits + TWA: u7, + }), + /// TWI Data register + TWDR: u8, + /// TWI Control Register + TWCR: mmio.Mmio(packed struct(u8) { + /// TWI Interrupt Enable + TWIE: u1, + reserved2: u1, + /// TWI Enable Bit + TWEN: u1, + /// TWI Write Collition Flag + TWWC: u1, + /// TWI Stop Condition Bit + TWSTO: u1, + /// TWI Start Condition Bit + TWSTA: u1, + /// TWI Enable Acknowledge Bit + TWEA: u1, + /// TWI Interrupt Flag + TWINT: u1, + }), + /// TWI (Slave) Address Mask Register + TWAMR: mmio.Mmio(packed struct(u8) { + reserved1: u1, + TWAM: u7, + }), + }; + + /// Timer/Counter, 16-bit + pub const TC16 = struct { + pub const CLK_SEL_3BIT_EXT = enum(u3) { + /// No Clock Source (Stopped) + NO_CLOCK_SOURCE_STOPPED = 0x0, + /// Running, No Prescaling + RUNNING_NO_PRESCALING = 0x1, + /// Running, CLK/8 + RUNNING_CLK_8 = 0x2, + /// Running, CLK/64 + RUNNING_CLK_64 = 0x3, + /// Running, CLK/256 + RUNNING_CLK_256 = 0x4, + /// Running, CLK/1024 + RUNNING_CLK_1024 = 0x5, + /// Running, ExtClk Tn Falling Edge + RUNNING_EXTCLK_TN_FALLING_EDGE = 0x6, + /// Running, ExtClk Tn Rising Edge + RUNNING_EXTCLK_TN_RISING_EDGE = 0x7, + }; + + /// Timer/Counter, 16-bit + pub const TC1 = extern struct { + /// Timer/Counter Interrupt Flag register + TIFR1: mmio.Mmio(packed struct(u8) { + /// Timer/Counter1 Overflow Flag + TOV1: u1, + /// Output Compare Flag 1A + OCF1A: u1, + /// Output Compare Flag 1B + OCF1B: u1, + reserved5: u2, + /// Input Capture Flag 1 + ICF1: u1, + padding: u2, + }), + reserved13: [12]u8, + /// General Timer/Counter Control Register + GTCCR: mmio.Mmio(packed struct(u8) { + /// Prescaler Reset Timer/Counter1 and Timer/Counter0 + PSRSYNC: u1, + reserved7: u6, + /// Timer/Counter Synchronization Mode + TSM: u1, + }), + reserved57: [43]u8, + /// Timer/Counter Interrupt Mask Register + TIMSK1: mmio.Mmio(packed struct(u8) { + /// Timer/Counter1 Overflow Interrupt Enable + TOIE1: u1, + /// Timer/Counter1 Output CompareA Match Interrupt Enable + OCIE1A: u1, + /// Timer/Counter1 Output CompareB Match Interrupt Enable + OCIE1B: u1, + reserved5: u2, + /// Timer/Counter1 Input Capture Interrupt Enable + ICIE1: u1, + padding: u2, + }), + reserved74: [16]u8, + /// Timer/Counter1 Control Register A + TCCR1A: mmio.Mmio(packed struct(u8) { + /// Waveform Generation Mode + WGM1: u2, + reserved4: u2, + /// Compare Output Mode 1B, bits + COM1B: u2, + /// Compare Output Mode 1A, bits + COM1A: u2, + }), + /// Timer/Counter1 Control Register B + TCCR1B: mmio.Mmio(packed struct(u8) { + /// Prescaler source of Timer/Counter 1 + CS1: packed union { + raw: u3, + value: CLK_SEL_3BIT_EXT, + }, + /// Waveform Generation Mode + WGM1: u2, + reserved6: u1, + /// Input Capture 1 Edge Select + ICES1: u1, + /// Input Capture 1 Noise Canceler + ICNC1: u1, + }), + /// Timer/Counter1 Control Register C + TCCR1C: mmio.Mmio(packed struct(u8) { + reserved6: u6, + FOC1B: u1, + FOC1A: u1, + }), + reserved78: [1]u8, + /// Timer/Counter1 Bytes + TCNT1: u16, + /// Timer/Counter1 Input Capture Register Bytes + ICR1: u16, + /// Timer/Counter1 Output Compare Register Bytes + OCR1A: u16, + /// Timer/Counter1 Output Compare Register Bytes + OCR1B: u16, + }; + }; + + /// Timer/Counter, 8-bit Async + pub const TC8_ASYNC = struct { + pub const CLK_SEL_3BIT = enum(u3) { + /// No Clock Source (Stopped) + NO_CLOCK_SOURCE_STOPPED = 0x0, + /// Running, No Prescaling + RUNNING_NO_PRESCALING = 0x1, + /// Running, CLK/8 + RUNNING_CLK_8 = 0x2, + /// Running, CLK/32 + RUNNING_CLK_32 = 0x3, + /// Running, CLK/64 + RUNNING_CLK_64 = 0x4, + /// Running, CLK/128 + RUNNING_CLK_128 = 0x5, + /// Running, CLK/256 + RUNNING_CLK_256 = 0x6, + /// Running, CLK/1024 + RUNNING_CLK_1024 = 0x7, + }; + + /// Timer/Counter, 8-bit Async + pub const TC2 = extern struct { + /// Timer/Counter Interrupt Flag Register + TIFR2: mmio.Mmio(packed struct(u8) { + /// Timer/Counter2 Overflow Flag + TOV2: u1, + /// Output Compare Flag 2A + OCF2A: u1, + /// Output Compare Flag 2B + OCF2B: u1, + padding: u5, + }), + reserved12: [11]u8, + /// General Timer Counter Control register + GTCCR: mmio.Mmio(packed struct(u8) { + reserved1: u1, + /// Prescaler Reset Timer/Counter2 + PSRASY: u1, + reserved7: u5, + /// Timer/Counter Synchronization Mode + TSM: u1, + }), + reserved57: [44]u8, + /// Timer/Counter Interrupt Mask register + TIMSK2: mmio.Mmio(packed struct(u8) { + /// Timer/Counter2 Overflow Interrupt Enable + TOIE2: u1, + /// Timer/Counter2 Output Compare Match A Interrupt Enable + OCIE2A: u1, + /// Timer/Counter2 Output Compare Match B Interrupt Enable + OCIE2B: u1, + padding: u5, + }), + reserved121: [63]u8, + /// Timer/Counter2 Control Register A + TCCR2A: mmio.Mmio(packed struct(u8) { + /// Waveform Genration Mode + WGM2: u2, + reserved4: u2, + /// Compare Output Mode bits + COM2B: u2, + /// Compare Output Mode bits + COM2A: u2, + }), + /// Timer/Counter2 Control Register B + TCCR2B: mmio.Mmio(packed struct(u8) { + /// Clock Select bits + CS2: packed union { + raw: u3, + value: CLK_SEL_3BIT, + }, + /// Waveform Generation Mode + WGM22: u1, + reserved6: u2, + /// Force Output Compare B + FOC2B: u1, + /// Force Output Compare A + FOC2A: u1, + }), + /// Timer/Counter2 + TCNT2: u8, + /// Timer/Counter2 Output Compare Register A + OCR2A: u8, + /// Timer/Counter2 Output Compare Register B + OCR2B: u8, + reserved127: [1]u8, + /// Asynchronous Status Register + ASSR: mmio.Mmio(packed struct(u8) { + /// Timer/Counter Control Register2 Update Busy + TCR2BUB: u1, + /// Timer/Counter Control Register2 Update Busy + TCR2AUB: u1, + /// Output Compare Register 2 Update Busy + OCR2BUB: u1, + /// Output Compare Register2 Update Busy + OCR2AUB: u1, + /// Timer/Counter2 Update Busy + TCN2UB: u1, + /// Asynchronous Timer/Counter2 + AS2: u1, + /// Enable External Clock Input + EXCLK: u1, + padding: u1, + }), + }; + }; + + /// Analog-to-Digital Converter + pub const ADC = extern struct { + pub const ANALOG_ADC_V_REF3 = enum(u2) { + /// AREF, Internal Vref turned off + AREF_INTERNAL_VREF_TURNED_OFF = 0x0, + /// AVCC with external capacitor at AREF pin + AVCC_WITH_EXTERNAL_CAPACITOR_AT_AREF_PIN = 0x1, + /// Reserved + RESERVED = 0x2, + /// Internal 1.1V Voltage Reference with external capacitor at AREF pin + INTERNAL_1_1V_VOLTAGE_REFERENCE_WITH_EXTERNAL_CAPACITOR_AT_AREF_PIN = 0x3, + }; + + pub const ADC_MUX_SINGLE = enum(u4) { + /// ADC Single Ended Input pin 0 + ADC0 = 0x0, + /// ADC Single Ended Input pin 1 + ADC1 = 0x1, + /// ADC Single Ended Input pin 2 + ADC2 = 0x2, + /// ADC Single Ended Input pin 3 + ADC3 = 0x3, + /// ADC Single Ended Input pin 4 + ADC4 = 0x4, + /// ADC Single Ended Input pin 5 + ADC5 = 0x5, + /// ADC Single Ended Input pin 6 + ADC6 = 0x6, + /// ADC Single Ended Input pin 7 + ADC7 = 0x7, + /// Temperature sensor + TEMPSENS = 0x8, + /// Internal Reference (VBG) + ADC_VBG = 0xe, + /// 0V (GND) + ADC_GND = 0xf, + _, + }; + + pub const ANALOG_ADC_PRESCALER = enum(u3) { + /// 2 + @"2" = 0x0, + /// 2 + @"2" = 0x1, + /// 4 + @"4" = 0x2, + /// 8 + @"8" = 0x3, + /// 16 + @"16" = 0x4, + /// 32 + @"32" = 0x5, + /// 64 + @"64" = 0x6, + /// 128 + @"128" = 0x7, + }; + + pub const ANALOG_ADC_AUTO_TRIGGER = enum(u3) { + /// Free Running mode + FREE_RUNNING_MODE = 0x0, + /// Analog Comparator + ANALOG_COMPARATOR = 0x1, + /// External Interrupt Request 0 + EXTERNAL_INTERRUPT_REQUEST_0 = 0x2, + /// Timer/Counter0 Compare Match A + TIMER_COUNTER0_COMPARE_MATCH_A = 0x3, + /// Timer/Counter0 Overflow + TIMER_COUNTER0_OVERFLOW = 0x4, + /// Timer/Counter1 Compare Match B + TIMER_COUNTER1_COMPARE_MATCH_B = 0x5, + /// Timer/Counter1 Overflow + TIMER_COUNTER1_OVERFLOW = 0x6, + /// Timer/Counter1 Capture Event + TIMER_COUNTER1_CAPTURE_EVENT = 0x7, + }; + + /// ADC Data Register Bytes + ADC: u16, + /// The ADC Control and Status register A + ADCSRA: mmio.Mmio(packed struct(u8) { + /// ADC Prescaler Select Bits + ADPS: packed union { + raw: u3, + value: ANALOG_ADC_PRESCALER, + }, + /// ADC Interrupt Enable + ADIE: u1, + /// ADC Interrupt Flag + ADIF: u1, + /// ADC Auto Trigger Enable + ADATE: u1, + /// ADC Start Conversion + ADSC: u1, + /// ADC Enable + ADEN: u1, + }), + /// The ADC Control and Status register B + ADCSRB: mmio.Mmio(packed struct(u8) { + /// ADC Auto Trigger Source bits + ADTS: packed union { + raw: u3, + value: ANALOG_ADC_AUTO_TRIGGER, + }, + reserved6: u3, + ACME: u1, + padding: u1, + }), + /// The ADC multiplexer Selection Register + ADMUX: mmio.Mmio(packed struct(u8) { + /// Analog Channel Selection Bits + MUX: packed union { + raw: u4, + value: ADC_MUX_SINGLE, + }, + reserved5: u1, + /// Left Adjust Result + ADLAR: u1, + /// Reference Selection Bits + REFS: packed union { + raw: u2, + value: ANALOG_ADC_V_REF3, + }, + }), + reserved6: [1]u8, + /// Digital Input Disable Register + DIDR0: mmio.Mmio(packed struct(u8) { + ADC0D: u1, + ADC1D: u1, + ADC2D: u1, + ADC3D: u1, + ADC4D: u1, + ADC5D: u1, + padding: u2, + }), + }; + + /// Analog Comparator + pub const AC = extern struct { + pub const ANALOG_COMP_INTERRUPT = enum(u2) { + /// Interrupt on Toggle + INTERRUPT_ON_TOGGLE = 0x0, + /// Reserved + RESERVED = 0x1, + /// Interrupt on Falling Edge + INTERRUPT_ON_FALLING_EDGE = 0x2, + /// Interrupt on Rising Edge + INTERRUPT_ON_RISING_EDGE = 0x3, + }; + + /// Analog Comparator Control And Status Register + ACSR: mmio.Mmio(packed struct(u8) { + /// Analog Comparator Interrupt Mode Select bits + ACIS: packed union { + raw: u2, + value: ANALOG_COMP_INTERRUPT, + }, + /// Analog Comparator Input Capture Enable + ACIC: u1, + /// Analog Comparator Interrupt Enable + ACIE: u1, + /// Analog Comparator Interrupt Flag + ACI: u1, + /// Analog Compare Output + ACO: u1, + /// Analog Comparator Bandgap Select + ACBG: u1, + /// Analog Comparator Disable + ACD: u1, + }), + reserved47: [46]u8, + /// Digital Input Disable Register 1 + DIDR1: mmio.Mmio(packed struct(u8) { + /// AIN0 Digital Input Disable + AIN0D: u1, + /// AIN1 Digital Input Disable + AIN1D: u1, + padding: u6, + }), + }; + + /// I/O Port + pub const PORT = struct { + /// I/O Port + pub const PORTB = extern struct { + /// Port B Input Pins + PINB: u8, + /// Port B Data Direction Register + DDRB: u8, + /// Port B Data Register + PORTB: u8, + }; + + /// I/O Port + pub const PORTC = extern struct { + /// Port C Input Pins + PINC: u8, + /// Port C Data Direction Register + DDRC: u8, + /// Port C Data Register + PORTC: u8, + }; + + /// I/O Port + pub const PORTD = extern struct { + /// Port D Input Pins + PIND: u8, + /// Port D Data Direction Register + DDRD: u8, + /// Port D Data Register + PORTD: u8, + }; + }; + + /// Timer/Counter, 8-bit + pub const TC8 = struct { + pub const CLK_SEL_3BIT_EXT = enum(u3) { + /// No Clock Source (Stopped) + NO_CLOCK_SOURCE_STOPPED = 0x0, + /// Running, No Prescaling + RUNNING_NO_PRESCALING = 0x1, + /// Running, CLK/8 + RUNNING_CLK_8 = 0x2, + /// Running, CLK/64 + RUNNING_CLK_64 = 0x3, + /// Running, CLK/256 + RUNNING_CLK_256 = 0x4, + /// Running, CLK/1024 + RUNNING_CLK_1024 = 0x5, + /// Running, ExtClk Tn Falling Edge + RUNNING_EXTCLK_TN_FALLING_EDGE = 0x6, + /// Running, ExtClk Tn Rising Edge + RUNNING_EXTCLK_TN_RISING_EDGE = 0x7, + }; + + /// Timer/Counter, 8-bit + pub const TC0 = extern struct { + /// Timer/Counter0 Interrupt Flag register + TIFR0: mmio.Mmio(packed struct(u8) { + /// Timer/Counter0 Overflow Flag + TOV0: u1, + /// Timer/Counter0 Output Compare Flag 0A + OCF0A: u1, + /// Timer/Counter0 Output Compare Flag 0B + OCF0B: u1, + padding: u5, + }), + reserved14: [13]u8, + /// General Timer/Counter Control Register + GTCCR: mmio.Mmio(packed struct(u8) { + /// Prescaler Reset Timer/Counter1 and Timer/Counter0 + PSRSYNC: u1, + reserved7: u6, + /// Timer/Counter Synchronization Mode + TSM: u1, + }), + /// Timer/Counter Control Register A + TCCR0A: mmio.Mmio(packed struct(u8) { + /// Waveform Generation Mode + WGM0: u2, + reserved4: u2, + /// Compare Output Mode, Fast PWm + COM0B: u2, + /// Compare Output Mode, Phase Correct PWM Mode + COM0A: u2, + }), + /// Timer/Counter Control Register B + TCCR0B: mmio.Mmio(packed struct(u8) { + /// Clock Select + CS0: packed union { + raw: u3, + value: CLK_SEL_3BIT_EXT, + }, + WGM02: u1, + reserved6: u2, + /// Force Output Compare B + FOC0B: u1, + /// Force Output Compare A + FOC0A: u1, + }), + /// Timer/Counter0 + TCNT0: u8, + /// Timer/Counter0 Output Compare Register + OCR0A: u8, + /// Timer/Counter0 Output Compare Register + OCR0B: u8, + reserved57: [37]u8, + /// Timer/Counter0 Interrupt Mask Register + TIMSK0: mmio.Mmio(packed struct(u8) { + /// Timer/Counter0 Overflow Interrupt Enable + TOIE0: u1, + /// Timer/Counter0 Output Compare Match A Interrupt Enable + OCIE0A: u1, + /// Timer/Counter0 Output Compare Match B Interrupt Enable + OCIE0B: u1, + padding: u5, + }), + }; + }; + + /// External Interrupts + pub const EXINT = extern struct { + /// Interrupt Sense Control + pub const INTERRUPT_SENSE_CONTROL = enum(u2) { + /// Low Level of INTX + LOW_LEVEL_OF_INTX = 0x0, + /// Any Logical Change of INTX + ANY_LOGICAL_CHANGE_OF_INTX = 0x1, + /// Falling Edge of INTX + FALLING_EDGE_OF_INTX = 0x2, + /// Rising Edge of INTX + RISING_EDGE_OF_INTX = 0x3, + }; + + /// Pin Change Interrupt Flag Register + PCIFR: mmio.Mmio(packed struct(u8) { + /// Pin Change Interrupt Flags + PCIF: u3, + padding: u5, + }), + /// External Interrupt Flag Register + EIFR: mmio.Mmio(packed struct(u8) { + /// External Interrupt Flags + INTF: u2, + padding: u6, + }), + /// External Interrupt Mask Register + EIMSK: mmio.Mmio(packed struct(u8) { + /// External Interrupt Request 1 Enable + INT: u2, + padding: u6, + }), + reserved45: [42]u8, + /// Pin Change Interrupt Control Register + PCICR: mmio.Mmio(packed struct(u8) { + /// Pin Change Interrupt Enables + PCIE: u3, + padding: u5, + }), + /// External Interrupt Control Register + EICRA: mmio.Mmio(packed struct(u8) { + /// External Interrupt Sense Control 0 Bits + ISC0: packed union { + raw: u2, + value: INTERRUPT_SENSE_CONTROL, + }, + /// External Interrupt Sense Control 1 Bits + ISC1: packed union { + raw: u2, + value: INTERRUPT_SENSE_CONTROL, + }, + padding: u4, + }), + reserved48: [1]u8, + /// Pin Change Mask Register 0 + PCMSK0: mmio.Mmio(packed struct(u8) { + /// Pin Change Enable Masks + PCINT: u8, + }), + /// Pin Change Mask Register 1 + PCMSK1: mmio.Mmio(packed struct(u8) { + /// Pin Change Enable Masks + PCINT: u7, + padding: u1, + }), + /// Pin Change Mask Register 2 + PCMSK2: mmio.Mmio(packed struct(u8) { + /// Pin Change Enable Masks + PCINT: u8, + }), + }; + + /// Serial Peripheral Interface + pub const SPI = extern struct { + pub const COMM_SCK_RATE_3BIT = enum(u2) { + /// fosc/2 or fosc/4 + FOSC_2_OR_FOSC_4 = 0x0, + /// fosc/8 or fosc/16 + FOSC_8_OR_FOSC_16 = 0x1, + /// fosc/32 or fosc/64 + FOSC_32_OR_FOSC_64 = 0x2, + /// fosc/64 or fosc/128 + FOSC_64_OR_FOSC_128 = 0x3, + }; + + /// SPI Control Register + SPCR: mmio.Mmio(packed struct(u8) { + /// SPI Clock Rate Selects + SPR: packed union { + raw: u2, + value: COMM_SCK_RATE_3BIT, + }, + /// Clock Phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master/Slave Select + MSTR: u1, + /// Data Order + DORD: u1, + /// SPI Enable + SPE: u1, + /// SPI Interrupt Enable + SPIE: u1, + }), + /// SPI Status Register + SPSR: mmio.Mmio(packed struct(u8) { + /// Double SPI Speed Bit + SPI2X: u1, + reserved6: u5, + /// Write Collision Flag + WCOL: u1, + /// SPI Interrupt Flag + SPIF: u1, + }), + /// SPI Data Register + SPDR: u8, + }; + + /// Watchdog Timer + pub const WDT = extern struct { + pub const WDOG_TIMER_PRESCALE_4BITS = enum(u4) { + /// Oscillator Cycles 2K + OSCILLATOR_CYCLES_2K = 0x0, + /// Oscillator Cycles 4K + OSCILLATOR_CYCLES_4K = 0x1, + /// Oscillator Cycles 8K + OSCILLATOR_CYCLES_8K = 0x2, + /// Oscillator Cycles 16K + OSCILLATOR_CYCLES_16K = 0x3, + /// Oscillator Cycles 32K + OSCILLATOR_CYCLES_32K = 0x4, + /// Oscillator Cycles 64K + OSCILLATOR_CYCLES_64K = 0x5, + /// Oscillator Cycles 128K + OSCILLATOR_CYCLES_128K = 0x6, + /// Oscillator Cycles 256K + OSCILLATOR_CYCLES_256K = 0x7, + /// Oscillator Cycles 512K + OSCILLATOR_CYCLES_512K = 0x8, + /// Oscillator Cycles 1024K + OSCILLATOR_CYCLES_1024K = 0x9, + _, + }; + + /// Watchdog Timer Control Register + WDTCSR: mmio.Mmio(packed struct(u8) { + /// Watchdog Timer Prescaler Bits + WDP_bit0: u1, + /// Watchdog Timer Prescaler Bits + WDP_bit1: u1, + /// Watchdog Timer Prescaler Bits + WDP_bit2: u1, + /// Watch Dog Enable + WDE: u1, + /// Watchdog Change Enable + WDCE: u1, + /// Watchdog Timer Prescaler Bits + WDP_bit3: u1, + /// Watchdog Timeout Interrupt Enable + WDIE: u1, + /// Watchdog Timeout Interrupt Flag + WDIF: u1, + }), + }; + + /// CPU Registers + pub const CPU = extern struct { + pub const CPU_CLK_PRESCALE_4_BITS_SMALL = enum(u4) { + /// 1 + @"1" = 0x0, + /// 2 + @"2" = 0x1, + /// 4 + @"4" = 0x2, + /// 8 + @"8" = 0x3, + /// 16 + @"16" = 0x4, + /// 32 + @"32" = 0x5, + /// 64 + @"64" = 0x6, + /// 128 + @"128" = 0x7, + /// 256 + @"256" = 0x8, + _, + }; + + pub const CPU_SLEEP_MODE_3BITS2 = enum(u3) { + /// Idle + IDLE = 0x0, + /// ADC Noise Reduction (If Available) + ADC = 0x1, + /// Power Down + PDOWN = 0x2, + /// Power Save + PSAVE = 0x3, + /// Reserved + VAL_0x04 = 0x4, + /// Reserved + VAL_0x05 = 0x5, + /// Standby + STDBY = 0x6, + /// Extended Standby + ESTDBY = 0x7, + }; + + /// Oscillator Calibration Values + pub const OSCCAL_VALUE_ADDRESSES = enum(u1) { + /// 8.0 MHz + @"8_0_MHz" = 0x0, + _, + }; + + /// General Purpose I/O Register 0 + GPIOR0: u8, + reserved12: [11]u8, + /// General Purpose I/O Register 1 + GPIOR1: u8, + /// General Purpose I/O Register 2 + GPIOR2: u8, + reserved21: [7]u8, + /// Sleep Mode Control Register + SMCR: mmio.Mmio(packed struct(u8) { + /// Sleep Enable + SE: u1, + /// Sleep Mode Select Bits + SM: packed union { + raw: u3, + value: CPU_SLEEP_MODE_3BITS2, + }, + padding: u4, + }), + /// MCU Status Register + MCUSR: mmio.Mmio(packed struct(u8) { + /// Power-on reset flag + PORF: u1, + /// External Reset Flag + EXTRF: u1, + /// Brown-out Reset Flag + BORF: u1, + /// Watchdog Reset Flag + WDRF: u1, + padding: u4, + }), + /// MCU Control Register + MCUCR: mmio.Mmio(packed struct(u8) { + IVCE: u1, + IVSEL: u1, + reserved4: u2, + PUD: u1, + /// BOD Sleep Enable + BODSE: u1, + /// BOD Sleep + BODS: u1, + padding: u1, + }), + reserved25: [1]u8, + /// Store Program Memory Control and Status Register + SPMCSR: mmio.Mmio(packed struct(u8) { + /// Store Program Memory + SPMEN: u1, + /// Page Erase + PGERS: u1, + /// Page Write + PGWRT: u1, + /// Boot Lock Bit Set + BLBSET: u1, + /// Read-While-Write section read enable + RWWSRE: u1, + /// Signature Row Read + SIGRD: u1, + /// Read-While-Write Section Busy + RWWSB: u1, + /// SPM Interrupt Enable + SPMIE: u1, + }), + reserved31: [5]u8, + /// Stack Pointer + SP: u16, + /// Status Register + SREG: mmio.Mmio(packed struct(u8) { + /// Carry Flag + C: u1, + /// Zero Flag + Z: u1, + /// Negative Flag + N: u1, + /// Two's Complement Overflow Flag + V: u1, + /// Sign Bit + S: u1, + /// Half Carry Flag + H: u1, + /// Bit Copy Storage + T: u1, + /// Global Interrupt Enable + I: u1, + }), + reserved35: [1]u8, + /// Clock Prescale Register + CLKPR: mmio.Mmio(packed struct(u8) { + /// Clock Prescaler Select Bits + CLKPS: packed union { + raw: u4, + value: CPU_CLK_PRESCALE_4_BITS_SMALL, + }, + reserved7: u3, + /// Clock Prescaler Change Enable + CLKPCE: u1, + }), + reserved38: [2]u8, + /// Power Reduction Register + PRR: mmio.Mmio(packed struct(u8) { + /// Power Reduction ADC + PRADC: u1, + /// Power Reduction USART + PRUSART0: u1, + /// Power Reduction Serial Peripheral Interface + PRSPI: u1, + /// Power Reduction Timer/Counter1 + PRTIM1: u1, + reserved5: u1, + /// Power Reduction Timer/Counter0 + PRTIM0: u1, + /// Power Reduction Timer/Counter2 + PRTIM2: u1, + /// Power Reduction TWI + PRTWI: u1, + }), + reserved40: [1]u8, + /// Oscillator Calibration Value + OSCCAL: mmio.Mmio(packed struct(u8) { + /// Oscillator Calibration + OSCCAL: u8, + }), + }; + + /// EEPROM + pub const EEPROM = extern struct { + pub const EEP_MODE = enum(u2) { + /// Erase and Write in one operation + ERASE_AND_WRITE_IN_ONE_OPERATION = 0x0, + /// Erase Only + ERASE_ONLY = 0x1, + /// Write Only + WRITE_ONLY = 0x2, + _, + }; + + /// EEPROM Control Register + EECR: mmio.Mmio(packed struct(u8) { + /// EEPROM Read Enable + EERE: u1, + /// EEPROM Write Enable + EEPE: u1, + /// EEPROM Master Write Enable + EEMPE: u1, + /// EEPROM Ready Interrupt Enable + EERIE: u1, + /// EEPROM Programming Mode Bits + EEPM: packed union { + raw: u2, + value: EEP_MODE, + }, + padding: u2, + }), + /// EEPROM Data Register + EEDR: u8, + /// EEPROM Address Register Bytes + EEAR: u16, + }; + }; +}; diff --git a/src/hals/ATmega328P.zig b/src/hals/ATmega328P.zig new file mode 100644 index 0000000..b836c65 --- /dev/null +++ b/src/hals/ATmega328P.zig @@ -0,0 +1,191 @@ +const std = @import("std"); +const micro = @import("microzig"); + +pub usingnamespace @import("registers.zig"); +const regz = @import("registers.zig").registers; + +pub const cpu = micro.cpu; +const Port = enum(u8) { + B = 1, + C = 2, + D = 3, +}; + +pub const clock = struct { + pub const Domain = enum { + cpu, + }; +}; + +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec.len != 3) + @compileError(invalid_format_msg); + if (spec[0] != 'P') + @compileError(invalid_format_msg); + + return struct { + pub const port: Port = std.meta.stringToEnum(Port, spec[1..2]) orelse @compileError(invalid_format_msg); + pub const pin: u3 = std.fmt.parseInt(u3, spec[2..3], 10) catch @compileError(invalid_format_msg); + }; +} + +pub const gpio = struct { + fn regs(comptime desc: type) type { + return struct { + // io address + const pin_addr: u5 = 3 * @enumToInt(desc.port) + 0x00; + const dir_addr: u5 = 3 * @enumToInt(desc.port) + 0x01; + const port_addr: u5 = 3 * @enumToInt(desc.port) + 0x02; + + // ram mapping + const pin = @intToPtr(*volatile u8, 0x20 + @as(usize, pin_addr)); + const dir = @intToPtr(*volatile u8, 0x20 + @as(usize, dir_addr)); + const port = @intToPtr(*volatile u8, 0x20 + @as(usize, port_addr)); + }; + } + + pub fn setOutput(comptime pin: type) void { + cpu.sbi(regs(pin).dir_addr, pin.pin); + } + + pub fn setInput(comptime pin: type) void { + cpu.cbi(regs(pin).dir_addr, pin.pin); + } + + pub fn read(comptime pin: type) micro.gpio.State { + return if ((regs(pin).pin.* & (1 << pin.pin)) != 0) + .high + else + .low; + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + if (state == .high) { + cpu.sbi(regs(pin).port_addr, pin.pin); + } else { + cpu.cbi(regs(pin).port_addr, pin.pin); + } + } + + pub fn toggle(comptime pin: type) void { + cpu.sbi(regs(pin).pin_addr, pin.pin); + } +}; + +pub const uart = struct { + pub const DataBits = enum { + five, + six, + seven, + eight, + nine, + }; + + pub const StopBits = enum { + one, + two, + }; + + pub const Parity = enum { + odd, + even, + }; +}; + +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { + if (index != 0) @compileError("Atmega328p only has a single uart!"); + if (pins.tx != null or pins.rx != null) + @compileError("Atmega328p has fixed pins for uart!"); + + return struct { + const Self = @This(); + + fn computeDivider(baud_rate: u32) !u12 { + const pclk = micro.clock.get().cpu; + const divider = ((pclk + (8 * baud_rate)) / (16 * baud_rate)) - 1; + + return std.math.cast(u12, divider) orelse return error.UnsupportedBaudRate; + } + + fn computeBaudRate(divider: u12) u32 { + return micro.clock.get().cpu / (16 * @as(u32, divider) + 1); + } + + pub fn init(config: micro.uart.Config) !Self { + const ucsz: u3 = switch (config.data_bits) { + .five => 0b000, + .six => 0b001, + .seven => 0b010, + .eight => 0b011, + .nine => return error.UnsupportedWordSize, // 0b111 + }; + + const upm: u2 = if (config.parity) |parity| switch (parity) { + .even => @as(u2, 0b10), // even + .odd => @as(u2, 0b11), // odd + } else 0b00; // parity disabled + + const usbs: u1 = switch (config.stop_bits) { + .one => 0b0, + .two => 0b1, + }; + + const umsel: u2 = 0b00; // Asynchronous USART + + // baud is computed like this: + // f(osc) + // BAUD = ---------------- + // 16 * (UBRRn + 1) + + const ubrr_val = try computeDivider(config.baud_rate); + + regz.USART0.UCSR0A.modify(.{ + .MPCM0 = 0, + .U2X0 = 0, + }); + regz.USART0.UCSR0B.write(.{ + .TXB80 = 0, // we don't care about these btw + .RXB80 = 0, // we don't care about these btw + .UCSZ02 = @truncate(u1, (ucsz & 0x04) >> 2), + .TXEN0 = 1, + .RXEN0 = 1, + .UDRIE0 = 0, // no interrupts + .TXCIE0 = 0, // no interrupts + .RXCIE0 = 0, // no interrupts + }); + regz.USART0.UCSR0C.write(.{ + .UCPOL0 = 0, // async mode + .UCSZ0 = @truncate(u2, (ucsz & 0x03) >> 0), + .USBS0 = usbs, + .UPM0 = upm, + .UMSEL0 = umsel, + }); + + regz.USART0.UBRR0.modify(ubrr_val); + + return Self{}; + } + + pub fn canWrite(self: Self) bool { + _ = self; + return (regz.USART0.UCSR0A.read().UDRE0 == 1); + } + + pub fn tx(self: Self, ch: u8) void { + while (!self.canWrite()) {} // Wait for Previous transmission + regz.USART0.UDR0.* = ch; // Load the data to be transmitted + } + + pub fn canRead(self: Self) bool { + _ = self; + return (regz.USART0.UCSR0A.read().RXC0 == 1); + } + + pub fn rx(self: Self) u8 { + while (!self.canRead()) {} // Wait till the data is received + return regz.USART0.UDR0.*; // Read received data + } + }; +}