From d8e329d90b75800964f3681df2e41ee8d19f7a77 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 18 Feb 2023 07:22:55 -0500 Subject: [PATCH 01/20] restructure for regz rewrite --- .gitignore | 2 + README.adoc | 7 + build.zig | 20 + src/chips.zig | 43 + src/chips/nrf52.json | 34901 ++++++++++++++++++++++++++++ src/chips/nrf52.zig | 16821 ++++++++++++++ src/chips/nrf52840.json | 44867 ++++++++++++++++++++++++++++++++++++ src/chips/nrf52840.zig | 21782 +++++++++++++++++ test/nrf52840.robot | 10 + test/programs/minimal.zig | 5 + 10 files changed, 118458 insertions(+) create mode 100644 .gitignore create mode 100644 README.adoc create mode 100644 build.zig create mode 100644 src/chips.zig create mode 100644 src/chips/nrf52.json create mode 100644 src/chips/nrf52.zig create mode 100644 src/chips/nrf52840.json create mode 100644 src/chips/nrf52840.zig create mode 100644 test/nrf52840.robot create mode 100644 test/programs/minimal.zig diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..c26d4af --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +zig-out +zig-cache diff --git a/README.adoc b/README.adoc new file mode 100644 index 0000000..0a66afd --- /dev/null +++ b/README.adoc @@ -0,0 +1,7 @@ += Nordic nrf5x + +HALs and register definitions for nrf5x devices + +== Renode supports: + +- nrf52840 development kit diff --git a/build.zig b/build.zig new file mode 100644 index 0000000..4039838 --- /dev/null +++ b/build.zig @@ -0,0 +1,20 @@ +const std = @import("std"); +const microzig = @import("deps/microzig/src/main.zig"); +const chips = @import("src/chips.zig"); + +pub fn build(b: *std.build.Builder) void { + const optimize = b.standardOptimizeOption(.{}); + inline for (@typeInfo(chips).Struct.decls) |decl| { + if (!decl.is_pub) + continue; + + const exe = microzig.addEmbeddedExecutable( + b, + decl.name ++ ".minimal", + "test/programs/minimal.zig", + .{ .chip = @field(chips, decl.name) }, + .{ .optimize = optimize }, + ); + exe.install(); + } +} diff --git a/src/chips.zig b/src/chips.zig new file mode 100644 index 0000000..50b2aad --- /dev/null +++ b/src/chips.zig @@ -0,0 +1,43 @@ +const std = @import("std"); +const micro = @import("../deps/microzig/src/main.zig"); +const Chip = micro.Chip; +const MemoryRegion = micro.MemoryRegion; + +fn root_dir() []const u8 { + return std.fs.path.dirname(@src().file) orelse unreachable; +} + +pub const nrf52840 = Chip{ + .name = "nrf52840", + .source = .{ + .path = root_dir() ++ "/chips/nrf52840.zig", + }, + .json_register_schema = .{ + .path = root_dir() ++ "/chips.nrf52840.json", + }, + .cpu = micro.cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x00000000, .length = 0x100000, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + + // EXTFLASH + MemoryRegion{ .offset = 0x12000000, .length = 0x8000000, .kind = .flash }, + // CODE_RAM + MemoryRegion{ .offset = 0x800000, .length = 0x40000, .kind = .ram }, + }, +}; + +pub const nrf52832 = Chip{ + .name = "nrf52", + .source = .{ + .path = root_dir() ++ "/chips/nrf52.zig", + }, + .json_register_schema = .{ + .path = root_dir() ++ "/chips.nrf52.json", + }, + .cpu = micro.cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, +}; diff --git a/src/chips/nrf52.json b/src/chips/nrf52.json new file mode 100644 index 0000000..8c71c64 --- /dev/null +++ b/src/chips/nrf52.json @@ -0,0 +1,34901 @@ +{ + "version": "0.1.0", + "types": { + "peripherals": { + "SCS": { + "description": "System Control Space", + "children": { + "register_groups": { + "SysTick": { + "description": "System Tick Timer", + "children": { + "registers": { + "CTRL": { + "description": "SysTick Control and Status Register", + "offset": 0, + "size": 32, + "children": { + "fields": { + "ENABLE": { + "offset": 0, + "size": 1 + }, + "TICKINT": { + "offset": 1, + "size": 1 + }, + "CLKSOURCE": { + "offset": 2, + "size": 1 + }, + "COUNTFLAG": { + "offset": 16, + "size": 1 + } + } + } + }, + "LOAD": { + "description": "SysTick Reload Value Register", + "offset": 4, + "size": 32, + "children": { + "fields": { + "RELOAD": { + "offset": 0, + "size": 24 + } + } + } + }, + "VAL": { + "description": "SysTick Current Value Register", + "offset": 8, + "size": 32, + "children": { + "fields": { + "CURRENT": { + "offset": 0, + "size": 24 + } + } + } + }, + "CALIB": { + "description": "SysTick Calibration Register", + "offset": 12, + "size": 32, + "access": "read-only", + "children": { + "fields": { + "TENMS": { + "offset": 0, + "size": 24 + }, + "SKEW": { + "offset": 30, + "size": 1 + }, + "NOREF": { + "offset": 31, + "size": 1 + } + } + } + } + } + } + } + } + } + }, + "FICR": { + "description": "Factory Information Configuration Registers", + "children": { + "registers": { + "CODEPAGESIZE": { + "description": "Code memory page size", + "offset": 16, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CODEPAGESIZE": { + "description": "Code memory page size", + "offset": 0, + "size": 32 + } + } + } + }, + "CODESIZE": { + "description": "Code memory size", + "offset": 20, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CODESIZE": { + "description": "Code memory size in number of pages", + "offset": 0, + "size": 32 + } + } + } + }, + "DEVICEID": { + "description": "Description collection[0]: Device identifier", + "offset": 96, + "size": 32, + "count": 2, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DEVICEID": { + "description": "64 bit unique device identifier", + "offset": 0, + "size": 32 + } + } + } + }, + "ER": { + "description": "Description collection[0]: Encryption Root, word 0", + "offset": 128, + "size": 32, + "count": 4, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ER": { + "description": "Encryption Root, word n", + "offset": 0, + "size": 32 + } + } + } + }, + "IR": { + "description": "Description collection[0]: Identity Root, word 0", + "offset": 144, + "size": 32, + "count": 4, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IR": { + "description": "Identity Root, word n", + "offset": 0, + "size": 32 + } + } + } + }, + "DEVICEADDRTYPE": { + "description": "Device address type", + "offset": 160, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DEVICEADDRTYPE": { + "description": "Device address type", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Public": { + "description": "Public address", + "value": 0 + }, + "Random": { + "description": "Random address", + "value": 1 + } + } + } + } + } + } + } + }, + "DEVICEADDR": { + "description": "Description collection[0]: Device address 0", + "offset": 164, + "size": 32, + "count": 2, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DEVICEADDR": { + "description": "48 bit device address", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "UICR": { + "description": "User Information Configuration Registers", + "children": { + "registers": { + "UNUSED0": { + "description": "Unspecified", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "UNUSED1": { + "description": "Unspecified", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "UNUSED2": { + "description": "Unspecified", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "UNUSED3": { + "description": "Unspecified", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "NRFFW": { + "description": "Description collection[0]: Reserved for Nordic firmware design", + "offset": 20, + "size": 32, + "count": 15, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "NRFFW": { + "description": "Reserved for Nordic firmware design", + "offset": 0, + "size": 32 + } + } + } + }, + "NRFHW": { + "description": "Description collection[0]: Reserved for Nordic hardware design", + "offset": 80, + "size": 32, + "count": 12, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "NRFHW": { + "description": "Reserved for Nordic hardware design", + "offset": 0, + "size": 32 + } + } + } + }, + "CUSTOMER": { + "description": "Description collection[0]: Reserved for customer", + "offset": 128, + "size": 32, + "count": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "CUSTOMER": { + "description": "Reserved for customer", + "offset": 0, + "size": 32 + } + } + } + }, + "PSELRESET": { + "description": "Description collection[0]: Mapping of the nRESET function (see POWER chapter for details)", + "offset": 512, + "size": 32, + "count": 2, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN": { + "description": "GPIO number P0.n onto which Reset is exposed", + "offset": 0, + "size": 6 + }, + "CONNECT": { + "description": "Connection", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disconnected": { + "description": "Disconnect", + "value": 1 + }, + "Connected": { + "description": "Connect", + "value": 0 + } + } + } + } + } + } + } + }, + "APPROTECT": { + "description": "Access Port protection", + "offset": 520, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PALL": { + "description": "Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection.", + "offset": 0, + "size": 8, + "enum": { + "size": 8, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 255 + }, + "Enabled": { + "description": "Enable", + "value": 0 + } + } + } + } + } + } + } + }, + "NFCPINS": { + "description": "Setting of pins dedicated to NFC functionality: NFC antenna or GPIO", + "offset": 524, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PROTECT": { + "description": "Setting of pins dedicated to NFC functionality", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Operation as GPIO pins. Same protection as normal GPIO pins", + "value": 0 + }, + "NFC": { + "description": "Operation as NFC antenna pins. Configures the protection for NFC operation", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "BPROT": { + "description": "Block Protect", + "children": { + "registers": { + "CONFIG0": { + "description": "Block protect configuration register 0", + "offset": 1536, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION0": { + "description": "Enable protection for region 0. Write '0' has no effect.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION1": { + "description": "Enable protection for region 1. Write '0' has no effect.", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION2": { + "description": "Enable protection for region 2. Write '0' has no effect.", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION3": { + "description": "Enable protection for region 3. Write '0' has no effect.", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION4": { + "description": "Enable protection for region 4. Write '0' has no effect.", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION5": { + "description": "Enable protection for region 5. Write '0' has no effect.", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION6": { + "description": "Enable protection for region 6. Write '0' has no effect.", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION7": { + "description": "Enable protection for region 7. Write '0' has no effect.", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION8": { + "description": "Enable protection for region 8. Write '0' has no effect.", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION9": { + "description": "Enable protection for region 9. Write '0' has no effect.", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION10": { + "description": "Enable protection for region 10. Write '0' has no effect.", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION11": { + "description": "Enable protection for region 11. Write '0' has no effect.", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION12": { + "description": "Enable protection for region 12. Write '0' has no effect.", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION13": { + "description": "Enable protection for region 13. Write '0' has no effect.", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION14": { + "description": "Enable protection for region 14. Write '0' has no effect.", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION15": { + "description": "Enable protection for region 15. Write '0' has no effect.", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION16": { + "description": "Enable protection for region 16. Write '0' has no effect.", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION17": { + "description": "Enable protection for region 17. Write '0' has no effect.", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION18": { + "description": "Enable protection for region 18. Write '0' has no effect.", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION19": { + "description": "Enable protection for region 19. Write '0' has no effect.", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION20": { + "description": "Enable protection for region 20. Write '0' has no effect.", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION21": { + "description": "Enable protection for region 21. Write '0' has no effect.", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION22": { + "description": "Enable protection for region 22. Write '0' has no effect.", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION23": { + "description": "Enable protection for region 23. Write '0' has no effect.", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION24": { + "description": "Enable protection for region 24. Write '0' has no effect.", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION25": { + "description": "Enable protection for region 25. Write '0' has no effect.", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION26": { + "description": "Enable protection for region 26. Write '0' has no effect.", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION27": { + "description": "Enable protection for region 27. Write '0' has no effect.", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION28": { + "description": "Enable protection for region 28. Write '0' has no effect.", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION29": { + "description": "Enable protection for region 29. Write '0' has no effect.", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION30": { + "description": "Enable protection for region 30. Write '0' has no effect.", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + }, + "REGION31": { + "description": "Enable protection for region 31. Write '0' has no effect.", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enable", + "value": 1 + } + } + } + } + } + } + } + }, + "CONFIG1": { + "description": "Block protect configuration register 1", + "offset": 1540, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION32": { + "description": "Enable protection for region 32. Write '0' has no effect.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION33": { + "description": "Enable protection for region 33. Write '0' has no effect.", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION34": { + "description": "Enable protection for region 34. Write '0' has no effect.", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION35": { + "description": "Enable protection for region 35. Write '0' has no effect.", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION36": { + "description": "Enable protection for region 36. Write '0' has no effect.", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION37": { + "description": "Enable protection for region 37. Write '0' has no effect.", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION38": { + "description": "Enable protection for region 38. Write '0' has no effect.", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION39": { + "description": "Enable protection for region 39. Write '0' has no effect.", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION40": { + "description": "Enable protection for region 40. Write '0' has no effect.", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION41": { + "description": "Enable protection for region 41. Write '0' has no effect.", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION42": { + "description": "Enable protection for region 42. Write '0' has no effect.", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION43": { + "description": "Enable protection for region 43. Write '0' has no effect.", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION44": { + "description": "Enable protection for region 44. Write '0' has no effect.", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION45": { + "description": "Enable protection for region 45. Write '0' has no effect.", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION46": { + "description": "Enable protection for region 46. Write '0' has no effect.", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION47": { + "description": "Enable protection for region 47. Write '0' has no effect.", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION48": { + "description": "Enable protection for region 48. Write '0' has no effect.", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION49": { + "description": "Enable protection for region 49. Write '0' has no effect.", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION50": { + "description": "Enable protection for region 50. Write '0' has no effect.", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION51": { + "description": "Enable protection for region 51. Write '0' has no effect.", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION52": { + "description": "Enable protection for region 52. Write '0' has no effect.", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION53": { + "description": "Enable protection for region 53. Write '0' has no effect.", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION54": { + "description": "Enable protection for region 54. Write '0' has no effect.", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION55": { + "description": "Enable protection for region 55. Write '0' has no effect.", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION56": { + "description": "Enable protection for region 56. Write '0' has no effect.", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION57": { + "description": "Enable protection for region 57. Write '0' has no effect.", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION58": { + "description": "Enable protection for region 58. Write '0' has no effect.", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION59": { + "description": "Enable protection for region 59. Write '0' has no effect.", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION60": { + "description": "Enable protection for region 60. Write '0' has no effect.", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION61": { + "description": "Enable protection for region 61. Write '0' has no effect.", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION62": { + "description": "Enable protection for region 62. Write '0' has no effect.", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION63": { + "description": "Enable protection for region 63. Write '0' has no effect.", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "DISABLEINDEBUG": { + "description": "Disable protection mechanism in debug interface mode", + "offset": 1544, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "DISABLEINDEBUG": { + "description": "Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable in debug", + "value": 1 + }, + "Enabled": { + "description": "Enable in debug", + "value": 0 + } + } + } + } + } + } + } + }, + "UNUSED0": { + "description": "Unspecified", + "offset": 1548, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "CONFIG2": { + "description": "Block protect configuration register 2", + "offset": 1552, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION64": { + "description": "Enable protection for region 64. Write '0' has no effect.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION65": { + "description": "Enable protection for region 65. Write '0' has no effect.", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION66": { + "description": "Enable protection for region 66. Write '0' has no effect.", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION67": { + "description": "Enable protection for region 67. Write '0' has no effect.", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION68": { + "description": "Enable protection for region 68. Write '0' has no effect.", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION69": { + "description": "Enable protection for region 69. Write '0' has no effect.", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION70": { + "description": "Enable protection for region 70. Write '0' has no effect.", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION71": { + "description": "Enable protection for region 71. Write '0' has no effect.", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION72": { + "description": "Enable protection for region 72. Write '0' has no effect.", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION73": { + "description": "Enable protection for region 73. Write '0' has no effect.", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION74": { + "description": "Enable protection for region 74. Write '0' has no effect.", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION75": { + "description": "Enable protection for region 75. Write '0' has no effect.", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION76": { + "description": "Enable protection for region 76. Write '0' has no effect.", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION77": { + "description": "Enable protection for region 77. Write '0' has no effect.", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION78": { + "description": "Enable protection for region 78. Write '0' has no effect.", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION79": { + "description": "Enable protection for region 79. Write '0' has no effect.", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION80": { + "description": "Enable protection for region 80. Write '0' has no effect.", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION81": { + "description": "Enable protection for region 81. Write '0' has no effect.", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION82": { + "description": "Enable protection for region 82. Write '0' has no effect.", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION83": { + "description": "Enable protection for region 83. Write '0' has no effect.", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION84": { + "description": "Enable protection for region 84. Write '0' has no effect.", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION85": { + "description": "Enable protection for region 85. Write '0' has no effect.", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION86": { + "description": "Enable protection for region 86. Write '0' has no effect.", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION87": { + "description": "Enable protection for region 87. Write '0' has no effect.", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION88": { + "description": "Enable protection for region 88. Write '0' has no effect.", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION89": { + "description": "Enable protection for region 89. Write '0' has no effect.", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION90": { + "description": "Enable protection for region 90. Write '0' has no effect.", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION91": { + "description": "Enable protection for region 91. Write '0' has no effect.", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION92": { + "description": "Enable protection for region 92. Write '0' has no effect.", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION93": { + "description": "Enable protection for region 93. Write '0' has no effect.", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION94": { + "description": "Enable protection for region 94. Write '0' has no effect.", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION95": { + "description": "Enable protection for region 95. Write '0' has no effect.", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "CONFIG3": { + "description": "Block protect configuration register 3", + "offset": 1556, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION96": { + "description": "Enable protection for region 96. Write '0' has no effect.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION97": { + "description": "Enable protection for region 97. Write '0' has no effect.", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION98": { + "description": "Enable protection for region 98. Write '0' has no effect.", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION99": { + "description": "Enable protection for region 99. Write '0' has no effect.", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION100": { + "description": "Enable protection for region 100. Write '0' has no effect.", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION101": { + "description": "Enable protection for region 101. Write '0' has no effect.", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION102": { + "description": "Enable protection for region 102. Write '0' has no effect.", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION103": { + "description": "Enable protection for region 103. Write '0' has no effect.", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION104": { + "description": "Enable protection for region 104. Write '0' has no effect.", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION105": { + "description": "Enable protection for region 105. Write '0' has no effect.", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION106": { + "description": "Enable protection for region 106. Write '0' has no effect.", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION107": { + "description": "Enable protection for region 107. Write '0' has no effect.", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION108": { + "description": "Enable protection for region 108. Write '0' has no effect.", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION109": { + "description": "Enable protection for region 109. Write '0' has no effect.", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION110": { + "description": "Enable protection for region 110. Write '0' has no effect.", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION111": { + "description": "Enable protection for region 111. Write '0' has no effect.", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION112": { + "description": "Enable protection for region 112. Write '0' has no effect.", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION113": { + "description": "Enable protection for region 113. Write '0' has no effect.", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION114": { + "description": "Enable protection for region 114. Write '0' has no effect.", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION115": { + "description": "Enable protection for region 115. Write '0' has no effect.", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION116": { + "description": "Enable protection for region 116. Write '0' has no effect.", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION117": { + "description": "Enable protection for region 117. Write '0' has no effect.", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION118": { + "description": "Enable protection for region 118. Write '0' has no effect.", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION119": { + "description": "Enable protection for region 119. Write '0' has no effect.", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION120": { + "description": "Enable protection for region 120. Write '0' has no effect.", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION121": { + "description": "Enable protection for region 121. Write '0' has no effect.", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION122": { + "description": "Enable protection for region 122. Write '0' has no effect.", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION123": { + "description": "Enable protection for region 123. Write '0' has no effect.", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION124": { + "description": "Enable protection for region 124. Write '0' has no effect.", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION125": { + "description": "Enable protection for region 125. Write '0' has no effect.", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION126": { + "description": "Enable protection for region 126. Write '0' has no effect.", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + }, + "REGION127": { + "description": "Enable protection for region 127. Write '0' has no effect.", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Protection disabled", + "value": 0 + }, + "Enabled": { + "description": "Protection enabled", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "POWER": { + "description": "Power control", + "children": { + "registers": { + "TASKS_CONSTLAT": { + "description": "Enable constant latency mode", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_LOWPWR": { + "description": "Enable low power mode (variable latency)", + "offset": 124, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_POFWARN": { + "description": "Power failure warning", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_SLEEPENTER": { + "description": "CPU entered WFI/WFE sleep", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_SLEEPEXIT": { + "description": "CPU exited WFI/WFE sleep", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "POFWARN": { + "description": "Write '1' to Enable interrupt for POFWARN event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SLEEPENTER": { + "description": "Write '1' to Enable interrupt for SLEEPENTER event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SLEEPEXIT": { + "description": "Write '1' to Enable interrupt for SLEEPEXIT event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "POFWARN": { + "description": "Write '1' to Disable interrupt for POFWARN event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SLEEPENTER": { + "description": "Write '1' to Disable interrupt for SLEEPENTER event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SLEEPEXIT": { + "description": "Write '1' to Disable interrupt for SLEEPEXIT event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "RESETREAS": { + "description": "Reset reason", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RESETPIN": { + "description": "Reset from pin-reset detected", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "DOG": { + "description": "Reset from watchdog detected", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "SREQ": { + "description": "Reset from soft reset detected", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "LOCKUP": { + "description": "Reset from CPU lock-up detected", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "OFF": { + "description": "Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "LPCOMP": { + "description": "Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "DIF": { + "description": "Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "NFC": { + "description": "Reset due to wake up from System OFF mode by NFC field detect", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + } + } + } + }, + "RAMSTATUS": { + "description": "Deprecated register - RAM status register", + "offset": 1064, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RAMBLOCK0": { + "description": "RAM block 0 is on or off/powering up", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Off": { + "description": "Off", + "value": 0 + }, + "On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "RAMBLOCK1": { + "description": "RAM block 1 is on or off/powering up", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Off": { + "description": "Off", + "value": 0 + }, + "On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "RAMBLOCK2": { + "description": "RAM block 2 is on or off/powering up", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Off": { + "description": "Off", + "value": 0 + }, + "On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "RAMBLOCK3": { + "description": "RAM block 3 is on or off/powering up", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Off": { + "description": "Off", + "value": 0 + }, + "On": { + "description": "On", + "value": 1 + } + } + } + } + } + } + } + }, + "SYSTEMOFF": { + "description": "System OFF register", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "SYSTEMOFF": { + "description": "Enable System OFF mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Enter": { + "description": "Enable System OFF mode", + "value": 1 + } + } + } + } + } + } + } + }, + "POFCON": { + "description": "Power failure comparator configuration", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "POF": { + "description": "Enable or disable power failure comparator", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "THRESHOLD": { + "description": "Power failure comparator threshold setting", + "offset": 1, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "V17": { + "description": "Set threshold to 1.7 V", + "value": 4 + }, + "V18": { + "description": "Set threshold to 1.8 V", + "value": 5 + }, + "V19": { + "description": "Set threshold to 1.9 V", + "value": 6 + }, + "V20": { + "description": "Set threshold to 2.0 V", + "value": 7 + }, + "V21": { + "description": "Set threshold to 2.1 V", + "value": 8 + }, + "V22": { + "description": "Set threshold to 2.2 V", + "value": 9 + }, + "V23": { + "description": "Set threshold to 2.3 V", + "value": 10 + }, + "V24": { + "description": "Set threshold to 2.4 V", + "value": 11 + }, + "V25": { + "description": "Set threshold to 2.5 V", + "value": 12 + }, + "V26": { + "description": "Set threshold to 2.6 V", + "value": 13 + }, + "V27": { + "description": "Set threshold to 2.7 V", + "value": 14 + }, + "V28": { + "description": "Set threshold to 2.8 V", + "value": 15 + } + } + } + } + } + } + } + }, + "GPREGRET": { + "description": "General purpose retention register", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GPREGRET": { + "description": "General purpose retention register", + "offset": 0, + "size": 8 + } + } + } + }, + "GPREGRET2": { + "description": "General purpose retention register", + "offset": 1312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GPREGRET": { + "description": "General purpose retention register", + "offset": 0, + "size": 8 + } + } + } + }, + "RAMON": { + "description": "Deprecated register - RAM on/off register (this register is retained)", + "offset": 1316, + "size": 32, + "reset_value": 3, + "reset_mask": 4294967295, + "children": { + "fields": { + "ONRAM0": { + "description": "Keep RAM block 0 on or off in system ON Mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RAM0Off": { + "description": "Off", + "value": 0 + }, + "RAM0On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "ONRAM1": { + "description": "Keep RAM block 1 on or off in system ON Mode", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RAM1Off": { + "description": "Off", + "value": 0 + }, + "RAM1On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "OFFRAM0": { + "description": "Keep retention on RAM block 0 when RAM block is switched off", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RAM0Off": { + "description": "Off", + "value": 0 + }, + "RAM0On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "OFFRAM1": { + "description": "Keep retention on RAM block 1 when RAM block is switched off", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RAM1Off": { + "description": "Off", + "value": 0 + }, + "RAM1On": { + "description": "On", + "value": 1 + } + } + } + } + } + } + } + }, + "RAMONB": { + "description": "Deprecated register - RAM on/off register (this register is retained)", + "offset": 1364, + "size": 32, + "reset_value": 3, + "reset_mask": 4294967295, + "children": { + "fields": { + "ONRAM2": { + "description": "Keep RAM block 2 on or off in system ON Mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RAM2Off": { + "description": "Off", + "value": 0 + }, + "RAM2On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "ONRAM3": { + "description": "Keep RAM block 3 on or off in system ON Mode", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RAM3Off": { + "description": "Off", + "value": 0 + }, + "RAM3On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "OFFRAM2": { + "description": "Keep retention on RAM block 2 when RAM block is switched off", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RAM2Off": { + "description": "Off", + "value": 0 + }, + "RAM2On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "OFFRAM3": { + "description": "Keep retention on RAM block 3 when RAM block is switched off", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RAM3Off": { + "description": "Off", + "value": 0 + }, + "RAM3On": { + "description": "On", + "value": 1 + } + } + } + } + } + } + } + }, + "DCDCEN": { + "description": "DC/DC enable register", + "offset": 1400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCDCEN": { + "description": "Enable or disable DC/DC converter", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "CLOCK": { + "description": "Clock control", + "children": { + "registers": { + "TASKS_HFCLKSTART": { + "description": "Start HFCLK crystal oscillator", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_HFCLKSTOP": { + "description": "Stop HFCLK crystal oscillator", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_LFCLKSTART": { + "description": "Start LFCLK source", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_LFCLKSTOP": { + "description": "Stop LFCLK source", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_CAL": { + "description": "Start calibration of LFRC oscillator", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_CTSTART": { + "description": "Start calibration timer", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_CTSTOP": { + "description": "Stop calibration timer", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_HFCLKSTARTED": { + "description": "HFCLK oscillator started", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_LFCLKSTARTED": { + "description": "LFCLK started", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_DONE": { + "description": "Calibration of LFCLK RC oscillator complete event", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_CTTO": { + "description": "Calibration timer timeout", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HFCLKSTARTED": { + "description": "Write '1' to Enable interrupt for HFCLKSTARTED event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LFCLKSTARTED": { + "description": "Write '1' to Enable interrupt for LFCLKSTARTED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DONE": { + "description": "Write '1' to Enable interrupt for DONE event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CTTO": { + "description": "Write '1' to Enable interrupt for CTTO event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HFCLKSTARTED": { + "description": "Write '1' to Disable interrupt for HFCLKSTARTED event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LFCLKSTARTED": { + "description": "Write '1' to Disable interrupt for LFCLKSTARTED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DONE": { + "description": "Write '1' to Disable interrupt for DONE event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CTTO": { + "description": "Write '1' to Disable interrupt for CTTO event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "HFCLKRUN": { + "description": "Status indicating that HFCLKSTART task has been triggered", + "offset": 1032, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STATUS": { + "description": "HFCLKSTART task triggered or not", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotTriggered": { + "description": "Task not triggered", + "value": 0 + }, + "Triggered": { + "description": "Task triggered", + "value": 1 + } + } + } + } + } + } + } + }, + "HFCLKSTAT": { + "description": "HFCLK status", + "offset": 1036, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SRC": { + "description": "Source of HFCLK", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RC": { + "description": "64 MHz internal oscillator (HFINT)", + "value": 0 + }, + "Xtal": { + "description": "64 MHz crystal oscillator (HFXO)", + "value": 1 + } + } + } + } + }, + "STATE": { + "description": "HFCLK state", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotRunning": { + "description": "HFCLK not running", + "value": 0 + }, + "Running": { + "description": "HFCLK running", + "value": 1 + } + } + } + } + } + } + } + }, + "LFCLKRUN": { + "description": "Status indicating that LFCLKSTART task has been triggered", + "offset": 1044, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STATUS": { + "description": "LFCLKSTART task triggered or not", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotTriggered": { + "description": "Task not triggered", + "value": 0 + }, + "Triggered": { + "description": "Task triggered", + "value": 1 + } + } + } + } + } + } + } + }, + "LFCLKSTAT": { + "description": "LFCLK status", + "offset": 1048, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SRC": { + "description": "Source of LFCLK", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "RC": { + "description": "32.768 kHz RC oscillator", + "value": 0 + }, + "Xtal": { + "description": "32.768 kHz crystal oscillator", + "value": 1 + }, + "Synth": { + "description": "32.768 kHz synthesized from HFCLK", + "value": 2 + } + } + } + } + }, + "STATE": { + "description": "LFCLK state", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotRunning": { + "description": "LFCLK not running", + "value": 0 + }, + "Running": { + "description": "LFCLK running", + "value": 1 + } + } + } + } + } + } + } + }, + "LFCLKSRCCOPY": { + "description": "Copy of LFCLKSRC register, set when LFCLKSTART task was triggered", + "offset": 1052, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SRC": { + "description": "Clock source", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "RC": { + "description": "32.768 kHz RC oscillator", + "value": 0 + }, + "Xtal": { + "description": "32.768 kHz crystal oscillator", + "value": 1 + }, + "Synth": { + "description": "32.768 kHz synthesized from HFCLK", + "value": 2 + } + } + } + } + } + } + } + }, + "LFCLKSRC": { + "description": "Clock source for the LFCLK", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRC": { + "description": "Clock source", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "RC": { + "description": "32.768 kHz RC oscillator", + "value": 0 + }, + "Xtal": { + "description": "32.768 kHz crystal oscillator", + "value": 1 + }, + "Synth": { + "description": "32.768 kHz synthesized from HFCLK", + "value": 2 + } + } + } + } + }, + "BYPASS": { + "description": "Enable or disable bypass of LFCLK crystal oscillator with external clock source", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable (use with Xtal or low-swing external source)", + "value": 0 + }, + "Enabled": { + "description": "Enable (use with rail-to-rail external source)", + "value": 1 + } + } + } + } + }, + "EXTERNAL": { + "description": "Enable or disable external source for LFCLK", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable external source (use with Xtal)", + "value": 0 + }, + "Enabled": { + "description": "Enable use of external source instead of Xtal (SRC needs to be set to Xtal)", + "value": 1 + } + } + } + } + } + } + } + }, + "CTIV": { + "description": "Calibration timer interval", + "offset": 1336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTIV": { + "description": "Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.", + "offset": 0, + "size": 7 + } + } + } + }, + "TRACECONFIG": { + "description": "Clocking options for the Trace Port debug interface", + "offset": 1372, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TRACEPORTSPEED": { + "description": "Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two.", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "32MHz": { + "description": "32 MHz Trace Port clock (TRACECLK = 16 MHz)", + "value": 0 + }, + "16MHz": { + "description": "16 MHz Trace Port clock (TRACECLK = 8 MHz)", + "value": 1 + }, + "8MHz": { + "description": "8 MHz Trace Port clock (TRACECLK = 4 MHz)", + "value": 2 + }, + "4MHz": { + "description": "4 MHz Trace Port clock (TRACECLK = 2 MHz)", + "value": 3 + } + } + } + } + }, + "TRACEMUX": { + "description": "Pin multiplexing of trace signals.", + "offset": 16, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "GPIO": { + "description": "GPIOs multiplexed onto all trace-pins", + "value": 0 + }, + "Serial": { + "description": "SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins", + "value": 1 + }, + "Parallel": { + "description": "TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14.", + "value": 2 + } + } + } + } + } + } + } + } + } + } + }, + "RADIO": { + "description": "2.4 GHz Radio", + "children": { + "registers": { + "TASKS_TXEN": { + "description": "Enable RADIO in TX mode", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_RXEN": { + "description": "Enable RADIO in RX mode", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_START": { + "description": "Start RADIO", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop RADIO", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_DISABLE": { + "description": "Disable RADIO", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_RSSISTART": { + "description": "Start the RSSI and take one single sample of the receive signal strength.", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_RSSISTOP": { + "description": "Stop the RSSI measurement", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_BCSTART": { + "description": "Start the bit counter", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_BCSTOP": { + "description": "Stop the bit counter", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_READY": { + "description": "RADIO has ramped up and is ready to be started", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ADDRESS": { + "description": "Address sent or received", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_PAYLOAD": { + "description": "Packet payload sent or received", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_END": { + "description": "Packet sent or received", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_DISABLED": { + "description": "RADIO has been disabled", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_DEVMATCH": { + "description": "A device address match occurred on the last received packet", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_DEVMISS": { + "description": "No device address match occurred on the last received packet", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RSSIEND": { + "description": "Sampling of receive signal strength complete.", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_BCMATCH": { + "description": "Bit counter reached bit count value.", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_CRCOK": { + "description": "Packet received with CRC ok", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_CRCERROR": { + "description": "Packet received with CRC error", + "offset": 308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY_START": { + "description": "Shortcut between READY event and START task", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "END_DISABLE": { + "description": "Shortcut between END event and DISABLE task", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DISABLED_TXEN": { + "description": "Shortcut between DISABLED event and TXEN task", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DISABLED_RXEN": { + "description": "Shortcut between DISABLED event and RXEN task", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "ADDRESS_RSSISTART": { + "description": "Shortcut between ADDRESS event and RSSISTART task", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "END_START": { + "description": "Shortcut between END event and START task", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "ADDRESS_BCSTART": { + "description": "Shortcut between ADDRESS event and BCSTART task", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DISABLED_RSSISTOP": { + "description": "Shortcut between DISABLED event and RSSISTOP task", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to Enable interrupt for READY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ADDRESS": { + "description": "Write '1' to Enable interrupt for ADDRESS event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PAYLOAD": { + "description": "Write '1' to Enable interrupt for PAYLOAD event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to Enable interrupt for END event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DISABLED": { + "description": "Write '1' to Enable interrupt for DISABLED event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DEVMATCH": { + "description": "Write '1' to Enable interrupt for DEVMATCH event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DEVMISS": { + "description": "Write '1' to Enable interrupt for DEVMISS event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RSSIEND": { + "description": "Write '1' to Enable interrupt for RSSIEND event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "BCMATCH": { + "description": "Write '1' to Enable interrupt for BCMATCH event", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CRCOK": { + "description": "Write '1' to Enable interrupt for CRCOK event", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CRCERROR": { + "description": "Write '1' to Enable interrupt for CRCERROR event", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to Disable interrupt for READY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ADDRESS": { + "description": "Write '1' to Disable interrupt for ADDRESS event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PAYLOAD": { + "description": "Write '1' to Disable interrupt for PAYLOAD event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to Disable interrupt for END event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DISABLED": { + "description": "Write '1' to Disable interrupt for DISABLED event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DEVMATCH": { + "description": "Write '1' to Disable interrupt for DEVMATCH event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DEVMISS": { + "description": "Write '1' to Disable interrupt for DEVMISS event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RSSIEND": { + "description": "Write '1' to Disable interrupt for RSSIEND event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "BCMATCH": { + "description": "Write '1' to Disable interrupt for BCMATCH event", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CRCOK": { + "description": "Write '1' to Disable interrupt for CRCOK event", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CRCERROR": { + "description": "Write '1' to Disable interrupt for CRCERROR event", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "CRCSTATUS": { + "description": "CRC status", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CRCSTATUS": { + "description": "CRC status of packet received", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "CRCError": { + "description": "Packet received with CRC error", + "value": 0 + }, + "CRCOk": { + "description": "Packet received with CRC ok", + "value": 1 + } + } + } + } + } + } + } + }, + "RXMATCH": { + "description": "Received address", + "offset": 1032, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RXMATCH": { + "description": "Received address", + "offset": 0, + "size": 3 + } + } + } + }, + "RXCRC": { + "description": "CRC field of previously received packet", + "offset": 1036, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RXCRC": { + "description": "CRC field of previously received packet", + "offset": 0, + "size": 24 + } + } + } + }, + "DAI": { + "description": "Device address match index", + "offset": 1040, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DAI": { + "description": "Device address match index", + "offset": 0, + "size": 3 + } + } + } + }, + "PACKETPTR": { + "description": "Packet pointer", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PACKETPTR": { + "description": "Packet pointer", + "offset": 0, + "size": 32 + } + } + } + }, + "FREQUENCY": { + "description": "Frequency", + "offset": 1288, + "size": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQUENCY": { + "description": "Radio channel frequency", + "offset": 0, + "size": 7 + }, + "MAP": { + "description": "Channel map selection.", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Default": { + "description": "Channel map between 2400 MHZ .. 2500 MHz", + "value": 0 + }, + "Low": { + "description": "Channel map between 2360 MHZ .. 2460 MHz", + "value": 1 + } + } + } + } + } + } + } + }, + "TXPOWER": { + "description": "Output power", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXPOWER": { + "description": "RADIO output power.", + "offset": 0, + "size": 8, + "enum": { + "size": 8, + "children": { + "enum_fields": { + "Pos4dBm": { + "description": "+4 dBm", + "value": 4 + }, + "Pos3dBm": { + "description": "+3 dBm", + "value": 3 + }, + "0dBm": { + "description": "0 dBm", + "value": 0 + }, + "Neg4dBm": { + "description": "-4 dBm", + "value": 252 + }, + "Neg8dBm": { + "description": "-8 dBm", + "value": 248 + }, + "Neg12dBm": { + "description": "-12 dBm", + "value": 244 + }, + "Neg16dBm": { + "description": "-16 dBm", + "value": 240 + }, + "Neg20dBm": { + "description": "-20 dBm", + "value": 236 + }, + "Neg30dBm": { + "description": "Deprecated enumerator - -40 dBm", + "value": 255 + }, + "Neg40dBm": { + "description": "-40 dBm", + "value": 216 + } + } + } + } + } + } + } + }, + "MODE": { + "description": "Data rate and modulation", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation.", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Nrf_1Mbit": { + "description": "1 Mbit/s Nordic proprietary radio mode", + "value": 0 + }, + "Nrf_2Mbit": { + "description": "2 Mbit/s Nordic proprietary radio mode", + "value": 1 + }, + "Nrf_250Kbit": { + "description": "Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode", + "value": 2 + }, + "Ble_1Mbit": { + "description": "1 Mbit/s Bluetooth Low Energy", + "value": 3 + }, + "Ble_2Mbit": { + "description": "2 Mbit/s Bluetooth Low Energy", + "value": 4 + } + } + } + } + } + } + } + }, + "PCNF0": { + "description": "Packet configuration register 0", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LFLEN": { + "description": "Length on air of LENGTH field in number of bits.", + "offset": 0, + "size": 4 + }, + "S0LEN": { + "description": "Length on air of S0 field in number of bytes.", + "offset": 8, + "size": 1 + }, + "S1LEN": { + "description": "Length on air of S1 field in number of bits.", + "offset": 16, + "size": 4 + }, + "S1INCL": { + "description": "Include or exclude S1 field in RAM", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Automatic": { + "description": "Include S1 field in RAM only if S1LEN > 0", + "value": 0 + }, + "Include": { + "description": "Always include S1 field in RAM independent of S1LEN", + "value": 1 + } + } + } + } + }, + "PLEN": { + "description": "Length of preamble on air. Decision point: TASKS_START task", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "8bit": { + "description": "8-bit preamble", + "value": 0 + }, + "16bit": { + "description": "16-bit preamble", + "value": 1 + } + } + } + } + } + } + } + }, + "PCNF1": { + "description": "Packet configuration register 1", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MAXLEN": { + "description": "Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.", + "offset": 0, + "size": 8 + }, + "STATLEN": { + "description": "Static length in number of bytes", + "offset": 8, + "size": 8 + }, + "BALEN": { + "description": "Base address length in number of bytes", + "offset": 16, + "size": 3 + }, + "ENDIAN": { + "description": "On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Little": { + "description": "Least Significant bit on air first", + "value": 0 + }, + "Big": { + "description": "Most significant bit on air first", + "value": 1 + } + } + } + } + }, + "WHITEEN": { + "description": "Enable or disable packet whitening", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "BASE0": { + "description": "Base address 0", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BASE0": { + "description": "Base address 0", + "offset": 0, + "size": 32 + } + } + } + }, + "BASE1": { + "description": "Base address 1", + "offset": 1312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BASE1": { + "description": "Base address 1", + "offset": 0, + "size": 32 + } + } + } + }, + "PREFIX0": { + "description": "Prefixes bytes for logical addresses 0-3", + "offset": 1316, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AP0": { + "description": "Address prefix 0.", + "offset": 0, + "size": 8 + }, + "AP1": { + "description": "Address prefix 1.", + "offset": 8, + "size": 8 + }, + "AP2": { + "description": "Address prefix 2.", + "offset": 16, + "size": 8 + }, + "AP3": { + "description": "Address prefix 3.", + "offset": 24, + "size": 8 + } + } + } + }, + "PREFIX1": { + "description": "Prefixes bytes for logical addresses 4-7", + "offset": 1320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AP4": { + "description": "Address prefix 4.", + "offset": 0, + "size": 8 + }, + "AP5": { + "description": "Address prefix 5.", + "offset": 8, + "size": 8 + }, + "AP6": { + "description": "Address prefix 6.", + "offset": 16, + "size": 8 + }, + "AP7": { + "description": "Address prefix 7.", + "offset": 24, + "size": 8 + } + } + } + }, + "TXADDRESS": { + "description": "Transmit address select", + "offset": 1324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXADDRESS": { + "description": "Transmit address select", + "offset": 0, + "size": 3 + } + } + } + }, + "RXADDRESSES": { + "description": "Receive address select", + "offset": 1328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDR0": { + "description": "Enable or disable reception on logical address 0.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR1": { + "description": "Enable or disable reception on logical address 1.", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR2": { + "description": "Enable or disable reception on logical address 2.", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR3": { + "description": "Enable or disable reception on logical address 3.", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR4": { + "description": "Enable or disable reception on logical address 4.", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR5": { + "description": "Enable or disable reception on logical address 5.", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR6": { + "description": "Enable or disable reception on logical address 6.", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR7": { + "description": "Enable or disable reception on logical address 7.", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "CRCCNF": { + "description": "CRC configuration", + "offset": 1332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEN": { + "description": "CRC length in number of bytes.", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "CRC length is zero and CRC calculation is disabled", + "value": 0 + }, + "One": { + "description": "CRC length is one byte and CRC calculation is enabled", + "value": 1 + }, + "Two": { + "description": "CRC length is two bytes and CRC calculation is enabled", + "value": 2 + }, + "Three": { + "description": "CRC length is three bytes and CRC calculation is enabled", + "value": 3 + } + } + } + } + }, + "SKIPADDR": { + "description": "Include or exclude packet address field out of CRC calculation.", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Include": { + "description": "CRC calculation includes address field", + "value": 0 + }, + "Skip": { + "description": "CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.", + "value": 1 + } + } + } + } + } + } + } + }, + "CRCPOLY": { + "description": "CRC polynomial", + "offset": 1336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRCPOLY": { + "description": "CRC polynomial", + "offset": 0, + "size": 24 + } + } + } + }, + "CRCINIT": { + "description": "CRC initial value", + "offset": 1340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRCINIT": { + "description": "CRC initial value", + "offset": 0, + "size": 24 + } + } + } + }, + "UNUSED0": { + "description": "Unspecified", + "offset": 1344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "TIFS": { + "description": "Inter Frame Spacing in us", + "offset": 1348, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIFS": { + "description": "Inter Frame Spacing in us", + "offset": 0, + "size": 8 + } + } + } + }, + "RSSISAMPLE": { + "description": "RSSI sample", + "offset": 1352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RSSISAMPLE": { + "description": "RSSI sample", + "offset": 0, + "size": 7 + } + } + } + }, + "STATE": { + "description": "Current radio state", + "offset": 1360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STATE": { + "description": "Current radio state", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "RADIO is in the Disabled state", + "value": 0 + }, + "RxRu": { + "description": "RADIO is in the RXRU state", + "value": 1 + }, + "RxIdle": { + "description": "RADIO is in the RXIDLE state", + "value": 2 + }, + "Rx": { + "description": "RADIO is in the RX state", + "value": 3 + }, + "RxDisable": { + "description": "RADIO is in the RXDISABLED state", + "value": 4 + }, + "TxRu": { + "description": "RADIO is in the TXRU state", + "value": 9 + }, + "TxIdle": { + "description": "RADIO is in the TXIDLE state", + "value": 10 + }, + "Tx": { + "description": "RADIO is in the TX state", + "value": 11 + }, + "TxDisable": { + "description": "RADIO is in the TXDISABLED state", + "value": 12 + } + } + } + } + } + } + } + }, + "DATAWHITEIV": { + "description": "Data whitening initial value", + "offset": 1364, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATAWHITEIV": { + "description": "Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.", + "offset": 0, + "size": 7 + } + } + } + }, + "BCC": { + "description": "Bit counter compare", + "offset": 1376, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BCC": { + "description": "Bit counter compare", + "offset": 0, + "size": 32 + } + } + } + }, + "DAB": { + "description": "Description collection[0]: Device address base segment 0", + "offset": 1536, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAB": { + "description": "Device address base segment 0", + "offset": 0, + "size": 32 + } + } + } + }, + "DAP": { + "description": "Description collection[0]: Device address prefix 0", + "offset": 1568, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAP": { + "description": "Device address prefix 0", + "offset": 0, + "size": 16 + } + } + } + }, + "DACNF": { + "description": "Device address match configuration", + "offset": 1600, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENA0": { + "description": "Enable or disable device address matching using device address 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA1": { + "description": "Enable or disable device address matching using device address 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA2": { + "description": "Enable or disable device address matching using device address 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA3": { + "description": "Enable or disable device address matching using device address 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA4": { + "description": "Enable or disable device address matching using device address 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA5": { + "description": "Enable or disable device address matching using device address 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA6": { + "description": "Enable or disable device address matching using device address 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA7": { + "description": "Enable or disable device address matching using device address 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "TXADD0": { + "description": "TxAdd for device address 0", + "offset": 8, + "size": 1 + }, + "TXADD1": { + "description": "TxAdd for device address 1", + "offset": 9, + "size": 1 + }, + "TXADD2": { + "description": "TxAdd for device address 2", + "offset": 10, + "size": 1 + }, + "TXADD3": { + "description": "TxAdd for device address 3", + "offset": 11, + "size": 1 + }, + "TXADD4": { + "description": "TxAdd for device address 4", + "offset": 12, + "size": 1 + }, + "TXADD5": { + "description": "TxAdd for device address 5", + "offset": 13, + "size": 1 + }, + "TXADD6": { + "description": "TxAdd for device address 6", + "offset": 14, + "size": 1 + }, + "TXADD7": { + "description": "TxAdd for device address 7", + "offset": 15, + "size": 1 + } + } + } + }, + "MODECNF0": { + "description": "Radio mode configuration register 0", + "offset": 1616, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "RU": { + "description": "Radio ramp-up time", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Default": { + "description": "Default ramp-up time (tRXEN), compatible with firmware written for nRF51", + "value": 0 + }, + "Fast": { + "description": "Fast ramp-up (tRXEN,FAST), see electrical specification for more information", + "value": 1 + } + } + } + } + }, + "DTX": { + "description": "Default TX value", + "offset": 8, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "B1": { + "description": "Transmit '1'", + "value": 0 + }, + "B0": { + "description": "Transmit '0'", + "value": 1 + }, + "Center": { + "description": "Transmit center frequency", + "value": 2 + } + } + } + } + } + } + } + }, + "POWER": { + "description": "Peripheral power control", + "offset": 4092, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "POWER": { + "description": "Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Peripheral is powered off", + "value": 0 + }, + "Enabled": { + "description": "Peripheral is powered on", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "UARTE0": { + "description": "UART with EasyDMA", + "children": { + "registers": { + "TASKS_STARTRX": { + "description": "Start UART receiver", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOPRX": { + "description": "Stop UART receiver", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STARTTX": { + "description": "Start UART transmitter", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOPTX": { + "description": "Stop UART transmitter", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_FLUSHRX": { + "description": "Flush RX FIFO into RX buffer", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_CTS": { + "description": "CTS is activated (set low). Clear To Send.", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_NCTS": { + "description": "CTS is deactivated (set high). Not Clear To Send.", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RXDRDY": { + "description": "Data received in RXD (but potentially not yet transferred to Data RAM)", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ENDRX": { + "description": "Receive buffer is filled up", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_TXDRDY": { + "description": "Data sent from TXD", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ENDTX": { + "description": "Last TX byte transmitted", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ERROR": { + "description": "Error detected", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RXTO": { + "description": "Receiver timeout", + "offset": 324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RXSTARTED": { + "description": "UART receiver has started", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_TXSTARTED": { + "description": "UART transmitter has started", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_TXSTOPPED": { + "description": "Transmitter stopped", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDRX_STARTRX": { + "description": "Shortcut between ENDRX event and STARTRX task", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "ENDRX_STOPRX": { + "description": "Shortcut between ENDRX event and STOPRX task", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "Enable or disable interrupt for CTS event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "NCTS": { + "description": "Enable or disable interrupt for NCTS event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXDRDY": { + "description": "Enable or disable interrupt for RXDRDY event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Enable or disable interrupt for ENDRX event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXDRDY": { + "description": "Enable or disable interrupt for TXDRDY event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Enable or disable interrupt for ENDTX event", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Enable or disable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXTO": { + "description": "Enable or disable interrupt for RXTO event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Enable or disable interrupt for RXSTARTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Enable or disable interrupt for TXSTARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXSTOPPED": { + "description": "Enable or disable interrupt for TXSTOPPED event", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "Write '1' to Enable interrupt for CTS event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NCTS": { + "description": "Write '1' to Enable interrupt for NCTS event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDRDY": { + "description": "Write '1' to Enable interrupt for RXDRDY event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to Enable interrupt for ENDRX event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDRDY": { + "description": "Write '1' to Enable interrupt for TXDRDY event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to Enable interrupt for ENDTX event", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Enable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXTO": { + "description": "Write '1' to Enable interrupt for RXTO event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to Enable interrupt for RXSTARTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to Enable interrupt for TXSTARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTOPPED": { + "description": "Write '1' to Enable interrupt for TXSTOPPED event", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "Write '1' to Disable interrupt for CTS event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NCTS": { + "description": "Write '1' to Disable interrupt for NCTS event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDRDY": { + "description": "Write '1' to Disable interrupt for RXDRDY event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to Disable interrupt for ENDRX event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDRDY": { + "description": "Write '1' to Disable interrupt for TXDRDY event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to Disable interrupt for ENDTX event", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Disable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXTO": { + "description": "Write '1' to Disable interrupt for RXTO event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to Disable interrupt for RXSTARTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to Disable interrupt for TXSTARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTOPPED": { + "description": "Write '1' to Disable interrupt for TXSTOPPED event", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSRC": { + "description": "Error source", + "offset": 1152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERRUN": { + "description": "Overrun error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "PARITY": { + "description": "Parity error", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "FRAMING": { + "description": "Framing error occurred", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "BREAK": { + "description": "Break condition", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable UART", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable UARTE", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable UARTE", + "value": 0 + }, + "Enabled": { + "description": "Enable UARTE", + "value": 8 + } + } + } + } + } + } + } + }, + "BAUDRATE": { + "description": "Baud rate. Accuracy depends on the HFCLK source selected.", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "BAUDRATE": { + "description": "Baud rate", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Baud1200": { + "description": "1200 baud (actual rate: 1205)", + "value": 323584 + }, + "Baud2400": { + "description": "2400 baud (actual rate: 2396)", + "value": 643072 + }, + "Baud4800": { + "description": "4800 baud (actual rate: 4808)", + "value": 1290240 + }, + "Baud9600": { + "description": "9600 baud (actual rate: 9598)", + "value": 2576384 + }, + "Baud14400": { + "description": "14400 baud (actual rate: 14401)", + "value": 3862528 + }, + "Baud19200": { + "description": "19200 baud (actual rate: 19208)", + "value": 5152768 + }, + "Baud28800": { + "description": "28800 baud (actual rate: 28777)", + "value": 7716864 + }, + "Baud31250": { + "description": "31250 baud", + "value": 8388608 + }, + "Baud38400": { + "description": "38400 baud (actual rate: 38369)", + "value": 10289152 + }, + "Baud56000": { + "description": "56000 baud (actual rate: 55944)", + "value": 15007744 + }, + "Baud57600": { + "description": "57600 baud (actual rate: 57554)", + "value": 15400960 + }, + "Baud76800": { + "description": "76800 baud (actual rate: 76923)", + "value": 20615168 + }, + "Baud115200": { + "description": "115200 baud (actual rate: 115108)", + "value": 30801920 + }, + "Baud230400": { + "description": "230400 baud (actual rate: 231884)", + "value": 61865984 + }, + "Baud250000": { + "description": "250000 baud", + "value": 67108864 + }, + "Baud460800": { + "description": "460800 baud (actual rate: 457143)", + "value": 121634816 + }, + "Baud921600": { + "description": "921600 baud (actual rate: 941176)", + "value": 251658240 + }, + "Baud1M": { + "description": "1Mega baud", + "value": 268435456 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration of parity and hardware flow control", + "offset": 1388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HWFC": { + "description": "Hardware flow control", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "PARITY": { + "description": "Parity", + "offset": 1, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude parity bit", + "value": 0 + }, + "Included": { + "description": "Include parity bit", + "value": 7 + } + } + } + } + } + } + } + } + } + } + }, + "UART0": { + "description": "Universal Asynchronous Receiver/Transmitter", + "children": { + "registers": { + "TASKS_STARTRX": { + "description": "Start UART receiver", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOPRX": { + "description": "Stop UART receiver", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STARTTX": { + "description": "Start UART transmitter", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOPTX": { + "description": "Stop UART transmitter", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SUSPEND": { + "description": "Suspend UART", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_CTS": { + "description": "CTS is activated (set low). Clear To Send.", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_NCTS": { + "description": "CTS is deactivated (set high). Not Clear To Send.", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RXDRDY": { + "description": "Data received in RXD", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_TXDRDY": { + "description": "Data sent from TXD", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ERROR": { + "description": "Error detected", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RXTO": { + "description": "Receiver timeout", + "offset": 324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS_STARTRX": { + "description": "Shortcut between CTS event and STARTRX task", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "NCTS_STOPRX": { + "description": "Shortcut between NCTS event and STOPRX task", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "Write '1' to Enable interrupt for CTS event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NCTS": { + "description": "Write '1' to Enable interrupt for NCTS event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDRDY": { + "description": "Write '1' to Enable interrupt for RXDRDY event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDRDY": { + "description": "Write '1' to Enable interrupt for TXDRDY event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Enable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXTO": { + "description": "Write '1' to Enable interrupt for RXTO event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "Write '1' to Disable interrupt for CTS event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NCTS": { + "description": "Write '1' to Disable interrupt for NCTS event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDRDY": { + "description": "Write '1' to Disable interrupt for RXDRDY event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDRDY": { + "description": "Write '1' to Disable interrupt for TXDRDY event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Disable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXTO": { + "description": "Write '1' to Disable interrupt for RXTO event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSRC": { + "description": "Error source", + "offset": 1152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERRUN": { + "description": "Overrun error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "PARITY": { + "description": "Parity error", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "FRAMING": { + "description": "Framing error occurred", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "BREAK": { + "description": "Break condition", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable UART", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable UART", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable UART", + "value": 0 + }, + "Enabled": { + "description": "Enable UART", + "value": 4 + } + } + } + } + } + } + } + }, + "PSELRTS": { + "description": "Pin select for RTS", + "offset": 1288, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSELRTS": { + "description": "Pin number configuration for UART RTS signal", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Disconnected": { + "description": "Disconnect", + "value": 4294967295 + } + } + } + } + } + } + } + }, + "PSELTXD": { + "description": "Pin select for TXD", + "offset": 1292, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSELTXD": { + "description": "Pin number configuration for UART TXD signal", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Disconnected": { + "description": "Disconnect", + "value": 4294967295 + } + } + } + } + } + } + } + }, + "PSELCTS": { + "description": "Pin select for CTS", + "offset": 1296, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSELCTS": { + "description": "Pin number configuration for UART CTS signal", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Disconnected": { + "description": "Disconnect", + "value": 4294967295 + } + } + } + } + } + } + } + }, + "PSELRXD": { + "description": "Pin select for RXD", + "offset": 1300, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSELRXD": { + "description": "Pin number configuration for UART RXD signal", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Disconnected": { + "description": "Disconnect", + "value": 4294967295 + } + } + } + } + } + } + } + }, + "RXD": { + "description": "RXD register", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RXD": { + "description": "RX data received in previous transfers, double buffered", + "offset": 0, + "size": 8 + } + } + } + }, + "TXD": { + "description": "TXD register", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TXD": { + "description": "TX data to be transferred", + "offset": 0, + "size": 8 + } + } + } + }, + "BAUDRATE": { + "description": "Baud rate", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "BAUDRATE": { + "description": "Baud rate", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Baud1200": { + "description": "1200 baud (actual rate: 1205)", + "value": 323584 + }, + "Baud2400": { + "description": "2400 baud (actual rate: 2396)", + "value": 643072 + }, + "Baud4800": { + "description": "4800 baud (actual rate: 4808)", + "value": 1290240 + }, + "Baud9600": { + "description": "9600 baud (actual rate: 9598)", + "value": 2576384 + }, + "Baud14400": { + "description": "14400 baud (actual rate: 14414)", + "value": 3866624 + }, + "Baud19200": { + "description": "19200 baud (actual rate: 19208)", + "value": 5152768 + }, + "Baud28800": { + "description": "28800 baud (actual rate: 28829)", + "value": 7729152 + }, + "Baud31250": { + "description": "31250 baud", + "value": 8388608 + }, + "Baud38400": { + "description": "38400 baud (actual rate: 38462)", + "value": 10309632 + }, + "Baud56000": { + "description": "56000 baud (actual rate: 55944)", + "value": 15007744 + }, + "Baud57600": { + "description": "57600 baud (actual rate: 57762)", + "value": 15462400 + }, + "Baud76800": { + "description": "76800 baud (actual rate: 76923)", + "value": 20615168 + }, + "Baud115200": { + "description": "115200 baud (actual rate: 115942)", + "value": 30924800 + }, + "Baud230400": { + "description": "230400 baud (actual rate: 231884)", + "value": 61845504 + }, + "Baud250000": { + "description": "250000 baud", + "value": 67108864 + }, + "Baud460800": { + "description": "460800 baud (actual rate: 470588)", + "value": 123695104 + }, + "Baud921600": { + "description": "921600 baud (actual rate: 941176)", + "value": 247386112 + }, + "Baud1M": { + "description": "1Mega baud", + "value": 268435456 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration of parity and hardware flow control", + "offset": 1388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HWFC": { + "description": "Hardware flow control", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "PARITY": { + "description": "Parity", + "offset": 1, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude parity bit", + "value": 0 + }, + "Included": { + "description": "Include parity bit", + "value": 7 + } + } + } + } + } + } + } + } + } + } + }, + "SPIM0": { + "description": "Serial Peripheral Interface Master with EasyDMA 0", + "children": { + "registers": { + "TASKS_START": { + "description": "Start SPI transaction", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop SPI transaction", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SUSPEND": { + "description": "Suspend SPI transaction", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_RESUME": { + "description": "Resume SPI transaction", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_STOPPED": { + "description": "SPI transaction has stopped", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ENDRX": { + "description": "End of RXD buffer reached", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_END": { + "description": "End of RXD buffer and TXD buffer reached", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ENDTX": { + "description": "End of TXD buffer reached", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_STARTED": { + "description": "Transaction started", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END_START": { + "description": "Shortcut between END event and START task", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to Enable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to Enable interrupt for ENDRX event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to Enable interrupt for END event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to Enable interrupt for ENDTX event", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Write '1' to Enable interrupt for STARTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to Disable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to Disable interrupt for ENDRX event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to Disable interrupt for END event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to Disable interrupt for ENDTX event", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Write '1' to Disable interrupt for STARTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable SPIM", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable SPIM", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable SPIM", + "value": 0 + }, + "Enabled": { + "description": "Enable SPIM", + "value": 7 + } + } + } + } + } + } + } + }, + "FREQUENCY": { + "description": "SPI frequency. Accuracy depends on the HFCLK source selected.", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQUENCY": { + "description": "SPI master data rate", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "K125": { + "description": "125 kbps", + "value": 33554432 + }, + "K250": { + "description": "250 kbps", + "value": 67108864 + }, + "K500": { + "description": "500 kbps", + "value": 134217728 + }, + "M1": { + "description": "1 Mbps", + "value": 268435456 + }, + "M2": { + "description": "2 Mbps", + "value": 536870912 + }, + "M4": { + "description": "4 Mbps", + "value": 1073741824 + }, + "M8": { + "description": "8 Mbps", + "value": 2147483648 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORDER": { + "description": "Bit order", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "MsbFirst": { + "description": "Most significant bit shifted out first", + "value": 0 + }, + "LsbFirst": { + "description": "Least significant bit shifted out first", + "value": 1 + } + } + } + } + }, + "CPHA": { + "description": "Serial clock (SCK) phase", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Leading": { + "description": "Sample on leading edge of clock, shift serial data on trailing edge", + "value": 0 + }, + "Trailing": { + "description": "Sample on trailing edge of clock, shift serial data on leading edge", + "value": 1 + } + } + } + } + }, + "CPOL": { + "description": "Serial clock (SCK) polarity", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "ActiveHigh": { + "description": "Active high", + "value": 0 + }, + "ActiveLow": { + "description": "Active low", + "value": 1 + } + } + } + } + } + } + } + }, + "ORC": { + "description": "Over-read character. Character clocked out in case and over-read of the TXD buffer.", + "offset": 1472, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORC": { + "description": "Over-read character. Character clocked out in case and over-read of the TXD buffer.", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "SPIS0": { + "description": "SPI Slave 0", + "children": { + "registers": { + "TASKS_ACQUIRE": { + "description": "Acquire SPI semaphore", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_RELEASE": { + "description": "Release SPI semaphore, enabling the SPI slave to acquire it", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_END": { + "description": "Granted transaction completed", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ENDRX": { + "description": "End of RXD buffer reached", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ACQUIRED": { + "description": "Semaphore acquired", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END_ACQUIRE": { + "description": "Shortcut between END event and ACQUIRE task", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END": { + "description": "Write '1' to Enable interrupt for END event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to Enable interrupt for ENDRX event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ACQUIRED": { + "description": "Write '1' to Enable interrupt for ACQUIRED event", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END": { + "description": "Write '1' to Disable interrupt for END event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to Disable interrupt for ENDRX event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ACQUIRED": { + "description": "Write '1' to Disable interrupt for ACQUIRED event", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "SEMSTAT": { + "description": "Semaphore status register", + "offset": 1024, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SEMSTAT": { + "description": "Semaphore status", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Free": { + "description": "Semaphore is free", + "value": 0 + }, + "CPU": { + "description": "Semaphore is assigned to CPU", + "value": 1 + }, + "SPIS": { + "description": "Semaphore is assigned to SPI slave", + "value": 2 + }, + "CPUPending": { + "description": "Semaphore is assigned to SPI but a handover to the CPU is pending", + "value": 3 + } + } + } + } + } + } + } + }, + "STATUS": { + "description": "Status from last transaction", + "offset": 1088, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERREAD": { + "description": "TX buffer over-read detected, and prevented", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "OVERFLOW": { + "description": "RX buffer overflow detected, and prevented", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable SPI slave", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable SPI slave", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable SPI slave", + "value": 0 + }, + "Enabled": { + "description": "Enable SPI slave", + "value": 2 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORDER": { + "description": "Bit order", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "MsbFirst": { + "description": "Most significant bit shifted out first", + "value": 0 + }, + "LsbFirst": { + "description": "Least significant bit shifted out first", + "value": 1 + } + } + } + } + }, + "CPHA": { + "description": "Serial clock (SCK) phase", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Leading": { + "description": "Sample on leading edge of clock, shift serial data on trailing edge", + "value": 0 + }, + "Trailing": { + "description": "Sample on trailing edge of clock, shift serial data on leading edge", + "value": 1 + } + } + } + } + }, + "CPOL": { + "description": "Serial clock (SCK) polarity", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "ActiveHigh": { + "description": "Active high", + "value": 0 + }, + "ActiveLow": { + "description": "Active low", + "value": 1 + } + } + } + } + } + } + } + }, + "DEF": { + "description": "Default character. Character clocked out in case of an ignored transaction.", + "offset": 1372, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DEF": { + "description": "Default character. Character clocked out in case of an ignored transaction.", + "offset": 0, + "size": 8 + } + } + } + }, + "ORC": { + "description": "Over-read character", + "offset": 1472, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORC": { + "description": "Over-read character. Character clocked out after an over-read of the transmit buffer.", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "TWIM0": { + "description": "I2C compatible Two-Wire Master Interface with EasyDMA 0", + "children": { + "registers": { + "TASKS_STARTRX": { + "description": "Start TWI receive sequence", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STARTTX": { + "description": "Start TWI transmit sequence", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop TWI transaction. Must be issued while the TWI master is not suspended.", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SUSPEND": { + "description": "Suspend TWI transaction", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_RESUME": { + "description": "Resume TWI transaction", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_STOPPED": { + "description": "TWI stopped", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ERROR": { + "description": "TWI error", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_SUSPENDED": { + "description": "Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RXSTARTED": { + "description": "Receive sequence started", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_TXSTARTED": { + "description": "Transmit sequence started", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_LASTRX": { + "description": "Byte boundary, starting to receive the last byte", + "offset": 348, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_LASTTX": { + "description": "Byte boundary, starting to transmit the last byte", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LASTTX_STARTRX": { + "description": "Shortcut between LASTTX event and STARTRX task", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LASTTX_SUSPEND": { + "description": "Shortcut between LASTTX event and SUSPEND task", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LASTTX_STOP": { + "description": "Shortcut between LASTTX event and STOP task", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LASTRX_STARTTX": { + "description": "Shortcut between LASTRX event and STARTTX task", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LASTRX_STOP": { + "description": "Shortcut between LASTRX event and STOP task", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Enable or disable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Enable or disable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SUSPENDED": { + "description": "Enable or disable interrupt for SUSPENDED event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Enable or disable interrupt for RXSTARTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Enable or disable interrupt for TXSTARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "LASTRX": { + "description": "Enable or disable interrupt for LASTRX event", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "LASTTX": { + "description": "Enable or disable interrupt for LASTTX event", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to Enable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Enable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SUSPENDED": { + "description": "Write '1' to Enable interrupt for SUSPENDED event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to Enable interrupt for RXSTARTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to Enable interrupt for TXSTARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LASTRX": { + "description": "Write '1' to Enable interrupt for LASTRX event", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LASTTX": { + "description": "Write '1' to Enable interrupt for LASTTX event", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to Disable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Disable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SUSPENDED": { + "description": "Write '1' to Disable interrupt for SUSPENDED event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to Disable interrupt for RXSTARTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to Disable interrupt for TXSTARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LASTRX": { + "description": "Write '1' to Disable interrupt for LASTRX event", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LASTTX": { + "description": "Write '1' to Disable interrupt for LASTTX event", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSRC": { + "description": "Error source", + "offset": 1220, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERRUN": { + "description": "Overrun error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotReceived": { + "description": "Error did not occur", + "value": 0 + }, + "Received": { + "description": "Error occurred", + "value": 1 + } + } + } + } + }, + "ANACK": { + "description": "NACK received after sending the address (write '1' to clear)", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotReceived": { + "description": "Error did not occur", + "value": 0 + }, + "Received": { + "description": "Error occurred", + "value": 1 + } + } + } + } + }, + "DNACK": { + "description": "NACK received after sending a data byte (write '1' to clear)", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotReceived": { + "description": "Error did not occur", + "value": 0 + }, + "Received": { + "description": "Error occurred", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable TWIM", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable TWIM", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable TWIM", + "value": 0 + }, + "Enabled": { + "description": "Enable TWIM", + "value": 6 + } + } + } + } + } + } + } + }, + "FREQUENCY": { + "description": "TWI frequency", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQUENCY": { + "description": "TWI master clock frequency", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "K100": { + "description": "100 kbps", + "value": 26738688 + }, + "K250": { + "description": "250 kbps", + "value": 67108864 + }, + "K400": { + "description": "400 kbps", + "value": 104857600 + } + } + } + } + } + } + } + }, + "ADDRESS": { + "description": "Address used in the TWI transfer", + "offset": 1416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS": { + "description": "Address used in the TWI transfer", + "offset": 0, + "size": 7 + } + } + } + } + } + } + }, + "TWIS0": { + "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 0", + "children": { + "registers": { + "TASKS_STOP": { + "description": "Stop TWI transaction", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SUSPEND": { + "description": "Suspend TWI transaction", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_RESUME": { + "description": "Resume TWI transaction", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_PREPARERX": { + "description": "Prepare the TWI slave to respond to a write command", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_PREPARETX": { + "description": "Prepare the TWI slave to respond to a read command", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_STOPPED": { + "description": "TWI stopped", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ERROR": { + "description": "TWI error", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RXSTARTED": { + "description": "Receive sequence started", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_TXSTARTED": { + "description": "Transmit sequence started", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_WRITE": { + "description": "Write command received", + "offset": 356, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_READ": { + "description": "Read command received", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WRITE_SUSPEND": { + "description": "Shortcut between WRITE event and SUSPEND task", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "READ_SUSPEND": { + "description": "Shortcut between READ event and SUSPEND task", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Enable or disable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Enable or disable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Enable or disable interrupt for RXSTARTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Enable or disable interrupt for TXSTARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "WRITE": { + "description": "Enable or disable interrupt for WRITE event", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "READ": { + "description": "Enable or disable interrupt for READ event", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to Enable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Enable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to Enable interrupt for RXSTARTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to Enable interrupt for TXSTARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "WRITE": { + "description": "Write '1' to Enable interrupt for WRITE event", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "READ": { + "description": "Write '1' to Enable interrupt for READ event", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to Disable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Disable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to Disable interrupt for RXSTARTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to Disable interrupt for TXSTARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "WRITE": { + "description": "Write '1' to Disable interrupt for WRITE event", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "READ": { + "description": "Write '1' to Disable interrupt for READ event", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSRC": { + "description": "Error source", + "offset": 1232, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERFLOW": { + "description": "RX buffer overflow detected, and prevented", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Error did not occur", + "value": 0 + }, + "Detected": { + "description": "Error occurred", + "value": 1 + } + } + } + } + }, + "DNACK": { + "description": "NACK sent after receiving a data byte", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotReceived": { + "description": "Error did not occur", + "value": 0 + }, + "Received": { + "description": "Error occurred", + "value": 1 + } + } + } + } + }, + "OVERREAD": { + "description": "TX buffer over-read detected, and prevented", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Error did not occur", + "value": 0 + }, + "Detected": { + "description": "Error occurred", + "value": 1 + } + } + } + } + } + } + } + }, + "MATCH": { + "description": "Status register indicating which address had a match", + "offset": 1236, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "MATCH": { + "description": "Which of the addresses in {ADDRESS} matched the incoming address", + "offset": 0, + "size": 1 + } + } + } + }, + "ENABLE": { + "description": "Enable TWIS", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable TWIS", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable TWIS", + "value": 0 + }, + "Enabled": { + "description": "Enable TWIS", + "value": 9 + } + } + } + } + } + } + } + }, + "ADDRESS": { + "description": "Description collection[0]: TWI slave address 0", + "offset": 1416, + "size": 32, + "count": 2, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS": { + "description": "TWI slave address", + "offset": 0, + "size": 7 + } + } + } + }, + "CONFIG": { + "description": "Configuration register for the address match mechanism", + "offset": 1428, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS0": { + "description": "Enable or disable address matching on ADDRESS[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ADDRESS1": { + "description": "Enable or disable address matching on ADDRESS[1]", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ORC": { + "description": "Over-read character. Character sent out in case of an over-read of the transmit buffer.", + "offset": 1472, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORC": { + "description": "Over-read character. Character sent out in case of an over-read of the transmit buffer.", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "SPI0": { + "description": "Serial Peripheral Interface 0", + "children": { + "registers": { + "EVENTS_READY": { + "description": "TXD byte sent and RXD byte received", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to Enable interrupt for READY event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to Disable interrupt for READY event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable SPI", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable SPI", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable SPI", + "value": 0 + }, + "Enabled": { + "description": "Enable SPI", + "value": 1 + } + } + } + } + } + } + } + }, + "RXD": { + "description": "RXD register", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RXD": { + "description": "RX data received. Double buffered", + "offset": 0, + "size": 8 + } + } + } + }, + "TXD": { + "description": "TXD register", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXD": { + "description": "TX data to send. Double buffered", + "offset": 0, + "size": 8 + } + } + } + }, + "FREQUENCY": { + "description": "SPI frequency", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQUENCY": { + "description": "SPI master data rate", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "K125": { + "description": "125 kbps", + "value": 33554432 + }, + "K250": { + "description": "250 kbps", + "value": 67108864 + }, + "K500": { + "description": "500 kbps", + "value": 134217728 + }, + "M1": { + "description": "1 Mbps", + "value": 268435456 + }, + "M2": { + "description": "2 Mbps", + "value": 536870912 + }, + "M4": { + "description": "4 Mbps", + "value": 1073741824 + }, + "M8": { + "description": "8 Mbps", + "value": 2147483648 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORDER": { + "description": "Bit order", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "MsbFirst": { + "description": "Most significant bit shifted out first", + "value": 0 + }, + "LsbFirst": { + "description": "Least significant bit shifted out first", + "value": 1 + } + } + } + } + }, + "CPHA": { + "description": "Serial clock (SCK) phase", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Leading": { + "description": "Sample on leading edge of clock, shift serial data on trailing edge", + "value": 0 + }, + "Trailing": { + "description": "Sample on trailing edge of clock, shift serial data on leading edge", + "value": 1 + } + } + } + } + }, + "CPOL": { + "description": "Serial clock (SCK) polarity", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "ActiveHigh": { + "description": "Active high", + "value": 0 + }, + "ActiveLow": { + "description": "Active low", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "TWI0": { + "description": "I2C compatible Two-Wire Interface 0", + "children": { + "registers": { + "TASKS_STARTRX": { + "description": "Start TWI receive sequence", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STARTTX": { + "description": "Start TWI transmit sequence", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop TWI transaction", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SUSPEND": { + "description": "Suspend TWI transaction", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_RESUME": { + "description": "Resume TWI transaction", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_STOPPED": { + "description": "TWI stopped", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RXDREADY": { + "description": "TWI RXD byte received", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_TXDSENT": { + "description": "TWI TXD byte sent", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ERROR": { + "description": "TWI error", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_BB": { + "description": "TWI byte boundary, generated before each byte that is sent or received", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_SUSPENDED": { + "description": "TWI entered the suspended state", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BB_SUSPEND": { + "description": "Shortcut between BB event and SUSPEND task", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "BB_STOP": { + "description": "Shortcut between BB event and STOP task", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to Enable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDREADY": { + "description": "Write '1' to Enable interrupt for RXDREADY event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDSENT": { + "description": "Write '1' to Enable interrupt for TXDSENT event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Enable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "BB": { + "description": "Write '1' to Enable interrupt for BB event", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SUSPENDED": { + "description": "Write '1' to Enable interrupt for SUSPENDED event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to Disable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDREADY": { + "description": "Write '1' to Disable interrupt for RXDREADY event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDSENT": { + "description": "Write '1' to Disable interrupt for TXDSENT event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Disable interrupt for ERROR event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "BB": { + "description": "Write '1' to Disable interrupt for BB event", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SUSPENDED": { + "description": "Write '1' to Disable interrupt for SUSPENDED event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSRC": { + "description": "Error source", + "offset": 1220, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERRUN": { + "description": "Overrun error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: no overrun occured", + "value": 0 + }, + "Present": { + "description": "Read: overrun occured", + "value": 1 + } + } + } + } + }, + "ANACK": { + "description": "NACK received after sending the address (write '1' to clear)", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "DNACK": { + "description": "NACK received after sending a data byte (write '1' to clear)", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable TWI", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable TWI", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable TWI", + "value": 0 + }, + "Enabled": { + "description": "Enable TWI", + "value": 5 + } + } + } + } + } + } + } + }, + "PSELSCL": { + "description": "Pin select for SCL", + "offset": 1288, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSELSCL": { + "description": "Pin number configuration for TWI SCL signal", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Disconnected": { + "description": "Disconnect", + "value": 4294967295 + } + } + } + } + } + } + } + }, + "PSELSDA": { + "description": "Pin select for SDA", + "offset": 1292, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSELSDA": { + "description": "Pin number configuration for TWI SDA signal", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Disconnected": { + "description": "Disconnect", + "value": 4294967295 + } + } + } + } + } + } + } + }, + "RXD": { + "description": "RXD register", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RXD": { + "description": "RXD register", + "offset": 0, + "size": 8 + } + } + } + }, + "TXD": { + "description": "TXD register", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXD": { + "description": "TXD register", + "offset": 0, + "size": 8 + } + } + } + }, + "FREQUENCY": { + "description": "TWI frequency", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQUENCY": { + "description": "TWI master clock frequency", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "K100": { + "description": "100 kbps", + "value": 26738688 + }, + "K250": { + "description": "250 kbps", + "value": 67108864 + }, + "K400": { + "description": "400 kbps (actual rate 410.256 kbps)", + "value": 107479040 + } + } + } + } + } + } + } + }, + "ADDRESS": { + "description": "Address used in the TWI transfer", + "offset": 1416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS": { + "description": "Address used in the TWI transfer", + "offset": 0, + "size": 7 + } + } + } + } + } + } + }, + "P0": { + "description": "GPIO Port 1", + "children": { + "registers": { + "OUT": { + "description": "Write GPIO port", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + } + } + } + }, + "OUTSET": { + "description": "Set individual bits in GPIO port", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + } + } + } + }, + "OUTCLR": { + "description": "Clear individual bits in GPIO port", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + } + } + } + }, + "IN": { + "description": "Read GPIO port", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PIN0": { + "description": "Pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + } + } + } + }, + "DIR": { + "description": "Direction of GPIO pins", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + } + } + } + }, + "DIRSET": { + "description": "DIR set register", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Set as output pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Set as output pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Set as output pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Set as output pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Set as output pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Set as output pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Set as output pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Set as output pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Set as output pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Set as output pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Set as output pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Set as output pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Set as output pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Set as output pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Set as output pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Set as output pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Set as output pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Set as output pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Set as output pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Set as output pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Set as output pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Set as output pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Set as output pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Set as output pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Set as output pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Set as output pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Set as output pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Set as output pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Set as output pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Set as output pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Set as output pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Set as output pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + } + } + } + }, + "DIRCLR": { + "description": "DIR clear register", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Set as input pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Set as input pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Set as input pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Set as input pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Set as input pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Set as input pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Set as input pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Set as input pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Set as input pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Set as input pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Set as input pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Set as input pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Set as input pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Set as input pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Set as input pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Set as input pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Set as input pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Set as input pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Set as input pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Set as input pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Set as input pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Set as input pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Set as input pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Set as input pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Set as input pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Set as input pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Set as input pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Set as input pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Set as input pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Set as input pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Set as input pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Set as input pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + } + } + } + }, + "LATCH": { + "description": "Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers", + "offset": 1312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + } + } + } + }, + "DETECTMODE": { + "description": "Select between default DETECT signal behaviour and LDETECT mode", + "offset": 1316, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DETECTMODE": { + "description": "Select between default DETECT signal behaviour and LDETECT mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Default": { + "description": "DETECT directly connected to PIN DETECT signals", + "value": 0 + }, + "LDETECT": { + "description": "Use the latched LDETECT behaviour", + "value": 1 + } + } + } + } + } + } + } + }, + "PIN_CNF": { + "description": "Description collection[0]: Configuration of GPIO pins", + "offset": 1792, + "size": 32, + "count": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "DIR": { + "description": "Pin direction. Same physical register as DIR register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Configure pin as an input pin", + "value": 0 + }, + "Output": { + "description": "Configure pin as an output pin", + "value": 1 + } + } + } + } + }, + "INPUT": { + "description": "Connect or disconnect input buffer", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Connect": { + "description": "Connect input buffer", + "value": 0 + }, + "Disconnect": { + "description": "Disconnect input buffer", + "value": 1 + } + } + } + } + }, + "PULL": { + "description": "Pull configuration", + "offset": 2, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "No pull", + "value": 0 + }, + "Pulldown": { + "description": "Pull down on pin", + "value": 1 + }, + "Pullup": { + "description": "Pull up on pin", + "value": 3 + } + } + } + } + }, + "DRIVE": { + "description": "Drive configuration", + "offset": 8, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "S0S1": { + "description": "Standard '0', standard '1'", + "value": 0 + }, + "H0S1": { + "description": "High drive '0', standard '1'", + "value": 1 + }, + "S0H1": { + "description": "Standard '0', high drive '1'", + "value": 2 + }, + "H0H1": { + "description": "High drive '0', high 'drive '1''", + "value": 3 + }, + "D0S1": { + "description": "Disconnect '0' standard '1' (normally used for wired-or connections)", + "value": 4 + }, + "D0H1": { + "description": "Disconnect '0', high drive '1' (normally used for wired-or connections)", + "value": 5 + }, + "S0D1": { + "description": "Standard '0'. disconnect '1' (normally used for wired-and connections)", + "value": 6 + }, + "H0D1": { + "description": "High drive '0', disconnect '1' (normally used for wired-and connections)", + "value": 7 + } + } + } + } + }, + "SENSE": { + "description": "Pin sensing mechanism", + "offset": 16, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "High": { + "description": "Sense for high level", + "value": 2 + }, + "Low": { + "description": "Sense for low level", + "value": 3 + } + } + } + } + } + } + } + } + } + } + }, + "FPU": { + "description": "FPU", + "children": { + "registers": { + "UNUSED": { + "description": "Unused.", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only" + } + } + } + }, + "I2S": { + "description": "Inter-IC Sound", + "children": { + "registers": { + "TASKS_START": { + "description": "Starts continuous I2S transfer. Also starts MCK generator when this is enabled.", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated.", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_RXPTRUPD": { + "description": "The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_STOPPED": { + "description": "I2S transfer stopped.", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_TXPTRUPD": { + "description": "The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXPTRUPD": { + "description": "Enable or disable interrupt for RXPTRUPD event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Enable or disable interrupt for STOPPED event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXPTRUPD": { + "description": "Enable or disable interrupt for TXPTRUPD event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXPTRUPD": { + "description": "Write '1' to Enable interrupt for RXPTRUPD event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to Enable interrupt for STOPPED event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXPTRUPD": { + "description": "Write '1' to Enable interrupt for TXPTRUPD event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXPTRUPD": { + "description": "Write '1' to Disable interrupt for RXPTRUPD event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to Disable interrupt for STOPPED event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXPTRUPD": { + "description": "Write '1' to Disable interrupt for TXPTRUPD event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable I2S module.", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable I2S module.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "EGU0": { + "description": "Event Generator Unit 0", + "children": { + "registers": { + "TASKS_TRIGGER": { + "description": "Description collection[0]: Trigger 0 for triggering the corresponding TRIGGERED[0] event", + "offset": 0, + "size": 32, + "count": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_TRIGGERED": { + "description": "Description collection[0]: Event number 0 generated by triggering the corresponding TRIGGER[0] task", + "offset": 256, + "size": 32, + "count": 16, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TRIGGERED0": { + "description": "Enable or disable interrupt for TRIGGERED[0] event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED1": { + "description": "Enable or disable interrupt for TRIGGERED[1] event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED2": { + "description": "Enable or disable interrupt for TRIGGERED[2] event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED3": { + "description": "Enable or disable interrupt for TRIGGERED[3] event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED4": { + "description": "Enable or disable interrupt for TRIGGERED[4] event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED5": { + "description": "Enable or disable interrupt for TRIGGERED[5] event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED6": { + "description": "Enable or disable interrupt for TRIGGERED[6] event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED7": { + "description": "Enable or disable interrupt for TRIGGERED[7] event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED8": { + "description": "Enable or disable interrupt for TRIGGERED[8] event", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED9": { + "description": "Enable or disable interrupt for TRIGGERED[9] event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED10": { + "description": "Enable or disable interrupt for TRIGGERED[10] event", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED11": { + "description": "Enable or disable interrupt for TRIGGERED[11] event", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TRIGGERED12": { + "description": "Enable or disable interrupt for TRIGGERED[12] event", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + 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"Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION1WA": { + "description": "Write '1' to Disable interrupt for REGION[1].WA event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION1RA": { + "description": "Write '1' to Disable interrupt for REGION[1].RA event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION2WA": { + "description": "Write '1' to Disable interrupt for REGION[2].WA event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: 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"Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION2WA": { + "description": "Write '1' to Enable non-maskable interrupt for REGION[2].WA event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION2RA": { + "description": "Write '1' to Enable non-maskable interrupt for REGION[2].RA event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION3WA": { + "description": "Write '1' to Enable non-maskable interrupt for REGION[3].WA event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: 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"Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION1WA": { + "description": "Write '1' to Enable non-maskable interrupt for PREGION[1].WA event", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION1RA": { + "description": "Write '1' to Enable non-maskable interrupt for PREGION[1].RA event", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "NMIENCLR": { + "description": "Disable non-maskable interrupt", + "offset": 808, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, 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"children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "REGIONEN": { + "description": "Enable/disable regions watch", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RGN0WA": { + "description": "Enable/disable write access watch in region[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN0RA": { + "description": "Enable/disable read access watch in region[0]", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN1WA": { + "description": "Enable/disable write access watch in region[1]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN1RA": { + "description": "Enable/disable read access watch in region[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN2WA": { + "description": "Enable/disable write access watch in region[2]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN2RA": { + "description": "Enable/disable read access watch in region[2]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN3WA": { + "description": "Enable/disable write access watch in region[3]", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN3RA": { + "description": "Enable/disable read access watch in region[3]", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this region", + "value": 1 + } + } + } + } + }, + "PRGN0WA": { + "description": "Enable/disable write access watch in PREGION[0]", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this PREGION", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this PREGION", + "value": 1 + } + } + } + } + }, + "PRGN0RA": { + "description": "Enable/disable read access watch in PREGION[0]", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this PREGION", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this PREGION", + "value": 1 + } + } + } + } + }, + "PRGN1WA": { + "description": "Enable/disable write access watch in PREGION[1]", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this PREGION", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this PREGION", + "value": 1 + } + } + } + } + }, + "PRGN1RA": { + "description": "Enable/disable read access watch in PREGION[1]", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this PREGION", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this PREGION", + "value": 1 + } + } + } + } + } + } + } + }, + "REGIONENSET": { + "description": "Enable regions watch", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RGN0WA": { + "description": "Enable write access watch in region[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN0RA": { + "description": "Enable read access watch in region[0]", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN1WA": { + "description": "Enable write access watch in region[1]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access 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+ "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN3WA": { + "description": "Enable write access watch in region[3]", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN3RA": { + "description": "Enable read access watch in region[3]", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "PRGN0WA": { + "description": "Enable write access watch in PREGION[0]", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN0RA": { + "description": "Enable read access watch in PREGION[0]", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN1WA": { + "description": "Enable write access watch in PREGION[1]", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN1RA": { + "description": "Enable read access watch in PREGION[1]", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "REGIONENCLR": { + "description": "Disable regions watch", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RGN0WA": { + "description": "Disable write access watch in region[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN0RA": { + "description": "Disable read access watch in region[0]", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN1WA": { + "description": "Disable write access watch in region[1]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN1RA": { + "description": "Disable read access watch in region[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN2WA": { + "description": "Disable write access watch in region[2]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN2RA": { + "description": "Disable read access watch in region[2]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN3WA": { + "description": "Disable write access watch in region[3]", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN3RA": { + "description": "Disable read access watch in region[3]", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "PRGN0WA": { + "description": "Disable write access watch in PREGION[0]", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN0RA": { + "description": "Disable read access watch in PREGION[0]", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN1WA": { + "description": "Disable write access watch in PREGION[1]", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN1RA": { + "description": "Disable read access watch in PREGION[1]", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "PPI": { + "description": "Programmable Peripheral Interconnect", + "children": { + "registers": { + "CHEN": { + "description": "Channel enable register", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH0": { + "description": "Enable or disable channel 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH1": { + "description": "Enable or disable channel 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH2": { + "description": "Enable or disable channel 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH3": { + "description": "Enable or disable channel 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH4": { + "description": "Enable or disable channel 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH5": { + "description": "Enable or disable channel 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH6": { + "description": "Enable or disable channel 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH7": { + "description": "Enable or disable channel 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH8": { + "description": "Enable or disable channel 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH9": { + "description": "Enable or disable channel 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH10": { + "description": "Enable or disable channel 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH11": { + "description": "Enable or disable channel 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH12": { + "description": "Enable or disable channel 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH13": { + "description": "Enable or disable channel 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH14": { + "description": "Enable or disable channel 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH15": { + "description": "Enable or disable channel 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH16": { + "description": "Enable or disable channel 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH17": { + "description": "Enable or disable channel 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH18": { + "description": "Enable or disable channel 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH19": { + "description": "Enable or disable channel 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH20": { + "description": "Enable or disable channel 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH21": { + "description": "Enable or disable channel 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH22": { + "description": "Enable or disable channel 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH23": { + "description": "Enable or disable channel 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH24": { + "description": "Enable or disable channel 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH25": { + "description": "Enable or disable channel 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH26": { + "description": "Enable or disable channel 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH27": { + "description": "Enable or disable channel 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH28": { + "description": "Enable or disable channel 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH29": { + "description": "Enable or disable channel 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH30": { + "description": "Enable or disable channel 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH31": { + "description": "Enable or disable channel 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + } + } + } + }, + "CHENSET": { + "description": "Channel enable set register", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH0": { + "description": "Channel 0 enable set register. Writing '0' has no effect", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH1": { + "description": "Channel 1 enable set register. Writing '0' has no effect", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH2": { + "description": "Channel 2 enable set register. Writing '0' has no effect", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH3": { + "description": "Channel 3 enable set register. Writing '0' has no effect", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH4": { + "description": "Channel 4 enable set register. Writing '0' has no effect", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH5": { + "description": "Channel 5 enable set register. Writing '0' has no effect", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH6": { + "description": "Channel 6 enable set register. Writing '0' has no effect", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH7": { + "description": "Channel 7 enable set register. Writing '0' has no effect", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH8": { + "description": "Channel 8 enable set register. Writing '0' has no effect", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH9": { + "description": "Channel 9 enable set register. Writing '0' has no effect", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH10": { + "description": "Channel 10 enable set register. Writing '0' has no effect", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH11": { + "description": "Channel 11 enable set register. Writing '0' has no effect", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH12": { + "description": "Channel 12 enable set register. Writing '0' has no effect", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH13": { + "description": "Channel 13 enable set register. Writing '0' has no effect", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH14": { + "description": "Channel 14 enable set register. Writing '0' has no effect", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH15": { + "description": "Channel 15 enable set register. Writing '0' has no effect", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH16": { + "description": "Channel 16 enable set register. Writing '0' has no effect", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH17": { + "description": "Channel 17 enable set register. Writing '0' has no effect", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH18": { + "description": "Channel 18 enable set register. Writing '0' has no effect", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH19": { + "description": "Channel 19 enable set register. Writing '0' has no effect", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH20": { + "description": "Channel 20 enable set register. Writing '0' has no effect", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH21": { + "description": "Channel 21 enable set register. Writing '0' has no effect", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH22": { + "description": "Channel 22 enable set register. Writing '0' has no effect", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH23": { + "description": "Channel 23 enable set register. Writing '0' has no effect", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH24": { + "description": "Channel 24 enable set register. Writing '0' has no effect", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH25": { + "description": "Channel 25 enable set register. Writing '0' has no effect", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH26": { + "description": "Channel 26 enable set register. Writing '0' has no effect", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH27": { + "description": "Channel 27 enable set register. Writing '0' has no effect", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH28": { + "description": "Channel 28 enable set register. Writing '0' has no effect", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH29": { + "description": "Channel 29 enable set register. Writing '0' has no effect", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH30": { + "description": "Channel 30 enable set register. Writing '0' has no effect", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH31": { + "description": "Channel 31 enable set register. Writing '0' has no effect", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "CHENCLR": { + "description": "Channel enable clear register", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH0": { + "description": "Channel 0 enable clear register. Writing '0' has no effect", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH1": { + "description": "Channel 1 enable clear register. Writing '0' has no effect", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH2": { + "description": "Channel 2 enable clear register. Writing '0' has no effect", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH3": { + "description": "Channel 3 enable clear register. Writing '0' has no effect", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH4": { + "description": "Channel 4 enable clear register. Writing '0' has no effect", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH5": { + "description": "Channel 5 enable clear register. Writing '0' has no effect", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH6": { + "description": "Channel 6 enable clear register. Writing '0' has no effect", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH7": { + "description": "Channel 7 enable clear register. Writing '0' has no effect", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH8": { + "description": "Channel 8 enable clear register. Writing '0' has no effect", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH9": { + "description": "Channel 9 enable clear register. Writing '0' has no effect", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH10": { + "description": "Channel 10 enable clear register. Writing '0' has no effect", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH11": { + "description": "Channel 11 enable clear register. Writing '0' has no effect", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH12": { + "description": "Channel 12 enable clear register. Writing '0' has no effect", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH13": { + "description": "Channel 13 enable clear register. Writing '0' has no effect", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH14": { + "description": "Channel 14 enable clear register. Writing '0' has no effect", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH15": { + "description": "Channel 15 enable clear register. Writing '0' has no effect", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH16": { + "description": "Channel 16 enable clear register. Writing '0' has no effect", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH17": { + "description": "Channel 17 enable clear register. Writing '0' has no effect", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH18": { + "description": "Channel 18 enable clear register. Writing '0' has no effect", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH19": { + "description": "Channel 19 enable clear register. Writing '0' has no effect", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH20": { + "description": "Channel 20 enable clear register. Writing '0' has no effect", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH21": { + "description": "Channel 21 enable clear register. Writing '0' has no effect", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH22": { + "description": "Channel 22 enable clear register. Writing '0' has no effect", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH23": { + "description": "Channel 23 enable clear register. Writing '0' has no effect", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH24": { + "description": "Channel 24 enable clear register. Writing '0' has no effect", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH25": { + "description": "Channel 25 enable clear register. Writing '0' has no effect", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH26": { + "description": "Channel 26 enable clear register. Writing '0' has no effect", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH27": { + "description": "Channel 27 enable clear register. Writing '0' has no effect", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH28": { + "description": "Channel 28 enable clear register. Writing '0' has no effect", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH29": { + "description": "Channel 29 enable clear register. Writing '0' has no effect", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH30": { + "description": "Channel 30 enable clear register. Writing '0' has no effect", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH31": { + "description": "Channel 31 enable clear register. Writing '0' has no effect", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "CHG": { + "description": "Description collection[0]: Channel group 0", + "offset": 2048, + "size": 32, + "count": 6, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH0": { + "description": "Include or exclude channel 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH1": { + "description": "Include or exclude channel 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH2": { + "description": "Include or exclude channel 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH3": { + "description": "Include or exclude channel 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH4": { + "description": "Include or exclude channel 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH5": { + "description": "Include or exclude channel 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH6": { + "description": "Include or exclude channel 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH7": { + "description": "Include or exclude channel 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH8": { + "description": "Include or exclude channel 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH9": { + "description": "Include or exclude channel 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH10": { + "description": "Include or exclude channel 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH11": { + "description": "Include or exclude channel 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH12": { + "description": "Include or exclude channel 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH13": { + "description": "Include or exclude channel 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH14": { + "description": "Include or exclude channel 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH15": { + "description": "Include or exclude channel 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH16": { + "description": "Include or exclude channel 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH17": { + "description": "Include or exclude channel 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH18": { + "description": "Include or exclude channel 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH19": { + "description": "Include or exclude channel 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH20": { + "description": "Include or exclude channel 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH21": { + "description": "Include or exclude channel 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH22": { + "description": "Include or exclude channel 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH23": { + "description": "Include or exclude channel 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH24": { + "description": "Include or exclude channel 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH25": { + "description": "Include or exclude channel 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH26": { + "description": "Include or exclude channel 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH27": { + "description": "Include or exclude channel 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH28": { + "description": "Include or exclude channel 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH29": { + "description": "Include or exclude channel 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH30": { + "description": "Include or exclude channel 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH31": { + "description": "Include or exclude channel 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "NFCT": { + "description": "NFC-A compatible radio", + "children": { + "registers": { + "TASKS_ACTIVATE": { + "description": "Activate NFC peripheral for incoming and outgoing frames, change state to activated", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_DISABLE": { + "description": "Disable NFC peripheral", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SENSE": { + "description": "Enable NFC sense field mode, change state to sense mode", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STARTTX": { + "description": "Start transmission of a outgoing frame, change state to transmit", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_ENABLERXDATA": { + "description": "Initializes the EasyDMA for receive.", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_GOIDLE": { + "description": "Force state machine to IDLE state", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_GOSLEEP": { + "description": "Force state machine to SLEEP_A state", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_READY": { + "description": "The NFC peripheral is ready to receive and send frames", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_FIELDDETECTED": { + "description": "Remote NFC field detected", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_FIELDLOST": { + "description": "Remote NFC field lost", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_TXFRAMESTART": { + "description": "Marks the start of the first symbol of a transmitted frame", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_TXFRAMEEND": { + "description": "Marks the end of the last transmitted on-air symbol of a frame", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RXFRAMESTART": { + "description": "Marks the end of the first symbol of a received frame", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RXFRAMEEND": { + "description": "Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ERROR": { + "description": "NFC error reported. The ERRORSTATUS register contains details on the source of the error.", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RXERROR": { + "description": "NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ENDRX": { + "description": "RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ENDTX": { + "description": "Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_AUTOCOLRESSTARTED": { + "description": "Auto collision resolution process has started", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_COLLISION": { + "description": "NFC Auto collision resolution error reported.", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_SELECTED": { + "description": "NFC Auto collision resolution successfully completed", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_STARTED": { + "description": "EasyDMA is ready to receive or send frames.", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FIELDDETECTED_ACTIVATE": { + "description": "Shortcut between FIELDDETECTED event and ACTIVATE task", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "FIELDLOST_SENSE": { + "description": "Shortcut between FIELDLOST event and SENSE task", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Enable or disable interrupt for READY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "FIELDDETECTED": { + "description": "Enable or disable interrupt for FIELDDETECTED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "FIELDLOST": { + "description": "Enable or disable interrupt for FIELDLOST event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXFRAMESTART": { + "description": "Enable or disable interrupt for TXFRAMESTART event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXFRAMEEND": { + "description": "Enable or disable interrupt for TXFRAMEEND event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXFRAMESTART": { + "description": "Enable or disable interrupt for RXFRAMESTART event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXFRAMEEND": { + "description": "Enable or disable interrupt for RXFRAMEEND event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Enable or disable interrupt for ERROR event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXERROR": { + "description": "Enable or disable interrupt for RXERROR event", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Enable or disable interrupt for ENDRX event", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Enable or disable interrupt for ENDTX event", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "AUTOCOLRESSTARTED": { + "description": "Enable or disable interrupt for AUTOCOLRESSTARTED event", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "COLLISION": { + "description": "Enable or disable interrupt for COLLISION event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SELECTED": { + "description": "Enable or disable interrupt for SELECTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Enable or disable interrupt for STARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to Enable interrupt for READY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "FIELDDETECTED": { + "description": "Write '1' to Enable interrupt for FIELDDETECTED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "FIELDLOST": { + "description": "Write '1' to Enable interrupt for FIELDLOST event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXFRAMESTART": { + "description": "Write '1' to Enable interrupt for TXFRAMESTART event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXFRAMEEND": { + "description": "Write '1' to Enable interrupt for TXFRAMEEND event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXFRAMESTART": { + "description": "Write '1' to Enable interrupt for RXFRAMESTART event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXFRAMEEND": { + "description": "Write '1' to Enable interrupt for RXFRAMEEND event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Enable interrupt for ERROR event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXERROR": { + "description": "Write '1' to Enable interrupt for RXERROR event", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to Enable interrupt for ENDRX event", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to Enable interrupt for ENDTX event", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "AUTOCOLRESSTARTED": { + "description": "Write '1' to Enable interrupt for AUTOCOLRESSTARTED event", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COLLISION": { + "description": "Write '1' to Enable interrupt for COLLISION event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SELECTED": { + "description": "Write '1' to Enable interrupt for SELECTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Write '1' to Enable interrupt for STARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to Disable interrupt for READY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "FIELDDETECTED": { + "description": "Write '1' to Disable interrupt for FIELDDETECTED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "FIELDLOST": { + "description": "Write '1' to Disable interrupt for FIELDLOST event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXFRAMESTART": { + "description": "Write '1' to Disable interrupt for TXFRAMESTART event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXFRAMEEND": { + "description": "Write '1' to Disable interrupt for TXFRAMEEND event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXFRAMESTART": { + "description": "Write '1' to Disable interrupt for RXFRAMESTART event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXFRAMEEND": { + "description": "Write '1' to Disable interrupt for RXFRAMEEND event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Disable interrupt for ERROR event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXERROR": { + "description": "Write '1' to Disable interrupt for RXERROR event", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to Disable interrupt for ENDRX event", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to Disable interrupt for ENDTX event", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "AUTOCOLRESSTARTED": { + "description": "Write '1' to Disable interrupt for AUTOCOLRESSTARTED event", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COLLISION": { + "description": "Write '1' to Disable interrupt for COLLISION event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SELECTED": { + "description": "Write '1' to Disable interrupt for SELECTED event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Write '1' to Disable interrupt for STARTED event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSTATUS": { + "description": "NFC Error Status register", + "offset": 1028, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRAMEDELAYTIMEOUT": { + "description": "No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX", + "offset": 0, + "size": 1 + }, + "NFCFIELDTOOSTRONG": { + "description": "Field level is too high at max load resistance", + "offset": 2, + "size": 1 + }, + "NFCFIELDTOOWEAK": { + "description": "Field level is too low at min load resistance", + "offset": 3, + "size": 1 + } + } + } + }, + "CURRENTLOADCTRL": { + "description": "Current value driven to the NFC Load Control", + "offset": 1072, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CURRENTLOADCTRL": { + "description": "Current value driven to the NFC Load Control", + "offset": 0, + "size": 6 + } + } + } + }, + "FIELDPRESENT": { + "description": "Indicates the presence or not of a valid field", + "offset": 1084, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FIELDPRESENT": { + "description": "Indicates the presence or not of a valid field. Available only in the activated state.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoField": { + "description": "No valid field detected", + "value": 0 + }, + "FieldPresent": { + "description": "Valid field detected", + "value": 1 + } + } + } + } + }, + "LOCKDETECT": { + "description": "Indicates if the low level has locked to the field", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLocked": { + "description": "Not locked to field", + "value": 0 + }, + "Locked": { + "description": "Locked to field", + "value": 1 + } + } + } + } + } + } + } + }, + "FRAMEDELAYMIN": { + "description": "Minimum frame delay", + "offset": 1284, + "size": 32, + "reset_value": 1152, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRAMEDELAYMIN": { + "description": "Minimum frame delay in number of 13.56 MHz clocks", + "offset": 0, + "size": 16 + } + } + } + }, + "FRAMEDELAYMAX": { + "description": "Maximum frame delay", + "offset": 1288, + "size": 32, + "reset_value": 4096, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRAMEDELAYMAX": { + "description": "Maximum frame delay in number of 13.56 MHz clocks", + "offset": 0, + "size": 16 + } + } + } + }, + "FRAMEDELAYMODE": { + "description": "Configuration register for the Frame Delay Timer", + "offset": 1292, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRAMEDELAYMODE": { + "description": "Configuration register for the Frame Delay Timer", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "FreeRun": { + "description": "Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout.", + "value": 0 + }, + "Window": { + "description": "Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX", + "value": 1 + }, + "ExactVal": { + "description": "Frame is transmitted exactly at FRAMEDELAYMAX", + "value": 2 + }, + "WindowGrid": { + "description": "Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX", + "value": 3 + } + } + } + } + } + } + } + }, + "PACKETPTR": { + "description": "Packet pointer for TXD and RXD data storage in Data RAM", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTR": { + "description": "Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address.", + "offset": 0, + "size": 32 + } + } + } + }, + "MAXLEN": { + "description": "Size of allocated for TXD and RXD data storage buffer in Data RAM", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MAXLEN": { + "description": "Size of allocated for TXD and RXD data storage buffer in Data RAM", + "offset": 0, + "size": 9 + } + } + } + }, + "NFCID1_LAST": { + "description": "Last NFCID1 part (4, 7 or 10 bytes ID)", + "offset": 1424, + "size": 32, + "reset_value": 25443, + "reset_mask": 4294967295, + "children": { + "fields": { + "NFCID1_Z": { + "description": "NFCID1 byte Z (very last byte sent)", + "offset": 0, + "size": 8 + }, + "NFCID1_Y": { + "description": "NFCID1 byte Y", + "offset": 8, + "size": 8 + }, + "NFCID1_X": { + "description": "NFCID1 byte X", + "offset": 16, + "size": 8 + }, + "NFCID1_W": { + "description": "NFCID1 byte W", + "offset": 24, + "size": 8 + } + } + } + }, + "NFCID1_2ND_LAST": { + "description": "Second last NFCID1 part (7 or 10 bytes ID)", + "offset": 1428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NFCID1_V": { + "description": "NFCID1 byte V", + "offset": 0, + "size": 8 + }, + "NFCID1_U": { + "description": "NFCID1 byte U", + "offset": 8, + "size": 8 + }, + "NFCID1_T": { + "description": "NFCID1 byte T", + "offset": 16, + "size": 8 + } + } + } + }, + "NFCID1_3RD_LAST": { + "description": "Third last NFCID1 part (10 bytes ID)", + "offset": 1432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NFCID1_S": { + "description": "NFCID1 byte S", + "offset": 0, + "size": 8 + }, + "NFCID1_R": { + "description": "NFCID1 byte R", + "offset": 8, + "size": 8 + }, + "NFCID1_Q": { + "description": "NFCID1 byte Q", + "offset": 16, + "size": 8 + } + } + } + }, + "SENSRES": { + "description": "NFC-A SENS_RES auto-response settings", + "offset": 1440, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "BITFRAMESDD": { + "description": "Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification", + "offset": 0, + "size": 5, + "enum": { + "size": 5, + "children": { + "enum_fields": { + "SDD00000": { + "description": "SDD pattern 00000", + "value": 0 + }, + "SDD00001": { + "description": "SDD pattern 00001", + "value": 1 + }, + "SDD00010": { + "description": "SDD pattern 00010", + "value": 2 + }, + "SDD00100": { + "description": "SDD pattern 00100", + "value": 4 + }, + "SDD01000": { + "description": "SDD pattern 01000", + "value": 8 + }, + "SDD10000": { + "description": "SDD pattern 10000", + "value": 16 + } + } + } + } + }, + "RFU5": { + "description": "Reserved for future use. Shall be 0.", + "offset": 5, + "size": 1 + }, + "NFCIDSIZE": { + "description": "NFCID1 size. This value is used by the Auto collision resolution engine.", + "offset": 6, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "NFCID1Single": { + "description": "NFCID1 size: single (4 bytes)", + "value": 0 + }, + "NFCID1Double": { + "description": "NFCID1 size: double (7 bytes)", + "value": 1 + }, + "NFCID1Triple": { + "description": "NFCID1 size: triple (10 bytes)", + "value": 2 + } + } + } + } + }, + "PLATFCONFIG": { + "description": "Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification", + "offset": 8, + "size": 4 + }, + "RFU74": { + "description": "Reserved for future use. Shall be 0.", + "offset": 12, + "size": 4 + } + } + } + }, + "SELRES": { + "description": "NFC-A SEL_RES auto-response settings", + "offset": 1444, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFU10": { + "description": "Reserved for future use. Shall be 0.", + "offset": 0, + "size": 2 + }, + "CASCADE": { + "description": "Cascade bit (controlled by hardware, write has no effect)", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Complete": { + "description": "NFCID1 complete", + "value": 0 + }, + "NotComplete": { + "description": "NFCID1 not complete", + "value": 1 + } + } + } + } + }, + "RFU43": { + "description": "Reserved for future use. Shall be 0.", + "offset": 3, + "size": 2 + }, + "PROTOCOL": { + "description": "Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification", + "offset": 5, + "size": 2 + }, + "RFU7": { + "description": "Reserved for future use. Shall be 0.", + "offset": 7, + "size": 1 + } + } + } + } + } + } + }, + "GPIOTE": { + "description": "GPIO Tasks and Events", + "children": { + "registers": { + "TASKS_OUT": { + "description": "Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY.", + "offset": 0, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SET": { + "description": "Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high.", + "offset": 48, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_CLR": { + "description": "Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low.", + "offset": 96, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_IN": { + "description": "Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL", + "offset": 256, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_PORT": { + "description": "Event generated from multiple input GPIO pins with SENSE mechanism enabled", + "offset": 380, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IN0": { + "description": "Write '1' to Enable interrupt for IN[0] event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN1": { + "description": "Write '1' to Enable interrupt for IN[1] event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN2": { + "description": "Write '1' to Enable interrupt for IN[2] event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN3": { + "description": "Write '1' to Enable interrupt for IN[3] event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN4": { + "description": "Write '1' to Enable interrupt for IN[4] event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN5": { + "description": "Write '1' to Enable interrupt for IN[5] event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN6": { + "description": "Write '1' to Enable interrupt for IN[6] event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN7": { + "description": "Write '1' to Enable interrupt for IN[7] event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PORT": { + "description": "Write '1' to Enable interrupt for PORT event", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IN0": { + "description": "Write '1' to Disable interrupt for IN[0] event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN1": { + "description": "Write '1' to Disable interrupt for IN[1] event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN2": { + "description": "Write '1' to Disable interrupt for IN[2] event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN3": { + "description": "Write '1' to Disable interrupt for IN[3] event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN4": { + "description": "Write '1' to Disable interrupt for IN[4] event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN5": { + "description": "Write '1' to Disable interrupt for IN[5] event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN6": { + "description": "Write '1' to Disable interrupt for IN[6] event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN7": { + "description": "Write '1' to Disable interrupt for IN[7] event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PORT": { + "description": "Write '1' to Disable interrupt for PORT event", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event", + "offset": 1296, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "Mode", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.", + "value": 0 + }, + "Event": { + "description": "Event mode", + "value": 1 + }, + "Task": { + "description": "Task mode", + "value": 3 + } + } + } + } + }, + "PSEL": { + "description": "GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event", + "offset": 8, + "size": 5 + }, + "POLARITY": { + "description": "When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.", + "offset": 16, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "None": { + "description": "Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.", + "value": 0 + }, + "LoToHi": { + "description": "Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.", + "value": 1 + }, + "HiToLo": { + "description": "Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.", + "value": 2 + }, + "Toggle": { + "description": "Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.", + "value": 3 + } + } + } + } + }, + "OUTINIT": { + "description": "When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Task mode: Initial value of pin before task triggering is low", + "value": 0 + }, + "High": { + "description": "Task mode: Initial value of pin before task triggering is high", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "SAADC": { + "description": "Analog to Digital Converter", + "children": { + "registers": { + "TASKS_START": { + "description": "Start the ADC and prepare the result buffer in RAM", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SAMPLE": { + "description": "Take one ADC sample, if scan is enabled all channels are sampled", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop the ADC and terminate any on-going conversion", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_CALIBRATEOFFSET": { + "description": "Starts offset auto-calibration", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_STARTED": { + "description": "The ADC has started", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_END": { + "description": "The ADC has filled up the Result buffer", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_DONE": { + "description": "A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RESULTDONE": { + "description": "A result is ready to get transferred to RAM.", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_CALIBRATEDONE": { + "description": "Calibration is complete", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_STOPPED": { + "description": "The ADC has stopped", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Enable or disable interrupt for STARTED event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Enable or disable interrupt for END event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "DONE": { + "description": "Enable or disable interrupt for DONE event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RESULTDONE": { + "description": "Enable or disable interrupt for RESULTDONE event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CALIBRATEDONE": { + "description": "Enable or disable interrupt for CALIBRATEDONE event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Enable or disable interrupt for STOPPED event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH0LIMITH": { + "description": "Enable or disable interrupt for CH[0].LIMITH event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH0LIMITL": { + "description": "Enable or disable interrupt for CH[0].LIMITL event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH1LIMITH": { + "description": "Enable or disable interrupt for CH[1].LIMITH event", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH1LIMITL": { + "description": "Enable or disable interrupt for CH[1].LIMITL event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH2LIMITH": { + "description": "Enable or disable interrupt for CH[2].LIMITH event", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH2LIMITL": { + "description": "Enable or disable interrupt for CH[2].LIMITL event", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH3LIMITH": { + "description": "Enable or disable interrupt for CH[3].LIMITH event", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH3LIMITL": { + "description": "Enable or disable interrupt for CH[3].LIMITL event", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH4LIMITH": { + "description": "Enable or disable interrupt for CH[4].LIMITH event", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH4LIMITL": { + "description": "Enable or disable interrupt for CH[4].LIMITL event", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH5LIMITH": { + "description": "Enable or disable interrupt for CH[5].LIMITH event", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH5LIMITL": { + "description": "Enable or disable interrupt for CH[5].LIMITL event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH6LIMITH": { + "description": "Enable or disable interrupt for CH[6].LIMITH event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH6LIMITL": { + "description": "Enable or disable interrupt for CH[6].LIMITL event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH7LIMITH": { + "description": "Enable or disable interrupt for CH[7].LIMITH event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH7LIMITL": { + "description": "Enable or disable interrupt for CH[7].LIMITL event", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Write '1' to Enable interrupt for STARTED event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to Enable interrupt for END event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DONE": { + "description": "Write '1' to Enable interrupt for DONE event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RESULTDONE": { + "description": "Write '1' to Enable interrupt for RESULTDONE event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CALIBRATEDONE": { + "description": "Write '1' to Enable interrupt for CALIBRATEDONE event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to Enable interrupt for STOPPED event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH0LIMITH": { + "description": "Write '1' to Enable interrupt for CH[0].LIMITH event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH0LIMITL": { + "description": "Write '1' to Enable interrupt for CH[0].LIMITL event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH1LIMITH": { + "description": "Write '1' to Enable interrupt for CH[1].LIMITH event", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH1LIMITL": { + "description": "Write '1' to Enable interrupt for CH[1].LIMITL event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH2LIMITH": { + "description": "Write '1' to Enable interrupt for CH[2].LIMITH event", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH2LIMITL": { + "description": "Write '1' to Enable interrupt for CH[2].LIMITL event", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH3LIMITH": { + "description": "Write '1' to Enable interrupt for CH[3].LIMITH event", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH3LIMITL": { + "description": "Write '1' to Enable interrupt for CH[3].LIMITL event", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH4LIMITH": { + "description": "Write '1' to Enable interrupt for CH[4].LIMITH event", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH4LIMITL": { + "description": "Write '1' to Enable interrupt for CH[4].LIMITL event", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH5LIMITH": { + "description": "Write '1' to Enable interrupt for CH[5].LIMITH event", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH5LIMITL": { + "description": "Write '1' to Enable interrupt for CH[5].LIMITL event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH6LIMITH": { + "description": "Write '1' to Enable interrupt for CH[6].LIMITH event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH6LIMITL": { + "description": "Write '1' to Enable interrupt for CH[6].LIMITL event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH7LIMITH": { + "description": "Write '1' to Enable interrupt for CH[7].LIMITH event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH7LIMITL": { + "description": "Write '1' to Enable interrupt for CH[7].LIMITL event", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Write '1' to Disable interrupt for STARTED event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to Disable interrupt for END event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DONE": { + "description": "Write '1' to Disable interrupt for DONE event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RESULTDONE": { + "description": "Write '1' to Disable interrupt for RESULTDONE event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CALIBRATEDONE": { + "description": "Write '1' to Disable interrupt for CALIBRATEDONE event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to Disable interrupt for STOPPED event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH0LIMITH": { + "description": "Write '1' to Disable interrupt for CH[0].LIMITH event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH0LIMITL": { + "description": "Write '1' to Disable interrupt for CH[0].LIMITL event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH1LIMITH": { + "description": "Write '1' to Disable interrupt for CH[1].LIMITH event", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH1LIMITL": { + "description": "Write '1' to Disable interrupt for CH[1].LIMITL event", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH2LIMITH": { + "description": "Write '1' to Disable interrupt for CH[2].LIMITH event", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH2LIMITL": { + "description": "Write '1' to Disable interrupt for CH[2].LIMITL event", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH3LIMITH": { + "description": "Write '1' to Disable interrupt for CH[3].LIMITH event", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH3LIMITL": { + "description": "Write '1' to Disable interrupt for CH[3].LIMITL event", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH4LIMITH": { + "description": "Write '1' to Disable interrupt for CH[4].LIMITH event", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH4LIMITL": { + "description": "Write '1' to Disable interrupt for CH[4].LIMITL event", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH5LIMITH": { + "description": "Write '1' to Disable interrupt for CH[5].LIMITH event", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH5LIMITL": { + "description": "Write '1' to Disable interrupt for CH[5].LIMITL event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH6LIMITH": { + "description": "Write '1' to Disable interrupt for CH[6].LIMITH event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH6LIMITL": { + "description": "Write '1' to Disable interrupt for CH[6].LIMITL event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH7LIMITH": { + "description": "Write '1' to Disable interrupt for CH[7].LIMITH event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH7LIMITL": { + "description": "Write '1' to Disable interrupt for CH[7].LIMITL event", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "STATUS": { + "description": "Status", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STATUS": { + "description": "Status", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Ready": { + "description": "ADC is ready. No on-going conversion.", + "value": 0 + }, + "Busy": { + "description": "ADC is busy. Conversion in progress.", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable or disable ADC", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable ADC", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable ADC", + "value": 0 + }, + "Enabled": { + "description": "Enable ADC", + "value": 1 + } + } + } + } + } + } + } + }, + "RESOLUTION": { + "description": "Resolution configuration", + "offset": 1520, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "VAL": { + "description": "Set the resolution", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "8bit": { + "description": "8 bit", + "value": 0 + }, + "10bit": { + "description": "10 bit", + "value": 1 + }, + "12bit": { + "description": "12 bit", + "value": 2 + }, + "14bit": { + "description": "14 bit", + "value": 3 + } + } + } + } + } + } + } + }, + "OVERSAMPLE": { + "description": "Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.", + "offset": 1524, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERSAMPLE": { + "description": "Oversample control", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Bypass": { + "description": "Bypass oversampling", + "value": 0 + }, + "Over2x": { + "description": "Oversample 2x", + "value": 1 + }, + "Over4x": { + "description": "Oversample 4x", + "value": 2 + }, + "Over8x": { + "description": "Oversample 8x", + "value": 3 + }, + "Over16x": { + "description": "Oversample 16x", + "value": 4 + }, + "Over32x": { + "description": "Oversample 32x", + "value": 5 + }, + "Over64x": { + "description": "Oversample 64x", + "value": 6 + }, + "Over128x": { + "description": "Oversample 128x", + "value": 7 + }, + "Over256x": { + "description": "Oversample 256x", + "value": 8 + } + } + } + } + } + } + } + }, + "SAMPLERATE": { + "description": "Controls normal or continuous sample rate", + "offset": 1528, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC": { + "description": "Capture and compare value. Sample rate is 16 MHz/CC", + "offset": 0, + "size": 11 + }, + "MODE": { + "description": "Select mode for sample rate control", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Task": { + "description": "Rate is controlled from SAMPLE task", + "value": 0 + }, + "Timers": { + "description": "Rate is controlled from local timer (use CC to control the rate)", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "TIMER0": { + "description": "Timer/Counter 0", + "children": { + "registers": { + "TASKS_START": { + "description": "Start Timer", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop Timer", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_COUNT": { + "description": "Increment Timer (Counter mode only)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_CLEAR": { + "description": "Clear time", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SHUTDOWN": { + "description": "Deprecated register - Shut down timer", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_CAPTURE": { + "description": "Description collection[0]: Capture Timer value to CC[0] register", + "offset": 64, + "size": 32, + "count": 6, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_COMPARE": { + "description": "Description collection[0]: Compare event on CC[0] match", + "offset": 320, + "size": 32, + "count": 6, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMPARE0_CLEAR": { + "description": "Shortcut between COMPARE[0] event and CLEAR task", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE1_CLEAR": { + "description": "Shortcut between COMPARE[1] event and CLEAR task", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE2_CLEAR": { + "description": "Shortcut between COMPARE[2] event and CLEAR task", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE3_CLEAR": { + "description": "Shortcut between COMPARE[3] event and CLEAR task", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE4_CLEAR": { + "description": "Shortcut between COMPARE[4] event and CLEAR task", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE5_CLEAR": { + "description": "Shortcut between COMPARE[5] event and CLEAR task", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE0_STOP": { + "description": "Shortcut between COMPARE[0] event and STOP task", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE1_STOP": { + "description": "Shortcut between COMPARE[1] event and STOP task", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE2_STOP": { + "description": "Shortcut between COMPARE[2] event and STOP task", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE3_STOP": { + "description": "Shortcut between COMPARE[3] event and STOP task", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE4_STOP": { + "description": "Shortcut between COMPARE[4] event and STOP task", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE5_STOP": { + "description": "Shortcut between COMPARE[5] event and STOP task", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMPARE0": { + "description": "Write '1' to Enable interrupt for COMPARE[0] event", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to Enable interrupt for COMPARE[1] event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to Enable interrupt for COMPARE[2] event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to Enable interrupt for COMPARE[3] event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE4": { + "description": "Write '1' to Enable interrupt for COMPARE[4] event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE5": { + "description": "Write '1' to Enable interrupt for COMPARE[5] event", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMPARE0": { + "description": "Write '1' to Disable interrupt for COMPARE[0] event", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to Disable interrupt for COMPARE[1] event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to Disable interrupt for COMPARE[2] event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to Disable interrupt for COMPARE[3] event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE4": { + "description": "Write '1' to Disable interrupt for COMPARE[4] event", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE5": { + "description": "Write '1' to Disable interrupt for COMPARE[5] event", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "MODE": { + "description": "Timer mode selection", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "Timer mode", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Timer": { + "description": "Select Timer mode", + "value": 0 + }, + "Counter": { + "description": "Deprecated enumerator - Select Counter mode", + "value": 1 + }, + "LowPowerCounter": { + "description": "Select Low Power Counter mode", + "value": 2 + } + } + } + } + } + } + } + }, + "BITMODE": { + "description": "Configure the number of bits used by the TIMER", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BITMODE": { + "description": "Timer bit width", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "16Bit": { + "description": "16 bit timer bit width", + "value": 0 + }, + "08Bit": { + "description": "8 bit timer bit width", + "value": 1 + }, + "24Bit": { + "description": "24 bit timer bit width", + "value": 2 + }, + "32Bit": { + "description": "32 bit timer bit width", + "value": 3 + } + } + } + } + } + } + } + }, + "PRESCALER": { + "description": "Timer prescaler register", + "offset": 1296, + "size": 32, + "reset_value": 4, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRESCALER": { + "description": "Prescaler value", + "offset": 0, + "size": 4 + } + } + } + }, + "CC": { + "description": "Description collection[0]: Capture/Compare register 0", + "offset": 1344, + "size": 32, + "count": 6, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC": { + "description": "Capture/Compare value", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "NVMC": { + "description": "Non Volatile Memory Controller", + "children": { + "registers": { + "READY": { + "description": "Ready flag", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "READY": { + "description": "NVMC is ready or busy", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Busy": { + "description": "NVMC is busy (on-going write or erase operation)", + "value": 0 + }, + "Ready": { + "description": "NVMC is ready", + "value": 1 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WEN": { + "description": "Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Ren": { + "description": "Read only access", + "value": 0 + }, + "Wen": { + "description": "Write Enabled", + "value": 1 + }, + "Een": { + "description": "Erase enabled", + "value": 2 + } + } + } + } + } + } + } + }, + "ERASEPAGE": { + "description": "Register for erasing a page in Code area", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ERASEPAGE": { + "description": "Register for starting erase of a page in Code area", + "offset": 0, + "size": 32 + } + } + } + }, + "ERASEPCR1": { + "description": "Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE.", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ERASEPCR1": { + "description": "Register for erasing a page in Code area. Equivalent to ERASEPAGE.", + "offset": 0, + "size": 32 + } + } + } + }, + "ERASEALL": { + "description": "Register for erasing all non-volatile user memory", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ERASEALL": { + "description": "Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoOperation": { + "description": "No operation", + "value": 0 + }, + "Erase": { + "description": "Start chip erase", + "value": 1 + } + } + } + } + } + } + } + }, + "ERASEPCR0": { + "description": "Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE.", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ERASEPCR0": { + "description": "Register for starting erase of a page in Code area. Equivalent to ERASEPAGE.", + "offset": 0, + "size": 32 + } + } + } + }, + "ERASEUICR": { + "description": "Register for erasing User Information Configuration Registers", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ERASEUICR": { + "description": "Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoOperation": { + "description": "No operation", + "value": 0 + }, + "Erase": { + "description": "Start erase of UICR", + "value": 1 + } + } + } + } + } + } + } + }, + "ICACHECNF": { + "description": "I-Code cache configuration register.", + "offset": 1344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CACHEEN": { + "description": "Cache enable", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable cache. Invalidates all cache entries.", + "value": 0 + }, + "Enabled": { + "description": "Enable cache", + "value": 1 + } + } + } + } + }, + "CACHEPROFEN": { + "description": "Cache profiling enable", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable cache profiling", + "value": 0 + }, + "Enabled": { + "description": "Enable cache profiling", + "value": 1 + } + } + } + } + } + } + } + }, + "IHIT": { + "description": "I-Code cache hit counter.", + "offset": 1352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HITS": { + "description": "Number of cache hits", + "offset": 0, + "size": 32 + } + } + } + }, + "IMISS": { + "description": "I-Code cache miss counter.", + "offset": 1356, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MISSES": { + "description": "Number of cache misses", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "PDM": { + "description": "Pulse Density Modulation (Digital Microphone) Interface", + "children": { + "registers": { + "TASKS_START": { + "description": "Starts continuous PDM transfer", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stops PDM transfer", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_STARTED": { + "description": "PDM transfer has started", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_STOPPED": { + "description": "PDM transfer has finished", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_END": { + "description": "The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Enable or disable interrupt for STARTED event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Enable or disable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Enable or disable interrupt for END event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Write '1' to Enable interrupt for STARTED event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to Enable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to Enable interrupt for END event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Write '1' to Disable interrupt for STARTED event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to Disable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to Disable interrupt for END event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "PDM module enable register", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable PDM module", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "PDMCLKCTRL": { + "description": "PDM clock generator control", + "offset": 1284, + "size": 32, + "reset_value": 138412032, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQ": { + "description": "PDM_CLK frequency", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "1000K": { + "description": "PDM_CLK = 32 MHz / 32 = 1.000 MHz", + "value": 134217728 + }, + "Default": { + "description": "PDM_CLK = 32 MHz / 31 = 1.032 MHz", + "value": 138412032 + }, + "1067K": { + "description": "PDM_CLK = 32 MHz / 30 = 1.067 MHz", + "value": 142606336 + } + } + } + } + } + } + } + }, + "MODE": { + "description": "Defines the routing of the connected PDM microphones' signals", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OPERATION": { + "description": "Mono or stereo operation", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Stereo": { + "description": "Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]", + "value": 0 + }, + "Mono": { + "description": "Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]", + "value": 1 + } + } + } + } + }, + "EDGE": { + "description": "Defines on which PDM_CLK edge Left (or mono) is sampled", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "LeftFalling": { + "description": "Left (or mono) is sampled on falling edge of PDM_CLK", + "value": 0 + }, + "LeftRising": { + "description": "Left (or mono) is sampled on rising edge of PDM_CLK", + "value": 1 + } + } + } + } + } + } + } + }, + "GAINL": { + "description": "Left output gain adjustment", + "offset": 1304, + "size": 32, + "reset_value": 40, + "reset_mask": 4294967295, + "children": { + "fields": { + "GAINL": { + "description": "Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust", + "offset": 0, + "size": 7, + "enum": { + "size": 7, + "children": { + "enum_fields": { + "MinGain": { + "description": "-20dB gain adjustment (minimum)", + "value": 0 + }, + "DefaultGain": { + "description": "0dB gain adjustment ('2500 RMS' requirement)", + "value": 40 + }, + "MaxGain": { + "description": "+20dB gain adjustment (maximum)", + "value": 80 + } + } + } + } + } + } + } + }, + "GAINR": { + "description": "Right output gain adjustment", + "offset": 1308, + "size": 32, + "reset_value": 40, + "reset_mask": 4294967295, + "children": { + "fields": { + "GAINR": { + "description": "Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)", + "offset": 0, + "size": 8, + "enum": { + "size": 8, + "children": { + "enum_fields": { + "MinGain": { + "description": "-20dB gain adjustment (minimum)", + "value": 0 + }, + "DefaultGain": { + "description": "0dB gain adjustment ('2500 RMS' requirement)", + "value": 40 + }, + "MaxGain": { + "description": "+20dB gain adjustment (maximum)", + "value": 80 + } + } + } + } + } + } + } + } + } + } + }, + "RTC0": { + "description": "Real time counter 0", + "children": { + "registers": { + "TASKS_START": { + "description": "Start RTC COUNTER", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop RTC COUNTER", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_CLEAR": { + "description": "Clear RTC COUNTER", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_TRIGOVRFLW": { + "description": "Set COUNTER to 0xFFFFF0", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_TICK": { + "description": "Event on COUNTER increment", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_OVRFLW": { + "description": "Event on COUNTER overflow", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_COMPARE": { + "description": "Description collection[0]: Compare event on CC[0] match", + "offset": 320, + "size": 32, + "count": 4, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TICK": { + "description": "Write '1' to Enable interrupt for TICK event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "OVRFLW": { + "description": "Write '1' to Enable interrupt for OVRFLW event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE0": { + "description": "Write '1' to Enable interrupt for COMPARE[0] event", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to Enable interrupt for COMPARE[1] event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to Enable interrupt for COMPARE[2] event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to Enable interrupt for COMPARE[3] event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TICK": { + "description": "Write '1' to Disable interrupt for TICK event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "OVRFLW": { + "description": "Write '1' to Disable interrupt for OVRFLW event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE0": { + "description": "Write '1' to Disable interrupt for COMPARE[0] event", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to Disable interrupt for COMPARE[1] event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to Disable interrupt for COMPARE[2] event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to Disable interrupt for COMPARE[3] event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "EVTEN": { + "description": "Enable or disable event routing", + "offset": 832, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TICK": { + "description": "Enable or disable event routing for TICK event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "OVRFLW": { + "description": "Enable or disable event routing for OVRFLW event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "COMPARE0": { + "description": "Enable or disable event routing for COMPARE[0] event", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Enable or disable event routing for COMPARE[1] event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Enable or disable event routing for COMPARE[2] event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Enable or disable event routing for COMPARE[3] event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "EVTENSET": { + "description": "Enable event routing", + "offset": 836, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TICK": { + "description": "Write '1' to Enable event routing for TICK event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "OVRFLW": { + "description": "Write '1' to Enable event routing for OVRFLW event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE0": { + "description": "Write '1' to Enable event routing for COMPARE[0] event", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to Enable event routing for COMPARE[1] event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to Enable event routing for COMPARE[2] event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to Enable event routing for COMPARE[3] event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "EVTENCLR": { + "description": "Disable event routing", + "offset": 840, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TICK": { + "description": "Write '1' to Disable event routing for TICK event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "OVRFLW": { + "description": "Write '1' to Disable event routing for OVRFLW event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE0": { + "description": "Write '1' to Disable event routing for COMPARE[0] event", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to Disable event routing for COMPARE[1] event", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to Disable event routing for COMPARE[2] event", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to Disable event routing for COMPARE[3] event", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "COUNTER": { + "description": "Current COUNTER value", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "COUNTER": { + "description": "Counter value", + "offset": 0, + "size": 24 + } + } + } + }, + "PRESCALER": { + "description": "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRESCALER": { + "description": "Prescaler value", + "offset": 0, + "size": 12 + } + } + } + }, + "CC": { + "description": "Description collection[0]: Compare register 0", + "offset": 1344, + "size": 32, + "count": 4, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMPARE": { + "description": "Compare value", + "offset": 0, + "size": 24 + } + } + } + } + } + } + }, + "TEMP": { + "description": "Temperature Sensor", + "children": { + "registers": { + "TASKS_START": { + "description": "Start temperature measurement", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop temperature measurement", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_DATARDY": { + "description": "Temperature measurement complete, data ready", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATARDY": { + "description": "Write '1' to Enable interrupt for DATARDY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATARDY": { + "description": "Write '1' to Disable interrupt for DATARDY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "TEMP": { + "description": "Temperature in degC (0.25deg steps)", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TEMP": { + "description": "Temperature in degC (0.25deg steps)", + "offset": 0, + "size": 32 + } + } + } + }, + "A0": { + "description": "Slope of 1st piece wise linear function", + "offset": 1312, + "size": 32, + "reset_value": 800, + "reset_mask": 4294967295, + "children": { + "fields": { + "A0": { + "description": "Slope of 1st piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "A1": { + "description": "Slope of 2nd piece wise linear function", + "offset": 1316, + "size": 32, + "reset_value": 835, + "reset_mask": 4294967295, + "children": { + "fields": { + "A1": { + "description": "Slope of 2nd piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "A2": { + "description": "Slope of 3rd piece wise linear function", + "offset": 1320, + "size": 32, + "reset_value": 861, + "reset_mask": 4294967295, + "children": { + "fields": { + "A2": { + "description": "Slope of 3rd piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "A3": { + "description": "Slope of 4th piece wise linear function", + "offset": 1324, + "size": 32, + "reset_value": 1024, + "reset_mask": 4294967295, + "children": { + "fields": { + "A3": { + "description": "Slope of 4th piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "A4": { + "description": "Slope of 5th piece wise linear function", + "offset": 1328, + "size": 32, + "reset_value": 1151, + "reset_mask": 4294967295, + "children": { + "fields": { + "A4": { + "description": "Slope of 5th piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "A5": { + "description": "Slope of 6th piece wise linear function", + "offset": 1332, + "size": 32, + "reset_value": 891, + "reset_mask": 4294967295, + "children": { + "fields": { + "A5": { + "description": "Slope of 6th piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "B0": { + "description": "y-intercept of 1st piece wise linear function", + "offset": 1344, + "size": 32, + "reset_value": 16332, + "reset_mask": 4294967295, + "children": { + "fields": { + "B0": { + "description": "y-intercept of 1st piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "B1": { + "description": "y-intercept of 2nd piece wise linear function", + "offset": 1348, + "size": 32, + "reset_value": 16280, + "reset_mask": 4294967295, + "children": { + "fields": { + "B1": { + "description": "y-intercept of 2nd piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "B2": { + "description": "y-intercept of 3rd piece wise linear function", + "offset": 1352, + "size": 32, + "reset_value": 16280, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2": { + "description": "y-intercept of 3rd piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "B3": { + "description": "y-intercept of 4th piece wise linear function", + "offset": 1356, + "size": 32, + "reset_value": 18, + "reset_mask": 4294967295, + "children": { + "fields": { + "B3": { + "description": "y-intercept of 4th piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "B4": { + "description": "y-intercept of 5th piece wise linear function", + "offset": 1360, + "size": 32, + "reset_value": 106, + "reset_mask": 4294967295, + "children": { + "fields": { + "B4": { + "description": "y-intercept of 5th piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "B5": { + "description": "y-intercept of 6th piece wise linear function", + "offset": 1364, + "size": 32, + "reset_value": 15824, + "reset_mask": 4294967295, + "children": { + "fields": { + "B5": { + "description": "y-intercept of 6th piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "T0": { + "description": "End point of 1st piece wise linear function", + "offset": 1376, + "size": 32, + "reset_value": 226, + "reset_mask": 4294967295, + "children": { + "fields": { + "T0": { + "description": "End point of 1st piece wise linear function", + "offset": 0, + "size": 8 + } + } + } + }, + "T1": { + "description": "End point of 2nd piece wise linear function", + "offset": 1380, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "T1": { + "description": "End point of 2nd piece wise linear function", + "offset": 0, + "size": 8 + } + } + } + }, + "T2": { + "description": "End point of 3rd piece wise linear function", + "offset": 1384, + "size": 32, + "reset_value": 20, + "reset_mask": 4294967295, + "children": { + "fields": { + "T2": { + "description": "End point of 3rd piece wise linear function", + "offset": 0, + "size": 8 + } + } + } + }, + "T3": { + "description": "End point of 4th piece wise linear function", + "offset": 1388, + "size": 32, + "reset_value": 25, + "reset_mask": 4294967295, + "children": { + "fields": { + "T3": { + "description": "End point of 4th piece wise linear function", + "offset": 0, + "size": 8 + } + } + } + }, + "T4": { + "description": "End point of 5th piece wise linear function", + "offset": 1392, + "size": 32, + "reset_value": 80, + "reset_mask": 4294967295, + "children": { + "fields": { + "T4": { + "description": "End point of 5th piece wise linear function", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "RNG": { + "description": "Random Number Generator", + "children": { + "registers": { + "TASKS_START": { + "description": "Task starting the random number generator", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Task stopping the random number generator", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_VALRDY": { + "description": "Event being generated for every new random number written to the VALUE register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VALRDY_STOP": { + "description": "Shortcut between VALRDY event and STOP task", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VALRDY": { + "description": "Write '1' to Enable interrupt for VALRDY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VALRDY": { + "description": "Write '1' to Disable interrupt for VALRDY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DERCEN": { + "description": "Bias correction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "VALUE": { + "description": "Output random number", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "VALUE": { + "description": "Generated random number", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "ECB": { + "description": "AES ECB Mode Encryption", + "children": { + "registers": { + "TASKS_STARTECB": { + "description": "Start ECB block encrypt", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOPECB": { + "description": "Abort a possible executing ECB operation", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_ENDECB": { + "description": "ECB block encrypt complete", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ERRORECB": { + "description": "ECB block encrypt aborted because of a STOPECB task or due to an error", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDECB": { + "description": "Write '1' to Enable interrupt for ENDECB event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERRORECB": { + "description": "Write '1' to Enable interrupt for ERRORECB event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDECB": { + "description": "Write '1' to Disable interrupt for ENDECB event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERRORECB": { + "description": "Write '1' to Disable interrupt for ERRORECB event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ECBDATAPTR": { + "description": "ECB block encrypt memory pointers", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ECBDATAPTR": { + "description": "Pointer to the ECB data structure (see Table 1 ECB data structure overview)", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "CCM": { + "description": "AES CCM Mode Encryption", + "children": { + "registers": { + "TASKS_KSGEN": { + "description": "Start generation of key-stream. This operation will stop by itself when completed.", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_CRYPT": { + "description": "Start encryption/decryption. This operation will stop by itself when completed.", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop encryption/decryption", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_ENDKSGEN": { + "description": "Key-stream generation complete", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ENDCRYPT": { + "description": "Encrypt/decrypt complete", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ERROR": { + "description": "CCM error event", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDKSGEN_CRYPT": { + "description": "Shortcut between ENDKSGEN event and CRYPT task", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDKSGEN": { + "description": "Write '1' to Enable interrupt for ENDKSGEN event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDCRYPT": { + "description": "Write '1' to Enable interrupt for ENDCRYPT event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Enable interrupt for ERROR event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDKSGEN": { + "description": "Write '1' to Disable interrupt for ENDKSGEN event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDCRYPT": { + "description": "Write '1' to Disable interrupt for ENDCRYPT event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to Disable interrupt for ERROR event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "MICSTATUS": { + "description": "MIC check result", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "MICSTATUS": { + "description": "The result of the MIC check performed during the previous decryption operation", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "CheckFailed": { + "description": "MIC check failed", + "value": 0 + }, + "CheckPassed": { + "description": "MIC check passed", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable CCM", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 2 + } + } + } + } + } + } + } + }, + "MODE": { + "description": "Operation mode", + "offset": 1284, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "The mode of operation to be used", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Encryption": { + "description": "AES CCM packet encryption mode", + "value": 0 + }, + "Decryption": { + "description": "AES CCM packet decryption mode", + "value": 1 + } + } + } + } + }, + "DATARATE": { + "description": "Data rate that the CCM shall run in synch with", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "1Mbit": { + "description": "In synch with 1 Mbit data rate", + "value": 0 + }, + "2Mbit": { + "description": "In synch with 2 Mbit data rate", + "value": 1 + } + } + } + } + }, + "LENGTH": { + "description": "Packet length configuration", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Default": { + "description": "Default length. Effective length of LENGTH field is 5-bit", + "value": 0 + }, + "Extended": { + "description": "Extended length. Effective length of LENGTH field is 8-bit", + "value": 1 + } + } + } + } + } + } + } + }, + "CNFPTR": { + "description": "Pointer to data structure holding AES key and NONCE vector", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNFPTR": { + "description": "Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)", + "offset": 0, + "size": 32 + } + } + } + }, + "INPTR": { + "description": "Input pointer", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INPTR": { + "description": "Input pointer", + "offset": 0, + "size": 32 + } + } + } + }, + "OUTPTR": { + "description": "Output pointer", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OUTPTR": { + "description": "Output pointer", + "offset": 0, + "size": 32 + } + } + } + }, + "SCRATCHPTR": { + "description": "Pointer to data area used for temporary storage", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SCRATCHPTR": { + "description": "Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "AAR": { + "description": "Accelerated Address Resolver", + "children": { + "registers": { + "TASKS_START": { + "description": "Start resolving addresses based on IRKs specified in the IRK data structure", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop resolving addresses", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_END": { + "description": "Address resolution procedure complete", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_RESOLVED": { + "description": "Address resolved", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_NOTRESOLVED": { + "description": "Address not resolved", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END": { + "description": "Write '1' to Enable interrupt for END event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RESOLVED": { + "description": "Write '1' to Enable interrupt for RESOLVED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NOTRESOLVED": { + "description": "Write '1' to Enable interrupt for NOTRESOLVED event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END": { + "description": "Write '1' to Disable interrupt for END event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RESOLVED": { + "description": "Write '1' to Disable interrupt for RESOLVED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NOTRESOLVED": { + "description": "Write '1' to Disable interrupt for NOTRESOLVED event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "STATUS": { + "description": "Resolution status", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STATUS": { + "description": "The IRK that was used last time an address was resolved", + "offset": 0, + "size": 4 + } + } + } + }, + "ENABLE": { + "description": "Enable AAR", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable AAR", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 3 + } + } + } + } + } + } + } + }, + "NIRK": { + "description": "Number of IRKs", + "offset": 1284, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "NIRK": { + "description": "Number of Identity root keys available in the IRK data structure", + "offset": 0, + "size": 5 + } + } + } + }, + "IRKPTR": { + "description": "Pointer to IRK data structure", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IRKPTR": { + "description": "Pointer to the IRK data structure", + "offset": 0, + "size": 32 + } + } + } + }, + "ADDRPTR": { + "description": "Pointer to the resolvable address", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRPTR": { + "description": "Pointer to the resolvable address (6-bytes)", + "offset": 0, + "size": 32 + } + } + } + }, + "SCRATCHPTR": { + "description": "Pointer to data area used for temporary storage", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SCRATCHPTR": { + "description": "Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved.", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "WDT": { + "description": "Watchdog Timer", + "children": { + "registers": { + "TASKS_START": { + "description": "Start the watchdog", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_TIMEOUT": { + "description": "Watchdog timeout", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIMEOUT": { + "description": "Write '1' to Enable interrupt for TIMEOUT event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIMEOUT": { + "description": "Write '1' to Disable interrupt for TIMEOUT event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "RUNSTATUS": { + "description": "Run status", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RUNSTATUS": { + "description": "Indicates whether or not the watchdog is running", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotRunning": { + "description": "Watchdog not running", + "value": 0 + }, + "Running": { + "description": "Watchdog is running", + "value": 1 + } + } + } + } + } + } + } + }, + "REQSTATUS": { + "description": "Request status", + "offset": 1028, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RR0": { + "description": "Request status for RR[0] register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[0] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[0] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR1": { + "description": "Request status for RR[1] register", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[1] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[1] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR2": { + "description": "Request status for RR[2] register", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[2] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[2] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR3": { + "description": "Request status for RR[3] register", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[3] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[3] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR4": { + "description": "Request status for RR[4] register", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[4] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[4] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR5": { + "description": "Request status for RR[5] register", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[5] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[5] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR6": { + "description": "Request status for RR[6] register", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[6] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[6] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR7": { + "description": "Request status for RR[7] register", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[7] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[7] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + } + } + } + }, + "CRV": { + "description": "Counter reload value", + "offset": 1284, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRV": { + "description": "Counter reload value in number of cycles of the 32.768 kHz clock", + "offset": 0, + "size": 32 + } + } + } + }, + "RREN": { + "description": "Enable register for reload request registers", + "offset": 1288, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "RR0": { + "description": "Enable or disable RR[0] register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[0] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[0] register", + "value": 1 + } + } + } + } + }, + "RR1": { + "description": "Enable or disable RR[1] register", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[1] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[1] register", + "value": 1 + } + } + } + } + }, + "RR2": { + "description": "Enable or disable RR[2] register", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[2] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[2] register", + "value": 1 + } + } + } + } + }, + "RR3": { + "description": "Enable or disable RR[3] register", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[3] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[3] register", + "value": 1 + } + } + } + } + }, + "RR4": { + "description": "Enable or disable RR[4] register", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[4] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[4] register", + "value": 1 + } + } + } + } + }, + "RR5": { + "description": "Enable or disable RR[5] register", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[5] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[5] register", + "value": 1 + } + } + } + } + }, + "RR6": { + "description": "Enable or disable RR[6] register", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[6] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[6] register", + "value": 1 + } + } + } + } + }, + "RR7": { + "description": "Enable or disable RR[7] register", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[7] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[7] register", + "value": 1 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1292, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLEEP": { + "description": "Configure the watchdog to either be paused, or kept running, while the CPU is sleeping", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Pause": { + "description": "Pause watchdog while the CPU is sleeping", + "value": 0 + }, + "Run": { + "description": "Keep the watchdog running while the CPU is sleeping", + "value": 1 + } + } + } + } + }, + "HALT": { + "description": "Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Pause": { + "description": "Pause watchdog while the CPU is halted by the debugger", + "value": 0 + }, + "Run": { + "description": "Keep the watchdog running while the CPU is halted by the debugger", + "value": 1 + } + } + } + } + } + } + } + }, + "RR": { + "description": "Description collection[0]: Reload request 0", + "offset": 1536, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "RR": { + "description": "Reload request register", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Reload": { + "description": "Value to request a reload of the watchdog timer", + "value": 1850885685 + } + } + } + } + } + } + } + } + } + } + }, + "PWM0": { + "description": "Pulse Width Modulation Unit 0", + "children": { + "registers": { + "TASKS_STOP": { + "description": "Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SEQSTART": { + "description": "Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running.", + "offset": 8, + "size": 32, + "count": 2, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_NEXTSTEP": { + "description": "Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running.", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_STOPPED": { + "description": "Response to STOP task, emitted when PWM pulses are no longer generated", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_SEQSTARTED": { + "description": "Description collection[0]: First PWM period started on sequence 0", + "offset": 264, + "size": 32, + "count": 2, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_SEQEND": { + "description": "Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter", + "offset": 272, + "size": 32, + "count": 2, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_PWMPERIODEND": { + "description": "Emitted at the end of each PWM period", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_LOOPSDONE": { + "description": "Concatenated sequences have been played the amount of times defined in LOOP.CNT", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SEQEND0_STOP": { + "description": "Shortcut between SEQEND[0] event and STOP task", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "SEQEND1_STOP": { + "description": "Shortcut between SEQEND[1] event and STOP task", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LOOPSDONE_SEQSTART0": { + "description": "Shortcut between LOOPSDONE event and SEQSTART[0] task", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LOOPSDONE_SEQSTART1": { + "description": "Shortcut between LOOPSDONE event and SEQSTART[1] task", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LOOPSDONE_STOP": { + "description": "Shortcut between LOOPSDONE event and STOP task", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Enable or disable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SEQSTARTED0": { + "description": "Enable or disable interrupt for SEQSTARTED[0] event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SEQSTARTED1": { + "description": "Enable or disable interrupt for SEQSTARTED[1] event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SEQEND0": { + "description": "Enable or disable interrupt for SEQEND[0] event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SEQEND1": { + "description": "Enable or disable interrupt for SEQEND[1] event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "PWMPERIODEND": { + "description": "Enable or disable interrupt for PWMPERIODEND event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "LOOPSDONE": { + "description": "Enable or disable interrupt for LOOPSDONE event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to Enable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQSTARTED0": { + "description": "Write '1' to Enable interrupt for SEQSTARTED[0] event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQSTARTED1": { + "description": "Write '1' to Enable interrupt for SEQSTARTED[1] event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQEND0": { + "description": "Write '1' to Enable interrupt for SEQEND[0] event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQEND1": { + "description": "Write '1' to Enable interrupt for SEQEND[1] event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PWMPERIODEND": { + "description": "Write '1' to Enable interrupt for PWMPERIODEND event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LOOPSDONE": { + "description": "Write '1' to Enable interrupt for LOOPSDONE event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to Disable interrupt for STOPPED event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQSTARTED0": { + "description": "Write '1' to Disable interrupt for SEQSTARTED[0] event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQSTARTED1": { + "description": "Write '1' to Disable interrupt for SEQSTARTED[1] event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQEND0": { + "description": "Write '1' to Disable interrupt for SEQEND[0] event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQEND1": { + "description": "Write '1' to Disable interrupt for SEQEND[1] event", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PWMPERIODEND": { + "description": "Write '1' to Disable interrupt for PWMPERIODEND event", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LOOPSDONE": { + "description": "Write '1' to Disable interrupt for LOOPSDONE event", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "PWM module enable register", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable PWM module", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "MODE": { + "description": "Selects operating mode of the wave counter", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UPDOWN": { + "description": "Selects up or up and down as wave counter mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Up": { + "description": "Up counter - edge aligned PWM duty-cycle", + "value": 0 + }, + "UpAndDown": { + "description": "Up and down counter - center aligned PWM duty cycle", + "value": 1 + } + } + } + } + } + } + } + }, + "COUNTERTOP": { + "description": "Value up to which the pulse generator counter counts", + "offset": 1288, + "size": 32, + "reset_value": 1023, + "reset_mask": 4294967295, + "children": { + "fields": { + "COUNTERTOP": { + "description": "Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used.", + "offset": 0, + "size": 15 + } + } + } + }, + "PRESCALER": { + "description": "Configuration for PWM_CLK", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRESCALER": { + "description": "Pre-scaler of PWM_CLK", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "DIV_1": { + "description": "Divide by 1 (16MHz)", + "value": 0 + }, + "DIV_2": { + "description": "Divide by 2 ( 8MHz)", + "value": 1 + }, + "DIV_4": { + "description": "Divide by 4 ( 4MHz)", + "value": 2 + }, + "DIV_8": { + "description": "Divide by 8 ( 2MHz)", + "value": 3 + }, + "DIV_16": { + "description": "Divide by 16 ( 1MHz)", + "value": 4 + }, + "DIV_32": { + "description": "Divide by 32 ( 500kHz)", + "value": 5 + }, + "DIV_64": { + "description": "Divide by 64 ( 250kHz)", + "value": 6 + }, + "DIV_128": { + "description": "Divide by 128 ( 125kHz)", + "value": 7 + } + } + } + } + } + } + } + }, + "DECODER": { + "description": "Configuration of the decoder", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LOAD": { + "description": "How a sequence is read from RAM and spread to the compare register", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Common": { + "description": "1st half word (16-bit) used in all PWM channels 0..3", + "value": 0 + }, + "Grouped": { + "description": "1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3", + "value": 1 + }, + "Individual": { + "description": "1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3", + "value": 2 + }, + "WaveForm": { + "description": "1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP", + "value": 3 + } + } + } + } + }, + "MODE": { + "description": "Selects source for advancing the active sequence", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RefreshCount": { + "description": "SEQ[n].REFRESH is used to determine loading internal compare registers", + "value": 0 + }, + "NextStep": { + "description": "NEXTSTEP task causes a new value to be loaded to internal compare registers", + "value": 1 + } + } + } + } + } + } + } + }, + "LOOP": { + "description": "Amount of playback of a loop", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Amount of playback of pattern cycles", + "offset": 0, + "size": 16, + "enum": { + "size": 16, + "children": { + "enum_fields": { + "Disabled": { + "description": "Looping disabled (stop at the end of the sequence)", + "value": 0 + } + } + } + } + } + } + } + } + } + } + }, + "QDEC": { + "description": "Quadrature Decoder", + "children": { + "registers": { + "TASKS_START": { + "description": "Task starting the quadrature decoder", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Task stopping the quadrature decoder", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_READCLRACC": { + "description": "Read and clear ACC and ACCDBL", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_RDCLRACC": { + "description": "Read and clear ACC", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_RDCLRDBL": { + "description": "Read and clear ACCDBL", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_SAMPLERDY": { + "description": "Event being generated for every new sample value written to the SAMPLE register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_REPORTRDY": { + "description": "Non-null report ready", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_ACCOF": { + "description": "ACC or ACCDBL register overflow", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_DBLRDY": { + "description": "Double displacement(s) detected", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_STOPPED": { + "description": "QDEC has been stopped", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REPORTRDY_READCLRACC": { + "description": "Shortcut between REPORTRDY event and READCLRACC task", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "SAMPLERDY_STOP": { + "description": "Shortcut between SAMPLERDY event and STOP task", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "REPORTRDY_RDCLRACC": { + "description": "Shortcut between REPORTRDY event and RDCLRACC task", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "REPORTRDY_STOP": { + "description": "Shortcut between REPORTRDY event and STOP task", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DBLRDY_RDCLRDBL": { + "description": "Shortcut between DBLRDY event and RDCLRDBL task", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DBLRDY_STOP": { + "description": "Shortcut between DBLRDY event and STOP task", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "SAMPLERDY_READCLRACC": { + "description": "Shortcut between SAMPLERDY event and READCLRACC task", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SAMPLERDY": { + "description": "Write '1' to Enable interrupt for SAMPLERDY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REPORTRDY": { + "description": "Write '1' to Enable interrupt for REPORTRDY event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ACCOF": { + "description": "Write '1' to Enable interrupt for ACCOF event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DBLRDY": { + "description": "Write '1' to Enable interrupt for DBLRDY event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to Enable interrupt for STOPPED event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SAMPLERDY": { + "description": "Write '1' to Disable interrupt for SAMPLERDY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REPORTRDY": { + "description": "Write '1' to Disable interrupt for REPORTRDY event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ACCOF": { + "description": "Write '1' to Disable interrupt for ACCOF event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DBLRDY": { + "description": "Write '1' to Disable interrupt for DBLRDY event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to Disable interrupt for STOPPED event", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable the quadrature decoder", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable the quadrature decoder", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "LEDPOL": { + "description": "LED output pin polarity", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEDPOL": { + "description": "LED output pin polarity", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "ActiveLow": { + "description": "Led active on output pin low", + "value": 0 + }, + "ActiveHigh": { + "description": "Led active on output pin high", + "value": 1 + } + } + } + } + } + } + } + }, + "SAMPLEPER": { + "description": "Sample period", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SAMPLEPER": { + "description": "Sample period. The SAMPLE register will be updated for every new sample", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "128us": { + "description": "128 us", + "value": 0 + }, + "256us": { + "description": "256 us", + "value": 1 + }, + "512us": { + "description": "512 us", + "value": 2 + }, + "1024us": { + "description": "1024 us", + "value": 3 + }, + "2048us": { + "description": "2048 us", + "value": 4 + }, + "4096us": { + "description": "4096 us", + "value": 5 + }, + "8192us": { + "description": "8192 us", + "value": 6 + }, + "16384us": { + "description": "16384 us", + "value": 7 + }, + "32ms": { + "description": "32768 us", + "value": 8 + }, + "65ms": { + "description": "65536 us", + "value": 9 + }, + "131ms": { + "description": "131072 us", + "value": 10 + } + } + } + } + } + } + } + }, + "SAMPLE": { + "description": "Motion sample value", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SAMPLE": { + "description": "Last motion sample", + "offset": 0, + "size": 32 + } + } + } + }, + "REPORTPER": { + "description": "Number of samples to be taken before REPORTRDY and DBLRDY events can be generated", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REPORTPER": { + "description": "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "10Smpl": { + "description": "10 samples / report", + "value": 0 + }, + "40Smpl": { + "description": "40 samples / report", + "value": 1 + }, + "80Smpl": { + "description": "80 samples / report", + "value": 2 + }, + "120Smpl": { + "description": "120 samples / report", + "value": 3 + }, + "160Smpl": { + "description": "160 samples / report", + "value": 4 + }, + "200Smpl": { + "description": "200 samples / report", + "value": 5 + }, + "240Smpl": { + "description": "240 samples / report", + "value": 6 + }, + "280Smpl": { + "description": "280 samples / report", + "value": 7 + }, + "1Smpl": { + "description": "1 sample / report", + "value": 8 + } + } + } + } + } + } + } + }, + "ACC": { + "description": "Register accumulating the valid transitions", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACC": { + "description": "Register accumulating all valid samples (not double transition) read from the SAMPLE register", + "offset": 0, + "size": 32 + } + } + } + }, + "ACCREAD": { + "description": "Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACCREAD": { + "description": "Snapshot of the ACC register.", + "offset": 0, + "size": 32 + } + } + } + }, + "DBFEN": { + "description": "Enable input debounce filters", + "offset": 1320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBFEN": { + "description": "Enable input debounce filters", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Debounce input filters disabled", + "value": 0 + }, + "Enabled": { + "description": "Debounce input filters enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "LEDPRE": { + "description": "Time period the LED is switched ON prior to sampling", + "offset": 1344, + "size": 32, + "reset_value": 16, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEDPRE": { + "description": "Period in us the LED is switched on prior to sampling", + "offset": 0, + "size": 9 + } + } + } + }, + "ACCDBL": { + "description": "Register accumulating the number of detected double transitions", + "offset": 1348, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACCDBL": { + "description": "Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).", + "offset": 0, + "size": 4 + } + } + } + }, + "ACCDBLREAD": { + "description": "Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task", + "offset": 1352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACCDBLREAD": { + "description": "Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered.", + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "COMP": { + "description": "Comparator", + "children": { + "registers": { + "TASKS_START": { + "description": "Start comparator", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop comparator", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SAMPLE": { + "description": "Sample comparator value", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_READY": { + "description": "COMP is ready and output is valid", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_DOWN": { + "description": "Downward crossing", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_UP": { + "description": "Upward crossing", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_CROSS": { + "description": "Downward or upward crossing", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY_SAMPLE": { + "description": "Shortcut between READY event and SAMPLE task", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "READY_STOP": { + "description": "Shortcut between READY event and STOP task", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DOWN_STOP": { + "description": "Shortcut between DOWN event and STOP task", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "UP_STOP": { + "description": "Shortcut between UP event and STOP task", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "CROSS_STOP": { + "description": "Shortcut between CROSS event and STOP task", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Enable or disable interrupt for READY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "DOWN": { + "description": "Enable or disable interrupt for DOWN event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "UP": { + "description": "Enable or disable interrupt for UP event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CROSS": { + "description": "Enable or disable interrupt for CROSS event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to Enable interrupt for READY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DOWN": { + "description": "Write '1' to Enable interrupt for DOWN event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "UP": { + "description": "Write '1' to Enable interrupt for UP event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CROSS": { + "description": "Write '1' to Enable interrupt for CROSS event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to Disable interrupt for READY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DOWN": { + "description": "Write '1' to Disable interrupt for DOWN event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "UP": { + "description": "Write '1' to Disable interrupt for UP event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CROSS": { + "description": "Write '1' to Disable interrupt for CROSS event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "RESULT": { + "description": "Compare result", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RESULT": { + "description": "Result of last compare. Decision point SAMPLE task.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Below": { + "description": "Input voltage is below the threshold (VIN+ < VIN-)", + "value": 0 + }, + "Above": { + "description": "Input voltage is above the threshold (VIN+ > VIN-)", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "COMP enable", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable COMP", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 2 + } + } + } + } + } + } + } + }, + "PSEL": { + "description": "Pin select", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSEL": { + "description": "Analog pin select", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "AnalogInput0": { + "description": "AIN0 selected as analog input", + "value": 0 + }, + "AnalogInput1": { + "description": "AIN1 selected as analog input", + "value": 1 + }, + "AnalogInput2": { + "description": "AIN2 selected as analog input", + "value": 2 + }, + "AnalogInput3": { + "description": "AIN3 selected as analog input", + "value": 3 + }, + "AnalogInput4": { + "description": "AIN4 selected as analog input", + "value": 4 + }, + "AnalogInput5": { + "description": "AIN5 selected as analog input", + "value": 5 + }, + "AnalogInput6": { + "description": "AIN6 selected as analog input", + "value": 6 + }, + "AnalogInput7": { + "description": "AIN7 selected as analog input", + "value": 7 + } + } + } + } + } + } + } + }, + "REFSEL": { + "description": "Reference source select for single-ended mode", + "offset": 1288, + "size": 32, + "reset_value": 4, + "reset_mask": 4294967295, + "children": { + "fields": { + "REFSEL": { + "description": "Reference select", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "Int1V2": { + "description": "VREF = internal 1.2 V reference (VDD >= 1.7 V)", + "value": 0 + }, + "Int1V8": { + "description": "VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)", + "value": 1 + }, + "Int2V4": { + "description": "VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)", + "value": 2 + }, + "VDD": { + "description": "VREF = VDD", + "value": 4 + }, + "ARef": { + "description": "VREF = AREF (VDD >= VREF >= AREFMIN)", + "value": 7 + } + } + } + } + } + } + } + }, + "EXTREFSEL": { + "description": "External reference select", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTREFSEL": { + "description": "External analog reference select", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "AnalogReference0": { + "description": "Use AIN0 as external analog reference", + "value": 0 + }, + "AnalogReference1": { + "description": "Use AIN1 as external analog reference", + "value": 1 + }, + "AnalogReference2": { + "description": "Use AIN2 as external analog reference", + "value": 2 + }, + "AnalogReference3": { + "description": "Use AIN3 as external analog reference", + "value": 3 + }, + "AnalogReference4": { + "description": "Use AIN4 as external analog reference", + "value": 4 + }, + "AnalogReference5": { + "description": "Use AIN5 as external analog reference", + "value": 5 + }, + "AnalogReference6": { + "description": "Use AIN6 as external analog reference", + "value": 6 + }, + "AnalogReference7": { + "description": "Use AIN7 as external analog reference", + "value": 7 + } + } + } + } + } + } + } + }, + "TH": { + "description": "Threshold configuration for hysteresis unit", + "offset": 1328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "THDOWN": { + "description": "VDOWN = (THDOWN+1)/64*VREF", + "offset": 0, + "size": 6 + }, + "THUP": { + "description": "VUP = (THUP+1)/64*VREF", + "offset": 8, + "size": 6 + } + } + } + }, + "MODE": { + "description": "Mode configuration", + "offset": 1332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SP": { + "description": "Speed and power modes", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Low": { + "description": "Low-power mode", + "value": 0 + }, + "Normal": { + "description": "Normal mode", + "value": 1 + }, + "High": { + "description": "High-speed mode", + "value": 2 + } + } + } + } + }, + "MAIN": { + "description": "Main operation modes", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "SE": { + "description": "Single-ended mode", + "value": 0 + }, + "Diff": { + "description": "Differential mode", + "value": 1 + } + } + } + } + } + } + } + }, + "HYST": { + "description": "Comparator hysteresis enable", + "offset": 1336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HYST": { + "description": "Comparator hysteresis", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoHyst": { + "description": "Comparator hysteresis disabled", + "value": 0 + }, + "Hyst50mV": { + "description": "Comparator hysteresis enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ISOURCE": { + "description": "Current source select on analog input", + "offset": 1340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ISOURCE": { + "description": "Comparator hysteresis", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Off": { + "description": "Current source disabled", + "value": 0 + }, + "Ien2mA5": { + "description": "Current source enabled (+/- 2.5 uA)", + "value": 1 + }, + "Ien5mA": { + "description": "Current source enabled (+/- 5 uA)", + "value": 2 + }, + "Ien10mA": { + "description": "Current source enabled (+/- 10 uA)", + "value": 3 + } + } + } + } + } + } + } + } + } + } + }, + "LPCOMP": { + "description": "Low Power Comparator", + "children": { + "registers": { + "TASKS_START": { + "description": "Start comparator", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_STOP": { + "description": "Stop comparator", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "TASKS_SAMPLE": { + "description": "Sample comparator value", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only" + }, + "EVENTS_READY": { + "description": "LPCOMP is ready and output is valid", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_DOWN": { + "description": "Downward crossing", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_UP": { + "description": "Upward crossing", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "EVENTS_CROSS": { + "description": "Downward or upward crossing", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "SHORTS": { + "description": "Shortcut register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY_SAMPLE": { + "description": "Shortcut between READY event and SAMPLE task", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "READY_STOP": { + "description": "Shortcut between READY event and STOP task", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DOWN_STOP": { + "description": "Shortcut between DOWN event and STOP task", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "UP_STOP": { + "description": "Shortcut between UP event and STOP task", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "CROSS_STOP": { + "description": "Shortcut between CROSS event and STOP task", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to Enable interrupt for READY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DOWN": { + "description": "Write '1' to Enable interrupt for DOWN event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "UP": { + "description": "Write '1' to Enable interrupt for UP event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CROSS": { + "description": "Write '1' to Enable interrupt for CROSS event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to Disable interrupt for READY event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DOWN": { + "description": "Write '1' to Disable interrupt for DOWN event", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "UP": { + "description": "Write '1' to Disable interrupt for UP event", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CROSS": { + "description": "Write '1' to Disable interrupt for CROSS event", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "RESULT": { + "description": "Compare result", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RESULT": { + "description": "Result of last compare. Decision point SAMPLE task.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Below": { + "description": "Input voltage is below the reference threshold (VIN+ < VIN-).", + "value": 0 + }, + "Above": { + "description": "Input voltage is above the reference threshold (VIN+ > VIN-).", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable LPCOMP", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable LPCOMP", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "PSEL": { + "description": "Input pin select", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSEL": { + "description": "Analog pin select", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "AnalogInput0": { + "description": "AIN0 selected as analog input", + "value": 0 + }, + "AnalogInput1": { + "description": "AIN1 selected as analog input", + "value": 1 + }, + "AnalogInput2": { + "description": "AIN2 selected as analog input", + "value": 2 + }, + "AnalogInput3": { + "description": "AIN3 selected as analog input", + "value": 3 + }, + "AnalogInput4": { + "description": "AIN4 selected as analog input", + "value": 4 + }, + "AnalogInput5": { + "description": "AIN5 selected as analog input", + "value": 5 + }, + "AnalogInput6": { + "description": "AIN6 selected as analog input", + "value": 6 + }, + "AnalogInput7": { + "description": "AIN7 selected as analog input", + "value": 7 + } + } + } + } + } + } + } + }, + "REFSEL": { + "description": "Reference select", + "offset": 1288, + "size": 32, + "reset_value": 4, + "reset_mask": 4294967295, + "children": { + "fields": { + "REFSEL": { + "description": "Reference select", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Ref1_8Vdd": { + "description": "VDD * 1/8 selected as reference", + "value": 0 + }, + "Ref2_8Vdd": { + "description": "VDD * 2/8 selected as reference", + "value": 1 + }, + "Ref3_8Vdd": { + "description": "VDD * 3/8 selected as reference", + "value": 2 + }, + "Ref4_8Vdd": { + "description": "VDD * 4/8 selected as reference", + "value": 3 + }, + "Ref5_8Vdd": { + "description": "VDD * 5/8 selected as reference", + "value": 4 + }, + "Ref6_8Vdd": { + "description": "VDD * 6/8 selected as reference", + "value": 5 + }, + "Ref7_8Vdd": { + "description": "VDD * 7/8 selected as reference", + "value": 6 + }, + "ARef": { + "description": "External analog reference selected", + "value": 7 + }, + "Ref1_16Vdd": { + "description": "VDD * 1/16 selected as reference", + "value": 8 + }, + "Ref3_16Vdd": { + "description": "VDD * 3/16 selected as reference", + "value": 9 + }, + "Ref5_16Vdd": { + "description": "VDD * 5/16 selected as reference", + "value": 10 + }, + "Ref7_16Vdd": { + "description": "VDD * 7/16 selected as reference", + "value": 11 + }, + "Ref9_16Vdd": { + "description": "VDD * 9/16 selected as reference", + "value": 12 + }, + "Ref11_16Vdd": { + "description": "VDD * 11/16 selected as reference", + "value": 13 + }, + "Ref13_16Vdd": { + "description": "VDD * 13/16 selected as reference", + "value": 14 + }, + "Ref15_16Vdd": { + "description": "VDD * 15/16 selected as reference", + "value": 15 + } + } + } + } + } + } + } + }, + "EXTREFSEL": { + "description": "External reference select", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTREFSEL": { + "description": "External analog reference select", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "AnalogReference0": { + "description": "Use AIN0 as external analog reference", + "value": 0 + }, + "AnalogReference1": { + "description": "Use AIN1 as external analog reference", + "value": 1 + } + } + } + } + } + } + } + }, + "ANADETECT": { + "description": "Analog detect configuration", + "offset": 1312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ANADETECT": { + "description": "Analog detect configuration", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Cross": { + "description": "Generate ANADETECT on crossing, both upward crossing and downward crossing", + "value": 0 + }, + "Up": { + "description": "Generate ANADETECT on upward crossing only", + "value": 1 + }, + "Down": { + "description": "Generate ANADETECT on downward crossing only", + "value": 2 + } + } + } + } + } + } + } + }, + "HYST": { + "description": "Comparator hysteresis enable", + "offset": 1336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HYST": { + "description": "Comparator hysteresis enable", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoHyst": { + "description": "Comparator hysteresis disabled", + "value": 0 + }, + "Hyst50mV": { + "description": "Comparator hysteresis disabled (typ. 50 mV)", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "SWI0": { + "description": "Software interrupt 0", + "children": { + "registers": { + "UNUSED": { + "description": "Unused.", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only" + } + } + } + } + } + }, + "devices": { + "nrf52": { + "arch": "cortex_m4", + "description": "nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller ", + "properties": { + "cpu.nvic_prio_bits": "3", + "cpu.mpu": "1", + "cpu.fpu": "1", + "cpu.revision": "r0p1", + "cpu.vendor_systick_config": "0", + "license": "\nCopyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\\n\n\\n\nRedistribution and use in source and binary forms, with or without\\n\nmodification, are permitted provided that the following conditions are met:\\n\n\\n\n1. Redistributions of source code must retain the above copyright notice, this\\n\n list of conditions and the following disclaimer.\\n\n\\n\n2. Redistributions in binary form must reproduce the above copyright\\n\n notice, this list of conditions and the following disclaimer in the\\n\n documentation and/or other materials provided with the distribution.\\n\n\\n\n3. Neither the name of Nordic Semiconductor ASA nor the names of its\\n\n contributors may be used to endorse or promote products derived from this\\n\n software without specific prior written permission.\\n\n\\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\\n\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\\n\nIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\\n\nARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\\n\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\\n\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\\n\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\\n\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\\n\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\\n\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\\n\nPOSSIBILITY OF SUCH DAMAGE.\\n\n ", + "cpu.name": "CM4", + "cpu.endian": "little" + }, + "children": { + "interrupts": { + "MemManageFault": { + "index": -12 + }, + "BusFault": { + "index": -11 + }, + "UsageFault": { + "index": -10 + }, + "DebugMonitor": { + "index": -4 + }, + "NMI": { + "index": -14 + }, + "HardFault": { + "index": -13 + }, + "SVCall": { + "index": -5 + }, + "PendSV": { + "index": -2 + }, + "SysTick": { + "index": -1 + }, + "POWER_CLOCK": { + "index": 0 + }, + "RADIO": { + "index": 1 + }, + "UARTE0_UART0": { + "index": 2 + }, + "SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0": { + "index": 3 + }, + "SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1": { + "index": 4 + }, + "NFCT": { + "index": 5 + }, + "GPIOTE": { + "index": 6 + }, + "SAADC": { + "index": 7 + }, + "TIMER0": { + "index": 8 + }, + "TIMER1": { + "index": 9 + }, + "TIMER2": { + "index": 10 + }, + "RTC0": { + "index": 11 + }, + "TEMP": { + "index": 12 + }, + "RNG": { + "index": 13 + }, + "ECB": { + "index": 14 + }, + "CCM_AAR": { + "index": 15 + }, + "WDT": { + "index": 16 + }, + "RTC1": { + "index": 17 + }, + "QDEC": { + "index": 18 + }, + "COMP_LPCOMP": { + "index": 19 + }, + "SWI0_EGU0": { + "index": 20 + }, + "SWI1_EGU1": { + "index": 21 + }, + "SWI2_EGU2": { + "index": 22 + }, + "SWI3_EGU3": { + "index": 23 + }, + "SWI4_EGU4": { + "index": 24 + }, + "SWI5_EGU5": { + "index": 25 + }, + "TIMER3": { + "index": 26 + }, + "TIMER4": { + "index": 27 + }, + "PWM0": { + "index": 28 + }, + "PDM": { + "index": 29 + }, + "MWU": { + "index": 32 + }, + "PWM1": { + "index": 33 + }, + "PWM2": { + "index": 34 + }, + "SPIM2_SPIS2_SPI2": { + "index": 35 + }, + "RTC2": { + "index": 36 + }, + "I2S": { + "index": 37 + }, + "FPU": { + "index": 38 + } + }, + "peripheral_instances": { + "SysTick": { + "offset": 3758153744, + "type": "types.peripherals.SCS.children.register_groups.SysTick" + }, + "FICR": { + "description": "Factory Information Configuration Registers", + "offset": 268435456, + "type": "types.peripherals.FICR" + }, + "UICR": { + "description": "User Information Configuration Registers", + "offset": 268439552, + "type": "types.peripherals.UICR" + }, + "BPROT": { + "description": "Block Protect", + "offset": 1073741824, + "type": "types.peripherals.BPROT" + }, + "POWER": { + "description": "Power control", + "offset": 1073741824, + "type": "types.peripherals.POWER" + }, + "CLOCK": { + "description": "Clock control", + "offset": 1073741824, + "type": "types.peripherals.CLOCK" + }, + "RADIO": { + "description": "2.4 GHz Radio", + "offset": 1073745920, + "type": "types.peripherals.RADIO" + }, + "UARTE0": { + "description": "UART with EasyDMA", + "offset": 1073750016, + "type": "types.peripherals.UARTE0" + }, + "UART0": { + "description": "Universal Asynchronous Receiver/Transmitter", + "offset": 1073750016, + "type": "types.peripherals.UART0" + }, + "SPIM0": { + "description": "Serial Peripheral Interface Master with EasyDMA 0", + "offset": 1073754112, + "type": "types.peripherals.SPIM0" + }, + "SPIS0": { + "description": "SPI Slave 0", + "offset": 1073754112, + "type": "types.peripherals.SPIS0" + }, + "TWIM0": { + "description": "I2C compatible Two-Wire Master Interface with EasyDMA 0", + "offset": 1073754112, + "type": "types.peripherals.TWIM0" + }, + "TWIS0": { + "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 0", + "offset": 1073754112, + "type": "types.peripherals.TWIS0" + }, + "SPI0": { + "description": "Serial Peripheral Interface 0", + "offset": 1073754112, + "type": "types.peripherals.SPI0" + }, + "TWI0": { + "description": "I2C compatible Two-Wire Interface 0", + "offset": 1073754112, + "type": "types.peripherals.TWI0" + }, + "SPIM1": { + "description": "Serial Peripheral Interface Master with EasyDMA 1", + "offset": 1073758208, + "type": "types.peripherals.SPIM0" + }, + "SPIS1": { + "description": "SPI Slave 1", + "offset": 1073758208, + "type": "types.peripherals.SPIS0" + }, + "TWIM1": { + "description": "I2C compatible Two-Wire Master Interface with EasyDMA 1", + "offset": 1073758208, + "type": "types.peripherals.TWIM0" + }, + "TWIS1": { + "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 1", + "offset": 1073758208, + "type": "types.peripherals.TWIS0" + }, + "SPI1": { + "description": "Serial Peripheral Interface 1", + "offset": 1073758208, + "type": "types.peripherals.SPI0" + }, + "TWI1": { + "description": "I2C compatible Two-Wire Interface 1", + "offset": 1073758208, + "type": "types.peripherals.TWI0" + }, + "NFCT": { + "description": "NFC-A compatible radio", + "offset": 1073762304, + "type": "types.peripherals.NFCT" + }, + "GPIOTE": { + "description": "GPIO Tasks and Events", + "offset": 1073766400, + "type": "types.peripherals.GPIOTE" + }, + "SAADC": { + "description": "Analog to Digital Converter", + "offset": 1073770496, + "type": "types.peripherals.SAADC" + }, + "TIMER0": { + "description": "Timer/Counter 0", + "offset": 1073774592, + "type": "types.peripherals.TIMER0" + }, + "TIMER1": { + "description": "Timer/Counter 1", + "offset": 1073778688, + "type": "types.peripherals.TIMER0" + }, + "TIMER2": { + "description": "Timer/Counter 2", + "offset": 1073782784, + "type": "types.peripherals.TIMER0" + }, + "RTC0": { + "description": "Real time counter 0", + "offset": 1073786880, + "type": "types.peripherals.RTC0" + }, + "TEMP": { + "description": "Temperature Sensor", + "offset": 1073790976, + "type": "types.peripherals.TEMP" + }, + "RNG": { + "description": "Random Number Generator", + "offset": 1073795072, + "type": "types.peripherals.RNG" + }, + "ECB": { + "description": "AES ECB Mode Encryption", + "offset": 1073799168, + "type": "types.peripherals.ECB" + }, + "CCM": { + "description": "AES CCM Mode Encryption", + "offset": 1073803264, + "type": "types.peripherals.CCM" + }, + "AAR": { + "description": "Accelerated Address Resolver", + "offset": 1073803264, + "type": "types.peripherals.AAR" + }, + "WDT": { + "description": "Watchdog Timer", + "offset": 1073807360, + "type": "types.peripherals.WDT" + }, + "RTC1": { + "description": "Real time counter 1", + "offset": 1073811456, + "type": "types.peripherals.RTC0" + }, + "QDEC": { + "description": "Quadrature Decoder", + "offset": 1073815552, + "type": "types.peripherals.QDEC" + }, + "COMP": { + "description": "Comparator", + "offset": 1073819648, + "type": "types.peripherals.COMP" + }, + "LPCOMP": { + "description": "Low Power Comparator", + "offset": 1073819648, + "type": "types.peripherals.LPCOMP" + }, + "SWI0": { + "description": "Software interrupt 0", + "offset": 1073823744, + "type": "types.peripherals.SWI0" + }, + "EGU0": { + "description": "Event Generator Unit 0", + "offset": 1073823744, + "type": "types.peripherals.EGU0" + }, + "SWI1": { + "description": "Software interrupt 1", + "offset": 1073827840, + "type": "types.peripherals.SWI0" + }, + "EGU1": { + "description": "Event Generator Unit 1", + "offset": 1073827840, + "type": "types.peripherals.EGU0" + }, + "SWI2": { + "description": "Software interrupt 2", + "offset": 1073831936, + "type": "types.peripherals.SWI0" + }, + "EGU2": { + "description": "Event Generator Unit 2", + "offset": 1073831936, + "type": "types.peripherals.EGU0" + }, + "SWI3": { + "description": "Software interrupt 3", + "offset": 1073836032, + "type": "types.peripherals.SWI0" + }, + "EGU3": { + "description": "Event Generator Unit 3", + "offset": 1073836032, + "type": "types.peripherals.EGU0" + }, + "SWI4": { + "description": "Software interrupt 4", + "offset": 1073840128, + "type": "types.peripherals.SWI0" + }, + "EGU4": { + "description": "Event Generator Unit 4", + "offset": 1073840128, + "type": "types.peripherals.EGU0" + }, + "SWI5": { + "description": "Software interrupt 5", + "offset": 1073844224, + "type": "types.peripherals.SWI0" + }, + "EGU5": { + "description": "Event Generator Unit 5", + "offset": 1073844224, + "type": "types.peripherals.EGU0" + }, + "TIMER3": { + "description": "Timer/Counter 3", + "offset": 1073848320, + "type": "types.peripherals.TIMER0" + }, + "TIMER4": { + "description": "Timer/Counter 4", + "offset": 1073852416, + "type": "types.peripherals.TIMER0" + }, + "PWM0": { + "description": "Pulse Width Modulation Unit 0", + "offset": 1073856512, + "type": "types.peripherals.PWM0" + }, + "PDM": { + "description": "Pulse Density Modulation (Digital Microphone) Interface", + "offset": 1073860608, + "type": "types.peripherals.PDM" + }, + "NVMC": { + "description": "Non Volatile Memory Controller", + "offset": 1073864704, + "type": "types.peripherals.NVMC" + }, + "PPI": { + "description": "Programmable Peripheral Interconnect", + "offset": 1073868800, + "type": "types.peripherals.PPI" + }, + "MWU": { + "description": "Memory Watch Unit", + "offset": 1073872896, + "type": "types.peripherals.MWU" + }, + "PWM1": { + "description": "Pulse Width Modulation Unit 1", + "offset": 1073876992, + "type": "types.peripherals.PWM0" + }, + "PWM2": { + "description": "Pulse Width Modulation Unit 2", + "offset": 1073881088, + "type": "types.peripherals.PWM0" + }, + "SPIM2": { + "description": "Serial Peripheral Interface Master with EasyDMA 2", + "offset": 1073885184, + "type": "types.peripherals.SPIM0" + }, + "SPIS2": { + "description": "SPI Slave 2", + "offset": 1073885184, + "type": "types.peripherals.SPIS0" + }, + "SPI2": { + "description": "Serial Peripheral Interface 2", + "offset": 1073885184, + "type": "types.peripherals.SPI0" + }, + "RTC2": { + "description": "Real time counter 2", + "offset": 1073889280, + "type": "types.peripherals.RTC0" + }, + "I2S": { + "description": "Inter-IC Sound", + "offset": 1073893376, + "type": "types.peripherals.I2S" + }, + "FPU": { + "description": "FPU", + "offset": 1073897472, + "type": "types.peripherals.FPU" + }, + "P0": { + "description": "GPIO Port 1", + "offset": 1342177280, + "type": "types.peripherals.P0" + } + } + } + } + } +} \ No newline at end of file diff --git a/src/chips/nrf52.zig b/src/chips/nrf52.zig new file mode 100644 index 0000000..1e3de3b --- /dev/null +++ b/src/chips/nrf52.zig @@ -0,0 +1,16821 @@ +const micro = @import("microzig"); +const mmio = micro.mmio; + +pub const devices = struct { + /// nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + pub const nrf52 = struct { + pub const properties = struct { + pub const @"cpu.nvic_prio_bits" = "3"; + pub const @"cpu.mpu" = "1"; + pub const @"cpu.fpu" = "1"; + pub const @"cpu.revision" = "r0p1"; + pub const @"cpu.vendor_systick_config" = "0"; + pub const license = + \\ + \\Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n + \\\n + \\Redistribution and use in source and binary forms, with or without\n + \\modification, are permitted provided that the following conditions are met:\n + \\\n + \\1. Redistributions of source code must retain the above copyright notice, this\n + \\ list of conditions and the following disclaimer.\n + \\\n + \\2. Redistributions in binary form must reproduce the above copyright\n + \\ notice, this list of conditions and the following disclaimer in the\n + \\ documentation and/or other materials provided with the distribution.\n + \\\n + \\3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + \\ contributors may be used to endorse or promote products derived from this\n + \\ software without specific prior written permission.\n + \\\n + \\THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n + \\AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n + \\IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n + \\ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n + \\LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n + \\CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n + \\SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n + \\INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n + \\CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n + \\ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n + \\POSSIBILITY OF SUCH DAMAGE.\n + \\ + ; + pub const @"cpu.name" = "CM4"; + pub const @"cpu.endian" = "little"; + }; + + pub const VectorTable = extern struct { + const Handler = micro.interrupt.Handler; + const unhandled = micro.interrupt.unhandled; + + initial_stack_pointer: u32, + Reset: Handler = unhandled, + NMI: Handler = unhandled, + HardFault: Handler = unhandled, + MemManageFault: Handler = unhandled, + BusFault: Handler = unhandled, + UsageFault: Handler = unhandled, + reserved5: [4]u32 = undefined, + SVCall: Handler = unhandled, + DebugMonitor: Handler = unhandled, + reserved11: [1]u32 = undefined, + PendSV: Handler = unhandled, + SysTick: Handler = unhandled, + POWER_CLOCK: Handler = unhandled, + RADIO: Handler = unhandled, + UARTE0_UART0: Handler = unhandled, + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: Handler = unhandled, + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: Handler = unhandled, + NFCT: Handler = unhandled, + GPIOTE: Handler = unhandled, + SAADC: Handler = unhandled, + TIMER0: Handler = unhandled, + TIMER1: Handler = unhandled, + TIMER2: Handler = unhandled, + RTC0: Handler = unhandled, + TEMP: Handler = unhandled, + RNG: Handler = unhandled, + ECB: Handler = unhandled, + CCM_AAR: Handler = unhandled, + WDT: Handler = unhandled, + RTC1: Handler = unhandled, + QDEC: Handler = unhandled, + COMP_LPCOMP: Handler = unhandled, + SWI0_EGU0: Handler = unhandled, + SWI1_EGU1: Handler = unhandled, + SWI2_EGU2: Handler = unhandled, + SWI3_EGU3: Handler = unhandled, + SWI4_EGU4: Handler = unhandled, + SWI5_EGU5: Handler = unhandled, + TIMER3: Handler = unhandled, + TIMER4: Handler = unhandled, + PWM0: Handler = unhandled, + PDM: Handler = unhandled, + reserved44: [2]u32 = undefined, + MWU: Handler = unhandled, + PWM1: Handler = unhandled, + PWM2: Handler = unhandled, + SPIM2_SPIS2_SPI2: Handler = unhandled, + RTC2: Handler = unhandled, + I2S: Handler = unhandled, + FPU: Handler = unhandled, + }; + + pub const peripherals = struct { + /// Factory Information Configuration Registers + pub const FICR = @intToPtr(*volatile types.peripherals.FICR, 0x10000000); + /// User Information Configuration Registers + pub const UICR = @intToPtr(*volatile types.peripherals.UICR, 0x10001000); + /// Block Protect + pub const BPROT = @intToPtr(*volatile types.peripherals.BPROT, 0x40000000); + /// Power control + pub const POWER = @intToPtr(*volatile types.peripherals.POWER, 0x40000000); + /// Clock control + pub const CLOCK = @intToPtr(*volatile types.peripherals.CLOCK, 0x40000000); + /// 2.4 GHz Radio + pub const RADIO = @intToPtr(*volatile types.peripherals.RADIO, 0x40001000); + /// UART with EasyDMA + pub const UARTE0 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40002000); + /// Universal Asynchronous Receiver/Transmitter + pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x40002000); + /// Serial Peripheral Interface Master with EasyDMA 0 + pub const SPIM0 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40003000); + /// SPI Slave 0 + pub const SPIS0 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40003000); + /// I2C compatible Two-Wire Master Interface with EasyDMA 0 + pub const TWIM0 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40003000); + /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 + pub const TWIS0 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40003000); + /// Serial Peripheral Interface 0 + pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003000); + /// I2C compatible Two-Wire Interface 0 + pub const TWI0 = @intToPtr(*volatile types.peripherals.TWI0, 0x40003000); + /// Serial Peripheral Interface Master with EasyDMA 1 + pub const SPIM1 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40004000); + /// SPI Slave 1 + pub const SPIS1 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40004000); + /// I2C compatible Two-Wire Master Interface with EasyDMA 1 + pub const TWIM1 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40004000); + /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 + pub const TWIS1 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40004000); + /// Serial Peripheral Interface 1 + pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40004000); + /// I2C compatible Two-Wire Interface 1 + pub const TWI1 = @intToPtr(*volatile types.peripherals.TWI0, 0x40004000); + /// NFC-A compatible radio + pub const NFCT = @intToPtr(*volatile types.peripherals.NFCT, 0x40005000); + /// GPIO Tasks and Events + pub const GPIOTE = @intToPtr(*volatile types.peripherals.GPIOTE, 0x40006000); + /// Analog to Digital Converter + pub const SAADC = @intToPtr(*volatile types.peripherals.SAADC, 0x40007000); + /// Timer/Counter 0 + pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40008000); + /// Timer/Counter 1 + pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40009000); + /// Timer/Counter 2 + pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4000a000); + /// Real time counter 0 + pub const RTC0 = @intToPtr(*volatile types.peripherals.RTC0, 0x4000b000); + /// Temperature Sensor + pub const TEMP = @intToPtr(*volatile types.peripherals.TEMP, 0x4000c000); + /// Random Number Generator + pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x4000d000); + /// AES ECB Mode Encryption + pub const ECB = @intToPtr(*volatile types.peripherals.ECB, 0x4000e000); + /// AES CCM Mode Encryption + pub const CCM = @intToPtr(*volatile types.peripherals.CCM, 0x4000f000); + /// Accelerated Address Resolver + pub const AAR = @intToPtr(*volatile types.peripherals.AAR, 0x4000f000); + /// Watchdog Timer + pub const WDT = @intToPtr(*volatile types.peripherals.WDT, 0x40010000); + /// Real time counter 1 + pub const RTC1 = @intToPtr(*volatile types.peripherals.RTC0, 0x40011000); + /// Quadrature Decoder + pub const QDEC = @intToPtr(*volatile types.peripherals.QDEC, 0x40012000); + /// Comparator + pub const COMP = @intToPtr(*volatile types.peripherals.COMP, 0x40013000); + /// Low Power Comparator + pub const LPCOMP = @intToPtr(*volatile types.peripherals.LPCOMP, 0x40013000); + /// Software interrupt 0 + pub const SWI0 = @intToPtr(*volatile types.peripherals.SWI0, 0x40014000); + /// Event Generator Unit 0 + pub const EGU0 = @intToPtr(*volatile types.peripherals.EGU0, 0x40014000); + /// Software interrupt 1 + pub const SWI1 = @intToPtr(*volatile types.peripherals.SWI0, 0x40015000); + /// Event Generator Unit 1 + pub const EGU1 = @intToPtr(*volatile types.peripherals.EGU0, 0x40015000); + /// Software interrupt 2 + pub const SWI2 = @intToPtr(*volatile types.peripherals.SWI0, 0x40016000); + /// Event Generator Unit 2 + pub const EGU2 = @intToPtr(*volatile types.peripherals.EGU0, 0x40016000); + /// Software interrupt 3 + pub const SWI3 = @intToPtr(*volatile types.peripherals.SWI0, 0x40017000); + /// Event Generator Unit 3 + pub const EGU3 = @intToPtr(*volatile types.peripherals.EGU0, 0x40017000); + /// Software interrupt 4 + pub const SWI4 = @intToPtr(*volatile types.peripherals.SWI0, 0x40018000); + /// Event Generator Unit 4 + pub const EGU4 = @intToPtr(*volatile types.peripherals.EGU0, 0x40018000); + /// Software interrupt 5 + pub const SWI5 = @intToPtr(*volatile types.peripherals.SWI0, 0x40019000); + /// Event Generator Unit 5 + pub const EGU5 = @intToPtr(*volatile types.peripherals.EGU0, 0x40019000); + /// Timer/Counter 3 + pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001a000); + /// Timer/Counter 4 + pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001b000); + /// Pulse Width Modulation Unit 0 + pub const PWM0 = @intToPtr(*volatile types.peripherals.PWM0, 0x4001c000); + /// Pulse Density Modulation (Digital Microphone) Interface + pub const PDM = @intToPtr(*volatile types.peripherals.PDM, 0x4001d000); + /// Non Volatile Memory Controller + pub const NVMC = @intToPtr(*volatile types.peripherals.NVMC, 0x4001e000); + /// Programmable Peripheral Interconnect + pub const PPI = @intToPtr(*volatile types.peripherals.PPI, 0x4001f000); + /// Memory Watch Unit + pub const MWU = @intToPtr(*volatile types.peripherals.MWU, 0x40020000); + /// Pulse Width Modulation Unit 1 + pub const PWM1 = @intToPtr(*volatile types.peripherals.PWM0, 0x40021000); + /// Pulse Width Modulation Unit 2 + pub const PWM2 = @intToPtr(*volatile types.peripherals.PWM0, 0x40022000); + /// Serial Peripheral Interface Master with EasyDMA 2 + pub const SPIM2 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40023000); + /// SPI Slave 2 + pub const SPIS2 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40023000); + /// Serial Peripheral Interface 2 + pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40023000); + /// Real time counter 2 + pub const RTC2 = @intToPtr(*volatile types.peripherals.RTC0, 0x40024000); + /// Inter-IC Sound + pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x40025000); + /// FPU + pub const FPU = @intToPtr(*volatile types.peripherals.FPU, 0x40026000); + /// GPIO Port 1 + pub const P0 = @intToPtr(*volatile types.peripherals.P0, 0x50000000); + /// System Tick Timer + pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010); + }; + }; +}; + +pub const types = struct { + pub const peripherals = struct { + /// System Control Space + pub const SCS = struct { + /// System Tick Timer + pub const SysTick = extern struct { + /// SysTick Control and Status Register + CTRL: mmio.Mmio(packed struct(u32) { + ENABLE: u1, + TICKINT: u1, + CLKSOURCE: u1, + reserved16: u13, + COUNTFLAG: u1, + padding: u15, + }), + /// SysTick Reload Value Register + LOAD: mmio.Mmio(packed struct(u32) { + RELOAD: u24, + padding: u8, + }), + /// SysTick Current Value Register + VAL: mmio.Mmio(packed struct(u32) { + CURRENT: u24, + padding: u8, + }), + /// SysTick Calibration Register + CALIB: mmio.Mmio(packed struct(u32) { + TENMS: u24, + reserved30: u6, + SKEW: u1, + NOREF: u1, + }), + }; + }; + + /// Factory Information Configuration Registers + pub const FICR = extern struct { + reserved16: [16]u8, + /// Code memory page size + CODEPAGESIZE: mmio.Mmio(packed struct(u32) { + /// Code memory page size + CODEPAGESIZE: u32, + }), + /// Code memory size + CODESIZE: mmio.Mmio(packed struct(u32) { + /// Code memory size in number of pages + CODESIZE: u32, + }), + reserved96: [72]u8, + /// Description collection[0]: Device identifier + DEVICEID: [2]mmio.Mmio(packed struct(u32) { + /// 64 bit unique device identifier + DEVICEID: u32, + }), + reserved128: [24]u8, + /// Description collection[0]: Encryption Root, word 0 + ER: [4]mmio.Mmio(packed struct(u32) { + /// Encryption Root, word n + ER: u32, + }), + /// Description collection[0]: Identity Root, word 0 + IR: [4]mmio.Mmio(packed struct(u32) { + /// Identity Root, word n + IR: u32, + }), + /// Device address type + DEVICEADDRTYPE: mmio.Mmio(packed struct(u32) { + /// Device address type + DEVICEADDRTYPE: packed union { + raw: u1, + value: enum(u1) { + /// Public address + Public = 0x0, + /// Random address + Random = 0x1, + }, + }, + padding: u31, + }), + /// Description collection[0]: Device address 0 + DEVICEADDR: [2]mmio.Mmio(packed struct(u32) { + /// 48 bit device address + DEVICEADDR: u32, + }), + }; + + /// User Information Configuration Registers + pub const UICR = extern struct { + /// Unspecified + UNUSED0: u32, + /// Unspecified + UNUSED1: u32, + /// Unspecified + UNUSED2: u32, + reserved16: [4]u8, + /// Unspecified + UNUSED3: u32, + /// Description collection[0]: Reserved for Nordic firmware design + NRFFW: [15]mmio.Mmio(packed struct(u32) { + /// Reserved for Nordic firmware design + NRFFW: u32, + }), + /// Description collection[0]: Reserved for Nordic hardware design + NRFHW: [12]mmio.Mmio(packed struct(u32) { + /// Reserved for Nordic hardware design + NRFHW: u32, + }), + /// Description collection[0]: Reserved for customer + CUSTOMER: [32]mmio.Mmio(packed struct(u32) { + /// Reserved for customer + CUSTOMER: u32, + }), + reserved512: [256]u8, + /// Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) + PSELRESET: [2]mmio.Mmio(packed struct(u32) { + /// GPIO number P0.n onto which Reset is exposed + PIN: u6, + reserved31: u25, + /// Connection + CONNECT: packed union { + raw: u1, + value: enum(u1) { + /// Disconnect + Disconnected = 0x1, + /// Connect + Connected = 0x0, + }, + }, + }), + /// Access Port protection + APPROTECT: mmio.Mmio(packed struct(u32) { + /// Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. + PALL: packed union { + raw: u8, + value: enum(u8) { + /// Disable + Disabled = 0xff, + /// Enable + Enabled = 0x0, + _, + }, + }, + padding: u24, + }), + /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + NFCPINS: mmio.Mmio(packed struct(u32) { + /// Setting of pins dedicated to NFC functionality + PROTECT: packed union { + raw: u1, + value: enum(u1) { + /// Operation as GPIO pins. Same protection as normal GPIO pins + Disabled = 0x0, + /// Operation as NFC antenna pins. Configures the protection for NFC operation + NFC = 0x1, + }, + }, + padding: u31, + }), + }; + + /// Block Protect + pub const BPROT = extern struct { + reserved1536: [1536]u8, + /// Block protect configuration register 0 + CONFIG0: mmio.Mmio(packed struct(u32) { + /// Enable protection for region 0. Write '0' has no effect. + REGION0: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 1. Write '0' has no effect. + REGION1: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 2. Write '0' has no effect. + REGION2: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 3. Write '0' has no effect. + REGION3: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 4. Write '0' has no effect. + REGION4: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 5. Write '0' has no effect. + REGION5: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 6. Write '0' has no effect. + REGION6: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 7. Write '0' has no effect. + REGION7: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 8. Write '0' has no effect. + REGION8: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 9. Write '0' has no effect. + REGION9: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 10. Write '0' has no effect. + REGION10: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 11. Write '0' has no effect. + REGION11: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 12. Write '0' has no effect. + REGION12: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 13. Write '0' has no effect. + REGION13: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 14. Write '0' has no effect. + REGION14: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 15. Write '0' has no effect. + REGION15: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 16. Write '0' has no effect. + REGION16: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 17. Write '0' has no effect. + REGION17: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 18. Write '0' has no effect. + REGION18: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 19. Write '0' has no effect. + REGION19: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 20. Write '0' has no effect. + REGION20: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 21. Write '0' has no effect. + REGION21: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 22. Write '0' has no effect. + REGION22: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 23. Write '0' has no effect. + REGION23: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 24. Write '0' has no effect. + REGION24: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 25. Write '0' has no effect. + REGION25: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 26. Write '0' has no effect. + REGION26: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 27. Write '0' has no effect. + REGION27: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 28. Write '0' has no effect. + REGION28: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 29. Write '0' has no effect. + REGION29: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 30. Write '0' has no effect. + REGION30: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + /// Enable protection for region 31. Write '0' has no effect. + REGION31: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enable + Enabled = 0x1, + }, + }, + }), + /// Block protect configuration register 1 + CONFIG1: mmio.Mmio(packed struct(u32) { + /// Enable protection for region 32. Write '0' has no effect. + REGION32: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 33. Write '0' has no effect. + REGION33: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 34. Write '0' has no effect. + REGION34: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 35. Write '0' has no effect. + REGION35: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 36. Write '0' has no effect. + REGION36: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 37. Write '0' has no effect. + REGION37: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 38. Write '0' has no effect. + REGION38: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 39. Write '0' has no effect. + REGION39: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 40. Write '0' has no effect. + REGION40: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 41. Write '0' has no effect. + REGION41: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 42. Write '0' has no effect. + REGION42: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 43. Write '0' has no effect. + REGION43: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 44. Write '0' has no effect. + REGION44: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 45. Write '0' has no effect. + REGION45: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 46. Write '0' has no effect. + REGION46: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 47. Write '0' has no effect. + REGION47: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 48. Write '0' has no effect. + REGION48: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 49. Write '0' has no effect. + REGION49: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 50. Write '0' has no effect. + REGION50: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 51. Write '0' has no effect. + REGION51: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 52. Write '0' has no effect. + REGION52: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 53. Write '0' has no effect. + REGION53: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 54. Write '0' has no effect. + REGION54: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 55. Write '0' has no effect. + REGION55: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 56. Write '0' has no effect. + REGION56: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 57. Write '0' has no effect. + REGION57: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 58. Write '0' has no effect. + REGION58: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 59. Write '0' has no effect. + REGION59: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 60. Write '0' has no effect. + REGION60: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 61. Write '0' has no effect. + REGION61: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 62. Write '0' has no effect. + REGION62: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 63. Write '0' has no effect. + REGION63: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + }), + /// Disable protection mechanism in debug interface mode + DISABLEINDEBUG: mmio.Mmio(packed struct(u32) { + /// Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. + DISABLEINDEBUG: packed union { + raw: u1, + value: enum(u1) { + /// Disable in debug + Disabled = 0x1, + /// Enable in debug + Enabled = 0x0, + }, + }, + padding: u31, + }), + /// Unspecified + UNUSED0: u32, + /// Block protect configuration register 2 + CONFIG2: mmio.Mmio(packed struct(u32) { + /// Enable protection for region 64. Write '0' has no effect. + REGION64: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 65. Write '0' has no effect. + REGION65: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 66. Write '0' has no effect. + REGION66: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 67. Write '0' has no effect. + REGION67: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 68. Write '0' has no effect. + REGION68: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 69. Write '0' has no effect. + REGION69: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 70. Write '0' has no effect. + REGION70: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 71. Write '0' has no effect. + REGION71: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 72. Write '0' has no effect. + REGION72: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 73. Write '0' has no effect. + REGION73: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 74. Write '0' has no effect. + REGION74: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 75. Write '0' has no effect. + REGION75: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 76. Write '0' has no effect. + REGION76: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 77. Write '0' has no effect. + REGION77: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 78. Write '0' has no effect. + REGION78: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 79. Write '0' has no effect. + REGION79: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 80. Write '0' has no effect. + REGION80: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 81. Write '0' has no effect. + REGION81: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 82. Write '0' has no effect. + REGION82: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 83. Write '0' has no effect. + REGION83: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 84. Write '0' has no effect. + REGION84: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 85. Write '0' has no effect. + REGION85: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 86. Write '0' has no effect. + REGION86: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 87. Write '0' has no effect. + REGION87: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 88. Write '0' has no effect. + REGION88: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 89. Write '0' has no effect. + REGION89: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 90. Write '0' has no effect. + REGION90: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 91. Write '0' has no effect. + REGION91: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 92. Write '0' has no effect. + REGION92: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 93. Write '0' has no effect. + REGION93: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 94. Write '0' has no effect. + REGION94: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 95. Write '0' has no effect. + REGION95: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + }), + /// Block protect configuration register 3 + CONFIG3: mmio.Mmio(packed struct(u32) { + /// Enable protection for region 96. Write '0' has no effect. + REGION96: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 97. Write '0' has no effect. + REGION97: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 98. Write '0' has no effect. + REGION98: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 99. Write '0' has no effect. + REGION99: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 100. Write '0' has no effect. + REGION100: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 101. Write '0' has no effect. + REGION101: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 102. Write '0' has no effect. + REGION102: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 103. Write '0' has no effect. + REGION103: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 104. Write '0' has no effect. + REGION104: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 105. Write '0' has no effect. + REGION105: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 106. Write '0' has no effect. + REGION106: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 107. Write '0' has no effect. + REGION107: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 108. Write '0' has no effect. + REGION108: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 109. Write '0' has no effect. + REGION109: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 110. Write '0' has no effect. + REGION110: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 111. Write '0' has no effect. + REGION111: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 112. Write '0' has no effect. + REGION112: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 113. Write '0' has no effect. + REGION113: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 114. Write '0' has no effect. + REGION114: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 115. Write '0' has no effect. + REGION115: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 116. Write '0' has no effect. + REGION116: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 117. Write '0' has no effect. + REGION117: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 118. Write '0' has no effect. + REGION118: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 119. Write '0' has no effect. + REGION119: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 120. Write '0' has no effect. + REGION120: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 121. Write '0' has no effect. + REGION121: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 122. Write '0' has no effect. + REGION122: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 123. Write '0' has no effect. + REGION123: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 124. Write '0' has no effect. + REGION124: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 125. Write '0' has no effect. + REGION125: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 126. Write '0' has no effect. + REGION126: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + /// Enable protection for region 127. Write '0' has no effect. + REGION127: packed union { + raw: u1, + value: enum(u1) { + /// Protection disabled + Disabled = 0x0, + /// Protection enabled + Enabled = 0x1, + }, + }, + }), + }; + + /// Power control + pub const POWER = extern struct { + reserved120: [120]u8, + /// Enable constant latency mode + TASKS_CONSTLAT: u32, + /// Enable low power mode (variable latency) + TASKS_LOWPWR: u32, + reserved264: [136]u8, + /// Power failure warning + EVENTS_POFWARN: u32, + reserved276: [8]u8, + /// CPU entered WFI/WFE sleep + EVENTS_SLEEPENTER: u32, + /// CPU exited WFI/WFE sleep + EVENTS_SLEEPEXIT: u32, + reserved772: [488]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Write '1' to Enable interrupt for POFWARN event + POFWARN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved5: u2, + /// Write '1' to Enable interrupt for SLEEPENTER event + SLEEPENTER: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for SLEEPEXIT event + SLEEPEXIT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u25, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Write '1' to Disable interrupt for POFWARN event + POFWARN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved5: u2, + /// Write '1' to Disable interrupt for SLEEPENTER event + SLEEPENTER: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for SLEEPEXIT event + SLEEPEXIT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u25, + }), + reserved1024: [244]u8, + /// Reset reason + RESETREAS: mmio.Mmio(packed struct(u32) { + /// Reset from pin-reset detected + RESETPIN: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset from watchdog detected + DOG: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset from soft reset detected + SREQ: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset from CPU lock-up detected + LOCKUP: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + reserved16: u12, + /// Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO + OFF: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP + LPCOMP: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode + DIF: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset due to wake up from System OFF mode by NFC field detect + NFC: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + padding: u12, + }), + reserved1064: [36]u8, + /// Deprecated register - RAM status register + RAMSTATUS: mmio.Mmio(packed struct(u32) { + /// RAM block 0 is on or off/powering up + RAMBLOCK0: packed union { + raw: u1, + value: enum(u1) { + /// Off + Off = 0x0, + /// On + On = 0x1, + }, + }, + /// RAM block 1 is on or off/powering up + RAMBLOCK1: packed union { + raw: u1, + value: enum(u1) { + /// Off + Off = 0x0, + /// On + On = 0x1, + }, + }, + /// RAM block 2 is on or off/powering up + RAMBLOCK2: packed union { + raw: u1, + value: enum(u1) { + /// Off + Off = 0x0, + /// On + On = 0x1, + }, + }, + /// RAM block 3 is on or off/powering up + RAMBLOCK3: packed union { + raw: u1, + value: enum(u1) { + /// Off + Off = 0x0, + /// On + On = 0x1, + }, + }, + padding: u28, + }), + reserved1280: [212]u8, + /// System OFF register + SYSTEMOFF: mmio.Mmio(packed struct(u32) { + /// Enable System OFF mode + SYSTEMOFF: packed union { + raw: u1, + value: enum(u1) { + /// Enable System OFF mode + Enter = 0x1, + _, + }, + }, + padding: u31, + }), + reserved1296: [12]u8, + /// Power failure comparator configuration + POFCON: mmio.Mmio(packed struct(u32) { + /// Enable or disable power failure comparator + POF: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Power failure comparator threshold setting + THRESHOLD: packed union { + raw: u4, + value: enum(u4) { + /// Set threshold to 1.7 V + V17 = 0x4, + /// Set threshold to 1.8 V + V18 = 0x5, + /// Set threshold to 1.9 V + V19 = 0x6, + /// Set threshold to 2.0 V + V20 = 0x7, + /// Set threshold to 2.1 V + V21 = 0x8, + /// Set threshold to 2.2 V + V22 = 0x9, + /// Set threshold to 2.3 V + V23 = 0xa, + /// Set threshold to 2.4 V + V24 = 0xb, + /// Set threshold to 2.5 V + V25 = 0xc, + /// Set threshold to 2.6 V + V26 = 0xd, + /// Set threshold to 2.7 V + V27 = 0xe, + /// Set threshold to 2.8 V + V28 = 0xf, + _, + }, + }, + padding: u27, + }), + reserved1308: [8]u8, + /// General purpose retention register + GPREGRET: mmio.Mmio(packed struct(u32) { + /// General purpose retention register + GPREGRET: u8, + padding: u24, + }), + /// General purpose retention register + GPREGRET2: mmio.Mmio(packed struct(u32) { + /// General purpose retention register + GPREGRET: u8, + padding: u24, + }), + /// Deprecated register - RAM on/off register (this register is retained) + RAMON: mmio.Mmio(packed struct(u32) { + /// Keep RAM block 0 on or off in system ON Mode + ONRAM0: packed union { + raw: u1, + value: enum(u1) { + /// Off + RAM0Off = 0x0, + /// On + RAM0On = 0x1, + }, + }, + /// Keep RAM block 1 on or off in system ON Mode + ONRAM1: packed union { + raw: u1, + value: enum(u1) { + /// Off + RAM1Off = 0x0, + /// On + RAM1On = 0x1, + }, + }, + reserved16: u14, + /// Keep retention on RAM block 0 when RAM block is switched off + OFFRAM0: packed union { + raw: u1, + value: enum(u1) { + /// Off + RAM0Off = 0x0, + /// On + RAM0On = 0x1, + }, + }, + /// Keep retention on RAM block 1 when RAM block is switched off + OFFRAM1: packed union { + raw: u1, + value: enum(u1) { + /// Off + RAM1Off = 0x0, + /// On + RAM1On = 0x1, + }, + }, + padding: u14, + }), + reserved1364: [44]u8, + /// Deprecated register - RAM on/off register (this register is retained) + RAMONB: mmio.Mmio(packed struct(u32) { + /// Keep RAM block 2 on or off in system ON Mode + ONRAM2: packed union { + raw: u1, + value: enum(u1) { + /// Off + RAM2Off = 0x0, + /// On + RAM2On = 0x1, + }, + }, + /// Keep RAM block 3 on or off in system ON Mode + ONRAM3: packed union { + raw: u1, + value: enum(u1) { + /// Off + RAM3Off = 0x0, + /// On + RAM3On = 0x1, + }, + }, + reserved16: u14, + /// Keep retention on RAM block 2 when RAM block is switched off + OFFRAM2: packed union { + raw: u1, + value: enum(u1) { + /// Off + RAM2Off = 0x0, + /// On + RAM2On = 0x1, + }, + }, + /// Keep retention on RAM block 3 when RAM block is switched off + OFFRAM3: packed union { + raw: u1, + value: enum(u1) { + /// Off + RAM3Off = 0x0, + /// On + RAM3On = 0x1, + }, + }, + padding: u14, + }), + reserved1400: [32]u8, + /// DC/DC enable register + DCDCEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable DC/DC converter + DCDCEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + }; + + /// Clock control + pub const CLOCK = extern struct { + /// Start HFCLK crystal oscillator + TASKS_HFCLKSTART: u32, + /// Stop HFCLK crystal oscillator + TASKS_HFCLKSTOP: u32, + /// Start LFCLK source + TASKS_LFCLKSTART: u32, + /// Stop LFCLK source + TASKS_LFCLKSTOP: u32, + /// Start calibration of LFRC oscillator + TASKS_CAL: u32, + /// Start calibration timer + TASKS_CTSTART: u32, + /// Stop calibration timer + TASKS_CTSTOP: u32, + reserved256: [228]u8, + /// HFCLK oscillator started + EVENTS_HFCLKSTARTED: u32, + /// LFCLK started + EVENTS_LFCLKSTARTED: u32, + reserved268: [4]u8, + /// Calibration of LFCLK RC oscillator complete event + EVENTS_DONE: u32, + /// Calibration timer timeout + EVENTS_CTTO: u32, + reserved772: [496]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for HFCLKSTARTED event + HFCLKSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for LFCLKSTARTED event + LFCLKSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved3: u1, + /// Write '1' to Enable interrupt for DONE event + DONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CTTO event + CTTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u27, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for HFCLKSTARTED event + HFCLKSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for LFCLKSTARTED event + LFCLKSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved3: u1, + /// Write '1' to Disable interrupt for DONE event + DONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CTTO event + CTTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved1032: [252]u8, + /// Status indicating that HFCLKSTART task has been triggered + HFCLKRUN: mmio.Mmio(packed struct(u32) { + /// HFCLKSTART task triggered or not + STATUS: packed union { + raw: u1, + value: enum(u1) { + /// Task not triggered + NotTriggered = 0x0, + /// Task triggered + Triggered = 0x1, + }, + }, + padding: u31, + }), + /// HFCLK status + HFCLKSTAT: mmio.Mmio(packed struct(u32) { + /// Source of HFCLK + SRC: packed union { + raw: u1, + value: enum(u1) { + /// 64 MHz internal oscillator (HFINT) + RC = 0x0, + /// 64 MHz crystal oscillator (HFXO) + Xtal = 0x1, + }, + }, + reserved16: u15, + /// HFCLK state + STATE: packed union { + raw: u1, + value: enum(u1) { + /// HFCLK not running + NotRunning = 0x0, + /// HFCLK running + Running = 0x1, + }, + }, + padding: u15, + }), + reserved1044: [4]u8, + /// Status indicating that LFCLKSTART task has been triggered + LFCLKRUN: mmio.Mmio(packed struct(u32) { + /// LFCLKSTART task triggered or not + STATUS: packed union { + raw: u1, + value: enum(u1) { + /// Task not triggered + NotTriggered = 0x0, + /// Task triggered + Triggered = 0x1, + }, + }, + padding: u31, + }), + /// LFCLK status + LFCLKSTAT: mmio.Mmio(packed struct(u32) { + /// Source of LFCLK + SRC: packed union { + raw: u2, + value: enum(u2) { + /// 32.768 kHz RC oscillator + RC = 0x0, + /// 32.768 kHz crystal oscillator + Xtal = 0x1, + /// 32.768 kHz synthesized from HFCLK + Synth = 0x2, + _, + }, + }, + reserved16: u14, + /// LFCLK state + STATE: packed union { + raw: u1, + value: enum(u1) { + /// LFCLK not running + NotRunning = 0x0, + /// LFCLK running + Running = 0x1, + }, + }, + padding: u15, + }), + /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + LFCLKSRCCOPY: mmio.Mmio(packed struct(u32) { + /// Clock source + SRC: packed union { + raw: u2, + value: enum(u2) { + /// 32.768 kHz RC oscillator + RC = 0x0, + /// 32.768 kHz crystal oscillator + Xtal = 0x1, + /// 32.768 kHz synthesized from HFCLK + Synth = 0x2, + _, + }, + }, + padding: u30, + }), + reserved1304: [248]u8, + /// Clock source for the LFCLK + LFCLKSRC: mmio.Mmio(packed struct(u32) { + /// Clock source + SRC: packed union { + raw: u2, + value: enum(u2) { + /// 32.768 kHz RC oscillator + RC = 0x0, + /// 32.768 kHz crystal oscillator + Xtal = 0x1, + /// 32.768 kHz synthesized from HFCLK + Synth = 0x2, + _, + }, + }, + reserved16: u14, + /// Enable or disable bypass of LFCLK crystal oscillator with external clock source + BYPASS: packed union { + raw: u1, + value: enum(u1) { + /// Disable (use with Xtal or low-swing external source) + Disabled = 0x0, + /// Enable (use with rail-to-rail external source) + Enabled = 0x1, + }, + }, + /// Enable or disable external source for LFCLK + EXTERNAL: packed union { + raw: u1, + value: enum(u1) { + /// Disable external source (use with Xtal) + Disabled = 0x0, + /// Enable use of external source instead of Xtal (SRC needs to be set to Xtal) + Enabled = 0x1, + }, + }, + padding: u14, + }), + reserved1336: [28]u8, + /// Calibration timer interval + CTIV: mmio.Mmio(packed struct(u32) { + /// Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. + CTIV: u7, + padding: u25, + }), + reserved1372: [32]u8, + /// Clocking options for the Trace Port debug interface + TRACECONFIG: mmio.Mmio(packed struct(u32) { + /// Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. + TRACEPORTSPEED: packed union { + raw: u2, + value: enum(u2) { + /// 32 MHz Trace Port clock (TRACECLK = 16 MHz) + @"32MHz" = 0x0, + /// 16 MHz Trace Port clock (TRACECLK = 8 MHz) + @"16MHz" = 0x1, + /// 8 MHz Trace Port clock (TRACECLK = 4 MHz) + @"8MHz" = 0x2, + /// 4 MHz Trace Port clock (TRACECLK = 2 MHz) + @"4MHz" = 0x3, + }, + }, + reserved16: u14, + /// Pin multiplexing of trace signals. + TRACEMUX: packed union { + raw: u2, + value: enum(u2) { + /// GPIOs multiplexed onto all trace-pins + GPIO = 0x0, + /// SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins + Serial = 0x1, + /// TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. + Parallel = 0x2, + _, + }, + }, + padding: u14, + }), + }; + + /// 2.4 GHz Radio + pub const RADIO = extern struct { + /// Enable RADIO in TX mode + TASKS_TXEN: u32, + /// Enable RADIO in RX mode + TASKS_RXEN: u32, + /// Start RADIO + TASKS_START: u32, + /// Stop RADIO + TASKS_STOP: u32, + /// Disable RADIO + TASKS_DISABLE: u32, + /// Start the RSSI and take one single sample of the receive signal strength. + TASKS_RSSISTART: u32, + /// Stop the RSSI measurement + TASKS_RSSISTOP: u32, + /// Start the bit counter + TASKS_BCSTART: u32, + /// Stop the bit counter + TASKS_BCSTOP: u32, + reserved256: [220]u8, + /// RADIO has ramped up and is ready to be started + EVENTS_READY: u32, + /// Address sent or received + EVENTS_ADDRESS: u32, + /// Packet payload sent or received + EVENTS_PAYLOAD: u32, + /// Packet sent or received + EVENTS_END: u32, + /// RADIO has been disabled + EVENTS_DISABLED: u32, + /// A device address match occurred on the last received packet + EVENTS_DEVMATCH: u32, + /// No device address match occurred on the last received packet + EVENTS_DEVMISS: u32, + /// Sampling of receive signal strength complete. + EVENTS_RSSIEND: u32, + reserved296: [8]u8, + /// Bit counter reached bit count value. + EVENTS_BCMATCH: u32, + reserved304: [4]u8, + /// Packet received with CRC ok + EVENTS_CRCOK: u32, + /// Packet received with CRC error + EVENTS_CRCERROR: u32, + reserved512: [200]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between READY event and START task + READY_START: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between END event and DISABLE task + END_DISABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between DISABLED event and TXEN task + DISABLED_TXEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between DISABLED event and RXEN task + DISABLED_RXEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between ADDRESS event and RSSISTART task + ADDRESS_RSSISTART: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between END event and START task + END_START: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between ADDRESS event and BCSTART task + ADDRESS_BCSTART: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + reserved8: u1, + /// Shortcut between DISABLED event and RSSISTOP task + DISABLED_RSSISTOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u23, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for ADDRESS event + ADDRESS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for PAYLOAD event + PAYLOAD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for DISABLED event + DISABLED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for DEVMATCH event + DEVMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for DEVMISS event + DEVMISS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for RSSIEND event + RSSIEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u2, + /// Write '1' to Enable interrupt for BCMATCH event + BCMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved12: u1, + /// Write '1' to Enable interrupt for CRCOK event + CRCOK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CRCERROR event + CRCERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u18, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for ADDRESS event + ADDRESS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for PAYLOAD event + PAYLOAD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for DISABLED event + DISABLED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for DEVMATCH event + DEVMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for DEVMISS event + DEVMISS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for RSSIEND event + RSSIEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u2, + /// Write '1' to Disable interrupt for BCMATCH event + BCMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved12: u1, + /// Write '1' to Disable interrupt for CRCOK event + CRCOK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CRCERROR event + CRCERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u18, + }), + reserved1024: [244]u8, + /// CRC status + CRCSTATUS: mmio.Mmio(packed struct(u32) { + /// CRC status of packet received + CRCSTATUS: packed union { + raw: u1, + value: enum(u1) { + /// Packet received with CRC error + CRCError = 0x0, + /// Packet received with CRC ok + CRCOk = 0x1, + }, + }, + padding: u31, + }), + reserved1032: [4]u8, + /// Received address + RXMATCH: mmio.Mmio(packed struct(u32) { + /// Received address + RXMATCH: u3, + padding: u29, + }), + /// CRC field of previously received packet + RXCRC: mmio.Mmio(packed struct(u32) { + /// CRC field of previously received packet + RXCRC: u24, + padding: u8, + }), + /// Device address match index + DAI: mmio.Mmio(packed struct(u32) { + /// Device address match index + DAI: u3, + padding: u29, + }), + reserved1284: [240]u8, + /// Packet pointer + PACKETPTR: mmio.Mmio(packed struct(u32) { + /// Packet pointer + PACKETPTR: u32, + }), + /// Frequency + FREQUENCY: mmio.Mmio(packed struct(u32) { + /// Radio channel frequency + FREQUENCY: u7, + reserved8: u1, + /// Channel map selection. + MAP: packed union { + raw: u1, + value: enum(u1) { + /// Channel map between 2400 MHZ .. 2500 MHz + Default = 0x0, + /// Channel map between 2360 MHZ .. 2460 MHz + Low = 0x1, + }, + }, + padding: u23, + }), + /// Output power + TXPOWER: mmio.Mmio(packed struct(u32) { + /// RADIO output power. + TXPOWER: packed union { + raw: u8, + value: enum(u8) { + /// +4 dBm + Pos4dBm = 0x4, + /// +3 dBm + Pos3dBm = 0x3, + /// 0 dBm + @"0dBm" = 0x0, + /// -4 dBm + Neg4dBm = 0xfc, + /// -8 dBm + Neg8dBm = 0xf8, + /// -12 dBm + Neg12dBm = 0xf4, + /// -16 dBm + Neg16dBm = 0xf0, + /// -20 dBm + Neg20dBm = 0xec, + /// Deprecated enumerator - -40 dBm + Neg30dBm = 0xff, + /// -40 dBm + Neg40dBm = 0xd8, + _, + }, + }, + padding: u24, + }), + /// Data rate and modulation + MODE: mmio.Mmio(packed struct(u32) { + /// Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. + MODE: packed union { + raw: u4, + value: enum(u4) { + /// 1 Mbit/s Nordic proprietary radio mode + Nrf_1Mbit = 0x0, + /// 2 Mbit/s Nordic proprietary radio mode + Nrf_2Mbit = 0x1, + /// Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode + Nrf_250Kbit = 0x2, + /// 1 Mbit/s Bluetooth Low Energy + Ble_1Mbit = 0x3, + /// 2 Mbit/s Bluetooth Low Energy + Ble_2Mbit = 0x4, + _, + }, + }, + padding: u28, + }), + /// Packet configuration register 0 + PCNF0: mmio.Mmio(packed struct(u32) { + /// Length on air of LENGTH field in number of bits. + LFLEN: u4, + reserved8: u4, + /// Length on air of S0 field in number of bytes. + S0LEN: u1, + reserved16: u7, + /// Length on air of S1 field in number of bits. + S1LEN: u4, + /// Include or exclude S1 field in RAM + S1INCL: packed union { + raw: u1, + value: enum(u1) { + /// Include S1 field in RAM only if S1LEN > 0 + Automatic = 0x0, + /// Always include S1 field in RAM independent of S1LEN + Include = 0x1, + }, + }, + reserved24: u3, + /// Length of preamble on air. Decision point: TASKS_START task + PLEN: packed union { + raw: u1, + value: enum(u1) { + /// 8-bit preamble + @"8bit" = 0x0, + /// 16-bit preamble + @"16bit" = 0x1, + }, + }, + padding: u7, + }), + /// Packet configuration register 1 + PCNF1: mmio.Mmio(packed struct(u32) { + /// Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + MAXLEN: u8, + /// Static length in number of bytes + STATLEN: u8, + /// Base address length in number of bytes + BALEN: u3, + reserved24: u5, + /// On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. + ENDIAN: packed union { + raw: u1, + value: enum(u1) { + /// Least Significant bit on air first + Little = 0x0, + /// Most significant bit on air first + Big = 0x1, + }, + }, + /// Enable or disable packet whitening + WHITEEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u6, + }), + /// Base address 0 + BASE0: mmio.Mmio(packed struct(u32) { + /// Base address 0 + BASE0: u32, + }), + /// Base address 1 + BASE1: mmio.Mmio(packed struct(u32) { + /// Base address 1 + BASE1: u32, + }), + /// Prefixes bytes for logical addresses 0-3 + PREFIX0: mmio.Mmio(packed struct(u32) { + /// Address prefix 0. + AP0: u8, + /// Address prefix 1. + AP1: u8, + /// Address prefix 2. + AP2: u8, + /// Address prefix 3. + AP3: u8, + }), + /// Prefixes bytes for logical addresses 4-7 + PREFIX1: mmio.Mmio(packed struct(u32) { + /// Address prefix 4. + AP4: u8, + /// Address prefix 5. + AP5: u8, + /// Address prefix 6. + AP6: u8, + /// Address prefix 7. + AP7: u8, + }), + /// Transmit address select + TXADDRESS: mmio.Mmio(packed struct(u32) { + /// Transmit address select + TXADDRESS: u3, + padding: u29, + }), + /// Receive address select + RXADDRESSES: mmio.Mmio(packed struct(u32) { + /// Enable or disable reception on logical address 0. + ADDR0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 1. + ADDR1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 2. + ADDR2: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 3. + ADDR3: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 4. + ADDR4: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 5. + ADDR5: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 6. + ADDR6: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 7. + ADDR7: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u24, + }), + /// CRC configuration + CRCCNF: mmio.Mmio(packed struct(u32) { + /// CRC length in number of bytes. + LEN: packed union { + raw: u2, + value: enum(u2) { + /// CRC length is zero and CRC calculation is disabled + Disabled = 0x0, + /// CRC length is one byte and CRC calculation is enabled + One = 0x1, + /// CRC length is two bytes and CRC calculation is enabled + Two = 0x2, + /// CRC length is three bytes and CRC calculation is enabled + Three = 0x3, + }, + }, + reserved8: u6, + /// Include or exclude packet address field out of CRC calculation. + SKIPADDR: packed union { + raw: u1, + value: enum(u1) { + /// CRC calculation includes address field + Include = 0x0, + /// CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + Skip = 0x1, + }, + }, + padding: u23, + }), + /// CRC polynomial + CRCPOLY: mmio.Mmio(packed struct(u32) { + /// CRC polynomial + CRCPOLY: u24, + padding: u8, + }), + /// CRC initial value + CRCINIT: mmio.Mmio(packed struct(u32) { + /// CRC initial value + CRCINIT: u24, + padding: u8, + }), + /// Unspecified + UNUSED0: u32, + /// Inter Frame Spacing in us + TIFS: mmio.Mmio(packed struct(u32) { + /// Inter Frame Spacing in us + TIFS: u8, + padding: u24, + }), + /// RSSI sample + RSSISAMPLE: mmio.Mmio(packed struct(u32) { + /// RSSI sample + RSSISAMPLE: u7, + padding: u25, + }), + reserved1360: [4]u8, + /// Current radio state + STATE: mmio.Mmio(packed struct(u32) { + /// Current radio state + STATE: packed union { + raw: u4, + value: enum(u4) { + /// RADIO is in the Disabled state + Disabled = 0x0, + /// RADIO is in the RXRU state + RxRu = 0x1, + /// RADIO is in the RXIDLE state + RxIdle = 0x2, + /// RADIO is in the RX state + Rx = 0x3, + /// RADIO is in the RXDISABLED state + RxDisable = 0x4, + /// RADIO is in the TXRU state + TxRu = 0x9, + /// RADIO is in the TXIDLE state + TxIdle = 0xa, + /// RADIO is in the TX state + Tx = 0xb, + /// RADIO is in the TXDISABLED state + TxDisable = 0xc, + _, + }, + }, + padding: u28, + }), + /// Data whitening initial value + DATAWHITEIV: mmio.Mmio(packed struct(u32) { + /// Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + DATAWHITEIV: u7, + padding: u25, + }), + reserved1376: [8]u8, + /// Bit counter compare + BCC: mmio.Mmio(packed struct(u32) { + /// Bit counter compare + BCC: u32, + }), + reserved1536: [156]u8, + /// Description collection[0]: Device address base segment 0 + DAB: [8]mmio.Mmio(packed struct(u32) { + /// Device address base segment 0 + DAB: u32, + }), + /// Description collection[0]: Device address prefix 0 + DAP: [8]mmio.Mmio(packed struct(u32) { + /// Device address prefix 0 + DAP: u16, + padding: u16, + }), + /// Device address match configuration + DACNF: mmio.Mmio(packed struct(u32) { + /// Enable or disable device address matching using device address 0 + ENA0: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 1 + ENA1: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 2 + ENA2: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 3 + ENA3: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 4 + ENA4: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 5 + ENA5: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 6 + ENA6: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 7 + ENA7: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// TxAdd for device address 0 + TXADD0: u1, + /// TxAdd for device address 1 + TXADD1: u1, + /// TxAdd for device address 2 + TXADD2: u1, + /// TxAdd for device address 3 + TXADD3: u1, + /// TxAdd for device address 4 + TXADD4: u1, + /// TxAdd for device address 5 + TXADD5: u1, + /// TxAdd for device address 6 + TXADD6: u1, + /// TxAdd for device address 7 + TXADD7: u1, + padding: u16, + }), + reserved1616: [12]u8, + /// Radio mode configuration register 0 + MODECNF0: mmio.Mmio(packed struct(u32) { + /// Radio ramp-up time + RU: packed union { + raw: u1, + value: enum(u1) { + /// Default ramp-up time (tRXEN), compatible with firmware written for nRF51 + Default = 0x0, + /// Fast ramp-up (tRXEN,FAST), see electrical specification for more information + Fast = 0x1, + }, + }, + reserved8: u7, + /// Default TX value + DTX: packed union { + raw: u2, + value: enum(u2) { + /// Transmit '1' + B1 = 0x0, + /// Transmit '0' + B0 = 0x1, + /// Transmit center frequency + Center = 0x2, + _, + }, + }, + padding: u22, + }), + reserved4092: [2472]u8, + /// Peripheral power control + POWER: mmio.Mmio(packed struct(u32) { + /// Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + POWER: packed union { + raw: u1, + value: enum(u1) { + /// Peripheral is powered off + Disabled = 0x0, + /// Peripheral is powered on + Enabled = 0x1, + }, + }, + padding: u31, + }), + }; + + /// UART with EasyDMA + pub const UARTE0 = extern struct { + /// Start UART receiver + TASKS_STARTRX: u32, + /// Stop UART receiver + TASKS_STOPRX: u32, + /// Start UART transmitter + TASKS_STARTTX: u32, + /// Stop UART transmitter + TASKS_STOPTX: u32, + reserved44: [28]u8, + /// Flush RX FIFO into RX buffer + TASKS_FLUSHRX: u32, + reserved256: [208]u8, + /// CTS is activated (set low). Clear To Send. + EVENTS_CTS: u32, + /// CTS is deactivated (set high). Not Clear To Send. + EVENTS_NCTS: u32, + /// Data received in RXD (but potentially not yet transferred to Data RAM) + EVENTS_RXDRDY: u32, + reserved272: [4]u8, + /// Receive buffer is filled up + EVENTS_ENDRX: u32, + reserved284: [8]u8, + /// Data sent from TXD + EVENTS_TXDRDY: u32, + /// Last TX byte transmitted + EVENTS_ENDTX: u32, + /// Error detected + EVENTS_ERROR: u32, + reserved324: [28]u8, + /// Receiver timeout + EVENTS_RXTO: u32, + reserved332: [4]u8, + /// UART receiver has started + EVENTS_RXSTARTED: u32, + /// UART transmitter has started + EVENTS_TXSTARTED: u32, + reserved344: [4]u8, + /// Transmitter stopped + EVENTS_TXSTOPPED: u32, + reserved512: [164]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Shortcut between ENDRX event and STARTRX task + ENDRX_STARTRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between ENDRX event and STOPRX task + ENDRX_STOPRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u25, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for CTS event + CTS: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for NCTS event + NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for RXDRDY event + RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved4: u1, + /// Enable or disable interrupt for ENDRX event + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved7: u2, + /// Enable or disable interrupt for TXDRDY event + TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for ENDTX event + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved17: u7, + /// Enable or disable interrupt for RXTO event + RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved19: u1, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved22: u1, + /// Enable or disable interrupt for TXSTOPPED event + TXSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u9, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for CTS event + CTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for NCTS event + NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for RXDRDY event + RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u2, + /// Write '1' to Enable interrupt for TXDRDY event + TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved17: u7, + /// Write '1' to Enable interrupt for RXTO event + RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u1, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved22: u1, + /// Write '1' to Enable interrupt for TXSTOPPED event + TXSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u9, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for CTS event + CTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for NCTS event + NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for RXDRDY event + RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u2, + /// Write '1' to Disable interrupt for TXDRDY event + TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved17: u7, + /// Write '1' to Disable interrupt for RXTO event + RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u1, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved22: u1, + /// Write '1' to Disable interrupt for TXSTOPPED event + TXSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u9, + }), + reserved1152: [372]u8, + /// Error source + ERRORSRC: mmio.Mmio(packed struct(u32) { + /// Overrun error + OVERRUN: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Parity error + PARITY: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Framing error occurred + FRAMING: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Break condition + BREAK: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + padding: u28, + }), + reserved1280: [124]u8, + /// Enable UART + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable UARTE + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable UARTE + Disabled = 0x0, + /// Enable UARTE + Enabled = 0x8, + _, + }, + }, + padding: u28, + }), + reserved1316: [32]u8, + /// Baud rate. Accuracy depends on the HFCLK source selected. + BAUDRATE: mmio.Mmio(packed struct(u32) { + /// Baud rate + BAUDRATE: packed union { + raw: u32, + value: enum(u32) { + /// 1200 baud (actual rate: 1205) + Baud1200 = 0x4f000, + /// 2400 baud (actual rate: 2396) + Baud2400 = 0x9d000, + /// 4800 baud (actual rate: 4808) + Baud4800 = 0x13b000, + /// 9600 baud (actual rate: 9598) + Baud9600 = 0x275000, + /// 14400 baud (actual rate: 14401) + Baud14400 = 0x3af000, + /// 19200 baud (actual rate: 19208) + Baud19200 = 0x4ea000, + /// 28800 baud (actual rate: 28777) + Baud28800 = 0x75c000, + /// 31250 baud + Baud31250 = 0x800000, + /// 38400 baud (actual rate: 38369) + Baud38400 = 0x9d0000, + /// 56000 baud (actual rate: 55944) + Baud56000 = 0xe50000, + /// 57600 baud (actual rate: 57554) + Baud57600 = 0xeb0000, + /// 76800 baud (actual rate: 76923) + Baud76800 = 0x13a9000, + /// 115200 baud (actual rate: 115108) + Baud115200 = 0x1d60000, + /// 230400 baud (actual rate: 231884) + Baud230400 = 0x3b00000, + /// 250000 baud + Baud250000 = 0x4000000, + /// 460800 baud (actual rate: 457143) + Baud460800 = 0x7400000, + /// 921600 baud (actual rate: 941176) + Baud921600 = 0xf000000, + /// 1Mega baud + Baud1M = 0x10000000, + _, + }, + }, + }), + reserved1388: [68]u8, + /// Configuration of parity and hardware flow control + CONFIG: mmio.Mmio(packed struct(u32) { + /// Hardware flow control + HWFC: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Parity + PARITY: packed union { + raw: u3, + value: enum(u3) { + /// Exclude parity bit + Excluded = 0x0, + /// Include parity bit + Included = 0x7, + _, + }, + }, + padding: u28, + }), + }; + + /// Universal Asynchronous Receiver/Transmitter + pub const UART0 = extern struct { + /// Start UART receiver + TASKS_STARTRX: u32, + /// Stop UART receiver + TASKS_STOPRX: u32, + /// Start UART transmitter + TASKS_STARTTX: u32, + /// Stop UART transmitter + TASKS_STOPTX: u32, + reserved28: [12]u8, + /// Suspend UART + TASKS_SUSPEND: u32, + reserved256: [224]u8, + /// CTS is activated (set low). Clear To Send. + EVENTS_CTS: u32, + /// CTS is deactivated (set high). Not Clear To Send. + EVENTS_NCTS: u32, + /// Data received in RXD + EVENTS_RXDRDY: u32, + reserved284: [16]u8, + /// Data sent from TXD + EVENTS_TXDRDY: u32, + reserved292: [4]u8, + /// Error detected + EVENTS_ERROR: u32, + reserved324: [28]u8, + /// Receiver timeout + EVENTS_RXTO: u32, + reserved512: [184]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Shortcut between CTS event and STARTRX task + CTS_STARTRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between NCTS event and STOPRX task + NCTS_STOPRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for CTS event + CTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for NCTS event + NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for RXDRDY event + RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u4, + /// Write '1' to Enable interrupt for TXDRDY event + TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved17: u7, + /// Write '1' to Enable interrupt for RXTO event + RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u14, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for CTS event + CTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for NCTS event + NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for RXDRDY event + RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u4, + /// Write '1' to Disable interrupt for TXDRDY event + TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved17: u7, + /// Write '1' to Disable interrupt for RXTO event + RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u14, + }), + reserved1152: [372]u8, + /// Error source + ERRORSRC: mmio.Mmio(packed struct(u32) { + /// Overrun error + OVERRUN: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Parity error + PARITY: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Framing error occurred + FRAMING: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Break condition + BREAK: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + padding: u28, + }), + reserved1280: [124]u8, + /// Enable UART + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable UART + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable UART + Disabled = 0x0, + /// Enable UART + Enabled = 0x4, + _, + }, + }, + padding: u28, + }), + reserved1288: [4]u8, + /// Pin select for RTS + PSELRTS: mmio.Mmio(packed struct(u32) { + /// Pin number configuration for UART RTS signal + PSELRTS: packed union { + raw: u32, + value: enum(u32) { + /// Disconnect + Disconnected = 0xffffffff, + _, + }, + }, + }), + /// Pin select for TXD + PSELTXD: mmio.Mmio(packed struct(u32) { + /// Pin number configuration for UART TXD signal + PSELTXD: packed union { + raw: u32, + value: enum(u32) { + /// Disconnect + Disconnected = 0xffffffff, + _, + }, + }, + }), + /// Pin select for CTS + PSELCTS: mmio.Mmio(packed struct(u32) { + /// Pin number configuration for UART CTS signal + PSELCTS: packed union { + raw: u32, + value: enum(u32) { + /// Disconnect + Disconnected = 0xffffffff, + _, + }, + }, + }), + /// Pin select for RXD + PSELRXD: mmio.Mmio(packed struct(u32) { + /// Pin number configuration for UART RXD signal + PSELRXD: packed union { + raw: u32, + value: enum(u32) { + /// Disconnect + Disconnected = 0xffffffff, + _, + }, + }, + }), + /// RXD register + RXD: mmio.Mmio(packed struct(u32) { + /// RX data received in previous transfers, double buffered + RXD: u8, + padding: u24, + }), + /// TXD register + TXD: mmio.Mmio(packed struct(u32) { + /// TX data to be transferred + TXD: u8, + padding: u24, + }), + reserved1316: [4]u8, + /// Baud rate + BAUDRATE: mmio.Mmio(packed struct(u32) { + /// Baud rate + BAUDRATE: packed union { + raw: u32, + value: enum(u32) { + /// 1200 baud (actual rate: 1205) + Baud1200 = 0x4f000, + /// 2400 baud (actual rate: 2396) + Baud2400 = 0x9d000, + /// 4800 baud (actual rate: 4808) + Baud4800 = 0x13b000, + /// 9600 baud (actual rate: 9598) + Baud9600 = 0x275000, + /// 14400 baud (actual rate: 14414) + Baud14400 = 0x3b0000, + /// 19200 baud (actual rate: 19208) + Baud19200 = 0x4ea000, + /// 28800 baud (actual rate: 28829) + Baud28800 = 0x75f000, + /// 31250 baud + Baud31250 = 0x800000, + /// 38400 baud (actual rate: 38462) + Baud38400 = 0x9d5000, + /// 56000 baud (actual rate: 55944) + Baud56000 = 0xe50000, + /// 57600 baud (actual rate: 57762) + Baud57600 = 0xebf000, + /// 76800 baud (actual rate: 76923) + Baud76800 = 0x13a9000, + /// 115200 baud (actual rate: 115942) + Baud115200 = 0x1d7e000, + /// 230400 baud (actual rate: 231884) + Baud230400 = 0x3afb000, + /// 250000 baud + Baud250000 = 0x4000000, + /// 460800 baud (actual rate: 470588) + Baud460800 = 0x75f7000, + /// 921600 baud (actual rate: 941176) + Baud921600 = 0xebed000, + /// 1Mega baud + Baud1M = 0x10000000, + _, + }, + }, + }), + reserved1388: [68]u8, + /// Configuration of parity and hardware flow control + CONFIG: mmio.Mmio(packed struct(u32) { + /// Hardware flow control + HWFC: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Parity + PARITY: packed union { + raw: u3, + value: enum(u3) { + /// Exclude parity bit + Excluded = 0x0, + /// Include parity bit + Included = 0x7, + _, + }, + }, + padding: u28, + }), + }; + + /// Serial Peripheral Interface Master with EasyDMA 0 + pub const SPIM0 = extern struct { + reserved16: [16]u8, + /// Start SPI transaction + TASKS_START: u32, + /// Stop SPI transaction + TASKS_STOP: u32, + reserved28: [4]u8, + /// Suspend SPI transaction + TASKS_SUSPEND: u32, + /// Resume SPI transaction + TASKS_RESUME: u32, + reserved260: [224]u8, + /// SPI transaction has stopped + EVENTS_STOPPED: u32, + reserved272: [8]u8, + /// End of RXD buffer reached + EVENTS_ENDRX: u32, + reserved280: [4]u8, + /// End of RXD buffer and TXD buffer reached + EVENTS_END: u32, + reserved288: [4]u8, + /// End of TXD buffer reached + EVENTS_ENDTX: u32, + reserved332: [40]u8, + /// Transaction started + EVENTS_STARTED: u32, + reserved512: [176]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + reserved17: u17, + /// Shortcut between END event and START task + END_START: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u14, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u2, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved6: u1, + /// Write '1' to Enable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved8: u1, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u10, + /// Write '1' to Enable interrupt for STARTED event + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u2, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved6: u1, + /// Write '1' to Disable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved8: u1, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u10, + /// Write '1' to Disable interrupt for STARTED event + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + reserved1280: [500]u8, + /// Enable SPIM + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable SPIM + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable SPIM + Disabled = 0x0, + /// Enable SPIM + Enabled = 0x7, + _, + }, + }, + padding: u28, + }), + reserved1316: [32]u8, + /// SPI frequency. Accuracy depends on the HFCLK source selected. + FREQUENCY: mmio.Mmio(packed struct(u32) { + /// SPI master data rate + FREQUENCY: packed union { + raw: u32, + value: enum(u32) { + /// 125 kbps + K125 = 0x2000000, + /// 250 kbps + K250 = 0x4000000, + /// 500 kbps + K500 = 0x8000000, + /// 1 Mbps + M1 = 0x10000000, + /// 2 Mbps + M2 = 0x20000000, + /// 4 Mbps + M4 = 0x40000000, + /// 8 Mbps + M8 = 0x80000000, + _, + }, + }, + }), + reserved1364: [44]u8, + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Bit order + ORDER: packed union { + raw: u1, + value: enum(u1) { + /// Most significant bit shifted out first + MsbFirst = 0x0, + /// Least significant bit shifted out first + LsbFirst = 0x1, + }, + }, + /// Serial clock (SCK) phase + CPHA: packed union { + raw: u1, + value: enum(u1) { + /// Sample on leading edge of clock, shift serial data on trailing edge + Leading = 0x0, + /// Sample on trailing edge of clock, shift serial data on leading edge + Trailing = 0x1, + }, + }, + /// Serial clock (SCK) polarity + CPOL: packed union { + raw: u1, + value: enum(u1) { + /// Active high + ActiveHigh = 0x0, + /// Active low + ActiveLow = 0x1, + }, + }, + padding: u29, + }), + reserved1472: [104]u8, + /// Over-read character. Character clocked out in case and over-read of the TXD buffer. + ORC: mmio.Mmio(packed struct(u32) { + /// Over-read character. Character clocked out in case and over-read of the TXD buffer. + ORC: u8, + padding: u24, + }), + }; + + /// SPI Slave 0 + pub const SPIS0 = extern struct { + reserved36: [36]u8, + /// Acquire SPI semaphore + TASKS_ACQUIRE: u32, + /// Release SPI semaphore, enabling the SPI slave to acquire it + TASKS_RELEASE: u32, + reserved260: [216]u8, + /// Granted transaction completed + EVENTS_END: u32, + reserved272: [8]u8, + /// End of RXD buffer reached + EVENTS_ENDRX: u32, + reserved296: [20]u8, + /// Semaphore acquired + EVENTS_ACQUIRED: u32, + reserved512: [212]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u29, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Enable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u2, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u5, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u21, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Disable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u2, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u5, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u21, + }), + reserved1024: [244]u8, + /// Semaphore status register + SEMSTAT: mmio.Mmio(packed struct(u32) { + /// Semaphore status + SEMSTAT: packed union { + raw: u2, + value: enum(u2) { + /// Semaphore is free + Free = 0x0, + /// Semaphore is assigned to CPU + CPU = 0x1, + /// Semaphore is assigned to SPI slave + SPIS = 0x2, + /// Semaphore is assigned to SPI but a handover to the CPU is pending + CPUPending = 0x3, + }, + }, + padding: u30, + }), + reserved1088: [60]u8, + /// Status from last transaction + STATUS: mmio.Mmio(packed struct(u32) { + /// TX buffer over-read detected, and prevented + OVERREAD: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// RX buffer overflow detected, and prevented + OVERFLOW: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + padding: u30, + }), + reserved1280: [188]u8, + /// Enable SPI slave + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable SPI slave + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable SPI slave + Disabled = 0x0, + /// Enable SPI slave + Enabled = 0x2, + _, + }, + }, + padding: u28, + }), + reserved1364: [80]u8, + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Bit order + ORDER: packed union { + raw: u1, + value: enum(u1) { + /// Most significant bit shifted out first + MsbFirst = 0x0, + /// Least significant bit shifted out first + LsbFirst = 0x1, + }, + }, + /// Serial clock (SCK) phase + CPHA: packed union { + raw: u1, + value: enum(u1) { + /// Sample on leading edge of clock, shift serial data on trailing edge + Leading = 0x0, + /// Sample on trailing edge of clock, shift serial data on leading edge + Trailing = 0x1, + }, + }, + /// Serial clock (SCK) polarity + CPOL: packed union { + raw: u1, + value: enum(u1) { + /// Active high + ActiveHigh = 0x0, + /// Active low + ActiveLow = 0x1, + }, + }, + padding: u29, + }), + reserved1372: [4]u8, + /// Default character. Character clocked out in case of an ignored transaction. + DEF: mmio.Mmio(packed struct(u32) { + /// Default character. Character clocked out in case of an ignored transaction. + DEF: u8, + padding: u24, + }), + reserved1472: [96]u8, + /// Over-read character + ORC: mmio.Mmio(packed struct(u32) { + /// Over-read character. Character clocked out after an over-read of the transmit buffer. + ORC: u8, + padding: u24, + }), + }; + + /// I2C compatible Two-Wire Master Interface with EasyDMA 0 + pub const TWIM0 = extern struct { + /// Start TWI receive sequence + TASKS_STARTRX: u32, + reserved8: [4]u8, + /// Start TWI transmit sequence + TASKS_STARTTX: u32, + reserved20: [8]u8, + /// Stop TWI transaction. Must be issued while the TWI master is not suspended. + TASKS_STOP: u32, + reserved28: [4]u8, + /// Suspend TWI transaction + TASKS_SUSPEND: u32, + /// Resume TWI transaction + TASKS_RESUME: u32, + reserved260: [224]u8, + /// TWI stopped + EVENTS_STOPPED: u32, + reserved292: [28]u8, + /// TWI error + EVENTS_ERROR: u32, + reserved328: [32]u8, + /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + EVENTS_SUSPENDED: u32, + /// Receive sequence started + EVENTS_RXSTARTED: u32, + /// Transmit sequence started + EVENTS_TXSTARTED: u32, + reserved348: [8]u8, + /// Byte boundary, starting to receive the last byte + EVENTS_LASTRX: u32, + /// Byte boundary, starting to transmit the last byte + EVENTS_LASTTX: u32, + reserved512: [156]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + reserved7: u7, + /// Shortcut between LASTTX event and STARTRX task + LASTTX_STARTRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between LASTTX event and SUSPEND task + LASTTX_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between LASTTX event and STOP task + LASTTX_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between LASTRX event and STARTTX task + LASTRX_STARTTX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + reserved12: u1, + /// Shortcut between LASTRX event and STOP task + LASTRX_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u19, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Enable or disable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved18: u8, + /// Enable or disable interrupt for SUSPENDED event + SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved23: u2, + /// Enable or disable interrupt for LASTRX event + LASTRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for LASTTX event + LASTTX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u7, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Write '1' to Enable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u8, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved23: u2, + /// Write '1' to Enable interrupt for LASTRX event + LASTRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for LASTTX event + LASTTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u7, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Write '1' to Disable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u8, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved23: u2, + /// Write '1' to Disable interrupt for LASTRX event + LASTRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for LASTTX event + LASTTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u7, + }), + reserved1220: [440]u8, + /// Error source + ERRORSRC: mmio.Mmio(packed struct(u32) { + /// Overrun error + OVERRUN: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotReceived = 0x0, + /// Error occurred + Received = 0x1, + }, + }, + /// NACK received after sending the address (write '1' to clear) + ANACK: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotReceived = 0x0, + /// Error occurred + Received = 0x1, + }, + }, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotReceived = 0x0, + /// Error occurred + Received = 0x1, + }, + }, + padding: u29, + }), + reserved1280: [56]u8, + /// Enable TWIM + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable TWIM + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable TWIM + Disabled = 0x0, + /// Enable TWIM + Enabled = 0x6, + _, + }, + }, + padding: u28, + }), + reserved1316: [32]u8, + /// TWI frequency + FREQUENCY: mmio.Mmio(packed struct(u32) { + /// TWI master clock frequency + FREQUENCY: packed union { + raw: u32, + value: enum(u32) { + /// 100 kbps + K100 = 0x1980000, + /// 250 kbps + K250 = 0x4000000, + /// 400 kbps + K400 = 0x6400000, + _, + }, + }, + }), + reserved1416: [96]u8, + /// Address used in the TWI transfer + ADDRESS: mmio.Mmio(packed struct(u32) { + /// Address used in the TWI transfer + ADDRESS: u7, + padding: u25, + }), + }; + + /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 + pub const TWIS0 = extern struct { + reserved20: [20]u8, + /// Stop TWI transaction + TASKS_STOP: u32, + reserved28: [4]u8, + /// Suspend TWI transaction + TASKS_SUSPEND: u32, + /// Resume TWI transaction + TASKS_RESUME: u32, + reserved48: [12]u8, + /// Prepare the TWI slave to respond to a write command + TASKS_PREPARERX: u32, + /// Prepare the TWI slave to respond to a read command + TASKS_PREPARETX: u32, + reserved260: [204]u8, + /// TWI stopped + EVENTS_STOPPED: u32, + reserved292: [28]u8, + /// TWI error + EVENTS_ERROR: u32, + reserved332: [36]u8, + /// Receive sequence started + EVENTS_RXSTARTED: u32, + /// Transmit sequence started + EVENTS_TXSTARTED: u32, + reserved356: [16]u8, + /// Write command received + EVENTS_WRITE: u32, + /// Read command received + EVENTS_READ: u32, + reserved512: [148]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// Shortcut between WRITE event and SUSPEND task + WRITE_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between READ event and SUSPEND task + READ_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u17, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Enable or disable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved19: u9, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved25: u4, + /// Enable or disable interrupt for WRITE event + WRITE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for READ event + READ: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u5, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Write '1' to Enable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u9, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved25: u4, + /// Write '1' to Enable interrupt for WRITE event + WRITE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for READ event + READ: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u5, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Write '1' to Disable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u9, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved25: u4, + /// Write '1' to Disable interrupt for WRITE event + WRITE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for READ event + READ: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u5, + }), + reserved1232: [452]u8, + /// Error source + ERRORSRC: mmio.Mmio(packed struct(u32) { + /// RX buffer overflow detected, and prevented + OVERFLOW: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotDetected = 0x0, + /// Error occurred + Detected = 0x1, + }, + }, + reserved2: u1, + /// NACK sent after receiving a data byte + DNACK: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotReceived = 0x0, + /// Error occurred + Received = 0x1, + }, + }, + /// TX buffer over-read detected, and prevented + OVERREAD: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotDetected = 0x0, + /// Error occurred + Detected = 0x1, + }, + }, + padding: u28, + }), + /// Status register indicating which address had a match + MATCH: mmio.Mmio(packed struct(u32) { + /// Which of the addresses in {ADDRESS} matched the incoming address + MATCH: u1, + padding: u31, + }), + reserved1280: [40]u8, + /// Enable TWIS + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable TWIS + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable TWIS + Disabled = 0x0, + /// Enable TWIS + Enabled = 0x9, + _, + }, + }, + padding: u28, + }), + reserved1416: [132]u8, + /// Description collection[0]: TWI slave address 0 + ADDRESS: [2]mmio.Mmio(packed struct(u32) { + /// TWI slave address + ADDRESS: u7, + padding: u25, + }), + reserved1428: [4]u8, + /// Configuration register for the address match mechanism + CONFIG: mmio.Mmio(packed struct(u32) { + /// Enable or disable address matching on ADDRESS[0] + ADDRESS0: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable address matching on ADDRESS[1] + ADDRESS1: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + padding: u30, + }), + reserved1472: [40]u8, + /// Over-read character. Character sent out in case of an over-read of the transmit buffer. + ORC: mmio.Mmio(packed struct(u32) { + /// Over-read character. Character sent out in case of an over-read of the transmit buffer. + ORC: u8, + padding: u24, + }), + }; + + /// Serial Peripheral Interface 0 + pub const SPI0 = extern struct { + reserved264: [264]u8, + /// TXD byte sent and RXD byte received + EVENTS_READY: u32, + reserved772: [504]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Write '1' to Enable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Write '1' to Disable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + reserved1280: [500]u8, + /// Enable SPI + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable SPI + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable SPI + Disabled = 0x0, + /// Enable SPI + Enabled = 0x1, + _, + }, + }, + padding: u28, + }), + reserved1304: [20]u8, + /// RXD register + RXD: mmio.Mmio(packed struct(u32) { + /// RX data received. Double buffered + RXD: u8, + padding: u24, + }), + /// TXD register + TXD: mmio.Mmio(packed struct(u32) { + /// TX data to send. Double buffered + TXD: u8, + padding: u24, + }), + reserved1316: [4]u8, + /// SPI frequency + FREQUENCY: mmio.Mmio(packed struct(u32) { + /// SPI master data rate + FREQUENCY: packed union { + raw: u32, + value: enum(u32) { + /// 125 kbps + K125 = 0x2000000, + /// 250 kbps + K250 = 0x4000000, + /// 500 kbps + K500 = 0x8000000, + /// 1 Mbps + M1 = 0x10000000, + /// 2 Mbps + M2 = 0x20000000, + /// 4 Mbps + M4 = 0x40000000, + /// 8 Mbps + M8 = 0x80000000, + _, + }, + }, + }), + reserved1364: [44]u8, + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Bit order + ORDER: packed union { + raw: u1, + value: enum(u1) { + /// Most significant bit shifted out first + MsbFirst = 0x0, + /// Least significant bit shifted out first + LsbFirst = 0x1, + }, + }, + /// Serial clock (SCK) phase + CPHA: packed union { + raw: u1, + value: enum(u1) { + /// Sample on leading edge of clock, shift serial data on trailing edge + Leading = 0x0, + /// Sample on trailing edge of clock, shift serial data on leading edge + Trailing = 0x1, + }, + }, + /// Serial clock (SCK) polarity + CPOL: packed union { + raw: u1, + value: enum(u1) { + /// Active high + ActiveHigh = 0x0, + /// Active low + ActiveLow = 0x1, + }, + }, + padding: u29, + }), + }; + + /// I2C compatible Two-Wire Interface 0 + pub const TWI0 = extern struct { + /// Start TWI receive sequence + TASKS_STARTRX: u32, + reserved8: [4]u8, + /// Start TWI transmit sequence + TASKS_STARTTX: u32, + reserved20: [8]u8, + /// Stop TWI transaction + TASKS_STOP: u32, + reserved28: [4]u8, + /// Suspend TWI transaction + TASKS_SUSPEND: u32, + /// Resume TWI transaction + TASKS_RESUME: u32, + reserved260: [224]u8, + /// TWI stopped + EVENTS_STOPPED: u32, + /// TWI RXD byte received + EVENTS_RXDREADY: u32, + reserved284: [16]u8, + /// TWI TXD byte sent + EVENTS_TXDSENT: u32, + reserved292: [4]u8, + /// TWI error + EVENTS_ERROR: u32, + reserved312: [16]u8, + /// TWI byte boundary, generated before each byte that is sent or received + EVENTS_BB: u32, + reserved328: [12]u8, + /// TWI entered the suspended state + EVENTS_SUSPENDED: u32, + reserved512: [180]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between BB event and SUSPEND task + BB_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between BB event and STOP task + BB_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u30, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for RXDREADY event + RXDREADY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u4, + /// Write '1' to Enable interrupt for TXDSENT event + TXDSENT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved14: u4, + /// Write '1' to Enable interrupt for BB event + BB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u3, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u13, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for RXDREADY event + RXDREADY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u4, + /// Write '1' to Disable interrupt for TXDSENT event + TXDSENT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved14: u4, + /// Write '1' to Disable interrupt for BB event + BB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u3, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u13, + }), + reserved1220: [440]u8, + /// Error source + ERRORSRC: mmio.Mmio(packed struct(u32) { + /// Overrun error + OVERRUN: packed union { + raw: u1, + value: enum(u1) { + /// Read: no overrun occured + NotPresent = 0x0, + /// Read: overrun occured + Present = 0x1, + }, + }, + /// NACK received after sending the address (write '1' to clear) + ANACK: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + padding: u29, + }), + reserved1280: [56]u8, + /// Enable TWI + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable TWI + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable TWI + Disabled = 0x0, + /// Enable TWI + Enabled = 0x5, + _, + }, + }, + padding: u28, + }), + reserved1288: [4]u8, + /// Pin select for SCL + PSELSCL: mmio.Mmio(packed struct(u32) { + /// Pin number configuration for TWI SCL signal + PSELSCL: packed union { + raw: u32, + value: enum(u32) { + /// Disconnect + Disconnected = 0xffffffff, + _, + }, + }, + }), + /// Pin select for SDA + PSELSDA: mmio.Mmio(packed struct(u32) { + /// Pin number configuration for TWI SDA signal + PSELSDA: packed union { + raw: u32, + value: enum(u32) { + /// Disconnect + Disconnected = 0xffffffff, + _, + }, + }, + }), + reserved1304: [8]u8, + /// RXD register + RXD: mmio.Mmio(packed struct(u32) { + /// RXD register + RXD: u8, + padding: u24, + }), + /// TXD register + TXD: mmio.Mmio(packed struct(u32) { + /// TXD register + TXD: u8, + padding: u24, + }), + reserved1316: [4]u8, + /// TWI frequency + FREQUENCY: mmio.Mmio(packed struct(u32) { + /// TWI master clock frequency + FREQUENCY: packed union { + raw: u32, + value: enum(u32) { + /// 100 kbps + K100 = 0x1980000, + /// 250 kbps + K250 = 0x4000000, + /// 400 kbps (actual rate 410.256 kbps) + K400 = 0x6680000, + _, + }, + }, + }), + reserved1416: [96]u8, + /// Address used in the TWI transfer + ADDRESS: mmio.Mmio(packed struct(u32) { + /// Address used in the TWI transfer + ADDRESS: u7, + padding: u25, + }), + }; + + /// GPIO Port 1 + pub const P0 = extern struct { + reserved1284: [1284]u8, + /// Write GPIO port + OUT: mmio.Mmio(packed struct(u32) { + /// Pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + }), + /// Set individual bits in GPIO port + OUTSET: mmio.Mmio(packed struct(u32) { + /// Pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + }), + /// Clear individual bits in GPIO port + OUTCLR: mmio.Mmio(packed struct(u32) { + /// Pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + }), + /// Read GPIO port + IN: mmio.Mmio(packed struct(u32) { + /// Pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + }), + /// Direction of GPIO pins + DIR: mmio.Mmio(packed struct(u32) { + /// Pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + }), + /// DIR set register + DIRSET: mmio.Mmio(packed struct(u32) { + /// Set as output pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + }), + /// DIR clear register + DIRCLR: mmio.Mmio(packed struct(u32) { + /// Set as input pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + }), + /// Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + LATCH: mmio.Mmio(packed struct(u32) { + /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + }), + /// Select between default DETECT signal behaviour and LDETECT mode + DETECTMODE: mmio.Mmio(packed struct(u32) { + /// Select between default DETECT signal behaviour and LDETECT mode + DETECTMODE: packed union { + raw: u1, + value: enum(u1) { + /// DETECT directly connected to PIN DETECT signals + Default = 0x0, + /// Use the latched LDETECT behaviour + LDETECT = 0x1, + }, + }, + padding: u31, + }), + reserved1792: [472]u8, + /// Description collection[0]: Configuration of GPIO pins + PIN_CNF: [32]mmio.Mmio(packed struct(u32) { + /// Pin direction. Same physical register as DIR register + DIR: packed union { + raw: u1, + value: enum(u1) { + /// Configure pin as an input pin + Input = 0x0, + /// Configure pin as an output pin + Output = 0x1, + }, + }, + /// Connect or disconnect input buffer + INPUT: packed union { + raw: u1, + value: enum(u1) { + /// Connect input buffer + Connect = 0x0, + /// Disconnect input buffer + Disconnect = 0x1, + }, + }, + /// Pull configuration + PULL: packed union { + raw: u2, + value: enum(u2) { + /// No pull + Disabled = 0x0, + /// Pull down on pin + Pulldown = 0x1, + /// Pull up on pin + Pullup = 0x3, + _, + }, + }, + reserved8: u4, + /// Drive configuration + DRIVE: packed union { + raw: u3, + value: enum(u3) { + /// Standard '0', standard '1' + S0S1 = 0x0, + /// High drive '0', standard '1' + H0S1 = 0x1, + /// Standard '0', high drive '1' + S0H1 = 0x2, + /// High drive '0', high 'drive '1'' + H0H1 = 0x3, + /// Disconnect '0' standard '1' (normally used for wired-or connections) + D0S1 = 0x4, + /// Disconnect '0', high drive '1' (normally used for wired-or connections) + D0H1 = 0x5, + /// Standard '0'. disconnect '1' (normally used for wired-and connections) + S0D1 = 0x6, + /// High drive '0', disconnect '1' (normally used for wired-and connections) + H0D1 = 0x7, + }, + }, + reserved16: u5, + /// Pin sensing mechanism + SENSE: packed union { + raw: u2, + value: enum(u2) { + /// Disabled + Disabled = 0x0, + /// Sense for high level + High = 0x2, + /// Sense for low level + Low = 0x3, + _, + }, + }, + padding: u14, + }), + }; + + /// FPU + pub const FPU = extern struct { + /// Unused. + UNUSED: u32, + }; + + /// Inter-IC Sound + pub const I2S = extern struct { + /// Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + TASKS_START: u32, + /// Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. + TASKS_STOP: u32, + reserved260: [252]u8, + /// The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + EVENTS_RXPTRUPD: u32, + /// I2S transfer stopped. + EVENTS_STOPPED: u32, + reserved276: [8]u8, + /// The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + EVENTS_TXPTRUPD: u32, + reserved768: [488]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Enable or disable interrupt for RXPTRUPD event + RXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved5: u2, + /// Enable or disable interrupt for TXPTRUPD event + TXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u26, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Enable interrupt for RXPTRUPD event + RXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved5: u2, + /// Write '1' to Enable interrupt for TXPTRUPD event + TXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u26, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Disable interrupt for RXPTRUPD event + RXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved5: u2, + /// Write '1' to Disable interrupt for TXPTRUPD event + TXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u26, + }), + reserved1280: [500]u8, + /// Enable I2S module. + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable I2S module. + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + }; + + /// Event Generator Unit 0 + pub const EGU0 = extern struct { + /// Description collection[0]: Trigger 0 for triggering the corresponding TRIGGERED[0] event + TASKS_TRIGGER: [16]u32, + reserved256: [192]u8, + /// Description collection[0]: Event number 0 generated by triggering the corresponding TRIGGER[0] task + EVENTS_TRIGGERED: [16]u32, + reserved768: [448]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u16, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u16, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u16, + }), + }; + + /// Memory Watch Unit + pub const MWU = extern struct { + reserved768: [768]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for REGION[0].WA event + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for REGION[0].RA event + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for REGION[1].WA event + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for REGION[1].RA event + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for REGION[2].WA event + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for REGION[2].RA event + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for REGION[3].WA event + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for REGION[3].RA event + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Enable or disable interrupt for PREGION[0].WA event + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for PREGION[0].RA event + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for PREGION[1].WA event + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for PREGION[1].RA event + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u4, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for REGION[0].WA event + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for REGION[0].RA event + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for REGION[1].WA event + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for REGION[1].RA event + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for REGION[2].WA event + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for REGION[2].RA event + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for REGION[3].WA event + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for REGION[3].RA event + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Write '1' to Enable interrupt for PREGION[0].WA event + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for PREGION[0].RA event + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for PREGION[1].WA event + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for PREGION[1].RA event + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for REGION[0].WA event + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for REGION[0].RA event + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for REGION[1].WA event + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for REGION[1].RA event + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for REGION[2].WA event + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for REGION[2].RA event + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for REGION[3].WA event + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for REGION[3].RA event + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Write '1' to Disable interrupt for PREGION[0].WA event + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for PREGION[0].RA event + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for PREGION[1].WA event + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for PREGION[1].RA event + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + reserved800: [20]u8, + /// Enable or disable non-maskable interrupt + NMIEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable non-maskable interrupt for REGION[0].WA event + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable non-maskable interrupt for REGION[0].RA event + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable non-maskable interrupt for REGION[1].WA event + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable non-maskable interrupt for REGION[1].RA event + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable non-maskable interrupt for REGION[2].WA event + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable non-maskable interrupt for REGION[2].RA event + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable non-maskable interrupt for REGION[3].WA event + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable non-maskable interrupt for REGION[3].RA event + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Enable or disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u4, + }), + /// Enable non-maskable interrupt + NMIENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable non-maskable interrupt for REGION[0].WA event + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable non-maskable interrupt for REGION[0].RA event + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable non-maskable interrupt for REGION[1].WA event + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable non-maskable interrupt for REGION[1].RA event + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable non-maskable interrupt for REGION[2].WA event + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable non-maskable interrupt for REGION[2].RA event + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable non-maskable interrupt for REGION[3].WA event + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable non-maskable interrupt for REGION[3].RA event + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Write '1' to Enable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + /// Disable non-maskable interrupt + NMIENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable non-maskable interrupt for REGION[0].WA event + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable non-maskable interrupt for REGION[0].RA event + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable non-maskable interrupt for REGION[1].WA event + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable non-maskable interrupt for REGION[1].RA event + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable non-maskable interrupt for REGION[2].WA event + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable non-maskable interrupt for REGION[2].RA event + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable non-maskable interrupt for REGION[3].WA event + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable non-maskable interrupt for REGION[3].RA event + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Write '1' to Disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + reserved1296: [484]u8, + /// Enable/disable regions watch + REGIONEN: mmio.Mmio(packed struct(u32) { + /// Enable/disable write access watch in region[0] + RGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this region + Disable = 0x0, + /// Enable write access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in region[0] + RGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this region + Disable = 0x0, + /// Enable read access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable write access watch in region[1] + RGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this region + Disable = 0x0, + /// Enable write access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in region[1] + RGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this region + Disable = 0x0, + /// Enable read access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable write access watch in region[2] + RGN2WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this region + Disable = 0x0, + /// Enable write access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in region[2] + RGN2RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this region + Disable = 0x0, + /// Enable read access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable write access watch in region[3] + RGN3WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this region + Disable = 0x0, + /// Enable write access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in region[3] + RGN3RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this region + Disable = 0x0, + /// Enable read access watch in this region + Enable = 0x1, + }, + }, + reserved24: u16, + /// Enable/disable write access watch in PREGION[0] + PRGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this PREGION + Disable = 0x0, + /// Enable write access watch in this PREGION + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in PREGION[0] + PRGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this PREGION + Disable = 0x0, + /// Enable read access watch in this PREGION + Enable = 0x1, + }, + }, + /// Enable/disable write access watch in PREGION[1] + PRGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this PREGION + Disable = 0x0, + /// Enable write access watch in this PREGION + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in PREGION[1] + PRGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this PREGION + Disable = 0x0, + /// Enable read access watch in this PREGION + Enable = 0x1, + }, + }, + padding: u4, + }), + /// Enable regions watch + REGIONENSET: mmio.Mmio(packed struct(u32) { + /// Enable write access watch in region[0] + RGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in region[0] + RGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable write access watch in region[1] + RGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in region[1] + RGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable write access watch in region[2] + RGN2WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in region[2] + RGN2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable write access watch in region[3] + RGN3WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in region[3] + RGN3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Enable write access watch in PREGION[0] + PRGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this PREGION is disabled + Disabled = 0x0, + /// Write access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in PREGION[0] + PRGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this PREGION is disabled + Disabled = 0x0, + /// Read access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Enable write access watch in PREGION[1] + PRGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this PREGION is disabled + Disabled = 0x0, + /// Write access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in PREGION[1] + PRGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this PREGION is disabled + Disabled = 0x0, + /// Read access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + /// Disable regions watch + REGIONENCLR: mmio.Mmio(packed struct(u32) { + /// Disable write access watch in region[0] + RGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in region[0] + RGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable write access watch in region[1] + RGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in region[1] + RGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable write access watch in region[2] + RGN2WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in region[2] + RGN2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable write access watch in region[3] + RGN3WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in region[3] + RGN3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Disable write access watch in PREGION[0] + PRGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this PREGION is disabled + Disabled = 0x0, + /// Write access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in PREGION[0] + PRGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this PREGION is disabled + Disabled = 0x0, + /// Read access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Disable write access watch in PREGION[1] + PRGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this PREGION is disabled + Disabled = 0x0, + /// Write access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in PREGION[1] + PRGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this PREGION is disabled + Disabled = 0x0, + /// Read access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + }; + + /// Programmable Peripheral Interconnect + pub const PPI = extern struct { + reserved1280: [1280]u8, + /// Channel enable register + CHEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable channel 0 + CH0: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 1 + CH1: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 2 + CH2: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 3 + CH3: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 4 + CH4: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 5 + CH5: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 6 + CH6: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 7 + CH7: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 8 + CH8: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 9 + CH9: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 10 + CH10: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 11 + CH11: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 12 + CH12: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 13 + CH13: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 14 + CH14: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 15 + CH15: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 16 + CH16: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 17 + CH17: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 18 + CH18: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 19 + CH19: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 20 + CH20: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 21 + CH21: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 22 + CH22: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 23 + CH23: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 24 + CH24: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 25 + CH25: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 26 + CH26: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 27 + CH27: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 28 + CH28: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 29 + CH29: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 30 + CH30: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 31 + CH31: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + }), + /// Channel enable set register + CHENSET: mmio.Mmio(packed struct(u32) { + /// Channel 0 enable set register. Writing '0' has no effect + CH0: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 1 enable set register. Writing '0' has no effect + CH1: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 2 enable set register. Writing '0' has no effect + CH2: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 3 enable set register. Writing '0' has no effect + CH3: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 4 enable set register. Writing '0' has no effect + CH4: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 5 enable set register. Writing '0' has no effect + CH5: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 6 enable set register. Writing '0' has no effect + CH6: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 7 enable set register. Writing '0' has no effect + CH7: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 8 enable set register. Writing '0' has no effect + CH8: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 9 enable set register. Writing '0' has no effect + CH9: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 10 enable set register. Writing '0' has no effect + CH10: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 11 enable set register. Writing '0' has no effect + CH11: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 12 enable set register. Writing '0' has no effect + CH12: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 13 enable set register. Writing '0' has no effect + CH13: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 14 enable set register. Writing '0' has no effect + CH14: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 15 enable set register. Writing '0' has no effect + CH15: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 16 enable set register. Writing '0' has no effect + CH16: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 17 enable set register. Writing '0' has no effect + CH17: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 18 enable set register. Writing '0' has no effect + CH18: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 19 enable set register. Writing '0' has no effect + CH19: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 20 enable set register. Writing '0' has no effect + CH20: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 21 enable set register. Writing '0' has no effect + CH21: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 22 enable set register. Writing '0' has no effect + CH22: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 23 enable set register. Writing '0' has no effect + CH23: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 24 enable set register. Writing '0' has no effect + CH24: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 25 enable set register. Writing '0' has no effect + CH25: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 26 enable set register. Writing '0' has no effect + CH26: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 27 enable set register. Writing '0' has no effect + CH27: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 28 enable set register. Writing '0' has no effect + CH28: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 29 enable set register. Writing '0' has no effect + CH29: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 30 enable set register. Writing '0' has no effect + CH30: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 31 enable set register. Writing '0' has no effect + CH31: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + }), + /// Channel enable clear register + CHENCLR: mmio.Mmio(packed struct(u32) { + /// Channel 0 enable clear register. Writing '0' has no effect + CH0: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 1 enable clear register. Writing '0' has no effect + CH1: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 2 enable clear register. Writing '0' has no effect + CH2: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 3 enable clear register. Writing '0' has no effect + CH3: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 4 enable clear register. Writing '0' has no effect + CH4: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 5 enable clear register. Writing '0' has no effect + CH5: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 6 enable clear register. Writing '0' has no effect + CH6: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 7 enable clear register. Writing '0' has no effect + CH7: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 8 enable clear register. Writing '0' has no effect + CH8: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 9 enable clear register. Writing '0' has no effect + CH9: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 10 enable clear register. Writing '0' has no effect + CH10: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 11 enable clear register. Writing '0' has no effect + CH11: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 12 enable clear register. Writing '0' has no effect + CH12: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 13 enable clear register. Writing '0' has no effect + CH13: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 14 enable clear register. Writing '0' has no effect + CH14: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 15 enable clear register. Writing '0' has no effect + CH15: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 16 enable clear register. Writing '0' has no effect + CH16: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 17 enable clear register. Writing '0' has no effect + CH17: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 18 enable clear register. Writing '0' has no effect + CH18: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 19 enable clear register. Writing '0' has no effect + CH19: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 20 enable clear register. Writing '0' has no effect + CH20: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 21 enable clear register. Writing '0' has no effect + CH21: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 22 enable clear register. Writing '0' has no effect + CH22: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 23 enable clear register. Writing '0' has no effect + CH23: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 24 enable clear register. Writing '0' has no effect + CH24: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 25 enable clear register. Writing '0' has no effect + CH25: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 26 enable clear register. Writing '0' has no effect + CH26: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 27 enable clear register. Writing '0' has no effect + CH27: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 28 enable clear register. Writing '0' has no effect + CH28: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 29 enable clear register. Writing '0' has no effect + CH29: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 30 enable clear register. Writing '0' has no effect + CH30: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 31 enable clear register. Writing '0' has no effect + CH31: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + }), + reserved2048: [756]u8, + /// Description collection[0]: Channel group 0 + CHG: [6]mmio.Mmio(packed struct(u32) { + /// Include or exclude channel 0 + CH0: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 1 + CH1: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 2 + CH2: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 3 + CH3: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 4 + CH4: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 5 + CH5: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 6 + CH6: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 7 + CH7: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 8 + CH8: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 9 + CH9: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 10 + CH10: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 11 + CH11: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 12 + CH12: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 13 + CH13: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 14 + CH14: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 15 + CH15: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 16 + CH16: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 17 + CH17: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 18 + CH18: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 19 + CH19: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 20 + CH20: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 21 + CH21: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 22 + CH22: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 23 + CH23: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 24 + CH24: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 25 + CH25: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 26 + CH26: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 27 + CH27: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 28 + CH28: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 29 + CH29: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 30 + CH30: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 31 + CH31: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + }), + }; + + /// NFC-A compatible radio + pub const NFCT = extern struct { + /// Activate NFC peripheral for incoming and outgoing frames, change state to activated + TASKS_ACTIVATE: u32, + /// Disable NFC peripheral + TASKS_DISABLE: u32, + /// Enable NFC sense field mode, change state to sense mode + TASKS_SENSE: u32, + /// Start transmission of a outgoing frame, change state to transmit + TASKS_STARTTX: u32, + reserved28: [12]u8, + /// Initializes the EasyDMA for receive. + TASKS_ENABLERXDATA: u32, + reserved36: [4]u8, + /// Force state machine to IDLE state + TASKS_GOIDLE: u32, + /// Force state machine to SLEEP_A state + TASKS_GOSLEEP: u32, + reserved256: [212]u8, + /// The NFC peripheral is ready to receive and send frames + EVENTS_READY: u32, + /// Remote NFC field detected + EVENTS_FIELDDETECTED: u32, + /// Remote NFC field lost + EVENTS_FIELDLOST: u32, + /// Marks the start of the first symbol of a transmitted frame + EVENTS_TXFRAMESTART: u32, + /// Marks the end of the last transmitted on-air symbol of a frame + EVENTS_TXFRAMEEND: u32, + /// Marks the end of the first symbol of a received frame + EVENTS_RXFRAMESTART: u32, + /// Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + EVENTS_RXFRAMEEND: u32, + /// NFC error reported. The ERRORSTATUS register contains details on the source of the error. + EVENTS_ERROR: u32, + reserved296: [8]u8, + /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + EVENTS_RXERROR: u32, + /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + EVENTS_ENDRX: u32, + /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + EVENTS_ENDTX: u32, + reserved312: [4]u8, + /// Auto collision resolution process has started + EVENTS_AUTOCOLRESSTARTED: u32, + reserved328: [12]u8, + /// NFC Auto collision resolution error reported. + EVENTS_COLLISION: u32, + /// NFC Auto collision resolution successfully completed + EVENTS_SELECTED: u32, + /// EasyDMA is ready to receive or send frames. + EVENTS_STARTED: u32, + reserved512: [172]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between FIELDDETECTED event and ACTIVATE task + FIELDDETECTED_ACTIVATE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between FIELDLOST event and SENSE task + FIELDLOST_SENSE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u30, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for FIELDDETECTED event + FIELDDETECTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for FIELDLOST event + FIELDLOST: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TXFRAMESTART event + TXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for TXFRAMEEND event + TXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for RXFRAMESTART event + RXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for RXFRAMEEND event + RXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved10: u2, + /// Enable or disable interrupt for RXERROR event + RXERROR: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for ENDRX event + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for ENDTX event + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved14: u1, + /// Enable or disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved18: u3, + /// Enable or disable interrupt for COLLISION event + COLLISION: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for SELECTED event + SELECTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for STARTED event + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u11, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for FIELDDETECTED event + FIELDDETECTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for FIELDLOST event + FIELDLOST: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TXFRAMESTART event + TXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for TXFRAMEEND event + TXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for RXFRAMESTART event + RXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for RXFRAMEEND event + RXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u2, + /// Write '1' to Enable interrupt for RXERROR event + RXERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved14: u1, + /// Write '1' to Enable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u3, + /// Write '1' to Enable interrupt for COLLISION event + COLLISION: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for SELECTED event + SELECTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for STARTED event + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u11, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for FIELDDETECTED event + FIELDDETECTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for FIELDLOST event + FIELDLOST: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TXFRAMESTART event + TXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for TXFRAMEEND event + TXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for RXFRAMESTART event + RXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for RXFRAMEEND event + RXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u2, + /// Write '1' to Disable interrupt for RXERROR event + RXERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved14: u1, + /// Write '1' to Disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u3, + /// Write '1' to Disable interrupt for COLLISION event + COLLISION: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for SELECTED event + SELECTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for STARTED event + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u11, + }), + reserved1028: [248]u8, + /// NFC Error Status register + ERRORSTATUS: mmio.Mmio(packed struct(u32) { + /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + FRAMEDELAYTIMEOUT: u1, + reserved2: u1, + /// Field level is too high at max load resistance + NFCFIELDTOOSTRONG: u1, + /// Field level is too low at min load resistance + NFCFIELDTOOWEAK: u1, + padding: u28, + }), + reserved1072: [40]u8, + /// Current value driven to the NFC Load Control + CURRENTLOADCTRL: mmio.Mmio(packed struct(u32) { + /// Current value driven to the NFC Load Control + CURRENTLOADCTRL: u6, + padding: u26, + }), + reserved1084: [8]u8, + /// Indicates the presence or not of a valid field + FIELDPRESENT: mmio.Mmio(packed struct(u32) { + /// Indicates the presence or not of a valid field. Available only in the activated state. + FIELDPRESENT: packed union { + raw: u1, + value: enum(u1) { + /// No valid field detected + NoField = 0x0, + /// Valid field detected + FieldPresent = 0x1, + }, + }, + /// Indicates if the low level has locked to the field + LOCKDETECT: packed union { + raw: u1, + value: enum(u1) { + /// Not locked to field + NotLocked = 0x0, + /// Locked to field + Locked = 0x1, + }, + }, + padding: u30, + }), + reserved1284: [196]u8, + /// Minimum frame delay + FRAMEDELAYMIN: mmio.Mmio(packed struct(u32) { + /// Minimum frame delay in number of 13.56 MHz clocks + FRAMEDELAYMIN: u16, + padding: u16, + }), + /// Maximum frame delay + FRAMEDELAYMAX: mmio.Mmio(packed struct(u32) { + /// Maximum frame delay in number of 13.56 MHz clocks + FRAMEDELAYMAX: u16, + padding: u16, + }), + /// Configuration register for the Frame Delay Timer + FRAMEDELAYMODE: mmio.Mmio(packed struct(u32) { + /// Configuration register for the Frame Delay Timer + FRAMEDELAYMODE: packed union { + raw: u2, + value: enum(u2) { + /// Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + FreeRun = 0x0, + /// Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + Window = 0x1, + /// Frame is transmitted exactly at FRAMEDELAYMAX + ExactVal = 0x2, + /// Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + WindowGrid = 0x3, + }, + }, + padding: u30, + }), + /// Packet pointer for TXD and RXD data storage in Data RAM + PACKETPTR: mmio.Mmio(packed struct(u32) { + /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. + PTR: u32, + }), + /// Size of allocated for TXD and RXD data storage buffer in Data RAM + MAXLEN: mmio.Mmio(packed struct(u32) { + /// Size of allocated for TXD and RXD data storage buffer in Data RAM + MAXLEN: u9, + padding: u23, + }), + reserved1424: [120]u8, + /// Last NFCID1 part (4, 7 or 10 bytes ID) + NFCID1_LAST: mmio.Mmio(packed struct(u32) { + /// NFCID1 byte Z (very last byte sent) + NFCID1_Z: u8, + /// NFCID1 byte Y + NFCID1_Y: u8, + /// NFCID1 byte X + NFCID1_X: u8, + /// NFCID1 byte W + NFCID1_W: u8, + }), + /// Second last NFCID1 part (7 or 10 bytes ID) + NFCID1_2ND_LAST: mmio.Mmio(packed struct(u32) { + /// NFCID1 byte V + NFCID1_V: u8, + /// NFCID1 byte U + NFCID1_U: u8, + /// NFCID1 byte T + NFCID1_T: u8, + padding: u8, + }), + /// Third last NFCID1 part (10 bytes ID) + NFCID1_3RD_LAST: mmio.Mmio(packed struct(u32) { + /// NFCID1 byte S + NFCID1_S: u8, + /// NFCID1 byte R + NFCID1_R: u8, + /// NFCID1 byte Q + NFCID1_Q: u8, + padding: u8, + }), + reserved1440: [4]u8, + /// NFC-A SENS_RES auto-response settings + SENSRES: mmio.Mmio(packed struct(u32) { + /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + BITFRAMESDD: packed union { + raw: u5, + value: enum(u5) { + /// SDD pattern 00000 + SDD00000 = 0x0, + /// SDD pattern 00001 + SDD00001 = 0x1, + /// SDD pattern 00010 + SDD00010 = 0x2, + /// SDD pattern 00100 + SDD00100 = 0x4, + /// SDD pattern 01000 + SDD01000 = 0x8, + /// SDD pattern 10000 + SDD10000 = 0x10, + _, + }, + }, + /// Reserved for future use. Shall be 0. + RFU5: u1, + /// NFCID1 size. This value is used by the Auto collision resolution engine. + NFCIDSIZE: packed union { + raw: u2, + value: enum(u2) { + /// NFCID1 size: single (4 bytes) + NFCID1Single = 0x0, + /// NFCID1 size: double (7 bytes) + NFCID1Double = 0x1, + /// NFCID1 size: triple (10 bytes) + NFCID1Triple = 0x2, + _, + }, + }, + /// Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + PLATFCONFIG: u4, + /// Reserved for future use. Shall be 0. + RFU74: u4, + padding: u16, + }), + /// NFC-A SEL_RES auto-response settings + SELRES: mmio.Mmio(packed struct(u32) { + /// Reserved for future use. Shall be 0. + RFU10: u2, + /// Cascade bit (controlled by hardware, write has no effect) + CASCADE: packed union { + raw: u1, + value: enum(u1) { + /// NFCID1 complete + Complete = 0x0, + /// NFCID1 not complete + NotComplete = 0x1, + }, + }, + /// Reserved for future use. Shall be 0. + RFU43: u2, + /// Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + PROTOCOL: u2, + /// Reserved for future use. Shall be 0. + RFU7: u1, + padding: u24, + }), + }; + + /// GPIO Tasks and Events + pub const GPIOTE = extern struct { + /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. + TASKS_OUT: [8]u32, + reserved48: [16]u8, + /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high. + TASKS_SET: [8]u32, + reserved96: [16]u8, + /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low. + TASKS_CLR: [8]u32, + reserved256: [128]u8, + /// Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL + EVENTS_IN: [8]u32, + reserved380: [92]u8, + /// Event generated from multiple input GPIO pins with SENSE mechanism enabled + EVENTS_PORT: u32, + reserved772: [388]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for IN[0] event + IN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for IN[1] event + IN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for IN[2] event + IN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for IN[3] event + IN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for IN[4] event + IN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for IN[5] event + IN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for IN[6] event + IN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for IN[7] event + IN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved31: u23, + /// Write '1' to Enable interrupt for PORT event + PORT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for IN[0] event + IN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for IN[1] event + IN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for IN[2] event + IN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for IN[3] event + IN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for IN[4] event + IN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for IN[5] event + IN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for IN[6] event + IN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for IN[7] event + IN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved31: u23, + /// Write '1' to Disable interrupt for PORT event + PORT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + }), + reserved1296: [516]u8, + /// Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + CONFIG: [8]mmio.Mmio(packed struct(u32) { + /// Mode + MODE: packed union { + raw: u2, + value: enum(u2) { + /// Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + Disabled = 0x0, + /// Event mode + Event = 0x1, + /// Task mode + Task = 0x3, + _, + }, + }, + reserved8: u6, + /// GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + PSEL: u5, + reserved16: u3, + /// When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + POLARITY: packed union { + raw: u2, + value: enum(u2) { + /// Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + None = 0x0, + /// Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + LoToHi = 0x1, + /// Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + HiToLo = 0x2, + /// Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + Toggle = 0x3, + }, + }, + reserved20: u2, + /// When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + OUTINIT: packed union { + raw: u1, + value: enum(u1) { + /// Task mode: Initial value of pin before task triggering is low + Low = 0x0, + /// Task mode: Initial value of pin before task triggering is high + High = 0x1, + }, + }, + padding: u11, + }), + }; + + /// Analog to Digital Converter + pub const SAADC = extern struct { + /// Start the ADC and prepare the result buffer in RAM + TASKS_START: u32, + /// Take one ADC sample, if scan is enabled all channels are sampled + TASKS_SAMPLE: u32, + /// Stop the ADC and terminate any on-going conversion + TASKS_STOP: u32, + /// Starts offset auto-calibration + TASKS_CALIBRATEOFFSET: u32, + reserved256: [240]u8, + /// The ADC has started + EVENTS_STARTED: u32, + /// The ADC has filled up the Result buffer + EVENTS_END: u32, + /// A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + EVENTS_DONE: u32, + /// A result is ready to get transferred to RAM. + EVENTS_RESULTDONE: u32, + /// Calibration is complete + EVENTS_CALIBRATEDONE: u32, + /// The ADC has stopped + EVENTS_STOPPED: u32, + reserved768: [488]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for STARTED event + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for DONE event + DONE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for RESULTDONE event + RESULTDONE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CALIBRATEDONE event + CALIBRATEDONE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[0].LIMITH event + CH0LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[0].LIMITL event + CH0LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[1].LIMITH event + CH1LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[1].LIMITL event + CH1LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[2].LIMITH event + CH2LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[2].LIMITL event + CH2LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[3].LIMITH event + CH3LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[3].LIMITL event + CH3LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[4].LIMITH event + CH4LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[4].LIMITL event + CH4LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[5].LIMITH event + CH5LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[5].LIMITL event + CH5LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[6].LIMITH event + CH6LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[6].LIMITL event + CH6LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[7].LIMITH event + CH7LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CH[7].LIMITL event + CH7LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u10, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for STARTED event + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for DONE event + DONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for RESULTDONE event + RESULTDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CALIBRATEDONE event + CALIBRATEDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[0].LIMITH event + CH0LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[0].LIMITL event + CH0LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[1].LIMITH event + CH1LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[1].LIMITL event + CH1LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[2].LIMITH event + CH2LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[2].LIMITL event + CH2LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[3].LIMITH event + CH3LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[3].LIMITL event + CH3LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[4].LIMITH event + CH4LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[4].LIMITL event + CH4LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[5].LIMITH event + CH5LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[5].LIMITL event + CH5LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[6].LIMITH event + CH6LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[6].LIMITL event + CH6LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[7].LIMITH event + CH7LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CH[7].LIMITL event + CH7LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u10, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for STARTED event + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for DONE event + DONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for RESULTDONE event + RESULTDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CALIBRATEDONE event + CALIBRATEDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[0].LIMITH event + CH0LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[0].LIMITL event + CH0LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[1].LIMITH event + CH1LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[1].LIMITL event + CH1LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[2].LIMITH event + CH2LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[2].LIMITL event + CH2LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[3].LIMITH event + CH3LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[3].LIMITL event + CH3LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[4].LIMITH event + CH4LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[4].LIMITL event + CH4LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[5].LIMITH event + CH5LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[5].LIMITL event + CH5LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[6].LIMITH event + CH6LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[6].LIMITL event + CH6LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[7].LIMITH event + CH7LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CH[7].LIMITL event + CH7LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u10, + }), + reserved1024: [244]u8, + /// Status + STATUS: mmio.Mmio(packed struct(u32) { + /// Status + STATUS: packed union { + raw: u1, + value: enum(u1) { + /// ADC is ready. No on-going conversion. + Ready = 0x0, + /// ADC is busy. Conversion in progress. + Busy = 0x1, + }, + }, + padding: u31, + }), + reserved1280: [252]u8, + /// Enable or disable ADC + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable ADC + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable ADC + Disabled = 0x0, + /// Enable ADC + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1520: [236]u8, + /// Resolution configuration + RESOLUTION: mmio.Mmio(packed struct(u32) { + /// Set the resolution + VAL: packed union { + raw: u3, + value: enum(u3) { + /// 8 bit + @"8bit" = 0x0, + /// 10 bit + @"10bit" = 0x1, + /// 12 bit + @"12bit" = 0x2, + /// 14 bit + @"14bit" = 0x3, + _, + }, + }, + padding: u29, + }), + /// Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + OVERSAMPLE: mmio.Mmio(packed struct(u32) { + /// Oversample control + OVERSAMPLE: packed union { + raw: u4, + value: enum(u4) { + /// Bypass oversampling + Bypass = 0x0, + /// Oversample 2x + Over2x = 0x1, + /// Oversample 4x + Over4x = 0x2, + /// Oversample 8x + Over8x = 0x3, + /// Oversample 16x + Over16x = 0x4, + /// Oversample 32x + Over32x = 0x5, + /// Oversample 64x + Over64x = 0x6, + /// Oversample 128x + Over128x = 0x7, + /// Oversample 256x + Over256x = 0x8, + _, + }, + }, + padding: u28, + }), + /// Controls normal or continuous sample rate + SAMPLERATE: mmio.Mmio(packed struct(u32) { + /// Capture and compare value. Sample rate is 16 MHz/CC + CC: u11, + reserved12: u1, + /// Select mode for sample rate control + MODE: packed union { + raw: u1, + value: enum(u1) { + /// Rate is controlled from SAMPLE task + Task = 0x0, + /// Rate is controlled from local timer (use CC to control the rate) + Timers = 0x1, + }, + }, + padding: u19, + }), + }; + + /// Timer/Counter 0 + pub const TIMER0 = extern struct { + /// Start Timer + TASKS_START: u32, + /// Stop Timer + TASKS_STOP: u32, + /// Increment Timer (Counter mode only) + TASKS_COUNT: u32, + /// Clear time + TASKS_CLEAR: u32, + /// Deprecated register - Shut down timer + TASKS_SHUTDOWN: u32, + reserved64: [44]u8, + /// Description collection[0]: Capture Timer value to CC[0] register + TASKS_CAPTURE: [6]u32, + reserved320: [232]u8, + /// Description collection[0]: Compare event on CC[0] match + EVENTS_COMPARE: [6]u32, + reserved512: [168]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + reserved8: u2, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u18, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u10, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u10, + }), + reserved1284: [504]u8, + /// Timer mode selection + MODE: mmio.Mmio(packed struct(u32) { + /// Timer mode + MODE: packed union { + raw: u2, + value: enum(u2) { + /// Select Timer mode + Timer = 0x0, + /// Deprecated enumerator - Select Counter mode + Counter = 0x1, + /// Select Low Power Counter mode + LowPowerCounter = 0x2, + _, + }, + }, + padding: u30, + }), + /// Configure the number of bits used by the TIMER + BITMODE: mmio.Mmio(packed struct(u32) { + /// Timer bit width + BITMODE: packed union { + raw: u2, + value: enum(u2) { + /// 16 bit timer bit width + @"16Bit" = 0x0, + /// 8 bit timer bit width + @"08Bit" = 0x1, + /// 24 bit timer bit width + @"24Bit" = 0x2, + /// 32 bit timer bit width + @"32Bit" = 0x3, + }, + }, + padding: u30, + }), + reserved1296: [4]u8, + /// Timer prescaler register + PRESCALER: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PRESCALER: u4, + padding: u28, + }), + reserved1344: [44]u8, + /// Description collection[0]: Capture/Compare register 0 + CC: [6]mmio.Mmio(packed struct(u32) { + /// Capture/Compare value + CC: u32, + }), + }; + + /// Non Volatile Memory Controller + pub const NVMC = extern struct { + reserved1024: [1024]u8, + /// Ready flag + READY: mmio.Mmio(packed struct(u32) { + /// NVMC is ready or busy + READY: packed union { + raw: u1, + value: enum(u1) { + /// NVMC is busy (on-going write or erase operation) + Busy = 0x0, + /// NVMC is ready + Ready = 0x1, + }, + }, + padding: u31, + }), + reserved1284: [256]u8, + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + WEN: packed union { + raw: u2, + value: enum(u2) { + /// Read only access + Ren = 0x0, + /// Write Enabled + Wen = 0x1, + /// Erase enabled + Een = 0x2, + _, + }, + }, + padding: u30, + }), + /// Register for erasing a page in Code area + ERASEPAGE: mmio.Mmio(packed struct(u32) { + /// Register for starting erase of a page in Code area + ERASEPAGE: u32, + }), + /// Register for erasing all non-volatile user memory + ERASEALL: mmio.Mmio(packed struct(u32) { + /// Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. + ERASEALL: packed union { + raw: u1, + value: enum(u1) { + /// No operation + NoOperation = 0x0, + /// Start chip erase + Erase = 0x1, + }, + }, + padding: u31, + }), + /// Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. + ERASEPCR0: mmio.Mmio(packed struct(u32) { + /// Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. + ERASEPCR0: u32, + }), + /// Register for erasing User Information Configuration Registers + ERASEUICR: mmio.Mmio(packed struct(u32) { + /// Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. + ERASEUICR: packed union { + raw: u1, + value: enum(u1) { + /// No operation + NoOperation = 0x0, + /// Start erase of UICR + Erase = 0x1, + }, + }, + padding: u31, + }), + reserved1344: [40]u8, + /// I-Code cache configuration register. + ICACHECNF: mmio.Mmio(packed struct(u32) { + /// Cache enable + CACHEEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable cache. Invalidates all cache entries. + Disabled = 0x0, + /// Enable cache + Enabled = 0x1, + }, + }, + reserved8: u7, + /// Cache profiling enable + CACHEPROFEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable cache profiling + Disabled = 0x0, + /// Enable cache profiling + Enabled = 0x1, + }, + }, + padding: u23, + }), + reserved1352: [4]u8, + /// I-Code cache hit counter. + IHIT: mmio.Mmio(packed struct(u32) { + /// Number of cache hits + HITS: u32, + }), + /// I-Code cache miss counter. + IMISS: mmio.Mmio(packed struct(u32) { + /// Number of cache misses + MISSES: u32, + }), + }; + + /// Pulse Density Modulation (Digital Microphone) Interface + pub const PDM = extern struct { + /// Starts continuous PDM transfer + TASKS_START: u32, + /// Stops PDM transfer + TASKS_STOP: u32, + reserved256: [248]u8, + /// PDM transfer has started + EVENTS_STARTED: u32, + /// PDM transfer has finished + EVENTS_STOPPED: u32, + /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + EVENTS_END: u32, + reserved768: [500]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for STARTED event + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u29, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for STARTED event + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for STARTED event + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + reserved1280: [500]u8, + /// PDM module enable register + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable PDM module + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// PDM clock generator control + PDMCLKCTRL: mmio.Mmio(packed struct(u32) { + /// PDM_CLK frequency + FREQ: packed union { + raw: u32, + value: enum(u32) { + /// PDM_CLK = 32 MHz / 32 = 1.000 MHz + @"1000K" = 0x8000000, + /// PDM_CLK = 32 MHz / 31 = 1.032 MHz + Default = 0x8400000, + /// PDM_CLK = 32 MHz / 30 = 1.067 MHz + @"1067K" = 0x8800000, + _, + }, + }, + }), + /// Defines the routing of the connected PDM microphones' signals + MODE: mmio.Mmio(packed struct(u32) { + /// Mono or stereo operation + OPERATION: packed union { + raw: u1, + value: enum(u1) { + /// Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] + Stereo = 0x0, + /// Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] + Mono = 0x1, + }, + }, + /// Defines on which PDM_CLK edge Left (or mono) is sampled + EDGE: packed union { + raw: u1, + value: enum(u1) { + /// Left (or mono) is sampled on falling edge of PDM_CLK + LeftFalling = 0x0, + /// Left (or mono) is sampled on rising edge of PDM_CLK + LeftRising = 0x1, + }, + }, + padding: u30, + }), + reserved1304: [12]u8, + /// Left output gain adjustment + GAINL: mmio.Mmio(packed struct(u32) { + /// Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + GAINL: packed union { + raw: u7, + value: enum(u7) { + /// -20dB gain adjustment (minimum) + MinGain = 0x0, + /// 0dB gain adjustment ('2500 RMS' requirement) + DefaultGain = 0x28, + /// +20dB gain adjustment (maximum) + MaxGain = 0x50, + _, + }, + }, + padding: u25, + }), + /// Right output gain adjustment + GAINR: mmio.Mmio(packed struct(u32) { + /// Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + GAINR: packed union { + raw: u8, + value: enum(u8) { + /// -20dB gain adjustment (minimum) + MinGain = 0x0, + /// 0dB gain adjustment ('2500 RMS' requirement) + DefaultGain = 0x28, + /// +20dB gain adjustment (maximum) + MaxGain = 0x50, + _, + }, + }, + padding: u24, + }), + }; + + /// Real time counter 0 + pub const RTC0 = extern struct { + /// Start RTC COUNTER + TASKS_START: u32, + /// Stop RTC COUNTER + TASKS_STOP: u32, + /// Clear RTC COUNTER + TASKS_CLEAR: u32, + /// Set COUNTER to 0xFFFFF0 + TASKS_TRIGOVRFLW: u32, + reserved256: [240]u8, + /// Event on COUNTER increment + EVENTS_TICK: u32, + /// Event on COUNTER overflow + EVENTS_OVRFLW: u32, + reserved320: [56]u8, + /// Description collection[0]: Compare event on CC[0] match + EVENTS_COMPARE: [4]u32, + reserved772: [436]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for TICK event + TICK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved16: u14, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for TICK event + TICK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved16: u14, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + reserved832: [52]u8, + /// Enable or disable event routing + EVTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable event routing for TICK event + TICK: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable event routing for OVRFLW event + OVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved16: u14, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u12, + }), + /// Enable event routing + EVTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable event routing for TICK event + TICK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved16: u14, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + /// Disable event routing + EVTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable event routing for TICK event + TICK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved16: u14, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + reserved1284: [440]u8, + /// Current COUNTER value + COUNTER: mmio.Mmio(packed struct(u32) { + /// Counter value + COUNTER: u24, + padding: u8, + }), + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + PRESCALER: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PRESCALER: u12, + padding: u20, + }), + reserved1344: [52]u8, + /// Description collection[0]: Compare register 0 + CC: [4]mmio.Mmio(packed struct(u32) { + /// Compare value + COMPARE: u24, + padding: u8, + }), + }; + + /// Temperature Sensor + pub const TEMP = extern struct { + /// Start temperature measurement + TASKS_START: u32, + /// Stop temperature measurement + TASKS_STOP: u32, + reserved256: [248]u8, + /// Temperature measurement complete, data ready + EVENTS_DATARDY: u32, + reserved772: [512]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for DATARDY event + DATARDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for DATARDY event + DATARDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1288: [508]u8, + /// Temperature in degC (0.25deg steps) + TEMP: mmio.Mmio(packed struct(u32) { + /// Temperature in degC (0.25deg steps) + TEMP: u32, + }), + reserved1312: [20]u8, + /// Slope of 1st piece wise linear function + A0: mmio.Mmio(packed struct(u32) { + /// Slope of 1st piece wise linear function + A0: u12, + padding: u20, + }), + /// Slope of 2nd piece wise linear function + A1: mmio.Mmio(packed struct(u32) { + /// Slope of 2nd piece wise linear function + A1: u12, + padding: u20, + }), + /// Slope of 3rd piece wise linear function + A2: mmio.Mmio(packed struct(u32) { + /// Slope of 3rd piece wise linear function + A2: u12, + padding: u20, + }), + /// Slope of 4th piece wise linear function + A3: mmio.Mmio(packed struct(u32) { + /// Slope of 4th piece wise linear function + A3: u12, + padding: u20, + }), + /// Slope of 5th piece wise linear function + A4: mmio.Mmio(packed struct(u32) { + /// Slope of 5th piece wise linear function + A4: u12, + padding: u20, + }), + /// Slope of 6th piece wise linear function + A5: mmio.Mmio(packed struct(u32) { + /// Slope of 6th piece wise linear function + A5: u12, + padding: u20, + }), + reserved1344: [8]u8, + /// y-intercept of 1st piece wise linear function + B0: mmio.Mmio(packed struct(u32) { + /// y-intercept of 1st piece wise linear function + B0: u14, + padding: u18, + }), + /// y-intercept of 2nd piece wise linear function + B1: mmio.Mmio(packed struct(u32) { + /// y-intercept of 2nd piece wise linear function + B1: u14, + padding: u18, + }), + /// y-intercept of 3rd piece wise linear function + B2: mmio.Mmio(packed struct(u32) { + /// y-intercept of 3rd piece wise linear function + B2: u14, + padding: u18, + }), + /// y-intercept of 4th piece wise linear function + B3: mmio.Mmio(packed struct(u32) { + /// y-intercept of 4th piece wise linear function + B3: u14, + padding: u18, + }), + /// y-intercept of 5th piece wise linear function + B4: mmio.Mmio(packed struct(u32) { + /// y-intercept of 5th piece wise linear function + B4: u14, + padding: u18, + }), + /// y-intercept of 6th piece wise linear function + B5: mmio.Mmio(packed struct(u32) { + /// y-intercept of 6th piece wise linear function + B5: u14, + padding: u18, + }), + reserved1376: [8]u8, + /// End point of 1st piece wise linear function + T0: mmio.Mmio(packed struct(u32) { + /// End point of 1st piece wise linear function + T0: u8, + padding: u24, + }), + /// End point of 2nd piece wise linear function + T1: mmio.Mmio(packed struct(u32) { + /// End point of 2nd piece wise linear function + T1: u8, + padding: u24, + }), + /// End point of 3rd piece wise linear function + T2: mmio.Mmio(packed struct(u32) { + /// End point of 3rd piece wise linear function + T2: u8, + padding: u24, + }), + /// End point of 4th piece wise linear function + T3: mmio.Mmio(packed struct(u32) { + /// End point of 4th piece wise linear function + T3: u8, + padding: u24, + }), + /// End point of 5th piece wise linear function + T4: mmio.Mmio(packed struct(u32) { + /// End point of 5th piece wise linear function + T4: u8, + padding: u24, + }), + }; + + /// Random Number Generator + pub const RNG = extern struct { + /// Task starting the random number generator + TASKS_START: u32, + /// Task stopping the random number generator + TASKS_STOP: u32, + reserved256: [248]u8, + /// Event being generated for every new random number written to the VALUE register + EVENTS_VALRDY: u32, + reserved512: [252]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between VALRDY event and STOP task + VALRDY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for VALRDY event + VALRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for VALRDY event + VALRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1284: [504]u8, + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Bias correction + DERCEN: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Output random number + VALUE: mmio.Mmio(packed struct(u32) { + /// Generated random number + VALUE: u8, + padding: u24, + }), + }; + + /// AES ECB Mode Encryption + pub const ECB = extern struct { + /// Start ECB block encrypt + TASKS_STARTECB: u32, + /// Abort a possible executing ECB operation + TASKS_STOPECB: u32, + reserved256: [248]u8, + /// ECB block encrypt complete + EVENTS_ENDECB: u32, + /// ECB block encrypt aborted because of a STOPECB task or due to an error + EVENTS_ERRORECB: u32, + reserved772: [508]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for ENDECB event + ENDECB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for ERRORECB event + ERRORECB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u30, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for ENDECB event + ENDECB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for ERRORECB event + ERRORECB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u30, + }), + reserved1284: [504]u8, + /// ECB block encrypt memory pointers + ECBDATAPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to the ECB data structure (see Table 1 ECB data structure overview) + ECBDATAPTR: u32, + }), + }; + + /// AES CCM Mode Encryption + pub const CCM = extern struct { + /// Start generation of key-stream. This operation will stop by itself when completed. + TASKS_KSGEN: u32, + /// Start encryption/decryption. This operation will stop by itself when completed. + TASKS_CRYPT: u32, + /// Stop encryption/decryption + TASKS_STOP: u32, + reserved256: [244]u8, + /// Key-stream generation complete + EVENTS_ENDKSGEN: u32, + /// Encrypt/decrypt complete + EVENTS_ENDCRYPT: u32, + /// CCM error event + EVENTS_ERROR: u32, + reserved512: [244]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between ENDKSGEN event and CRYPT task + ENDKSGEN_CRYPT: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for ENDKSGEN event + ENDKSGEN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for ENDCRYPT event + ENDCRYPT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for ENDKSGEN event + ENDKSGEN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for ENDCRYPT event + ENDCRYPT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for ERROR event + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + reserved1024: [244]u8, + /// MIC check result + MICSTATUS: mmio.Mmio(packed struct(u32) { + /// The result of the MIC check performed during the previous decryption operation + MICSTATUS: packed union { + raw: u1, + value: enum(u1) { + /// MIC check failed + CheckFailed = 0x0, + /// MIC check passed + CheckPassed = 0x1, + }, + }, + padding: u31, + }), + reserved1280: [252]u8, + /// Enable + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable CCM + ENABLE: packed union { + raw: u2, + value: enum(u2) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x2, + _, + }, + }, + padding: u30, + }), + /// Operation mode + MODE: mmio.Mmio(packed struct(u32) { + /// The mode of operation to be used + MODE: packed union { + raw: u1, + value: enum(u1) { + /// AES CCM packet encryption mode + Encryption = 0x0, + /// AES CCM packet decryption mode + Decryption = 0x1, + }, + }, + reserved16: u15, + /// Data rate that the CCM shall run in synch with + DATARATE: packed union { + raw: u1, + value: enum(u1) { + /// In synch with 1 Mbit data rate + @"1Mbit" = 0x0, + /// In synch with 2 Mbit data rate + @"2Mbit" = 0x1, + }, + }, + reserved24: u7, + /// Packet length configuration + LENGTH: packed union { + raw: u1, + value: enum(u1) { + /// Default length. Effective length of LENGTH field is 5-bit + Default = 0x0, + /// Extended length. Effective length of LENGTH field is 8-bit + Extended = 0x1, + }, + }, + padding: u7, + }), + /// Pointer to data structure holding AES key and NONCE vector + CNFPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + CNFPTR: u32, + }), + /// Input pointer + INPTR: mmio.Mmio(packed struct(u32) { + /// Input pointer + INPTR: u32, + }), + /// Output pointer + OUTPTR: mmio.Mmio(packed struct(u32) { + /// Output pointer + OUTPTR: u32, + }), + /// Pointer to data area used for temporary storage + SCRATCHPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. + SCRATCHPTR: u32, + }), + }; + + /// Accelerated Address Resolver + pub const AAR = extern struct { + /// Start resolving addresses based on IRKs specified in the IRK data structure + TASKS_START: u32, + reserved8: [4]u8, + /// Stop resolving addresses + TASKS_STOP: u32, + reserved256: [244]u8, + /// Address resolution procedure complete + EVENTS_END: u32, + /// Address resolved + EVENTS_RESOLVED: u32, + /// Address not resolved + EVENTS_NOTRESOLVED: u32, + reserved772: [504]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for RESOLVED event + RESOLVED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for NOTRESOLVED event + NOTRESOLVED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for END event + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for RESOLVED event + RESOLVED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for NOTRESOLVED event + NOTRESOLVED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + reserved1024: [244]u8, + /// Resolution status + STATUS: mmio.Mmio(packed struct(u32) { + /// The IRK that was used last time an address was resolved + STATUS: u4, + padding: u28, + }), + reserved1280: [252]u8, + /// Enable AAR + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable AAR + ENABLE: packed union { + raw: u2, + value: enum(u2) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x3, + _, + }, + }, + padding: u30, + }), + /// Number of IRKs + NIRK: mmio.Mmio(packed struct(u32) { + /// Number of Identity root keys available in the IRK data structure + NIRK: u5, + padding: u27, + }), + /// Pointer to IRK data structure + IRKPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to the IRK data structure + IRKPTR: u32, + }), + reserved1296: [4]u8, + /// Pointer to the resolvable address + ADDRPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to the resolvable address (6-bytes) + ADDRPTR: u32, + }), + /// Pointer to data area used for temporary storage + SCRATCHPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. + SCRATCHPTR: u32, + }), + }; + + /// Watchdog Timer + pub const WDT = extern struct { + /// Start the watchdog + TASKS_START: u32, + reserved256: [252]u8, + /// Watchdog timeout + EVENTS_TIMEOUT: u32, + reserved772: [512]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for TIMEOUT event + TIMEOUT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for TIMEOUT event + TIMEOUT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1024: [244]u8, + /// Run status + RUNSTATUS: mmio.Mmio(packed struct(u32) { + /// Indicates whether or not the watchdog is running + RUNSTATUS: packed union { + raw: u1, + value: enum(u1) { + /// Watchdog not running + NotRunning = 0x0, + /// Watchdog is running + Running = 0x1, + }, + }, + padding: u31, + }), + /// Request status + REQSTATUS: mmio.Mmio(packed struct(u32) { + /// Request status for RR[0] register + RR0: packed union { + raw: u1, + value: enum(u1) { + /// RR[0] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[0] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[1] register + RR1: packed union { + raw: u1, + value: enum(u1) { + /// RR[1] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[1] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[2] register + RR2: packed union { + raw: u1, + value: enum(u1) { + /// RR[2] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[2] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[3] register + RR3: packed union { + raw: u1, + value: enum(u1) { + /// RR[3] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[3] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[4] register + RR4: packed union { + raw: u1, + value: enum(u1) { + /// RR[4] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[4] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[5] register + RR5: packed union { + raw: u1, + value: enum(u1) { + /// RR[5] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[5] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[6] register + RR6: packed union { + raw: u1, + value: enum(u1) { + /// RR[6] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[6] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[7] register + RR7: packed union { + raw: u1, + value: enum(u1) { + /// RR[7] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[7] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + padding: u24, + }), + reserved1284: [252]u8, + /// Counter reload value + CRV: mmio.Mmio(packed struct(u32) { + /// Counter reload value in number of cycles of the 32.768 kHz clock + CRV: u32, + }), + /// Enable register for reload request registers + RREN: mmio.Mmio(packed struct(u32) { + /// Enable or disable RR[0] register + RR0: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[0] register + Disabled = 0x0, + /// Enable RR[0] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[1] register + RR1: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[1] register + Disabled = 0x0, + /// Enable RR[1] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[2] register + RR2: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[2] register + Disabled = 0x0, + /// Enable RR[2] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[3] register + RR3: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[3] register + Disabled = 0x0, + /// Enable RR[3] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[4] register + RR4: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[4] register + Disabled = 0x0, + /// Enable RR[4] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[5] register + RR5: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[5] register + Disabled = 0x0, + /// Enable RR[5] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[6] register + RR6: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[6] register + Disabled = 0x0, + /// Enable RR[6] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[7] register + RR7: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[7] register + Disabled = 0x0, + /// Enable RR[7] register + Enabled = 0x1, + }, + }, + padding: u24, + }), + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + SLEEP: packed union { + raw: u1, + value: enum(u1) { + /// Pause watchdog while the CPU is sleeping + Pause = 0x0, + /// Keep the watchdog running while the CPU is sleeping + Run = 0x1, + }, + }, + reserved3: u2, + /// Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + HALT: packed union { + raw: u1, + value: enum(u1) { + /// Pause watchdog while the CPU is halted by the debugger + Pause = 0x0, + /// Keep the watchdog running while the CPU is halted by the debugger + Run = 0x1, + }, + }, + padding: u28, + }), + reserved1536: [240]u8, + /// Description collection[0]: Reload request 0 + RR: [8]mmio.Mmio(packed struct(u32) { + /// Reload request register + RR: packed union { + raw: u32, + value: enum(u32) { + /// Value to request a reload of the watchdog timer + Reload = 0x6e524635, + _, + }, + }, + }), + }; + + /// Pulse Width Modulation Unit 0 + pub const PWM0 = extern struct { + reserved4: [4]u8, + /// Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + TASKS_STOP: u32, + /// Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running. + TASKS_SEQSTART: [2]u32, + /// Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running. + TASKS_NEXTSTEP: u32, + reserved260: [240]u8, + /// Response to STOP task, emitted when PWM pulses are no longer generated + EVENTS_STOPPED: u32, + /// Description collection[0]: First PWM period started on sequence 0 + EVENTS_SEQSTARTED: [2]u32, + /// Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter + EVENTS_SEQEND: [2]u32, + /// Emitted at the end of each PWM period + EVENTS_PWMPERIODEND: u32, + /// Concatenated sequences have been played the amount of times defined in LOOP.CNT + EVENTS_LOOPSDONE: u32, + reserved512: [224]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u24, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u24, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u24, + }), + reserved1280: [500]u8, + /// PWM module enable register + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable PWM module + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Selects operating mode of the wave counter + MODE: mmio.Mmio(packed struct(u32) { + /// Selects up or up and down as wave counter mode + UPDOWN: packed union { + raw: u1, + value: enum(u1) { + /// Up counter - edge aligned PWM duty-cycle + Up = 0x0, + /// Up and down counter - center aligned PWM duty cycle + UpAndDown = 0x1, + }, + }, + padding: u31, + }), + /// Value up to which the pulse generator counter counts + COUNTERTOP: mmio.Mmio(packed struct(u32) { + /// Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. + COUNTERTOP: u15, + padding: u17, + }), + /// Configuration for PWM_CLK + PRESCALER: mmio.Mmio(packed struct(u32) { + /// Pre-scaler of PWM_CLK + PRESCALER: packed union { + raw: u3, + value: enum(u3) { + /// Divide by 1 (16MHz) + DIV_1 = 0x0, + /// Divide by 2 ( 8MHz) + DIV_2 = 0x1, + /// Divide by 4 ( 4MHz) + DIV_4 = 0x2, + /// Divide by 8 ( 2MHz) + DIV_8 = 0x3, + /// Divide by 16 ( 1MHz) + DIV_16 = 0x4, + /// Divide by 32 ( 500kHz) + DIV_32 = 0x5, + /// Divide by 64 ( 250kHz) + DIV_64 = 0x6, + /// Divide by 128 ( 125kHz) + DIV_128 = 0x7, + }, + }, + padding: u29, + }), + /// Configuration of the decoder + DECODER: mmio.Mmio(packed struct(u32) { + /// How a sequence is read from RAM and spread to the compare register + LOAD: packed union { + raw: u2, + value: enum(u2) { + /// 1st half word (16-bit) used in all PWM channels 0..3 + Common = 0x0, + /// 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + Grouped = 0x1, + /// 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + Individual = 0x2, + /// 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + WaveForm = 0x3, + }, + }, + reserved8: u6, + /// Selects source for advancing the active sequence + MODE: packed union { + raw: u1, + value: enum(u1) { + /// SEQ[n].REFRESH is used to determine loading internal compare registers + RefreshCount = 0x0, + /// NEXTSTEP task causes a new value to be loaded to internal compare registers + NextStep = 0x1, + }, + }, + padding: u23, + }), + /// Amount of playback of a loop + LOOP: mmio.Mmio(packed struct(u32) { + /// Amount of playback of pattern cycles + CNT: packed union { + raw: u16, + value: enum(u16) { + /// Looping disabled (stop at the end of the sequence) + Disabled = 0x0, + _, + }, + }, + padding: u16, + }), + }; + + /// Quadrature Decoder + pub const QDEC = extern struct { + /// Task starting the quadrature decoder + TASKS_START: u32, + /// Task stopping the quadrature decoder + TASKS_STOP: u32, + /// Read and clear ACC and ACCDBL + TASKS_READCLRACC: u32, + /// Read and clear ACC + TASKS_RDCLRACC: u32, + /// Read and clear ACCDBL + TASKS_RDCLRDBL: u32, + reserved256: [236]u8, + /// Event being generated for every new sample value written to the SAMPLE register + EVENTS_SAMPLERDY: u32, + /// Non-null report ready + EVENTS_REPORTRDY: u32, + /// ACC or ACCDBL register overflow + EVENTS_ACCOF: u32, + /// Double displacement(s) detected + EVENTS_DBLRDY: u32, + /// QDEC has been stopped + EVENTS_STOPPED: u32, + reserved512: [236]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between REPORTRDY event and READCLRACC task + REPORTRDY_READCLRACC: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between SAMPLERDY event and STOP task + SAMPLERDY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between REPORTRDY event and RDCLRACC task + REPORTRDY_RDCLRACC: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between REPORTRDY event and STOP task + REPORTRDY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between DBLRDY event and RDCLRDBL task + DBLRDY_RDCLRDBL: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between DBLRDY event and STOP task + DBLRDY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between SAMPLERDY event and READCLRACC task + SAMPLERDY_READCLRACC: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u25, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for SAMPLERDY event + SAMPLERDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for REPORTRDY event + REPORTRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for ACCOF event + ACCOF: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for DBLRDY event + DBLRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u27, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for SAMPLERDY event + SAMPLERDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for REPORTRDY event + REPORTRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for ACCOF event + ACCOF: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for DBLRDY event + DBLRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved1280: [500]u8, + /// Enable the quadrature decoder + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable the quadrature decoder + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// LED output pin polarity + LEDPOL: mmio.Mmio(packed struct(u32) { + /// LED output pin polarity + LEDPOL: packed union { + raw: u1, + value: enum(u1) { + /// Led active on output pin low + ActiveLow = 0x0, + /// Led active on output pin high + ActiveHigh = 0x1, + }, + }, + padding: u31, + }), + /// Sample period + SAMPLEPER: mmio.Mmio(packed struct(u32) { + /// Sample period. The SAMPLE register will be updated for every new sample + SAMPLEPER: packed union { + raw: u4, + value: enum(u4) { + /// 128 us + @"128us" = 0x0, + /// 256 us + @"256us" = 0x1, + /// 512 us + @"512us" = 0x2, + /// 1024 us + @"1024us" = 0x3, + /// 2048 us + @"2048us" = 0x4, + /// 4096 us + @"4096us" = 0x5, + /// 8192 us + @"8192us" = 0x6, + /// 16384 us + @"16384us" = 0x7, + /// 32768 us + @"32ms" = 0x8, + /// 65536 us + @"65ms" = 0x9, + /// 131072 us + @"131ms" = 0xa, + _, + }, + }, + padding: u28, + }), + /// Motion sample value + SAMPLE: mmio.Mmio(packed struct(u32) { + /// Last motion sample + SAMPLE: u32, + }), + /// Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + REPORTPER: mmio.Mmio(packed struct(u32) { + /// Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + REPORTPER: packed union { + raw: u4, + value: enum(u4) { + /// 10 samples / report + @"10Smpl" = 0x0, + /// 40 samples / report + @"40Smpl" = 0x1, + /// 80 samples / report + @"80Smpl" = 0x2, + /// 120 samples / report + @"120Smpl" = 0x3, + /// 160 samples / report + @"160Smpl" = 0x4, + /// 200 samples / report + @"200Smpl" = 0x5, + /// 240 samples / report + @"240Smpl" = 0x6, + /// 280 samples / report + @"280Smpl" = 0x7, + /// 1 sample / report + @"1Smpl" = 0x8, + _, + }, + }, + padding: u28, + }), + /// Register accumulating the valid transitions + ACC: mmio.Mmio(packed struct(u32) { + /// Register accumulating all valid samples (not double transition) read from the SAMPLE register + ACC: u32, + }), + /// Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + ACCREAD: mmio.Mmio(packed struct(u32) { + /// Snapshot of the ACC register. + ACCREAD: u32, + }), + reserved1320: [12]u8, + /// Enable input debounce filters + DBFEN: mmio.Mmio(packed struct(u32) { + /// Enable input debounce filters + DBFEN: packed union { + raw: u1, + value: enum(u1) { + /// Debounce input filters disabled + Disabled = 0x0, + /// Debounce input filters enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1344: [20]u8, + /// Time period the LED is switched ON prior to sampling + LEDPRE: mmio.Mmio(packed struct(u32) { + /// Period in us the LED is switched on prior to sampling + LEDPRE: u9, + padding: u23, + }), + /// Register accumulating the number of detected double transitions + ACCDBL: mmio.Mmio(packed struct(u32) { + /// Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + ACCDBL: u4, + padding: u28, + }), + /// Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + ACCDBLREAD: mmio.Mmio(packed struct(u32) { + /// Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + ACCDBLREAD: u4, + padding: u28, + }), + }; + + /// Comparator + pub const COMP = extern struct { + /// Start comparator + TASKS_START: u32, + /// Stop comparator + TASKS_STOP: u32, + /// Sample comparator value + TASKS_SAMPLE: u32, + reserved256: [244]u8, + /// COMP is ready and output is valid + EVENTS_READY: u32, + /// Downward crossing + EVENTS_DOWN: u32, + /// Upward crossing + EVENTS_UP: u32, + /// Downward or upward crossing + EVENTS_CROSS: u32, + reserved512: [240]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between READY event and SAMPLE task + READY_SAMPLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between READY event and STOP task + READY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between DOWN event and STOP task + DOWN_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between UP event and STOP task + UP_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between CROSS event and STOP task + CROSS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for DOWN event + DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for UP event + UP: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for CROSS event + CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u28, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for DOWN event + DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for UP event + UP: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CROSS event + CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u28, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for DOWN event + DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for UP event + UP: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CROSS event + CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u28, + }), + reserved1024: [244]u8, + /// Compare result + RESULT: mmio.Mmio(packed struct(u32) { + /// Result of last compare. Decision point SAMPLE task. + RESULT: packed union { + raw: u1, + value: enum(u1) { + /// Input voltage is below the threshold (VIN+ < VIN-) + Below = 0x0, + /// Input voltage is above the threshold (VIN+ > VIN-) + Above = 0x1, + }, + }, + padding: u31, + }), + reserved1280: [252]u8, + /// COMP enable + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable COMP + ENABLE: packed union { + raw: u2, + value: enum(u2) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x2, + _, + }, + }, + padding: u30, + }), + /// Pin select + PSEL: mmio.Mmio(packed struct(u32) { + /// Analog pin select + PSEL: packed union { + raw: u3, + value: enum(u3) { + /// AIN0 selected as analog input + AnalogInput0 = 0x0, + /// AIN1 selected as analog input + AnalogInput1 = 0x1, + /// AIN2 selected as analog input + AnalogInput2 = 0x2, + /// AIN3 selected as analog input + AnalogInput3 = 0x3, + /// AIN4 selected as analog input + AnalogInput4 = 0x4, + /// AIN5 selected as analog input + AnalogInput5 = 0x5, + /// AIN6 selected as analog input + AnalogInput6 = 0x6, + /// AIN7 selected as analog input + AnalogInput7 = 0x7, + }, + }, + padding: u29, + }), + /// Reference source select for single-ended mode + REFSEL: mmio.Mmio(packed struct(u32) { + /// Reference select + REFSEL: packed union { + raw: u3, + value: enum(u3) { + /// VREF = internal 1.2 V reference (VDD >= 1.7 V) + Int1V2 = 0x0, + /// VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) + Int1V8 = 0x1, + /// VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) + Int2V4 = 0x2, + /// VREF = VDD + VDD = 0x4, + /// VREF = AREF (VDD >= VREF >= AREFMIN) + ARef = 0x7, + _, + }, + }, + padding: u29, + }), + /// External reference select + EXTREFSEL: mmio.Mmio(packed struct(u32) { + /// External analog reference select + EXTREFSEL: packed union { + raw: u3, + value: enum(u3) { + /// Use AIN0 as external analog reference + AnalogReference0 = 0x0, + /// Use AIN1 as external analog reference + AnalogReference1 = 0x1, + /// Use AIN2 as external analog reference + AnalogReference2 = 0x2, + /// Use AIN3 as external analog reference + AnalogReference3 = 0x3, + /// Use AIN4 as external analog reference + AnalogReference4 = 0x4, + /// Use AIN5 as external analog reference + AnalogReference5 = 0x5, + /// Use AIN6 as external analog reference + AnalogReference6 = 0x6, + /// Use AIN7 as external analog reference + AnalogReference7 = 0x7, + }, + }, + padding: u29, + }), + reserved1328: [32]u8, + /// Threshold configuration for hysteresis unit + TH: mmio.Mmio(packed struct(u32) { + /// VDOWN = (THDOWN+1)/64*VREF + THDOWN: u6, + reserved8: u2, + /// VUP = (THUP+1)/64*VREF + THUP: u6, + padding: u18, + }), + /// Mode configuration + MODE: mmio.Mmio(packed struct(u32) { + /// Speed and power modes + SP: packed union { + raw: u2, + value: enum(u2) { + /// Low-power mode + Low = 0x0, + /// Normal mode + Normal = 0x1, + /// High-speed mode + High = 0x2, + _, + }, + }, + reserved8: u6, + /// Main operation modes + MAIN: packed union { + raw: u1, + value: enum(u1) { + /// Single-ended mode + SE = 0x0, + /// Differential mode + Diff = 0x1, + }, + }, + padding: u23, + }), + /// Comparator hysteresis enable + HYST: mmio.Mmio(packed struct(u32) { + /// Comparator hysteresis + HYST: packed union { + raw: u1, + value: enum(u1) { + /// Comparator hysteresis disabled + NoHyst = 0x0, + /// Comparator hysteresis enabled + Hyst50mV = 0x1, + }, + }, + padding: u31, + }), + /// Current source select on analog input + ISOURCE: mmio.Mmio(packed struct(u32) { + /// Comparator hysteresis + ISOURCE: packed union { + raw: u2, + value: enum(u2) { + /// Current source disabled + Off = 0x0, + /// Current source enabled (+/- 2.5 uA) + Ien2mA5 = 0x1, + /// Current source enabled (+/- 5 uA) + Ien5mA = 0x2, + /// Current source enabled (+/- 10 uA) + Ien10mA = 0x3, + }, + }, + padding: u30, + }), + }; + + /// Low Power Comparator + pub const LPCOMP = extern struct { + /// Start comparator + TASKS_START: u32, + /// Stop comparator + TASKS_STOP: u32, + /// Sample comparator value + TASKS_SAMPLE: u32, + reserved256: [244]u8, + /// LPCOMP is ready and output is valid + EVENTS_READY: u32, + /// Downward crossing + EVENTS_DOWN: u32, + /// Upward crossing + EVENTS_UP: u32, + /// Downward or upward crossing + EVENTS_CROSS: u32, + reserved512: [240]u8, + /// Shortcut register + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between READY event and SAMPLE task + READY_SAMPLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between READY event and STOP task + READY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between DOWN event and STOP task + DOWN_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between UP event and STOP task + UP_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between CROSS event and STOP task + CROSS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to Enable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for DOWN event + DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for UP event + UP: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Enable interrupt for CROSS event + CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u28, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to Disable interrupt for READY event + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for DOWN event + DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for UP event + UP: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to Disable interrupt for CROSS event + CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u28, + }), + reserved1024: [244]u8, + /// Compare result + RESULT: mmio.Mmio(packed struct(u32) { + /// Result of last compare. Decision point SAMPLE task. + RESULT: packed union { + raw: u1, + value: enum(u1) { + /// Input voltage is below the reference threshold (VIN+ < VIN-). + Below = 0x0, + /// Input voltage is above the reference threshold (VIN+ > VIN-). + Above = 0x1, + }, + }, + padding: u31, + }), + reserved1280: [252]u8, + /// Enable LPCOMP + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable LPCOMP + ENABLE: packed union { + raw: u2, + value: enum(u2) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + _, + }, + }, + padding: u30, + }), + /// Input pin select + PSEL: mmio.Mmio(packed struct(u32) { + /// Analog pin select + PSEL: packed union { + raw: u3, + value: enum(u3) { + /// AIN0 selected as analog input + AnalogInput0 = 0x0, + /// AIN1 selected as analog input + AnalogInput1 = 0x1, + /// AIN2 selected as analog input + AnalogInput2 = 0x2, + /// AIN3 selected as analog input + AnalogInput3 = 0x3, + /// AIN4 selected as analog input + AnalogInput4 = 0x4, + /// AIN5 selected as analog input + AnalogInput5 = 0x5, + /// AIN6 selected as analog input + AnalogInput6 = 0x6, + /// AIN7 selected as analog input + AnalogInput7 = 0x7, + }, + }, + padding: u29, + }), + /// Reference select + REFSEL: mmio.Mmio(packed struct(u32) { + /// Reference select + REFSEL: packed union { + raw: u4, + value: enum(u4) { + /// VDD * 1/8 selected as reference + Ref1_8Vdd = 0x0, + /// VDD * 2/8 selected as reference + Ref2_8Vdd = 0x1, + /// VDD * 3/8 selected as reference + Ref3_8Vdd = 0x2, + /// VDD * 4/8 selected as reference + Ref4_8Vdd = 0x3, + /// VDD * 5/8 selected as reference + Ref5_8Vdd = 0x4, + /// VDD * 6/8 selected as reference + Ref6_8Vdd = 0x5, + /// VDD * 7/8 selected as reference + Ref7_8Vdd = 0x6, + /// External analog reference selected + ARef = 0x7, + /// VDD * 1/16 selected as reference + Ref1_16Vdd = 0x8, + /// VDD * 3/16 selected as reference + Ref3_16Vdd = 0x9, + /// VDD * 5/16 selected as reference + Ref5_16Vdd = 0xa, + /// VDD * 7/16 selected as reference + Ref7_16Vdd = 0xb, + /// VDD * 9/16 selected as reference + Ref9_16Vdd = 0xc, + /// VDD * 11/16 selected as reference + Ref11_16Vdd = 0xd, + /// VDD * 13/16 selected as reference + Ref13_16Vdd = 0xe, + /// VDD * 15/16 selected as reference + Ref15_16Vdd = 0xf, + }, + }, + padding: u28, + }), + /// External reference select + EXTREFSEL: mmio.Mmio(packed struct(u32) { + /// External analog reference select + EXTREFSEL: packed union { + raw: u1, + value: enum(u1) { + /// Use AIN0 as external analog reference + AnalogReference0 = 0x0, + /// Use AIN1 as external analog reference + AnalogReference1 = 0x1, + }, + }, + padding: u31, + }), + reserved1312: [16]u8, + /// Analog detect configuration + ANADETECT: mmio.Mmio(packed struct(u32) { + /// Analog detect configuration + ANADETECT: packed union { + raw: u2, + value: enum(u2) { + /// Generate ANADETECT on crossing, both upward crossing and downward crossing + Cross = 0x0, + /// Generate ANADETECT on upward crossing only + Up = 0x1, + /// Generate ANADETECT on downward crossing only + Down = 0x2, + _, + }, + }, + padding: u30, + }), + reserved1336: [20]u8, + /// Comparator hysteresis enable + HYST: mmio.Mmio(packed struct(u32) { + /// Comparator hysteresis enable + HYST: packed union { + raw: u1, + value: enum(u1) { + /// Comparator hysteresis disabled + NoHyst = 0x0, + /// Comparator hysteresis disabled (typ. 50 mV) + Hyst50mV = 0x1, + }, + }, + padding: u31, + }), + }; + + /// Software interrupt 0 + pub const SWI0 = extern struct { + /// Unused. + UNUSED: u32, + }; + }; +}; diff --git a/src/chips/nrf52840.json b/src/chips/nrf52840.json new file mode 100644 index 0000000..a758e21 --- /dev/null +++ b/src/chips/nrf52840.json @@ -0,0 +1,44867 @@ +{ + "version": "0.1.0", + "types": { + "peripherals": { + "SCS": { + "description": "System Control Space", + "children": { + "register_groups": { + "SysTick": { + "description": "System Tick Timer", + "children": { + "registers": { + "CTRL": { + "description": "SysTick Control and Status Register", + "offset": 0, + "size": 32, + "children": { + "fields": { + "ENABLE": { + "offset": 0, + "size": 1 + }, + "TICKINT": { + "offset": 1, + "size": 1 + }, + "CLKSOURCE": { + "offset": 2, + "size": 1 + }, + "COUNTFLAG": { + "offset": 16, + "size": 1 + } + } + } + }, + "LOAD": { + "description": "SysTick Reload Value Register", + "offset": 4, + "size": 32, + "children": { + "fields": { + "RELOAD": { + "offset": 0, + "size": 24 + } + } + } + }, + "VAL": { + "description": "SysTick Current Value Register", + "offset": 8, + "size": 32, + "children": { + "fields": { + "CURRENT": { + "offset": 0, + "size": 24 + } + } + } + }, + "CALIB": { + "description": "SysTick Calibration Register", + "offset": 12, + "size": 32, + "access": "read-only", + "children": { + "fields": { + "TENMS": { + "offset": 0, + "size": 24 + }, + "SKEW": { + "offset": 30, + "size": 1 + }, + "NOREF": { + "offset": 31, + "size": 1 + } + } + } + } + } + } + } + } + } + }, + "FICR": { + "description": "Factory information configuration registers", + "children": { + "registers": { + "CODEPAGESIZE": { + "description": "Code memory page size", + "offset": 16, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CODEPAGESIZE": { + "description": "Code memory page size", + "offset": 0, + "size": 32 + } + } + } + }, + "CODESIZE": { + "description": "Code memory size", + "offset": 20, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CODESIZE": { + "description": "Code memory size in number of pages", + "offset": 0, + "size": 32 + } + } + } + }, + "DEVICEID": { + "description": "Description collection: Device identifier", + "offset": 96, + "size": 32, + "count": 2, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DEVICEID": { + "description": "64 bit unique device identifier", + "offset": 0, + "size": 32 + } + } + } + }, + "ER": { + "description": "Description collection: Encryption root, word n", + "offset": 128, + "size": 32, + "count": 4, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ER": { + "description": "Encryption root, word n", + "offset": 0, + "size": 32 + } + } + } + }, + "IR": { + "description": "Description collection: Identity Root, word n", + "offset": 144, + "size": 32, + "count": 4, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IR": { + "description": "Identity Root, word n", + "offset": 0, + "size": 32 + } + } + } + }, + "DEVICEADDRTYPE": { + "description": "Device address type", + "offset": 160, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DEVICEADDRTYPE": { + "description": "Device address type", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Public": { + "description": "Public address", + "value": 0 + }, + "Random": { + "description": "Random address", + "value": 1 + } + } + } + } + } + } + } + }, + "DEVICEADDR": { + "description": "Description collection: Device address n", + "offset": 164, + "size": 32, + "count": 2, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DEVICEADDR": { + "description": "48 bit device address", + "offset": 0, + "size": 32 + } + } + } + }, + "PRODTEST": { + "description": "Description collection: Production test signature n", + "offset": 848, + "size": 32, + "count": 3, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PRODTEST": { + "description": "Production test signature n", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Done": { + "description": "Production tests done", + "value": 3141677471 + }, + "NotDone": { + "description": "Production tests not done", + "value": 4294967295 + } + } + } + } + } + } + } + } + } + } + }, + "UICR": { + "description": "User information configuration registers", + "children": { + "registers": { + "NRFFW": { + "description": "Description collection: Reserved for Nordic firmware design", + "offset": 20, + "size": 32, + "count": 13, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "NRFFW": { + "description": "Reserved for Nordic firmware design", + "offset": 0, + "size": 32 + } + } + } + }, + "NRFHW": { + "description": "Description collection: Reserved for Nordic hardware design", + "offset": 80, + "size": 32, + "count": 12, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "NRFHW": { + "description": "Reserved for Nordic hardware design", + "offset": 0, + "size": 32 + } + } + } + }, + "CUSTOMER": { + "description": "Description collection: Reserved for customer", + "offset": 128, + "size": 32, + "count": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "CUSTOMER": { + "description": "Reserved for customer", + "offset": 0, + "size": 32 + } + } + } + }, + "PSELRESET": { + "description": "Description collection: Mapping of the nRESET function (see POWER chapter for details)", + "offset": 512, + "size": 32, + "count": 2, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN": { + "description": "GPIO pin number onto which nRESET is exposed", + "offset": 0, + "size": 5 + }, + "PORT": { + "description": "Port number onto which nRESET is exposed", + "offset": 5, + "size": 1 + }, + "CONNECT": { + "description": "Connection", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disconnected": { + "description": "Disconnect", + "value": 1 + }, + "Connected": { + "description": "Connect", + "value": 0 + } + } + } + } + } + } + } + }, + "APPROTECT": { + "description": "Access port protection", + "offset": 520, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PALL": { + "description": "Enable or disable access port protection.", + "offset": 0, + "size": 8, + "enum": { + "size": 8, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 255 + }, + "Enabled": { + "description": "Enable", + "value": 0 + } + } + } + } + } + } + } + }, + "NFCPINS": { + "description": "Setting of pins dedicated to NFC functionality: NFC antenna or GPIO", + "offset": 524, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PROTECT": { + "description": "Setting of pins dedicated to NFC functionality", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Operation as GPIO pins. Same protection as normal GPIO pins", + "value": 0 + }, + "NFC": { + "description": "Operation as NFC antenna pins. Configures the protection for NFC operation", + "value": 1 + } + } + } + } + } + } + } + }, + "DEBUGCTRL": { + "description": "Processor debug control", + "offset": 528, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "CPUNIDEN": { + "description": "Configure CPU non-intrusive debug features", + "offset": 0, + "size": 8, + "enum": { + "size": 8, + "children": { + "enum_fields": { + "Enabled": { + "description": "Enable CPU ITM and ETM functionality (default behavior)", + "value": 255 + }, + "Disabled": { + "description": "Disable CPU ITM and ETM functionality", + "value": 0 + } + } + } + } + }, + "CPUFPBEN": { + "description": "Configure CPU flash patch and breakpoint (FPB) unit behavior", + "offset": 8, + "size": 8, + "enum": { + "size": 8, + "children": { + "enum_fields": { + "Enabled": { + "description": "Enable CPU FPB unit (default behavior)", + "value": 255 + }, + "Disabled": { + "description": "Disable CPU FPB unit. Writes into the FPB registers will be ignored.", + "value": 0 + } + } + } + } + } + } + } + }, + "REGOUT0": { + "description": "GPIO reference voltage / external output supply voltage in high voltage mode", + "offset": 772, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "VOUT": { + "description": "Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF.", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "1V8": { + "description": "1.8 V", + "value": 0 + }, + "2V1": { + "description": "2.1 V", + "value": 1 + }, + "2V4": { + "description": "2.4 V", + "value": 2 + }, + "2V7": { + "description": "2.7 V", + "value": 3 + }, + "3V0": { + "description": "3.0 V", + "value": 4 + }, + "3V3": { + "description": "3.3 V", + "value": 5 + }, + "DEFAULT": { + "description": "Default voltage: 1.8 V", + "value": 7 + } + } + } + } + } + } + } + } + } + } + }, + "CLOCK": { + "description": "Clock control", + "children": { + "registers": { + "TASKS_HFCLKSTART": { + "description": "Start HFXO crystal oscillator", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_HFCLKSTART": { + "description": "Start HFXO crystal oscillator", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_HFCLKSTOP": { + "description": "Stop HFXO crystal oscillator", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_HFCLKSTOP": { + "description": "Stop HFXO crystal oscillator", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_LFCLKSTART": { + "description": "Start LFCLK", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_LFCLKSTART": { + "description": "Start LFCLK", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_LFCLKSTOP": { + "description": "Stop LFCLK", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_LFCLKSTOP": { + "description": "Stop LFCLK", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_CAL": { + "description": "Start calibration of LFRC", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CAL": { + "description": "Start calibration of LFRC", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_CTSTART": { + "description": "Start calibration timer", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CTSTART": { + "description": "Start calibration timer", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_CTSTOP": { + "description": "Stop calibration timer", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CTSTOP": { + "description": "Stop calibration timer", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_HFCLKSTARTED": { + "description": "HFXO crystal oscillator started", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_HFCLKSTARTED": { + "description": "HFXO crystal oscillator started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_LFCLKSTARTED": { + "description": "LFCLK started", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_LFCLKSTARTED": { + "description": "LFCLK started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_DONE": { + "description": "Calibration of LFRC completed", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_DONE": { + "description": "Calibration of LFRC completed", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CTTO": { + "description": "Calibration timer timeout", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CTTO": { + "description": "Calibration timer timeout", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CTSTARTED": { + "description": "Calibration timer has been started and is ready to process new tasks", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CTSTARTED": { + "description": "Calibration timer has been started and is ready to process new tasks", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CTSTOPPED": { + "description": "Calibration timer has been stopped and is ready to process new tasks", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CTSTOPPED": { + "description": "Calibration timer has been stopped and is ready to process new tasks", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HFCLKSTARTED": { + "description": "Write '1' to enable interrupt for event HFCLKSTARTED", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LFCLKSTARTED": { + "description": "Write '1' to enable interrupt for event LFCLKSTARTED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DONE": { + "description": "Write '1' to enable interrupt for event DONE", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CTTO": { + "description": "Write '1' to enable interrupt for event CTTO", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CTSTARTED": { + "description": "Write '1' to enable interrupt for event CTSTARTED", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CTSTOPPED": { + "description": "Write '1' to enable interrupt for event CTSTOPPED", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HFCLKSTARTED": { + "description": "Write '1' to disable interrupt for event HFCLKSTARTED", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LFCLKSTARTED": { + "description": "Write '1' to disable interrupt for event LFCLKSTARTED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DONE": { + "description": "Write '1' to disable interrupt for event DONE", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CTTO": { + "description": "Write '1' to disable interrupt for event CTTO", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CTSTARTED": { + "description": "Write '1' to disable interrupt for event CTSTARTED", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CTSTOPPED": { + "description": "Write '1' to disable interrupt for event CTSTOPPED", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "HFCLKRUN": { + "description": "Status indicating that HFCLKSTART task has been triggered", + "offset": 1032, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STATUS": { + "description": "HFCLKSTART task triggered or not", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotTriggered": { + "description": "Task not triggered", + "value": 0 + }, + "Triggered": { + "description": "Task triggered", + "value": 1 + } + } + } + } + } + } + } + }, + "HFCLKSTAT": { + "description": "HFCLK status", + "offset": 1036, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SRC": { + "description": "Source of HFCLK", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RC": { + "description": "64 MHz internal oscillator (HFINT)", + "value": 0 + }, + "Xtal": { + "description": "64 MHz crystal oscillator (HFXO)", + "value": 1 + } + } + } + } + }, + "STATE": { + "description": "HFCLK state", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotRunning": { + "description": "HFCLK not running", + "value": 0 + }, + "Running": { + "description": "HFCLK running", + "value": 1 + } + } + } + } + } + } + } + }, + "LFCLKRUN": { + "description": "Status indicating that LFCLKSTART task has been triggered", + "offset": 1044, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STATUS": { + "description": "LFCLKSTART task triggered or not", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotTriggered": { + "description": "Task not triggered", + "value": 0 + }, + "Triggered": { + "description": "Task triggered", + "value": 1 + } + } + } + } + } + } + } + }, + "LFCLKSTAT": { + "description": "LFCLK status", + "offset": 1048, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SRC": { + "description": "Source of LFCLK", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "RC": { + "description": "32.768 kHz RC oscillator (LFRC)", + "value": 0 + }, + "Xtal": { + "description": "32.768 kHz crystal oscillator (LFXO)", + "value": 1 + }, + "Synth": { + "description": "32.768 kHz synthesized from HFCLK (LFSYNT)", + "value": 2 + } + } + } + } + }, + "STATE": { + "description": "LFCLK state", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotRunning": { + "description": "LFCLK not running", + "value": 0 + }, + "Running": { + "description": "LFCLK running", + "value": 1 + } + } + } + } + } + } + } + }, + "LFCLKSRCCOPY": { + "description": "Copy of LFCLKSRC register, set when LFCLKSTART task was triggered", + "offset": 1052, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SRC": { + "description": "Clock source", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "RC": { + "description": "32.768 kHz RC oscillator (LFRC)", + "value": 0 + }, + "Xtal": { + "description": "32.768 kHz crystal oscillator (LFXO)", + "value": 1 + }, + "Synth": { + "description": "32.768 kHz synthesized from HFCLK (LFSYNT)", + "value": 2 + } + } + } + } + } + } + } + }, + "LFCLKSRC": { + "description": "Clock source for the LFCLK", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRC": { + "description": "Clock source", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "RC": { + "description": "32.768 kHz RC oscillator (LFRC)", + "value": 0 + }, + "Xtal": { + "description": "32.768 kHz crystal oscillator (LFXO)", + "value": 1 + }, + "Synth": { + "description": "32.768 kHz synthesized from HFCLK (LFSYNT)", + "value": 2 + } + } + } + } + }, + "BYPASS": { + "description": "Enable or disable bypass of LFCLK crystal oscillator with external clock source", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable (use with Xtal or low-swing external source)", + "value": 0 + }, + "Enabled": { + "description": "Enable (use with rail-to-rail external source)", + "value": 1 + } + } + } + } + }, + "EXTERNAL": { + "description": "Enable or disable external source for LFCLK", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable external source (use with Xtal)", + "value": 0 + }, + "Enabled": { + "description": "Enable use of external source instead of Xtal (SRC needs to be set to Xtal)", + "value": 1 + } + } + } + } + } + } + } + }, + "HFXODEBOUNCE": { + "description": "HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task.", + "offset": 1320, + "size": 32, + "reset_value": 16, + "reset_mask": 4294967295, + "children": { + "fields": { + "HFXODEBOUNCE": { + "description": "HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us.", + "offset": 0, + "size": 8, + "enum": { + "size": 8, + "children": { + "enum_fields": { + "Db256us": { + "description": "256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals.", + "value": 16 + }, + "Db1024us": { + "description": "1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals.", + "value": 64 + } + } + } + } + } + } + } + }, + "CTIV": { + "description": "Calibration timer interval", + "offset": 1336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTIV": { + "description": "Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.", + "offset": 0, + "size": 7 + } + } + } + }, + "TRACECONFIG": { + "description": "Clocking options for the trace port debug interface", + "offset": 1372, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TRACEPORTSPEED": { + "description": "Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two.", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "32MHz": { + "description": "32 MHz trace port clock (TRACECLK = 16 MHz)", + "value": 0 + }, + "16MHz": { + "description": "16 MHz trace port clock (TRACECLK = 8 MHz)", + "value": 1 + }, + "8MHz": { + "description": "8 MHz trace port clock (TRACECLK = 4 MHz)", + "value": 2 + }, + "4MHz": { + "description": "4 MHz trace port clock (TRACECLK = 2 MHz)", + "value": 3 + } + } + } + } + }, + "TRACEMUX": { + "description": "Pin multiplexing of trace signals. See pin assignment chapter for more details.", + "offset": 16, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "GPIO": { + "description": "No trace signals routed to pins. All pins can be used as regular GPIOs.", + "value": 0 + }, + "Serial": { + "description": "SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs.", + "value": 1 + }, + "Parallel": { + "description": "All trace signals (TRACECLK and TRACEDATA[n]) routed to pins.", + "value": 2 + } + } + } + } + } + } + } + }, + "LFRCMODE": { + "description": "LFRC mode configuration", + "offset": 1460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "Set LFRC mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Normal": { + "description": "Normal mode", + "value": 0 + }, + "ULP": { + "description": "Ultra-low power mode (ULP)", + "value": 1 + } + } + } + } + }, + "STATUS": { + "description": "Active LFRC mode. This field is read only.", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Normal": { + "description": "Normal mode", + "value": 0 + }, + "ULP": { + "description": "Ultra-low power mode (ULP)", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "POWER": { + "description": "Power control", + "children": { + "registers": { + "TASKS_CONSTLAT": { + "description": "Enable Constant Latency mode", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CONSTLAT": { + "description": "Enable Constant Latency mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_LOWPWR": { + "description": "Enable Low-power mode (variable latency)", + "offset": 124, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_LOWPWR": { + "description": "Enable Low-power mode (variable latency)", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_POFWARN": { + "description": "Power failure warning", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_POFWARN": { + "description": "Power failure warning", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_SLEEPENTER": { + "description": "CPU entered WFI/WFE sleep", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_SLEEPENTER": { + "description": "CPU entered WFI/WFE sleep", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_SLEEPEXIT": { + "description": "CPU exited WFI/WFE sleep", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_SLEEPEXIT": { + "description": "CPU exited WFI/WFE sleep", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_USBDETECTED": { + "description": "Voltage supply detected on VBUS", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_USBDETECTED": { + "description": "Voltage supply detected on VBUS", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_USBREMOVED": { + "description": "Voltage supply removed from VBUS", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_USBREMOVED": { + "description": "Voltage supply removed from VBUS", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_USBPWRRDY": { + "description": "USB 3.3 V supply ready", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_USBPWRRDY": { + "description": "USB 3.3 V supply ready", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "POFWARN": { + "description": "Write '1' to enable interrupt for event POFWARN", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SLEEPENTER": { + "description": "Write '1' to enable interrupt for event SLEEPENTER", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SLEEPEXIT": { + "description": "Write '1' to enable interrupt for event SLEEPEXIT", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "USBDETECTED": { + "description": "Write '1' to enable interrupt for event USBDETECTED", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "USBREMOVED": { + "description": "Write '1' to enable interrupt for event USBREMOVED", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "USBPWRRDY": { + "description": "Write '1' to enable interrupt for event USBPWRRDY", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "POFWARN": { + "description": "Write '1' to disable interrupt for event POFWARN", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SLEEPENTER": { + "description": "Write '1' to disable interrupt for event SLEEPENTER", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SLEEPEXIT": { + "description": "Write '1' to disable interrupt for event SLEEPEXIT", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "USBDETECTED": { + "description": "Write '1' to disable interrupt for event USBDETECTED", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "USBREMOVED": { + "description": "Write '1' to disable interrupt for event USBREMOVED", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "USBPWRRDY": { + "description": "Write '1' to disable interrupt for event USBPWRRDY", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "RESETREAS": { + "description": "Reset reason", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RESETPIN": { + "description": "Reset from pin-reset detected", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "DOG": { + "description": "Reset from watchdog detected", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "SREQ": { + "description": "Reset from soft reset detected", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "LOCKUP": { + "description": "Reset from CPU lock-up detected", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "OFF": { + "description": "Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "LPCOMP": { + "description": "Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "DIF": { + "description": "Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "NFC": { + "description": "Reset due to wake up from System OFF mode by NFC field detect", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + }, + "VBUS": { + "description": "Reset due to wake up from System OFF mode by VBUS rising into valid range", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Not detected", + "value": 0 + }, + "Detected": { + "description": "Detected", + "value": 1 + } + } + } + } + } + } + } + }, + "RAMSTATUS": { + "description": "Deprecated register - RAM status register", + "offset": 1064, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RAMBLOCK0": { + "description": "RAM block 0 is on or off/powering up", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Off": { + "description": "Off", + "value": 0 + }, + "On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "RAMBLOCK1": { + "description": "RAM block 1 is on or off/powering up", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Off": { + "description": "Off", + "value": 0 + }, + "On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "RAMBLOCK2": { + "description": "RAM block 2 is on or off/powering up", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Off": { + "description": "Off", + "value": 0 + }, + "On": { + "description": "On", + "value": 1 + } + } + } + } + }, + "RAMBLOCK3": { + "description": "RAM block 3 is on or off/powering up", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Off": { + "description": "Off", + "value": 0 + }, + "On": { + "description": "On", + "value": 1 + } + } + } + } + } + } + } + }, + "USBREGSTATUS": { + "description": "USB supply status", + "offset": 1080, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "VBUSDETECT": { + "description": "VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information)", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoVbus": { + "description": "VBUS voltage below valid threshold", + "value": 0 + }, + "VbusPresent": { + "description": "VBUS voltage above valid threshold", + "value": 1 + } + } + } + } + }, + "OUTPUTRDY": { + "description": "USB supply output settling time elapsed", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotReady": { + "description": "USBREG output settling time not elapsed", + "value": 0 + }, + "Ready": { + "description": "USBREG output settling time elapsed (same information as USBPWRRDY event)", + "value": 1 + } + } + } + } + } + } + } + }, + "SYSTEMOFF": { + "description": "System OFF register", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "SYSTEMOFF": { + "description": "Enable System OFF mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Enter": { + "description": "Enable System OFF mode", + "value": 1 + } + } + } + } + } + } + } + }, + "POFCON": { + "description": "Power-fail comparator configuration", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "POF": { + "description": "Enable or disable power failure warning", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "THRESHOLD": { + "description": "Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages.", + "offset": 1, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "V17": { + "description": "Set threshold to 1.7 V", + "value": 4 + }, + "V18": { + "description": "Set threshold to 1.8 V", + "value": 5 + }, + "V19": { + "description": "Set threshold to 1.9 V", + "value": 6 + }, + "V20": { + "description": "Set threshold to 2.0 V", + "value": 7 + }, + "V21": { + "description": "Set threshold to 2.1 V", + "value": 8 + }, + "V22": { + "description": "Set threshold to 2.2 V", + "value": 9 + }, + "V23": { + "description": "Set threshold to 2.3 V", + "value": 10 + }, + "V24": { + "description": "Set threshold to 2.4 V", + "value": 11 + }, + "V25": { + "description": "Set threshold to 2.5 V", + "value": 12 + }, + "V26": { + "description": "Set threshold to 2.6 V", + "value": 13 + }, + "V27": { + "description": "Set threshold to 2.7 V", + "value": 14 + }, + "V28": { + "description": "Set threshold to 2.8 V", + "value": 15 + } + } + } + } + }, + "THRESHOLDVDDH": { + "description": "Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH).", + "offset": 8, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "V27": { + "description": "Set threshold to 2.7 V", + "value": 0 + }, + "V28": { + "description": "Set threshold to 2.8 V", + "value": 1 + }, + "V29": { + "description": "Set threshold to 2.9 V", + "value": 2 + }, + "V30": { + "description": "Set threshold to 3.0 V", + "value": 3 + }, + "V31": { + "description": "Set threshold to 3.1 V", + "value": 4 + }, + "V32": { + "description": "Set threshold to 3.2 V", + "value": 5 + }, + "V33": { + "description": "Set threshold to 3.3 V", + "value": 6 + }, + "V34": { + "description": "Set threshold to 3.4 V", + "value": 7 + }, + "V35": { + "description": "Set threshold to 3.5 V", + "value": 8 + }, + "V36": { + "description": "Set threshold to 3.6 V", + "value": 9 + }, + "V37": { + "description": "Set threshold to 3.7 V", + "value": 10 + }, + "V38": { + "description": "Set threshold to 3.8 V", + "value": 11 + }, + "V39": { + "description": "Set threshold to 3.9 V", + "value": 12 + }, + "V40": { + "description": "Set threshold to 4.0 V", + "value": 13 + }, + "V41": { + "description": "Set threshold to 4.1 V", + "value": 14 + }, + "V42": { + "description": "Set threshold to 4.2 V", + "value": 15 + } + } + } + } + } + } + } + }, + "GPREGRET": { + "description": "General purpose retention register", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GPREGRET": { + "description": "General purpose retention register", + "offset": 0, + "size": 8 + } + } + } + }, + "GPREGRET2": { + "description": "General purpose retention register", + "offset": 1312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GPREGRET": { + "description": "General purpose retention register", + "offset": 0, + "size": 8 + } + } + } + }, + "DCDCEN": { + "description": "Enable DC/DC converter for REG1 stage", + "offset": 1400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCDCEN": { + "description": "Enable DC/DC converter for REG1 stage.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "DCDCEN0": { + "description": "Enable DC/DC converter for REG0 stage", + "offset": 1408, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCDCEN": { + "description": "Enable DC/DC converter for REG0 stage.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "MAINREGSTATUS": { + "description": "Main supply status", + "offset": 1600, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "MAINREGSTATUS": { + "description": "Main supply status", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Normal": { + "description": "Normal voltage mode. Voltage supplied on VDD.", + "value": 0 + }, + "High": { + "description": "High voltage mode. Voltage supplied on VDDH.", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "P0": { + "description": "GPIO Port 1", + "children": { + "registers": { + "OUT": { + "description": "Write GPIO port", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin driver is low", + "value": 0 + }, + "High": { + "description": "Pin driver is high", + "value": 1 + } + } + } + } + } + } + } + }, + "OUTSET": { + "description": "Set individual bits in GPIO port", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + } + } + } + }, + "OUTCLR": { + "description": "Clear individual bits in GPIO port", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Read: pin driver is low", + "value": 0 + }, + "High": { + "description": "Read: pin driver is high", + "value": 1 + } + } + } + } + } + } + } + }, + "IN": { + "description": "Read GPIO port", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PIN0": { + "description": "Pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Pin input is low", + "value": 0 + }, + "High": { + "description": "Pin input is high", + "value": 1 + } + } + } + } + } + } + } + }, + "DIR": { + "description": "Direction of GPIO pins", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Pin set as input", + "value": 0 + }, + "Output": { + "description": "Pin set as output", + "value": 1 + } + } + } + } + } + } + } + }, + "DIRSET": { + "description": "DIR set register", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Set as output pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Set as output pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Set as output pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Set as output pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Set as output pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Set as output pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Set as output pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Set as output pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Set as output pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Set as output pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Set as output pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Set as output pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Set as output pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Set as output pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Set as output pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Set as output pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Set as output pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Set as output pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Set as output pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Set as output pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Set as output pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Set as output pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Set as output pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Set as output pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Set as output pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Set as output pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Set as output pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Set as output pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Set as output pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Set as output pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Set as output pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Set as output pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + } + } + } + }, + "DIRCLR": { + "description": "DIR clear register", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Set as input pin 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Set as input pin 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Set as input pin 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Set as input pin 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Set as input pin 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Set as input pin 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Set as input pin 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Set as input pin 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Set as input pin 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Set as input pin 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Set as input pin 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Set as input pin 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Set as input pin 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Set as input pin 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Set as input pin 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Set as input pin 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Set as input pin 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Set as input pin 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Set as input pin 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Set as input pin 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Set as input pin 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Set as input pin 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Set as input pin 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Set as input pin 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Set as input pin 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Set as input pin 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Set as input pin 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Set as input pin 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Set as input pin 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Set as input pin 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Set as input pin 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Set as input pin 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Read: pin set as input", + "value": 0 + }, + "Output": { + "description": "Read: pin set as output", + "value": 1 + } + } + } + } + } + } + } + }, + "LATCH": { + "description": "Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers", + "offset": 1312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN0": { + "description": "Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN1": { + "description": "Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN2": { + "description": "Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN3": { + "description": "Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN4": { + "description": "Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN5": { + "description": "Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN6": { + "description": "Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN7": { + "description": "Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN8": { + "description": "Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN9": { + "description": "Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN10": { + "description": "Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN11": { + "description": "Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN12": { + "description": "Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN13": { + "description": "Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN14": { + "description": "Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN15": { + "description": "Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN16": { + "description": "Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN17": { + "description": "Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN18": { + "description": "Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN19": { + "description": "Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN20": { + "description": "Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN21": { + "description": "Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN22": { + "description": "Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN23": { + "description": "Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN24": { + "description": "Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN25": { + "description": "Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN26": { + "description": "Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN27": { + "description": "Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN28": { + "description": "Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN29": { + "description": "Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN30": { + "description": "Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + }, + "PIN31": { + "description": "Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLatched": { + "description": "Criteria has not been met", + "value": 0 + }, + "Latched": { + "description": "Criteria has been met", + "value": 1 + } + } + } + } + } + } + } + }, + "DETECTMODE": { + "description": "Select between default DETECT signal behaviour and LDETECT mode", + "offset": 1316, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DETECTMODE": { + "description": "Select between default DETECT signal behaviour and LDETECT mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Default": { + "description": "DETECT directly connected to PIN DETECT signals", + "value": 0 + }, + "LDETECT": { + "description": "Use the latched LDETECT behaviour", + "value": 1 + } + } + } + } + } + } + } + }, + "PIN_CNF": { + "description": "Description collection: Configuration of GPIO pins", + "offset": 1792, + "size": 32, + "count": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "DIR": { + "description": "Pin direction. Same physical register as DIR register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Input": { + "description": "Configure pin as an input pin", + "value": 0 + }, + "Output": { + "description": "Configure pin as an output pin", + "value": 1 + } + } + } + } + }, + "INPUT": { + "description": "Connect or disconnect input buffer", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Connect": { + "description": "Connect input buffer", + "value": 0 + }, + "Disconnect": { + "description": "Disconnect input buffer", + "value": 1 + } + } + } + } + }, + "PULL": { + "description": "Pull configuration", + "offset": 2, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "No pull", + "value": 0 + }, + "Pulldown": { + "description": "Pull down on pin", + "value": 1 + }, + "Pullup": { + "description": "Pull up on pin", + "value": 3 + } + } + } + } + }, + "DRIVE": { + "description": "Drive configuration", + "offset": 8, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "S0S1": { + "description": "Standard '0', standard '1'", + "value": 0 + }, + "H0S1": { + "description": "High drive '0', standard '1'", + "value": 1 + }, + "S0H1": { + "description": "Standard '0', high drive '1'", + "value": 2 + }, + "H0H1": { + "description": "High drive '0', high 'drive '1''", + "value": 3 + }, + "D0S1": { + "description": "Disconnect '0' standard '1' (normally used for wired-or connections)", + "value": 4 + }, + "D0H1": { + "description": "Disconnect '0', high drive '1' (normally used for wired-or connections)", + "value": 5 + }, + "S0D1": { + "description": "Standard '0'. disconnect '1' (normally used for wired-and connections)", + "value": 6 + }, + "H0D1": { + "description": "High drive '0', disconnect '1' (normally used for wired-and connections)", + "value": 7 + } + } + } + } + }, + "SENSE": { + "description": "Pin sensing mechanism", + "offset": 16, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "High": { + "description": "Sense for high level", + "value": 2 + }, + "Low": { + "description": "Sense for low level", + "value": 3 + } + } + } + } + } + } + } + } + } + } + }, + "ACL": { + "description": "Access control lists" + }, + "RADIO": { + "description": "2.4 GHz radio", + "children": { + "registers": { + "TASKS_TXEN": { + "description": "Enable RADIO in TX mode", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_TXEN": { + "description": "Enable RADIO in TX mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_RXEN": { + "description": "Enable RADIO in RX mode", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_RXEN": { + "description": "Enable RADIO in RX mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_START": { + "description": "Start RADIO", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Start RADIO", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stop RADIO", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop RADIO", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_DISABLE": { + "description": "Disable RADIO", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_DISABLE": { + "description": "Disable RADIO", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_RSSISTART": { + "description": "Start the RSSI and take one single sample of the receive signal strength", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_RSSISTART": { + "description": "Start the RSSI and take one single sample of the receive signal strength", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_RSSISTOP": { + "description": "Stop the RSSI measurement", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_RSSISTOP": { + "description": "Stop the RSSI measurement", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_BCSTART": { + "description": "Start the bit counter", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_BCSTART": { + "description": "Start the bit counter", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_BCSTOP": { + "description": "Stop the bit counter", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_BCSTOP": { + "description": "Stop the bit counter", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_EDSTART": { + "description": "Start the energy detect measurement used in IEEE 802.15.4 mode", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_EDSTART": { + "description": "Start the energy detect measurement used in IEEE 802.15.4 mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_EDSTOP": { + "description": "Stop the energy detect measurement", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_EDSTOP": { + "description": "Stop the energy detect measurement", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_CCASTART": { + "description": "Start the clear channel assessment used in IEEE 802.15.4 mode", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CCASTART": { + "description": "Start the clear channel assessment used in IEEE 802.15.4 mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_CCASTOP": { + "description": "Stop the clear channel assessment", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CCASTOP": { + "description": "Stop the clear channel assessment", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_READY": { + "description": "RADIO has ramped up and is ready to be started", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_READY": { + "description": "RADIO has ramped up and is ready to be started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ADDRESS": { + "description": "Address sent or received", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ADDRESS": { + "description": "Address sent or received", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_PAYLOAD": { + "description": "Packet payload sent or received", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_PAYLOAD": { + "description": "Packet payload sent or received", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_END": { + "description": "Packet sent or received", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_END": { + "description": "Packet sent or received", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_DISABLED": { + "description": "RADIO has been disabled", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_DISABLED": { + "description": "RADIO has been disabled", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_DEVMATCH": { + "description": "A device address match occurred on the last received packet", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_DEVMATCH": { + "description": "A device address match occurred on the last received packet", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_DEVMISS": { + "description": "No device address match occurred on the last received packet", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_DEVMISS": { + "description": "No device address match occurred on the last received packet", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RSSIEND": { + "description": "Sampling of receive signal strength complete", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RSSIEND": { + "description": "Sampling of receive signal strength complete", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_BCMATCH": { + "description": "Bit counter reached bit count value", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_BCMATCH": { + "description": "Bit counter reached bit count value", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CRCOK": { + "description": "Packet received with CRC ok", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CRCOK": { + "description": "Packet received with CRC ok", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CRCERROR": { + "description": "Packet received with CRC error", + "offset": 308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CRCERROR": { + "description": "Packet received with CRC error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_FRAMESTART": { + "description": "IEEE 802.15.4 length field received", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_FRAMESTART": { + "description": "IEEE 802.15.4 length field received", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_EDEND": { + "description": "Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.", + "offset": 316, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_EDEND": { + "description": "Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_EDSTOPPED": { + "description": "The sampling of energy detection has stopped", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_EDSTOPPED": { + "description": "The sampling of energy detection has stopped", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CCAIDLE": { + "description": "Wireless medium in idle - clear to send", + "offset": 324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CCAIDLE": { + "description": "Wireless medium in idle - clear to send", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CCABUSY": { + "description": "Wireless medium busy - do not send", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CCABUSY": { + "description": "Wireless medium busy - do not send", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CCASTOPPED": { + "description": "The CCA has stopped", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CCASTOPPED": { + "description": "The CCA has stopped", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RATEBOOST": { + "description": "Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RATEBOOST": { + "description": "Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TXREADY": { + "description": "RADIO has ramped up and is ready to be started TX path", + "offset": 340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TXREADY": { + "description": "RADIO has ramped up and is ready to be started TX path", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXREADY": { + "description": "RADIO has ramped up and is ready to be started RX path", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXREADY": { + "description": "RADIO has ramped up and is ready to be started RX path", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_MHRMATCH": { + "description": "MAC header match found", + "offset": 348, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_MHRMATCH": { + "description": "MAC header match found", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_SYNC": { + "description": "Preamble indicator.", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_SYNC": { + "description": "Preamble indicator.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_PHYEND": { + "description": "Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air.", + "offset": 364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_PHYEND": { + "description": "Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY_START": { + "description": "Shortcut between event READY and task START", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "END_DISABLE": { + "description": "Shortcut between event END and task DISABLE", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DISABLED_TXEN": { + "description": "Shortcut between event DISABLED and task TXEN", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DISABLED_RXEN": { + "description": "Shortcut between event DISABLED and task RXEN", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "ADDRESS_RSSISTART": { + "description": "Shortcut between event ADDRESS and task RSSISTART", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "END_START": { + "description": "Shortcut between event END and task START", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "ADDRESS_BCSTART": { + "description": "Shortcut between event ADDRESS and task BCSTART", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DISABLED_RSSISTOP": { + "description": "Shortcut between event DISABLED and task RSSISTOP", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "RXREADY_CCASTART": { + "description": "Shortcut between event RXREADY and task CCASTART", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "CCAIDLE_TXEN": { + "description": "Shortcut between event CCAIDLE and task TXEN", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "CCABUSY_DISABLE": { + "description": "Shortcut between event CCABUSY and task DISABLE", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "FRAMESTART_BCSTART": { + "description": "Shortcut between event FRAMESTART and task BCSTART", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "READY_EDSTART": { + "description": "Shortcut between event READY and task EDSTART", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "EDEND_DISABLE": { + "description": "Shortcut between event EDEND and task DISABLE", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "CCAIDLE_STOP": { + "description": "Shortcut between event CCAIDLE and task STOP", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "TXREADY_START": { + "description": "Shortcut between event TXREADY and task START", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "RXREADY_START": { + "description": "Shortcut between event RXREADY and task START", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "PHYEND_DISABLE": { + "description": "Shortcut between event PHYEND and task DISABLE", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "PHYEND_START": { + "description": "Shortcut between event PHYEND and task START", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to enable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ADDRESS": { + "description": "Write '1' to enable interrupt for event ADDRESS", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PAYLOAD": { + "description": "Write '1' to enable interrupt for event PAYLOAD", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to enable interrupt for event END", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DISABLED": { + "description": "Write '1' to enable interrupt for event DISABLED", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DEVMATCH": { + "description": "Write '1' to enable interrupt for event DEVMATCH", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DEVMISS": { + "description": "Write '1' to enable interrupt for event DEVMISS", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RSSIEND": { + "description": "Write '1' to enable interrupt for event RSSIEND", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "BCMATCH": { + "description": "Write '1' to enable interrupt for event BCMATCH", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CRCOK": { + "description": "Write '1' to enable interrupt for event CRCOK", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CRCERROR": { + "description": "Write '1' to enable interrupt for event CRCERROR", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "FRAMESTART": { + "description": "Write '1' to enable interrupt for event FRAMESTART", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "EDEND": { + "description": "Write '1' to enable interrupt for event EDEND", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "EDSTOPPED": { + "description": "Write '1' to enable interrupt for event EDSTOPPED", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CCAIDLE": { + "description": "Write '1' to enable interrupt for event CCAIDLE", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CCABUSY": { + "description": "Write '1' to enable interrupt for event CCABUSY", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CCASTOPPED": { + "description": "Write '1' to enable interrupt for event CCASTOPPED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RATEBOOST": { + "description": "Write '1' to enable interrupt for event RATEBOOST", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXREADY": { + "description": "Write '1' to enable interrupt for event TXREADY", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXREADY": { + "description": "Write '1' to enable interrupt for event RXREADY", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "MHRMATCH": { + "description": "Write '1' to enable interrupt for event MHRMATCH", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SYNC": { + "description": "Write '1' to enable interrupt for event SYNC", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PHYEND": { + "description": "Write '1' to enable interrupt for event PHYEND", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to disable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ADDRESS": { + "description": "Write '1' to disable interrupt for event ADDRESS", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PAYLOAD": { + "description": "Write '1' to disable interrupt for event PAYLOAD", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to disable interrupt for event END", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DISABLED": { + "description": "Write '1' to disable interrupt for event DISABLED", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DEVMATCH": { + "description": "Write '1' to disable interrupt for event DEVMATCH", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DEVMISS": { + "description": "Write '1' to disable interrupt for event DEVMISS", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RSSIEND": { + "description": "Write '1' to disable interrupt for event RSSIEND", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "BCMATCH": { + "description": "Write '1' to disable interrupt for event BCMATCH", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CRCOK": { + "description": "Write '1' to disable interrupt for event CRCOK", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CRCERROR": { + "description": "Write '1' to disable interrupt for event CRCERROR", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "FRAMESTART": { + "description": "Write '1' to disable interrupt for event FRAMESTART", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "EDEND": { + "description": "Write '1' to disable interrupt for event EDEND", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "EDSTOPPED": { + "description": "Write '1' to disable interrupt for event EDSTOPPED", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CCAIDLE": { + "description": "Write '1' to disable interrupt for event CCAIDLE", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CCABUSY": { + "description": "Write '1' to disable interrupt for event CCABUSY", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CCASTOPPED": { + "description": "Write '1' to disable interrupt for event CCASTOPPED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RATEBOOST": { + "description": "Write '1' to disable interrupt for event RATEBOOST", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXREADY": { + "description": "Write '1' to disable interrupt for event TXREADY", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXREADY": { + "description": "Write '1' to disable interrupt for event RXREADY", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "MHRMATCH": { + "description": "Write '1' to disable interrupt for event MHRMATCH", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SYNC": { + "description": "Write '1' to disable interrupt for event SYNC", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PHYEND": { + "description": "Write '1' to disable interrupt for event PHYEND", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "CRCSTATUS": { + "description": "CRC status", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CRCSTATUS": { + "description": "CRC status of packet received", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "CRCError": { + "description": "Packet received with CRC error", + "value": 0 + }, + "CRCOk": { + "description": "Packet received with CRC ok", + "value": 1 + } + } + } + } + } + } + } + }, + "RXMATCH": { + "description": "Received address", + "offset": 1032, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RXMATCH": { + "description": "Received address", + "offset": 0, + "size": 3 + } + } + } + }, + "RXCRC": { + "description": "CRC field of previously received packet", + "offset": 1036, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RXCRC": { + "description": "CRC field of previously received packet", + "offset": 0, + "size": 24 + } + } + } + }, + "DAI": { + "description": "Device address match index", + "offset": 1040, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DAI": { + "description": "Device address match index", + "offset": 0, + "size": 3 + } + } + } + }, + "PDUSTAT": { + "description": "Payload status", + "offset": 1044, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PDUSTAT": { + "description": "Status on payload length vs. PCNF1.MAXLEN", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "LessThan": { + "description": "Payload less than PCNF1.MAXLEN", + "value": 0 + }, + "GreaterThan": { + "description": "Payload greater than PCNF1.MAXLEN", + "value": 1 + } + } + } + } + }, + "CISTAT": { + "description": "Status on what rate packet is received with in Long Range", + "offset": 1, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "LR125kbit": { + "description": "Frame is received at 125kbps", + "value": 0 + }, + "LR500kbit": { + "description": "Frame is received at 500kbps", + "value": 1 + } + } + } + } + } + } + } + }, + "PACKETPTR": { + "description": "Packet pointer", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PACKETPTR": { + "description": "Packet pointer", + "offset": 0, + "size": 32 + } + } + } + }, + "FREQUENCY": { + "description": "Frequency", + "offset": 1288, + "size": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQUENCY": { + "description": "Radio channel frequency", + "offset": 0, + "size": 7 + }, + "MAP": { + "description": "Channel map selection.", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Default": { + "description": "Channel map between 2400 MHZ .. 2500 MHz", + "value": 0 + }, + "Low": { + "description": "Channel map between 2360 MHZ .. 2460 MHz", + "value": 1 + } + } + } + } + } + } + } + }, + "TXPOWER": { + "description": "Output power", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXPOWER": { + "description": "RADIO output power", + "offset": 0, + "size": 8, + "enum": { + "size": 8, + "children": { + "enum_fields": { + "Pos8dBm": { + "description": "+8 dBm", + "value": 8 + }, + "Pos7dBm": { + "description": "+7 dBm", + "value": 7 + }, + "Pos6dBm": { + "description": "+6 dBm", + "value": 6 + }, + "Pos5dBm": { + "description": "+5 dBm", + "value": 5 + }, + "Pos4dBm": { + "description": "+4 dBm", + "value": 4 + }, + "Pos3dBm": { + "description": "+3 dBm", + "value": 3 + }, + "Pos2dBm": { + "description": "+2 dBm", + "value": 2 + }, + "0dBm": { + "description": "0 dBm", + "value": 0 + }, + "Neg4dBm": { + "description": "-4 dBm", + "value": 252 + }, + "Neg8dBm": { + "description": "-8 dBm", + "value": 248 + }, + "Neg12dBm": { + "description": "-12 dBm", + "value": 244 + }, + "Neg16dBm": { + "description": "-16 dBm", + "value": 240 + }, + "Neg20dBm": { + "description": "-20 dBm", + "value": 236 + }, + "Neg30dBm": { + "description": "Deprecated enumerator - -40 dBm", + "value": 226 + }, + "Neg40dBm": { + "description": "-40 dBm", + "value": 216 + } + } + } + } + } + } + } + }, + "MODE": { + "description": "Data rate and modulation", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation.", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Nrf_1Mbit": { + "description": "1 Mbit/s Nordic proprietary radio mode", + "value": 0 + }, + "Nrf_2Mbit": { + "description": "2 Mbit/s Nordic proprietary radio mode", + "value": 1 + }, + "Ble_1Mbit": { + "description": "1 Mbit/s BLE", + "value": 3 + }, + "Ble_2Mbit": { + "description": "2 Mbit/s BLE", + "value": 4 + }, + "Ble_LR125Kbit": { + "description": "Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX", + "value": 5 + }, + "Ble_LR500Kbit": { + "description": "Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX", + "value": 6 + }, + "Ieee802154_250Kbit": { + "description": "IEEE 802.15.4-2006 250 kbit/s", + "value": 15 + } + } + } + } + } + } + } + }, + "PCNF0": { + "description": "Packet configuration register 0", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LFLEN": { + "description": "Length on air of LENGTH field in number of bits.", + "offset": 0, + "size": 4 + }, + "S0LEN": { + "description": "Length on air of S0 field in number of bytes.", + "offset": 8, + "size": 1 + }, + "S1LEN": { + "description": "Length on air of S1 field in number of bits.", + "offset": 16, + "size": 4 + }, + "S1INCL": { + "description": "Include or exclude S1 field in RAM", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Automatic": { + "description": "Include S1 field in RAM only if S1LEN > 0", + "value": 0 + }, + "Include": { + "description": "Always include S1 field in RAM independent of S1LEN", + "value": 1 + } + } + } + } + }, + "CILEN": { + "description": "Length of code indicator - long range", + "offset": 22, + "size": 2 + }, + "PLEN": { + "description": "Length of preamble on air. Decision point: TASKS_START task", + "offset": 24, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "8bit": { + "description": "8-bit preamble", + "value": 0 + }, + "16bit": { + "description": "16-bit preamble", + "value": 1 + }, + "32bitZero": { + "description": "32-bit zero preamble - used for IEEE 802.15.4", + "value": 2 + }, + "LongRange": { + "description": "Preamble - used for BLE long range", + "value": 3 + } + } + } + } + }, + "CRCINC": { + "description": "Indicates if LENGTH field contains CRC or not", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Exclude": { + "description": "LENGTH does not contain CRC", + "value": 0 + }, + "Include": { + "description": "LENGTH includes CRC", + "value": 1 + } + } + } + } + }, + "TERMLEN": { + "description": "Length of TERM field in Long Range operation", + "offset": 29, + "size": 2 + } + } + } + }, + "PCNF1": { + "description": "Packet configuration register 1", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MAXLEN": { + "description": "Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.", + "offset": 0, + "size": 8 + }, + "STATLEN": { + "description": "Static length in number of bytes", + "offset": 8, + "size": 8 + }, + "BALEN": { + "description": "Base address length in number of bytes", + "offset": 16, + "size": 3 + }, + "ENDIAN": { + "description": "On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Little": { + "description": "Least significant bit on air first", + "value": 0 + }, + "Big": { + "description": "Most significant bit on air first", + "value": 1 + } + } + } + } + }, + "WHITEEN": { + "description": "Enable or disable packet whitening", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "BASE0": { + "description": "Base address 0", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BASE0": { + "description": "Base address 0", + "offset": 0, + "size": 32 + } + } + } + }, + "BASE1": { + "description": "Base address 1", + "offset": 1312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BASE1": { + "description": "Base address 1", + "offset": 0, + "size": 32 + } + } + } + }, + "PREFIX0": { + "description": "Prefixes bytes for logical addresses 0-3", + "offset": 1316, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AP0": { + "description": "Address prefix 0.", + "offset": 0, + "size": 8 + }, + "AP1": { + "description": "Address prefix 1.", + "offset": 8, + "size": 8 + }, + "AP2": { + "description": "Address prefix 2.", + "offset": 16, + "size": 8 + }, + "AP3": { + "description": "Address prefix 3.", + "offset": 24, + "size": 8 + } + } + } + }, + "PREFIX1": { + "description": "Prefixes bytes for logical addresses 4-7", + "offset": 1320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AP4": { + "description": "Address prefix 4.", + "offset": 0, + "size": 8 + }, + "AP5": { + "description": "Address prefix 5.", + "offset": 8, + "size": 8 + }, + "AP6": { + "description": "Address prefix 6.", + "offset": 16, + "size": 8 + }, + "AP7": { + "description": "Address prefix 7.", + "offset": 24, + "size": 8 + } + } + } + }, + "TXADDRESS": { + "description": "Transmit address select", + "offset": 1324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXADDRESS": { + "description": "Transmit address select", + "offset": 0, + "size": 3 + } + } + } + }, + "RXADDRESSES": { + "description": "Receive address select", + "offset": 1328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDR0": { + "description": "Enable or disable reception on logical address 0.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR1": { + "description": "Enable or disable reception on logical address 1.", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR2": { + "description": "Enable or disable reception on logical address 2.", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR3": { + "description": "Enable or disable reception on logical address 3.", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR4": { + "description": "Enable or disable reception on logical address 4.", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR5": { + "description": "Enable or disable reception on logical address 5.", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR6": { + "description": "Enable or disable reception on logical address 6.", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ADDR7": { + "description": "Enable or disable reception on logical address 7.", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "CRCCNF": { + "description": "CRC configuration", + "offset": 1332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEN": { + "description": "CRC length in number of bytes.", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "CRC length is zero and CRC calculation is disabled", + "value": 0 + }, + "One": { + "description": "CRC length is one byte and CRC calculation is enabled", + "value": 1 + }, + "Two": { + "description": "CRC length is two bytes and CRC calculation is enabled", + "value": 2 + }, + "Three": { + "description": "CRC length is three bytes and CRC calculation is enabled", + "value": 3 + } + } + } + } + }, + "SKIPADDR": { + "description": "Include or exclude packet address field out of CRC calculation.", + "offset": 8, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Include": { + "description": "CRC calculation includes address field", + "value": 0 + }, + "Skip": { + "description": "CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.", + "value": 1 + }, + "Ieee802154": { + "description": "CRC calculation as per 802.15.4 standard. Starting at first byte after length field.", + "value": 2 + } + } + } + } + } + } + } + }, + "CRCPOLY": { + "description": "CRC polynomial", + "offset": 1336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRCPOLY": { + "description": "CRC polynomial", + "offset": 0, + "size": 24 + } + } + } + }, + "CRCINIT": { + "description": "CRC initial value", + "offset": 1340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRCINIT": { + "description": "CRC initial value", + "offset": 0, + "size": 24 + } + } + } + }, + "TIFS": { + "description": "Interframe spacing in us", + "offset": 1348, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIFS": { + "description": "Interframe spacing in us", + "offset": 0, + "size": 10 + } + } + } + }, + "RSSISAMPLE": { + "description": "RSSI sample", + "offset": 1352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RSSISAMPLE": { + "description": "RSSI sample", + "offset": 0, + "size": 7 + } + } + } + }, + "STATE": { + "description": "Current radio state", + "offset": 1360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STATE": { + "description": "Current radio state", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "RADIO is in the Disabled state", + "value": 0 + }, + "RxRu": { + "description": "RADIO is in the RXRU state", + "value": 1 + }, + "RxIdle": { + "description": "RADIO is in the RXIDLE state", + "value": 2 + }, + "Rx": { + "description": "RADIO is in the RX state", + "value": 3 + }, + "RxDisable": { + "description": "RADIO is in the RXDISABLED state", + "value": 4 + }, + "TxRu": { + "description": "RADIO is in the TXRU state", + "value": 9 + }, + "TxIdle": { + "description": "RADIO is in the TXIDLE state", + "value": 10 + }, + "Tx": { + "description": "RADIO is in the TX state", + "value": 11 + }, + "TxDisable": { + "description": "RADIO is in the TXDISABLED state", + "value": 12 + } + } + } + } + } + } + } + }, + "DATAWHITEIV": { + "description": "Data whitening initial value", + "offset": 1364, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATAWHITEIV": { + "description": "Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.", + "offset": 0, + "size": 7 + } + } + } + }, + "BCC": { + "description": "Bit counter compare", + "offset": 1376, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BCC": { + "description": "Bit counter compare", + "offset": 0, + "size": 32 + } + } + } + }, + "DAB": { + "description": "Description collection: Device address base segment n", + "offset": 1536, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAB": { + "description": "Device address base segment n", + "offset": 0, + "size": 32 + } + } + } + }, + "DAP": { + "description": "Description collection: Device address prefix n", + "offset": 1568, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAP": { + "description": "Device address prefix n", + "offset": 0, + "size": 16 + } + } + } + }, + "DACNF": { + "description": "Device address match configuration", + "offset": 1600, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENA0": { + "description": "Enable or disable device address matching using device address 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA1": { + "description": "Enable or disable device address matching using device address 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA2": { + "description": "Enable or disable device address matching using device address 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA3": { + "description": "Enable or disable device address matching using device address 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA4": { + "description": "Enable or disable device address matching using device address 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA5": { + "description": "Enable or disable device address matching using device address 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA6": { + "description": "Enable or disable device address matching using device address 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ENA7": { + "description": "Enable or disable device address matching using device address 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "TXADD0": { + "description": "TxAdd for device address 0", + "offset": 8, + "size": 1 + }, + "TXADD1": { + "description": "TxAdd for device address 1", + "offset": 9, + "size": 1 + }, + "TXADD2": { + "description": "TxAdd for device address 2", + "offset": 10, + "size": 1 + }, + "TXADD3": { + "description": "TxAdd for device address 3", + "offset": 11, + "size": 1 + }, + "TXADD4": { + "description": "TxAdd for device address 4", + "offset": 12, + "size": 1 + }, + "TXADD5": { + "description": "TxAdd for device address 5", + "offset": 13, + "size": 1 + }, + "TXADD6": { + "description": "TxAdd for device address 6", + "offset": 14, + "size": 1 + }, + "TXADD7": { + "description": "TxAdd for device address 7", + "offset": 15, + "size": 1 + } + } + } + }, + "MHRMATCHCONF": { + "description": "Search pattern configuration", + "offset": 1604, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MHRMATCHCONF": { + "description": "Search pattern configuration", + "offset": 0, + "size": 32 + } + } + } + }, + "MHRMATCHMAS": { + "description": "Pattern mask", + "offset": 1608, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MHRMATCHMAS": { + "description": "Pattern mask", + "offset": 0, + "size": 32 + } + } + } + }, + "MODECNF0": { + "description": "Radio mode configuration register 0", + "offset": 1616, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "RU": { + "description": "Radio ramp-up time", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Default": { + "description": "Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51", + "value": 0 + }, + "Fast": { + "description": "Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information", + "value": 1 + } + } + } + } + }, + "DTX": { + "description": "Default TX value", + "offset": 8, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "B1": { + "description": "Transmit '1'", + "value": 0 + }, + "B0": { + "description": "Transmit '0'", + "value": 1 + }, + "Center": { + "description": "Transmit center frequency", + "value": 2 + } + } + } + } + } + } + } + }, + "SFD": { + "description": "IEEE 802.15.4 start of frame delimiter", + "offset": 1632, + "size": 32, + "reset_value": 167, + "reset_mask": 4294967295, + "children": { + "fields": { + "SFD": { + "description": "IEEE 802.15.4 start of frame delimiter", + "offset": 0, + "size": 8 + } + } + } + }, + "EDCNT": { + "description": "IEEE 802.15.4 energy detect loop count", + "offset": 1636, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EDCNT": { + "description": "IEEE 802.15.4 energy detect loop count", + "offset": 0, + "size": 21 + } + } + } + }, + "EDSAMPLE": { + "description": "IEEE 802.15.4 energy detect level", + "offset": 1640, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EDLVL": { + "description": "IEEE 802.15.4 energy detect level", + "offset": 0, + "size": 8 + } + } + } + }, + "CCACTRL": { + "description": "IEEE 802.15.4 clear channel assessment control", + "offset": 1644, + "size": 32, + "reset_value": 86835200, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCAMODE": { + "description": "CCA mode of operation", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "EdMode": { + "description": "Energy above threshold", + "value": 0 + }, + "CarrierMode": { + "description": "Carrier seen", + "value": 1 + }, + "CarrierAndEdMode": { + "description": "Energy above threshold AND carrier seen", + "value": 2 + }, + "CarrierOrEdMode": { + "description": "Energy above threshold OR carrier seen", + "value": 3 + }, + "EdModeTest1": { + "description": "Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging.", + "value": 4 + } + } + } + } + }, + "CCAEDTHRES": { + "description": "CCA energy busy threshold. Used in all the CCA modes except CarrierMode.", + "offset": 8, + "size": 8 + }, + "CCACORRTHRES": { + "description": "CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode.", + "offset": 16, + "size": 8 + }, + "CCACORRCNT": { + "description": "Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled.", + "offset": 24, + "size": 8 + } + } + } + }, + "POWER": { + "description": "Peripheral power control", + "offset": 4092, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "POWER": { + "description": "Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Peripheral is powered off", + "value": 0 + }, + "Enabled": { + "description": "Peripheral is powered on", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "UART0": { + "description": "Universal Asynchronous Receiver/Transmitter", + "children": { + "registers": { + "TASKS_STARTRX": { + "description": "Start UART receiver", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTRX": { + "description": "Start UART receiver", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOPRX": { + "description": "Stop UART receiver", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOPRX": { + "description": "Stop UART receiver", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STARTTX": { + "description": "Start UART transmitter", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTTX": { + "description": "Start UART transmitter", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOPTX": { + "description": "Stop UART transmitter", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOPTX": { + "description": "Stop UART transmitter", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SUSPEND": { + "description": "Suspend UART", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SUSPEND": { + "description": "Suspend UART", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CTS": { + "description": "CTS is activated (set low). Clear To Send.", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CTS": { + "description": "CTS is activated (set low). Clear To Send.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_NCTS": { + "description": "CTS is deactivated (set high). Not Clear To Send.", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_NCTS": { + "description": "CTS is deactivated (set high). Not Clear To Send.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXDRDY": { + "description": "Data received in RXD", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXDRDY": { + "description": "Data received in RXD", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TXDRDY": { + "description": "Data sent from TXD", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TXDRDY": { + "description": "Data sent from TXD", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ERROR": { + "description": "Error detected", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ERROR": { + "description": "Error detected", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXTO": { + "description": "Receiver timeout", + "offset": 324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXTO": { + "description": "Receiver timeout", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS_STARTRX": { + "description": "Shortcut between event CTS and task STARTRX", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "NCTS_STOPRX": { + "description": "Shortcut between event NCTS and task STOPRX", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "Write '1' to enable interrupt for event CTS", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NCTS": { + "description": "Write '1' to enable interrupt for event NCTS", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDRDY": { + "description": "Write '1' to enable interrupt for event RXDRDY", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDRDY": { + "description": "Write '1' to enable interrupt for event TXDRDY", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to enable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXTO": { + "description": "Write '1' to enable interrupt for event RXTO", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "Write '1' to disable interrupt for event CTS", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NCTS": { + "description": "Write '1' to disable interrupt for event NCTS", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDRDY": { + "description": "Write '1' to disable interrupt for event RXDRDY", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDRDY": { + "description": "Write '1' to disable interrupt for event TXDRDY", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to disable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXTO": { + "description": "Write '1' to disable interrupt for event RXTO", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSRC": { + "description": "Error source", + "offset": 1152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERRUN": { + "description": "Overrun error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "PARITY": { + "description": "Parity error", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "FRAMING": { + "description": "Framing error occurred", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "BREAK": { + "description": "Break condition", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable UART", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable UART", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable UART", + "value": 0 + }, + "Enabled": { + "description": "Enable UART", + "value": 4 + } + } + } + } + } + } + } + }, + "RXD": { + "description": "RXD register", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RXD": { + "description": "RX data received in previous transfers, double buffered", + "offset": 0, + "size": 8 + } + } + } + }, + "TXD": { + "description": "TXD register", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TXD": { + "description": "TX data to be transferred", + "offset": 0, + "size": 8 + } + } + } + }, + "BAUDRATE": { + "description": "Baud rate. Accuracy depends on the HFCLK source selected.", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "BAUDRATE": { + "description": "Baud rate", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Baud1200": { + "description": "1200 baud (actual rate: 1205)", + "value": 323584 + }, + "Baud2400": { + "description": "2400 baud (actual rate: 2396)", + "value": 643072 + }, + "Baud4800": { + "description": "4800 baud (actual rate: 4808)", + "value": 1290240 + }, + "Baud9600": { + "description": "9600 baud (actual rate: 9598)", + "value": 2576384 + }, + "Baud14400": { + "description": "14400 baud (actual rate: 14414)", + "value": 3866624 + }, + "Baud19200": { + "description": "19200 baud (actual rate: 19208)", + "value": 5152768 + }, + "Baud28800": { + "description": "28800 baud (actual rate: 28829)", + "value": 7729152 + }, + "Baud31250": { + "description": "31250 baud", + "value": 8388608 + }, + "Baud38400": { + "description": "38400 baud (actual rate: 38462)", + "value": 10309632 + }, + "Baud56000": { + "description": "56000 baud (actual rate: 55944)", + "value": 15007744 + }, + "Baud57600": { + "description": "57600 baud (actual rate: 57762)", + "value": 15462400 + }, + "Baud76800": { + "description": "76800 baud (actual rate: 76923)", + "value": 20615168 + }, + "Baud115200": { + "description": "115200 baud (actual rate: 115942)", + "value": 30924800 + }, + "Baud230400": { + "description": "230400 baud (actual rate: 231884)", + "value": 61845504 + }, + "Baud250000": { + "description": "250000 baud", + "value": 67108864 + }, + "Baud460800": { + "description": "460800 baud (actual rate: 470588)", + "value": 123695104 + }, + "Baud921600": { + "description": "921600 baud (actual rate: 941176)", + "value": 247386112 + }, + "Baud1M": { + "description": "1Mega baud", + "value": 268435456 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration of parity and hardware flow control", + "offset": 1388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HWFC": { + "description": "Hardware flow control", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "PARITY": { + "description": "Parity", + "offset": 1, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude parity bit", + "value": 0 + }, + "Included": { + "description": "Include parity bit", + "value": 7 + } + } + } + } + }, + "STOP": { + "description": "Stop bits", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "One": { + "description": "One stop bit", + "value": 0 + }, + "Two": { + "description": "Two stop bits", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "UARTE0": { + "description": "UART with EasyDMA 0", + "children": { + "registers": { + "TASKS_STARTRX": { + "description": "Start UART receiver", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTRX": { + "description": "Start UART receiver", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOPRX": { + "description": "Stop UART receiver", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOPRX": { + "description": "Stop UART receiver", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STARTTX": { + "description": "Start UART transmitter", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTTX": { + "description": "Start UART transmitter", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOPTX": { + "description": "Stop UART transmitter", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOPTX": { + "description": "Stop UART transmitter", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_FLUSHRX": { + "description": "Flush RX FIFO into RX buffer", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_FLUSHRX": { + "description": "Flush RX FIFO into RX buffer", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CTS": { + "description": "CTS is activated (set low). Clear To Send.", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CTS": { + "description": "CTS is activated (set low). Clear To Send.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_NCTS": { + "description": "CTS is deactivated (set high). Not Clear To Send.", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_NCTS": { + "description": "CTS is deactivated (set high). Not Clear To Send.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXDRDY": { + "description": "Data received in RXD (but potentially not yet transferred to Data RAM)", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXDRDY": { + "description": "Data received in RXD (but potentially not yet transferred to Data RAM)", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDRX": { + "description": "Receive buffer is filled up", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDRX": { + "description": "Receive buffer is filled up", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TXDRDY": { + "description": "Data sent from TXD", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TXDRDY": { + "description": "Data sent from TXD", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDTX": { + "description": "Last TX byte transmitted", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDTX": { + "description": "Last TX byte transmitted", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ERROR": { + "description": "Error detected", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ERROR": { + "description": "Error detected", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXTO": { + "description": "Receiver timeout", + "offset": 324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXTO": { + "description": "Receiver timeout", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXSTARTED": { + "description": "UART receiver has started", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXSTARTED": { + "description": "UART receiver has started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TXSTARTED": { + "description": "UART transmitter has started", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TXSTARTED": { + "description": "UART transmitter has started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TXSTOPPED": { + "description": "Transmitter stopped", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TXSTOPPED": { + "description": "Transmitter stopped", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDRX_STARTRX": { + "description": "Shortcut between event ENDRX and task STARTRX", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "ENDRX_STOPRX": { + "description": "Shortcut between event ENDRX and task STOPRX", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "Enable or disable interrupt for event CTS", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "NCTS": { + "description": "Enable or disable interrupt for event NCTS", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXDRDY": { + "description": "Enable or disable interrupt for event RXDRDY", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Enable or disable interrupt for event ENDRX", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXDRDY": { + "description": "Enable or disable interrupt for event TXDRDY", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Enable or disable interrupt for event ENDTX", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Enable or disable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXTO": { + "description": "Enable or disable interrupt for event RXTO", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Enable or disable interrupt for event RXSTARTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Enable or disable interrupt for event TXSTARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXSTOPPED": { + "description": "Enable or disable interrupt for event TXSTOPPED", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "Write '1' to enable interrupt for event CTS", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NCTS": { + "description": "Write '1' to enable interrupt for event NCTS", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDRDY": { + "description": "Write '1' to enable interrupt for event RXDRDY", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to enable interrupt for event ENDRX", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDRDY": { + "description": "Write '1' to enable interrupt for event TXDRDY", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to enable interrupt for event ENDTX", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to enable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXTO": { + "description": "Write '1' to enable interrupt for event RXTO", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to enable interrupt for event RXSTARTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to enable interrupt for event TXSTARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTOPPED": { + "description": "Write '1' to enable interrupt for event TXSTOPPED", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "Write '1' to disable interrupt for event CTS", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NCTS": { + "description": "Write '1' to disable interrupt for event NCTS", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDRDY": { + "description": "Write '1' to disable interrupt for event RXDRDY", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to disable interrupt for event ENDRX", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDRDY": { + "description": "Write '1' to disable interrupt for event TXDRDY", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to disable interrupt for event ENDTX", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to disable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXTO": { + "description": "Write '1' to disable interrupt for event RXTO", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to disable interrupt for event RXSTARTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to disable interrupt for event TXSTARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTOPPED": { + "description": "Write '1' to disable interrupt for event TXSTOPPED", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSRC": { + "description": "Error source Note : this register is read / write one to clear.", + "offset": 1152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERRUN": { + "description": "Overrun error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "PARITY": { + "description": "Parity error", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "FRAMING": { + "description": "Framing error occurred", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "BREAK": { + "description": "Break condition", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable UART", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable UARTE", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable UARTE", + "value": 0 + }, + "Enabled": { + "description": "Enable UARTE", + "value": 8 + } + } + } + } + } + } + } + }, + "BAUDRATE": { + "description": "Baud rate. Accuracy depends on the HFCLK source selected.", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "BAUDRATE": { + "description": "Baud rate", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Baud1200": { + "description": "1200 baud (actual rate: 1205)", + "value": 323584 + }, + "Baud2400": { + "description": "2400 baud (actual rate: 2396)", + "value": 643072 + }, + "Baud4800": { + "description": "4800 baud (actual rate: 4808)", + "value": 1290240 + }, + "Baud9600": { + "description": "9600 baud (actual rate: 9598)", + "value": 2576384 + }, + "Baud14400": { + "description": "14400 baud (actual rate: 14401)", + "value": 3862528 + }, + "Baud19200": { + "description": "19200 baud (actual rate: 19208)", + "value": 5152768 + }, + "Baud28800": { + "description": "28800 baud (actual rate: 28777)", + "value": 7716864 + }, + "Baud31250": { + "description": "31250 baud", + "value": 8388608 + }, + "Baud38400": { + "description": "38400 baud (actual rate: 38369)", + "value": 10289152 + }, + "Baud56000": { + "description": "56000 baud (actual rate: 55944)", + "value": 15007744 + }, + "Baud57600": { + "description": "57600 baud (actual rate: 57554)", + "value": 15400960 + }, + "Baud76800": { + "description": "76800 baud (actual rate: 76923)", + "value": 20615168 + }, + "Baud115200": { + "description": "115200 baud (actual rate: 115108)", + "value": 30801920 + }, + "Baud230400": { + "description": "230400 baud (actual rate: 231884)", + "value": 61865984 + }, + "Baud250000": { + "description": "250000 baud", + "value": 67108864 + }, + "Baud460800": { + "description": "460800 baud (actual rate: 457143)", + "value": 121634816 + }, + "Baud921600": { + "description": "921600 baud (actual rate: 941176)", + "value": 251658240 + }, + "Baud1M": { + "description": "1Mega baud", + "value": 268435456 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration of parity and hardware flow control", + "offset": 1388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HWFC": { + "description": "Hardware flow control", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "PARITY": { + "description": "Parity", + "offset": 1, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude parity bit", + "value": 0 + }, + "Included": { + "description": "Include even parity bit", + "value": 7 + } + } + } + } + }, + "STOP": { + "description": "Stop bits", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "One": { + "description": "One stop bit", + "value": 0 + }, + "Two": { + "description": "Two stop bits", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "SPI0": { + "description": "Serial Peripheral Interface 0", + "children": { + "registers": { + "EVENTS_READY": { + "description": "TXD byte sent and RXD byte received", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_READY": { + "description": "TXD byte sent and RXD byte received", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to enable interrupt for event READY", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to disable interrupt for event READY", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable SPI", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable SPI", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable SPI", + "value": 0 + }, + "Enabled": { + "description": "Enable SPI", + "value": 1 + } + } + } + } + } + } + } + }, + "RXD": { + "description": "RXD register", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RXD": { + "description": "RX data received. Double buffered", + "offset": 0, + "size": 8 + } + } + } + }, + "TXD": { + "description": "TXD register", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXD": { + "description": "TX data to send. Double buffered", + "offset": 0, + "size": 8 + } + } + } + }, + "FREQUENCY": { + "description": "SPI frequency. Accuracy depends on the HFCLK source selected.", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQUENCY": { + "description": "SPI master data rate", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "K125": { + "description": "125 kbps", + "value": 33554432 + }, + "K250": { + "description": "250 kbps", + "value": 67108864 + }, + "K500": { + "description": "500 kbps", + "value": 134217728 + }, + "M1": { + "description": "1 Mbps", + "value": 268435456 + }, + "M2": { + "description": "2 Mbps", + "value": 536870912 + }, + "M4": { + "description": "4 Mbps", + "value": 1073741824 + }, + "M8": { + "description": "8 Mbps", + "value": 2147483648 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORDER": { + "description": "Bit order", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "MsbFirst": { + "description": "Most significant bit shifted out first", + "value": 0 + }, + "LsbFirst": { + "description": "Least significant bit shifted out first", + "value": 1 + } + } + } + } + }, + "CPHA": { + "description": "Serial clock (SCK) phase", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Leading": { + "description": "Sample on leading edge of clock, shift serial data on trailing edge", + "value": 0 + }, + "Trailing": { + "description": "Sample on trailing edge of clock, shift serial data on leading edge", + "value": 1 + } + } + } + } + }, + "CPOL": { + "description": "Serial clock (SCK) polarity", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "ActiveHigh": { + "description": "Active high", + "value": 0 + }, + "ActiveLow": { + "description": "Active low", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "SPIM0": { + "description": "Serial Peripheral Interface Master with EasyDMA 0", + "children": { + "registers": { + "TASKS_START": { + "description": "Start SPI transaction", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Start SPI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stop SPI transaction", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop SPI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SUSPEND": { + "description": "Suspend SPI transaction", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SUSPEND": { + "description": "Suspend SPI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_RESUME": { + "description": "Resume SPI transaction", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_RESUME": { + "description": "Resume SPI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STOPPED": { + "description": "SPI transaction has stopped", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STOPPED": { + "description": "SPI transaction has stopped", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDRX": { + "description": "End of RXD buffer reached", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDRX": { + "description": "End of RXD buffer reached", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_END": { + "description": "End of RXD buffer and TXD buffer reached", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_END": { + "description": "End of RXD buffer and TXD buffer reached", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDTX": { + "description": "End of TXD buffer reached", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDTX": { + "description": "End of TXD buffer reached", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STARTED": { + "description": "Transaction started", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STARTED": { + "description": "Transaction started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END_START": { + "description": "Shortcut between event END and task START", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to enable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to enable interrupt for event ENDRX", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to enable interrupt for event END", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to enable interrupt for event ENDTX", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Write '1' to enable interrupt for event STARTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to disable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to disable interrupt for event ENDRX", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to disable interrupt for event END", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to disable interrupt for event ENDTX", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Write '1' to disable interrupt for event STARTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "STALLSTAT": { + "description": "Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU.", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TX": { + "description": "Stall status for EasyDMA RAM reads", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NOSTALL": { + "description": "No stall", + "value": 0 + }, + "STALL": { + "description": "A stall has occurred", + "value": 1 + } + } + } + } + }, + "RX": { + "description": "Stall status for EasyDMA RAM writes", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NOSTALL": { + "description": "No stall", + "value": 0 + }, + "STALL": { + "description": "A stall has occurred", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable SPIM", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable SPIM", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable SPIM", + "value": 0 + }, + "Enabled": { + "description": "Enable SPIM", + "value": 7 + } + } + } + } + } + } + } + }, + "FREQUENCY": { + "description": "SPI frequency. Accuracy depends on the HFCLK source selected.", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQUENCY": { + "description": "SPI master data rate", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "K125": { + "description": "125 kbps", + "value": 33554432 + }, + "K250": { + "description": "250 kbps", + "value": 67108864 + }, + "K500": { + "description": "500 kbps", + "value": 134217728 + }, + "M1": { + "description": "1 Mbps", + "value": 268435456 + }, + "M2": { + "description": "2 Mbps", + "value": 536870912 + }, + "M4": { + "description": "4 Mbps", + "value": 1073741824 + }, + "M8": { + "description": "8 Mbps", + "value": 2147483648 + }, + "M16": { + "description": "16 Mbps", + "value": 167772160 + }, + "M32": { + "description": "32 Mbps", + "value": 335544320 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORDER": { + "description": "Bit order", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "MsbFirst": { + "description": "Most significant bit shifted out first", + "value": 0 + }, + "LsbFirst": { + "description": "Least significant bit shifted out first", + "value": 1 + } + } + } + } + }, + "CPHA": { + "description": "Serial clock (SCK) phase", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Leading": { + "description": "Sample on leading edge of clock, shift serial data on trailing edge", + "value": 0 + }, + "Trailing": { + "description": "Sample on trailing edge of clock, shift serial data on leading edge", + "value": 1 + } + } + } + } + }, + "CPOL": { + "description": "Serial clock (SCK) polarity", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "ActiveHigh": { + "description": "Active high", + "value": 0 + }, + "ActiveLow": { + "description": "Active low", + "value": 1 + } + } + } + } + } + } + } + }, + "CSNPOL": { + "description": "Polarity of CSN output", + "offset": 1384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSNPOL": { + "description": "Polarity of CSN output", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "LOW": { + "description": "Active low (idle state high)", + "value": 0 + }, + "HIGH": { + "description": "Active high (idle state low)", + "value": 1 + } + } + } + } + } + } + } + }, + "PSELDCX": { + "description": "Pin select for DCX signal", + "offset": 1388, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN": { + "description": "Pin number", + "offset": 0, + "size": 5 + }, + "PORT": { + "description": "Port number", + "offset": 5, + "size": 1 + }, + "CONNECT": { + "description": "Connection", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disconnected": { + "description": "Disconnect", + "value": 1 + }, + "Connected": { + "description": "Connect", + "value": 0 + } + } + } + } + } + } + } + }, + "DCXCNT": { + "description": "DCX configuration", + "offset": 1392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCXCNT": { + "description": "This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes.", + "offset": 0, + "size": 4 + } + } + } + }, + "ORC": { + "description": "Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT", + "offset": 1472, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORC": { + "description": "Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT.", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "SPIS0": { + "description": "SPI Slave 0", + "children": { + "registers": { + "TASKS_ACQUIRE": { + "description": "Acquire SPI semaphore", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_ACQUIRE": { + "description": "Acquire SPI semaphore", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_RELEASE": { + "description": "Release SPI semaphore, enabling the SPI slave to acquire it", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_RELEASE": { + "description": "Release SPI semaphore, enabling the SPI slave to acquire it", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_END": { + "description": "Granted transaction completed", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_END": { + "description": "Granted transaction completed", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDRX": { + "description": "End of RXD buffer reached", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDRX": { + "description": "End of RXD buffer reached", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ACQUIRED": { + "description": "Semaphore acquired", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ACQUIRED": { + "description": "Semaphore acquired", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END_ACQUIRE": { + "description": "Shortcut between event END and task ACQUIRE", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END": { + "description": "Write '1' to enable interrupt for event END", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to enable interrupt for event ENDRX", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ACQUIRED": { + "description": "Write '1' to enable interrupt for event ACQUIRED", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END": { + "description": "Write '1' to disable interrupt for event END", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to disable interrupt for event ENDRX", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ACQUIRED": { + "description": "Write '1' to disable interrupt for event ACQUIRED", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "SEMSTAT": { + "description": "Semaphore status register", + "offset": 1024, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SEMSTAT": { + "description": "Semaphore status", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Free": { + "description": "Semaphore is free", + "value": 0 + }, + "CPU": { + "description": "Semaphore is assigned to CPU", + "value": 1 + }, + "SPIS": { + "description": "Semaphore is assigned to SPI slave", + "value": 2 + }, + "CPUPending": { + "description": "Semaphore is assigned to SPI but a handover to the CPU is pending", + "value": 3 + } + } + } + } + } + } + } + }, + "STATUS": { + "description": "Status from last transaction", + "offset": 1088, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERREAD": { + "description": "TX buffer over-read detected, and prevented", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "OVERFLOW": { + "description": "RX buffer overflow detected, and prevented", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable SPI slave", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable SPI slave", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable SPI slave", + "value": 0 + }, + "Enabled": { + "description": "Enable SPI slave", + "value": 2 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORDER": { + "description": "Bit order", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "MsbFirst": { + "description": "Most significant bit shifted out first", + "value": 0 + }, + "LsbFirst": { + "description": "Least significant bit shifted out first", + "value": 1 + } + } + } + } + }, + "CPHA": { + "description": "Serial clock (SCK) phase", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Leading": { + "description": "Sample on leading edge of clock, shift serial data on trailing edge", + "value": 0 + }, + "Trailing": { + "description": "Sample on trailing edge of clock, shift serial data on leading edge", + "value": 1 + } + } + } + } + }, + "CPOL": { + "description": "Serial clock (SCK) polarity", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "ActiveHigh": { + "description": "Active high", + "value": 0 + }, + "ActiveLow": { + "description": "Active low", + "value": 1 + } + } + } + } + } + } + } + }, + "DEF": { + "description": "Default character. Character clocked out in case of an ignored transaction.", + "offset": 1372, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DEF": { + "description": "Default character. Character clocked out in case of an ignored transaction.", + "offset": 0, + "size": 8 + } + } + } + }, + "ORC": { + "description": "Over-read character", + "offset": 1472, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORC": { + "description": "Over-read character. Character clocked out after an over-read of the transmit buffer.", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "TWI0": { + "description": "I2C compatible Two-Wire Interface 0", + "children": { + "registers": { + "TASKS_STARTRX": { + "description": "Start TWI receive sequence", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTRX": { + "description": "Start TWI receive sequence", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STARTTX": { + "description": "Start TWI transmit sequence", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTTX": { + "description": "Start TWI transmit sequence", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stop TWI transaction", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop TWI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SUSPEND": { + "description": "Suspend TWI transaction", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SUSPEND": { + "description": "Suspend TWI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_RESUME": { + "description": "Resume TWI transaction", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_RESUME": { + "description": "Resume TWI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STOPPED": { + "description": "TWI stopped", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STOPPED": { + "description": "TWI stopped", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXDREADY": { + "description": "TWI RXD byte received", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXDREADY": { + "description": "TWI RXD byte received", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TXDSENT": { + "description": "TWI TXD byte sent", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TXDSENT": { + "description": "TWI TXD byte sent", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ERROR": { + "description": "TWI error", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ERROR": { + "description": "TWI error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_BB": { + "description": "TWI byte boundary, generated before each byte that is sent or received", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_BB": { + "description": "TWI byte boundary, generated before each byte that is sent or received", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_SUSPENDED": { + "description": "TWI entered the suspended state", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_SUSPENDED": { + "description": "TWI entered the suspended state", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BB_SUSPEND": { + "description": "Shortcut between event BB and task SUSPEND", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "BB_STOP": { + "description": "Shortcut between event BB and task STOP", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to enable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDREADY": { + "description": "Write '1' to enable interrupt for event RXDREADY", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDSENT": { + "description": "Write '1' to enable interrupt for event TXDSENT", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to enable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "BB": { + "description": "Write '1' to enable interrupt for event BB", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SUSPENDED": { + "description": "Write '1' to enable interrupt for event SUSPENDED", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to disable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXDREADY": { + "description": "Write '1' to disable interrupt for event RXDREADY", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXDSENT": { + "description": "Write '1' to disable interrupt for event TXDSENT", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to disable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "BB": { + "description": "Write '1' to disable interrupt for event BB", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SUSPENDED": { + "description": "Write '1' to disable interrupt for event SUSPENDED", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSRC": { + "description": "Error source", + "offset": 1220, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERRUN": { + "description": "Overrun error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: no overrun occured", + "value": 0 + }, + "Present": { + "description": "Read: overrun occured", + "value": 1 + } + } + } + } + }, + "ANACK": { + "description": "NACK received after sending the address (write '1' to clear)", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + }, + "DNACK": { + "description": "NACK received after sending a data byte (write '1' to clear)", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotPresent": { + "description": "Read: error not present", + "value": 0 + }, + "Present": { + "description": "Read: error present", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable TWI", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable TWI", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable TWI", + "value": 0 + }, + "Enabled": { + "description": "Enable TWI", + "value": 5 + } + } + } + } + } + } + } + }, + "RXD": { + "description": "RXD register", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RXD": { + "description": "RXD register", + "offset": 0, + "size": 8 + } + } + } + }, + "TXD": { + "description": "TXD register", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXD": { + "description": "TXD register", + "offset": 0, + "size": 8 + } + } + } + }, + "FREQUENCY": { + "description": "TWI frequency. Accuracy depends on the HFCLK source selected.", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQUENCY": { + "description": "TWI master clock frequency", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "K100": { + "description": "100 kbps", + "value": 26738688 + }, + "K250": { + "description": "250 kbps", + "value": 67108864 + }, + "K400": { + "description": "400 kbps (actual rate 410.256 kbps)", + "value": 107479040 + } + } + } + } + } + } + } + }, + "ADDRESS": { + "description": "Address used in the TWI transfer", + "offset": 1416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS": { + "description": "Address used in the TWI transfer", + "offset": 0, + "size": 7 + } + } + } + } + } + } + }, + "TWIM0": { + "description": "I2C compatible Two-Wire Master Interface with EasyDMA 0", + "children": { + "registers": { + "TASKS_STARTRX": { + "description": "Start TWI receive sequence", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTRX": { + "description": "Start TWI receive sequence", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STARTTX": { + "description": "Start TWI transmit sequence", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTTX": { + "description": "Start TWI transmit sequence", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stop TWI transaction. Must be issued while the TWI master is not suspended.", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop TWI transaction. Must be issued while the TWI master is not suspended.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SUSPEND": { + "description": "Suspend TWI transaction", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SUSPEND": { + "description": "Suspend TWI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_RESUME": { + "description": "Resume TWI transaction", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_RESUME": { + "description": "Resume TWI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STOPPED": { + "description": "TWI stopped", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STOPPED": { + "description": "TWI stopped", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ERROR": { + "description": "TWI error", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ERROR": { + "description": "TWI error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_SUSPENDED": { + "description": "Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_SUSPENDED": { + "description": "Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXSTARTED": { + "description": "Receive sequence started", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXSTARTED": { + "description": "Receive sequence started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TXSTARTED": { + "description": "Transmit sequence started", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TXSTARTED": { + "description": "Transmit sequence started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_LASTRX": { + "description": "Byte boundary, starting to receive the last byte", + "offset": 348, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_LASTRX": { + "description": "Byte boundary, starting to receive the last byte", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_LASTTX": { + "description": "Byte boundary, starting to transmit the last byte", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_LASTTX": { + "description": "Byte boundary, starting to transmit the last byte", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LASTTX_STARTRX": { + "description": "Shortcut between event LASTTX and task STARTRX", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LASTTX_SUSPEND": { + "description": "Shortcut between event LASTTX and task SUSPEND", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LASTTX_STOP": { + "description": "Shortcut between event LASTTX and task STOP", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LASTRX_STARTTX": { + "description": "Shortcut between event LASTRX and task STARTTX", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LASTRX_SUSPEND": { + "description": "Shortcut between event LASTRX and task SUSPEND", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LASTRX_STOP": { + "description": "Shortcut between event LASTRX and task STOP", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Enable or disable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Enable or disable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SUSPENDED": { + "description": "Enable or disable interrupt for event SUSPENDED", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Enable or disable interrupt for event RXSTARTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Enable or disable interrupt for event TXSTARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "LASTRX": { + "description": "Enable or disable interrupt for event LASTRX", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "LASTTX": { + "description": "Enable or disable interrupt for event LASTTX", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to enable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to enable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SUSPENDED": { + "description": "Write '1' to enable interrupt for event SUSPENDED", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to enable interrupt for event RXSTARTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to enable interrupt for event TXSTARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LASTRX": { + "description": "Write '1' to enable interrupt for event LASTRX", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LASTTX": { + "description": "Write '1' to enable interrupt for event LASTTX", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to disable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to disable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SUSPENDED": { + "description": "Write '1' to disable interrupt for event SUSPENDED", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to disable interrupt for event RXSTARTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to disable interrupt for event TXSTARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LASTRX": { + "description": "Write '1' to disable interrupt for event LASTRX", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LASTTX": { + "description": "Write '1' to disable interrupt for event LASTTX", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSRC": { + "description": "Error source", + "offset": 1220, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERRUN": { + "description": "Overrun error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotReceived": { + "description": "Error did not occur", + "value": 0 + }, + "Received": { + "description": "Error occurred", + "value": 1 + } + } + } + } + }, + "ANACK": { + "description": "NACK received after sending the address (write '1' to clear)", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotReceived": { + "description": "Error did not occur", + "value": 0 + }, + "Received": { + "description": "Error occurred", + "value": 1 + } + } + } + } + }, + "DNACK": { + "description": "NACK received after sending a data byte (write '1' to clear)", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotReceived": { + "description": "Error did not occur", + "value": 0 + }, + "Received": { + "description": "Error occurred", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable TWIM", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable TWIM", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable TWIM", + "value": 0 + }, + "Enabled": { + "description": "Enable TWIM", + "value": 6 + } + } + } + } + } + } + } + }, + "FREQUENCY": { + "description": "TWI frequency. Accuracy depends on the HFCLK source selected.", + "offset": 1316, + "size": 32, + "reset_value": 67108864, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQUENCY": { + "description": "TWI master clock frequency", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "K100": { + "description": "100 kbps", + "value": 26738688 + }, + "K250": { + "description": "250 kbps", + "value": 67108864 + }, + "K400": { + "description": "400 kbps", + "value": 104857600 + } + } + } + } + } + } + } + }, + "ADDRESS": { + "description": "Address used in the TWI transfer", + "offset": 1416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS": { + "description": "Address used in the TWI transfer", + "offset": 0, + "size": 7 + } + } + } + } + } + } + }, + "TWIS0": { + "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 0", + "children": { + "registers": { + "TASKS_STOP": { + "description": "Stop TWI transaction", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop TWI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SUSPEND": { + "description": "Suspend TWI transaction", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SUSPEND": { + "description": "Suspend TWI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_RESUME": { + "description": "Resume TWI transaction", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_RESUME": { + "description": "Resume TWI transaction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_PREPARERX": { + "description": "Prepare the TWI slave to respond to a write command", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_PREPARERX": { + "description": "Prepare the TWI slave to respond to a write command", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_PREPARETX": { + "description": "Prepare the TWI slave to respond to a read command", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_PREPARETX": { + "description": "Prepare the TWI slave to respond to a read command", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STOPPED": { + "description": "TWI stopped", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STOPPED": { + "description": "TWI stopped", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ERROR": { + "description": "TWI error", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ERROR": { + "description": "TWI error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXSTARTED": { + "description": "Receive sequence started", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXSTARTED": { + "description": "Receive sequence started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TXSTARTED": { + "description": "Transmit sequence started", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TXSTARTED": { + "description": "Transmit sequence started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_WRITE": { + "description": "Write command received", + "offset": 356, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_WRITE": { + "description": "Write command received", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_READ": { + "description": "Read command received", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_READ": { + "description": "Read command received", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WRITE_SUSPEND": { + "description": "Shortcut between event WRITE and task SUSPEND", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "READ_SUSPEND": { + "description": "Shortcut between event READ and task SUSPEND", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Enable or disable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Enable or disable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Enable or disable interrupt for event RXSTARTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Enable or disable interrupt for event TXSTARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "WRITE": { + "description": "Enable or disable interrupt for event WRITE", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "READ": { + "description": "Enable or disable interrupt for event READ", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to enable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to enable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to enable interrupt for event RXSTARTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to enable interrupt for event TXSTARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "WRITE": { + "description": "Write '1' to enable interrupt for event WRITE", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "READ": { + "description": "Write '1' to enable interrupt for event READ", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to disable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to disable interrupt for event ERROR", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXSTARTED": { + "description": "Write '1' to disable interrupt for event RXSTARTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXSTARTED": { + "description": "Write '1' to disable interrupt for event TXSTARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "WRITE": { + "description": "Write '1' to disable interrupt for event WRITE", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "READ": { + "description": "Write '1' to disable interrupt for event READ", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSRC": { + "description": "Error source", + "offset": 1232, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERFLOW": { + "description": "RX buffer overflow detected, and prevented", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Error did not occur", + "value": 0 + }, + "Detected": { + "description": "Error occurred", + "value": 1 + } + } + } + } + }, + "DNACK": { + "description": "NACK sent after receiving a data byte", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotReceived": { + "description": "Error did not occur", + "value": 0 + }, + "Received": { + "description": "Error occurred", + "value": 1 + } + } + } + } + }, + "OVERREAD": { + "description": "TX buffer over-read detected, and prevented", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Error did not occur", + "value": 0 + }, + "Detected": { + "description": "Error occurred", + "value": 1 + } + } + } + } + } + } + } + }, + "MATCH": { + "description": "Status register indicating which address had a match", + "offset": 1236, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "MATCH": { + "description": "Which of the addresses in {ADDRESS} matched the incoming address", + "offset": 0, + "size": 1 + } + } + } + }, + "ENABLE": { + "description": "Enable TWIS", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable TWIS", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable TWIS", + "value": 0 + }, + "Enabled": { + "description": "Enable TWIS", + "value": 9 + } + } + } + } + } + } + } + }, + "ADDRESS": { + "description": "Description collection: TWI slave address n", + "offset": 1416, + "size": 32, + "count": 2, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS": { + "description": "TWI slave address", + "offset": 0, + "size": 7 + } + } + } + }, + "CONFIG": { + "description": "Configuration register for the address match mechanism", + "offset": 1428, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS0": { + "description": "Enable or disable address matching on ADDRESS[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + }, + "ADDRESS1": { + "description": "Enable or disable address matching on ADDRESS[1]", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ORC": { + "description": "Over-read character. Character sent out in case of an over-read of the transmit buffer.", + "offset": 1472, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ORC": { + "description": "Over-read character. Character sent out in case of an over-read of the transmit buffer.", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "PDM": { + "description": "Pulse Density Modulation (Digital Microphone) Interface", + "children": { + "registers": { + "TASKS_START": { + "description": "Starts continuous PDM transfer", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Starts continuous PDM transfer", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stops PDM transfer", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stops PDM transfer", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STARTED": { + "description": "PDM transfer has started", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STARTED": { + "description": "PDM transfer has started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STOPPED": { + "description": "PDM transfer has finished", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STOPPED": { + "description": "PDM transfer has finished", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_END": { + "description": "The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_END": { + "description": "The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Enable or disable interrupt for event STARTED", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Enable or disable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Enable or disable interrupt for event END", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Write '1' to enable interrupt for event STARTED", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to enable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to enable interrupt for event END", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Write '1' to disable interrupt for event STARTED", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to disable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to disable interrupt for event END", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "PDM module enable register", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable PDM module", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "PDMCLKCTRL": { + "description": "PDM clock generator control", + "offset": 1284, + "size": 32, + "reset_value": 138412032, + "reset_mask": 4294967295, + "children": { + "fields": { + "FREQ": { + "description": "PDM_CLK frequency", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "1000K": { + "description": "PDM_CLK = 32 MHz / 32 = 1.000 MHz", + "value": 134217728 + }, + "Default": { + "description": "PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64.", + "value": 138412032 + }, + "1067K": { + "description": "PDM_CLK = 32 MHz / 30 = 1.067 MHz", + "value": 142606336 + }, + "1231K": { + "description": "PDM_CLK = 32 MHz / 26 = 1.231 MHz", + "value": 159383552 + }, + "1280K": { + "description": "PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80.", + "value": 167772160 + }, + "1333K": { + "description": "PDM_CLK = 32 MHz / 24 = 1.333 MHz", + "value": 176160768 + } + } + } + } + } + } + } + }, + "MODE": { + "description": "Defines the routing of the connected PDM microphones' signals", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OPERATION": { + "description": "Mono or stereo operation", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Stereo": { + "description": "Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]", + "value": 0 + }, + "Mono": { + "description": "Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]", + "value": 1 + } + } + } + } + }, + "EDGE": { + "description": "Defines on which PDM_CLK edge Left (or mono) is sampled", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "LeftFalling": { + "description": "Left (or mono) is sampled on falling edge of PDM_CLK", + "value": 0 + }, + "LeftRising": { + "description": "Left (or mono) is sampled on rising edge of PDM_CLK", + "value": 1 + } + } + } + } + } + } + } + }, + "GAINL": { + "description": "Left output gain adjustment", + "offset": 1304, + "size": 32, + "reset_value": 40, + "reset_mask": 4294967295, + "children": { + "fields": { + "GAINL": { + "description": "Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust", + "offset": 0, + "size": 7, + "enum": { + "size": 7, + "children": { + "enum_fields": { + "MinGain": { + "description": "-20dB gain adjustment (minimum)", + "value": 0 + }, + "DefaultGain": { + "description": "0dB gain adjustment", + "value": 40 + }, + "MaxGain": { + "description": "+20dB gain adjustment (maximum)", + "value": 80 + } + } + } + } + } + } + } + }, + "GAINR": { + "description": "Right output gain adjustment", + "offset": 1308, + "size": 32, + "reset_value": 40, + "reset_mask": 4294967295, + "children": { + "fields": { + "GAINR": { + "description": "Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)", + "offset": 0, + "size": 7, + "enum": { + "size": 7, + "children": { + "enum_fields": { + "MinGain": { + "description": "-20dB gain adjustment (minimum)", + "value": 0 + }, + "DefaultGain": { + "description": "0dB gain adjustment", + "value": 40 + }, + "MaxGain": { + "description": "+20dB gain adjustment (maximum)", + "value": 80 + } + } + } + } + } + } + } + }, + "RATIO": { + "description": "Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly.", + "offset": 1312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RATIO": { + "description": "Selects the ratio between PDM_CLK and output sample rate", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Ratio64": { + "description": "Ratio of 64", + "value": 0 + }, + "Ratio80": { + "description": "Ratio of 80", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "CRYPTOCELL": { + "description": "ARM TrustZone CryptoCell register interface", + "children": { + "registers": { + "ENABLE": { + "description": "Enable CRYPTOCELL subsystem", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable the CRYPTOCELL subsystem", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "CRYPTOCELL subsystem disabled", + "value": 0 + }, + "Enabled": { + "description": "CRYPTOCELL subsystem enabled", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "CC_HOST_RGF": { + "description": "CRYPTOCELL HOST_RGF interface", + "children": { + "registers": { + "HOST_CRYPTOKEY_SEL": { + "description": "AES hardware key select", + "offset": 6712, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HOST_CRYPTOKEY_SEL": { + "description": "Select the source of the HW key that is used by the AES engine", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "K_DR": { + "description": "Use device root key K_DR from CRYPTOCELL AO power domain", + "value": 0 + }, + "K_PRTL": { + "description": "Use hard-coded RTL key K_PRTL", + "value": 1 + }, + "Session": { + "description": "Use provided session key", + "value": 2 + } + } + } + } + } + } + } + }, + "HOST_IOT_KPRTL_LOCK": { + "description": "This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.", + "offset": 6732, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HOST_IOT_KPRTL_LOCK": { + "description": "This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL", + "value": 0 + }, + "Enabled": { + "description": "K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead.", + "value": 1 + } + } + } + } + } + } + } + }, + "HOST_IOT_KDR0": { + "description": "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained.", + "offset": 6736, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HOST_IOT_KDR0": { + "description": "Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain", + "offset": 0, + "size": 32 + } + } + } + }, + "HOST_IOT_KDR1": { + "description": "This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.", + "offset": 6740, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "HOST_IOT_KDR1": { + "description": "K_DR bits 63:32", + "offset": 0, + "size": 32 + } + } + } + }, + "HOST_IOT_KDR2": { + "description": "This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.", + "offset": 6744, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "HOST_IOT_KDR2": { + "description": "K_DR bits 95:64", + "offset": 0, + "size": 32 + } + } + } + }, + "HOST_IOT_KDR3": { + "description": "This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.", + "offset": 6748, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "HOST_IOT_KDR3": { + "description": "K_DR bits 127:96", + "offset": 0, + "size": 32 + } + } + } + }, + "HOST_IOT_LCS": { + "description": "Controls lifecycle state (LCS) for CRYPTOCELL subsystem", + "offset": 6752, + "size": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "LCS": { + "description": "Lifecycle state value. This field is write-once per reset.", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "Debug": { + "description": "CC310 operates in debug mode", + "value": 0 + }, + "Secure": { + "description": "CC310 operates in secure mode", + "value": 2 + } + } + } + } + }, + "LCS_IS_VALID": { + "description": "This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Invalid": { + "description": "A valid LCS is not yet retained in the CRYPTOCELL AO power domain", + "value": 0 + }, + "Valid": { + "description": "A valid LCS is successfully retained in the CRYPTOCELL AO power domain", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "QSPI": { + "description": "External flash interface", + "children": { + "registers": { + "TASKS_ACTIVATE": { + "description": "Activate QSPI interface", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_ACTIVATE": { + "description": "Activate QSPI interface", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_READSTART": { + "description": "Start transfer from external flash memory to internal RAM", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_READSTART": { + "description": "Start transfer from external flash memory to internal RAM", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_WRITESTART": { + "description": "Start transfer from internal RAM to external flash memory", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_WRITESTART": { + "description": "Start transfer from internal RAM to external flash memory", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_ERASESTART": { + "description": "Start external flash memory erase operation", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_ERASESTART": { + "description": "Start external flash memory erase operation", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_DEACTIVATE": { + "description": "Deactivate QSPI interface", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_DEACTIVATE": { + "description": "Deactivate QSPI interface", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_READY": { + "description": "QSPI peripheral is ready. This event will be generated as a response to any QSPI task.", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_READY": { + "description": "QSPI peripheral is ready. This event will be generated as a response to any QSPI task.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Enable or disable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to enable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to disable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable QSPI peripheral and acquire the pins selected in PSELn registers", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable QSPI", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable QSPI", + "value": 0 + }, + "Enabled": { + "description": "Enable QSPI", + "value": 1 + } + } + } + } + } + } + } + }, + "XIPOFFSET": { + "description": "Address offset into the external memory for Execute in Place operation.", + "offset": 1344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XIPOFFSET": { + "description": "Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4.", + "offset": 0, + "size": 32 + } + } + } + }, + "IFCONFIG0": { + "description": "Interface configuration.", + "offset": 1348, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READOC": { + "description": "Configure number of data lines and opcode used for reading.", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "FASTREAD": { + "description": "Single data line SPI. FAST_READ (opcode 0x0B).", + "value": 0 + }, + "READ2O": { + "description": "Dual data line SPI. READ2O (opcode 0x3B).", + "value": 1 + }, + "READ2IO": { + "description": "Dual data line SPI. READ2IO (opcode 0xBB).", + "value": 2 + }, + "READ4O": { + "description": "Quad data line SPI. READ4O (opcode 0x6B).", + "value": 3 + }, + "READ4IO": { + "description": "Quad data line SPI. READ4IO (opcode 0xEB).", + "value": 4 + } + } + } + } + }, + "WRITEOC": { + "description": "Configure number of data lines and opcode used for writing.", + "offset": 3, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "PP": { + "description": "Single data line SPI. PP (opcode 0x02).", + "value": 0 + }, + "PP2O": { + "description": "Dual data line SPI. PP2O (opcode 0xA2).", + "value": 1 + }, + "PP4O": { + "description": "Quad data line SPI. PP4O (opcode 0x32).", + "value": 2 + }, + "PP4IO": { + "description": "Quad data line SPI. PP4IO (opcode 0x38).", + "value": 3 + } + } + } + } + }, + "ADDRMODE": { + "description": "Addressing mode.", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "24BIT": { + "description": "24-bit addressing.", + "value": 0 + }, + "32BIT": { + "description": "32-bit addressing.", + "value": 1 + } + } + } + } + }, + "DPMENABLE": { + "description": "Enable deep power-down mode (DPM) feature.", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable DPM feature.", + "value": 0 + }, + "Enable": { + "description": "Enable DPM feature.", + "value": 1 + } + } + } + } + }, + "PPSIZE": { + "description": "Page size for commands PP, PP2O, PP4O and PP4IO.", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "256Bytes": { + "description": "256 bytes.", + "value": 0 + }, + "512Bytes": { + "description": "512 bytes.", + "value": 1 + } + } + } + } + } + } + } + }, + "IFCONFIG1": { + "description": "Interface configuration.", + "offset": 1536, + "size": 32, + "reset_value": 263296, + "reset_mask": 4294967295, + "children": { + "fields": { + "SCKDELAY": { + "description": "Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns).", + "offset": 0, + "size": 8 + }, + "DPMEN": { + "description": "Enter/exit deep power-down mode (DPM) for external flash memory.", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Exit": { + "description": "Exit DPM.", + "value": 0 + }, + "Enter": { + "description": "Enter DPM.", + "value": 1 + } + } + } + } + }, + "SPIMODE": { + "description": "Select SPI mode.", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "MODE0": { + "description": "Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0).", + "value": 0 + }, + "MODE3": { + "description": "Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1).", + "value": 1 + } + } + } + } + }, + "SCKFREQ": { + "description": "SCK frequency is given as 32 MHz / (SCKFREQ + 1).", + "offset": 28, + "size": 4 + } + } + } + }, + "STATUS": { + "description": "Status register.", + "offset": 1540, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DPM": { + "description": "Deep power-down mode (DPM) status of external flash.", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "External flash is not in DPM.", + "value": 0 + }, + "Enabled": { + "description": "External flash is in DPM.", + "value": 1 + } + } + } + } + }, + "READY": { + "description": "Ready status.", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "READY": { + "description": "QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM.", + "value": 1 + }, + "BUSY": { + "description": "QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM.", + "value": 0 + } + } + } + } + }, + "SREG": { + "description": "Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte.", + "offset": 24, + "size": 8 + } + } + } + }, + "DPMDUR": { + "description": "Set the duration required to enter/exit deep power-down mode (DPM).", + "offset": 1556, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENTER": { + "description": "Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns.", + "offset": 0, + "size": 16 + }, + "EXIT": { + "description": "Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns.", + "offset": 16, + "size": 16 + } + } + } + }, + "ADDRCONF": { + "description": "Extended address configuration.", + "offset": 1572, + "size": 32, + "reset_value": 183, + "reset_mask": 4294967295, + "children": { + "fields": { + "OPCODE": { + "description": "Opcode that enters the 32-bit addressing mode.", + "offset": 0, + "size": 8 + }, + "BYTE0": { + "description": "Byte 0 following opcode.", + "offset": 8, + "size": 8 + }, + "BYTE1": { + "description": "Byte 1 following byte 0.", + "offset": 16, + "size": 8 + }, + "MODE": { + "description": "Extended addressing mode.", + "offset": 24, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "NoInstr": { + "description": "Do not send any instruction.", + "value": 0 + }, + "Opcode": { + "description": "Send opcode.", + "value": 1 + }, + "OpByte0": { + "description": "Send opcode, byte0.", + "value": 2 + }, + "All": { + "description": "Send opcode, byte0, byte1.", + "value": 3 + } + } + } + } + }, + "WIPWAIT": { + "description": "Wait for write complete before sending command.", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "No wait.", + "value": 0 + }, + "Enable": { + "description": "Wait.", + "value": 1 + } + } + } + } + }, + "WREN": { + "description": "Send WREN (write enable opcode 0x06) before instruction.", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Do not send WREN.", + "value": 0 + }, + "Enable": { + "description": "Send WREN.", + "value": 1 + } + } + } + } + } + } + } + }, + "CINSTRCONF": { + "description": "Custom instruction configuration register.", + "offset": 1588, + "size": 32, + "reset_value": 8192, + "reset_mask": 4294967295, + "children": { + "fields": { + "OPCODE": { + "description": "Opcode of Custom instruction.", + "offset": 0, + "size": 8 + }, + "LENGTH": { + "description": "Length of custom instruction in number of bytes.", + "offset": 8, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "1B": { + "description": "Send opcode only.", + "value": 1 + }, + "2B": { + "description": "Send opcode, CINSTRDAT0.BYTE0.", + "value": 2 + }, + "3B": { + "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1.", + "value": 3 + }, + "4B": { + "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2.", + "value": 4 + }, + "5B": { + "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3.", + "value": 5 + }, + "6B": { + "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4.", + "value": 6 + }, + "7B": { + "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5.", + "value": 7 + }, + "8B": { + "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6.", + "value": 8 + }, + "9B": { + "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7.", + "value": 9 + } + } + } + } + }, + "LIO2": { + "description": "Level of the IO2 pin (if connected) during transmission of custom instruction.", + "offset": 12, + "size": 1 + }, + "LIO3": { + "description": "Level of the IO3 pin (if connected) during transmission of custom instruction.", + "offset": 13, + "size": 1 + }, + "WIPWAIT": { + "description": "Wait for write complete before sending command.", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "No wait.", + "value": 0 + }, + "Enable": { + "description": "Wait.", + "value": 1 + } + } + } + } + }, + "WREN": { + "description": "Send WREN (write enable opcode 0x06) before instruction.", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Do not send WREN.", + "value": 0 + }, + "Enable": { + "description": "Send WREN.", + "value": 1 + } + } + } + } + }, + "LFEN": { + "description": "Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field.", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Long frame mode disabled", + "value": 0 + }, + "Enable": { + "description": "Long frame mode enabled", + "value": 1 + } + } + } + } + }, + "LFSTOP": { + "description": "Stop (finalize) long frame transaction", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Stop": { + "description": "Stop", + "value": 1 + } + } + } + } + } + } + } + }, + "CINSTRDAT0": { + "description": "Custom instruction data register 0.", + "offset": 1592, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BYTE0": { + "description": "Data byte 0", + "offset": 0, + "size": 8 + }, + "BYTE1": { + "description": "Data byte 1", + "offset": 8, + "size": 8 + }, + "BYTE2": { + "description": "Data byte 2", + "offset": 16, + "size": 8 + }, + "BYTE3": { + "description": "Data byte 3", + "offset": 24, + "size": 8 + } + } + } + }, + "CINSTRDAT1": { + "description": "Custom instruction data register 1.", + "offset": 1596, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BYTE4": { + "description": "Data byte 4", + "offset": 0, + "size": 8 + }, + "BYTE5": { + "description": "Data byte 5", + "offset": 8, + "size": 8 + }, + "BYTE6": { + "description": "Data byte 6", + "offset": 16, + "size": 8 + }, + "BYTE7": { + "description": "Data byte 7", + "offset": 24, + "size": 8 + } + } + } + }, + "IFTIMING": { + "description": "SPI interface timing.", + "offset": 1600, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXDELAY": { + "description": "Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK.", + "offset": 8, + "size": 3 + } + } + } + } + } + } + }, + "PWM0": { + "description": "Pulse width modulation unit 0", + "children": { + "registers": { + "TASKS_STOP": { + "description": "Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SEQSTART": { + "description": "Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.", + "offset": 8, + "size": 32, + "count": 2, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SEQSTART": { + "description": "Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_NEXTSTEP": { + "description": "Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_NEXTSTEP": { + "description": "Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STOPPED": { + "description": "Response to STOP task, emitted when PWM pulses are no longer generated", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STOPPED": { + "description": "Response to STOP task, emitted when PWM pulses are no longer generated", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_SEQSTARTED": { + "description": "Description collection: First PWM period started on sequence n", + "offset": 264, + "size": 32, + "count": 2, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_SEQSTARTED": { + "description": "First PWM period started on sequence n", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_SEQEND": { + "description": "Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter", + "offset": 272, + "size": 32, + "count": 2, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_SEQEND": { + "description": "Emitted at end of every sequence n, when last value from RAM has been applied to wave counter", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_PWMPERIODEND": { + "description": "Emitted at the end of each PWM period", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_PWMPERIODEND": { + "description": "Emitted at the end of each PWM period", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_LOOPSDONE": { + "description": "Concatenated sequences have been played the amount of times defined in LOOP.CNT", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_LOOPSDONE": { + "description": "Concatenated sequences have been played the amount of times defined in LOOP.CNT", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SEQEND0_STOP": { + "description": "Shortcut between event SEQEND[0] and task STOP", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "SEQEND1_STOP": { + "description": "Shortcut between event SEQEND[1] and task STOP", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LOOPSDONE_SEQSTART0": { + "description": "Shortcut between event LOOPSDONE and task SEQSTART[0]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LOOPSDONE_SEQSTART1": { + "description": "Shortcut between event LOOPSDONE and task SEQSTART[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "LOOPSDONE_STOP": { + "description": "Shortcut between event LOOPSDONE and task STOP", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Enable or disable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SEQSTARTED0": { + "description": "Enable or disable interrupt for event SEQSTARTED[0]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SEQSTARTED1": { + "description": "Enable or disable interrupt for event SEQSTARTED[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SEQEND0": { + "description": "Enable or disable interrupt for event SEQEND[0]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SEQEND1": { + "description": "Enable or disable interrupt for event SEQEND[1]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "PWMPERIODEND": { + "description": "Enable or disable interrupt for event PWMPERIODEND", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "LOOPSDONE": { + "description": "Enable or disable interrupt for event LOOPSDONE", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to enable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQSTARTED0": { + "description": "Write '1' to enable interrupt for event SEQSTARTED[0]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQSTARTED1": { + "description": "Write '1' to enable interrupt for event SEQSTARTED[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQEND0": { + "description": "Write '1' to enable interrupt for event SEQEND[0]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQEND1": { + "description": "Write '1' to enable interrupt for event SEQEND[1]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PWMPERIODEND": { + "description": "Write '1' to enable interrupt for event PWMPERIODEND", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LOOPSDONE": { + "description": "Write '1' to enable interrupt for event LOOPSDONE", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STOPPED": { + "description": "Write '1' to disable interrupt for event STOPPED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQSTARTED0": { + "description": "Write '1' to disable interrupt for event SEQSTARTED[0]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQSTARTED1": { + "description": "Write '1' to disable interrupt for event SEQSTARTED[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQEND0": { + "description": "Write '1' to disable interrupt for event SEQEND[0]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SEQEND1": { + "description": "Write '1' to disable interrupt for event SEQEND[1]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PWMPERIODEND": { + "description": "Write '1' to disable interrupt for event PWMPERIODEND", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "LOOPSDONE": { + "description": "Write '1' to disable interrupt for event LOOPSDONE", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "PWM module enable register", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable PWM module", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "MODE": { + "description": "Selects operating mode of the wave counter", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UPDOWN": { + "description": "Selects up mode or up-and-down mode for the counter", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Up": { + "description": "Up counter, edge-aligned PWM duty cycle", + "value": 0 + }, + "UpAndDown": { + "description": "Up and down counter, center-aligned PWM duty cycle", + "value": 1 + } + } + } + } + } + } + } + }, + "COUNTERTOP": { + "description": "Value up to which the pulse generator counter counts", + "offset": 1288, + "size": 32, + "reset_value": 1023, + "reset_mask": 4294967295, + "children": { + "fields": { + "COUNTERTOP": { + "description": "Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used.", + "offset": 0, + "size": 15 + } + } + } + }, + "PRESCALER": { + "description": "Configuration for PWM_CLK", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRESCALER": { + "description": "Prescaler of PWM_CLK", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "DIV_1": { + "description": "Divide by 1 (16 MHz)", + "value": 0 + }, + "DIV_2": { + "description": "Divide by 2 (8 MHz)", + "value": 1 + }, + "DIV_4": { + "description": "Divide by 4 (4 MHz)", + "value": 2 + }, + "DIV_8": { + "description": "Divide by 8 (2 MHz)", + "value": 3 + }, + "DIV_16": { + "description": "Divide by 16 (1 MHz)", + "value": 4 + }, + "DIV_32": { + "description": "Divide by 32 (500 kHz)", + "value": 5 + }, + "DIV_64": { + "description": "Divide by 64 (250 kHz)", + "value": 6 + }, + "DIV_128": { + "description": "Divide by 128 (125 kHz)", + "value": 7 + } + } + } + } + } + } + } + }, + "DECODER": { + "description": "Configuration of the decoder", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LOAD": { + "description": "How a sequence is read from RAM and spread to the compare register", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Common": { + "description": "1st half word (16-bit) used in all PWM channels 0..3", + "value": 0 + }, + "Grouped": { + "description": "1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3", + "value": 1 + }, + "Individual": { + "description": "1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3", + "value": 2 + }, + "WaveForm": { + "description": "1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP", + "value": 3 + } + } + } + } + }, + "MODE": { + "description": "Selects source for advancing the active sequence", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "RefreshCount": { + "description": "SEQ[n].REFRESH is used to determine loading internal compare registers", + "value": 0 + }, + "NextStep": { + "description": "NEXTSTEP task causes a new value to be loaded to internal compare registers", + "value": 1 + } + } + } + } + } + } + } + }, + "LOOP": { + "description": "Number of playbacks of a loop", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Number of playbacks of pattern cycles", + "offset": 0, + "size": 16, + "enum": { + "size": 16, + "children": { + "enum_fields": { + "Disabled": { + "description": "Looping disabled (stop at the end of the sequence)", + "value": 0 + } + } + } + } + } + } + } + } + } + } + }, + "USBD": { + "description": "Universal serial bus device", + "children": { + "registers": { + "TASKS_STARTEPIN": { + "description": "Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host", + "offset": 4, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTEPIN": { + "description": "Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STARTISOIN": { + "description": "Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTISOIN": { + "description": "Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STARTEPOUT": { + "description": "Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host", + "offset": 40, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTEPOUT": { + "description": "Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STARTISOOUT": { + "description": "Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTISOOUT": { + "description": "Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_EP0RCVOUT": { + "description": "Allows OUT data stage on control endpoint 0", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_EP0RCVOUT": { + "description": "Allows OUT data stage on control endpoint 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_EP0STATUS": { + "description": "Allows status stage on control endpoint 0", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_EP0STATUS": { + "description": "Allows status stage on control endpoint 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_EP0STALL": { + "description": "Stalls data and status stage on control endpoint 0", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_EP0STALL": { + "description": "Stalls data and status stage on control endpoint 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_DPDMDRIVE": { + "description": "Forces D+ and D- lines into the state defined in the DPDMVALUE register", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_DPDMDRIVE": { + "description": "Forces D+ and D- lines into the state defined in the DPDMVALUE register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_DPDMNODRIVE": { + "description": "Stops forcing D+ and D- lines into any state (USB engine takes control)", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_DPDMNODRIVE": { + "description": "Stops forcing D+ and D- lines into any state (USB engine takes control)", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_USBRESET": { + "description": "Signals that a USB reset condition has been detected on USB lines", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_USBRESET": { + "description": "Signals that a USB reset condition has been detected on USB lines", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STARTED": { + "description": "Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STARTED": { + "description": "Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDEPIN": { + "description": "Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software.", + "offset": 264, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDEPIN": { + "description": "The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_EP0DATADONE": { + "description": "An acknowledged data transfer has taken place on the control endpoint", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_EP0DATADONE": { + "description": "An acknowledged data transfer has taken place on the control endpoint", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDISOIN": { + "description": "The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software.", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDISOIN": { + "description": "The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDEPOUT": { + "description": "Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software.", + "offset": 304, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDEPOUT": { + "description": "The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDISOOUT": { + "description": "The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software.", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDISOOUT": { + "description": "The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_SOF": { + "description": "Signals that a SOF (start of frame) condition has been detected on USB lines", + "offset": 340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_SOF": { + "description": "Signals that a SOF (start of frame) condition has been detected on USB lines", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_USBEVENT": { + "description": "An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause.", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_USBEVENT": { + "description": "An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_EP0SETUP": { + "description": "A valid SETUP token has been received (and acknowledged) on the control endpoint", + "offset": 348, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_EP0SETUP": { + "description": "A valid SETUP token has been received (and acknowledged) on the control endpoint", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_EPDATA": { + "description": "A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_EPDATA": { + "description": "A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EP0DATADONE_STARTEPIN0": { + "description": "Shortcut between event EP0DATADONE and task STARTEPIN[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "EP0DATADONE_STARTEPOUT0": { + "description": "Shortcut between event EP0DATADONE and task STARTEPOUT[0]", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "EP0DATADONE_EP0STATUS": { + "description": "Shortcut between event EP0DATADONE and task EP0STATUS", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "ENDEPOUT0_EP0STATUS": { + "description": "Shortcut between event ENDEPOUT[0] and task EP0STATUS", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "ENDEPOUT0_EP0RCVOUT": { + "description": "Shortcut between event ENDEPOUT[0] and task EP0RCVOUT", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "USBRESET": { + "description": "Enable or disable interrupt for event USBRESET", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Enable or disable interrupt for event STARTED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPIN0": { + "description": "Enable or disable interrupt for event ENDEPIN[0]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPIN1": { + "description": "Enable or disable interrupt for event ENDEPIN[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPIN2": { + "description": "Enable or disable interrupt for event ENDEPIN[2]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPIN3": { + "description": "Enable or disable interrupt for event ENDEPIN[3]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPIN4": { + "description": "Enable or disable interrupt for event ENDEPIN[4]", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPIN5": { + "description": "Enable or disable interrupt for event ENDEPIN[5]", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPIN6": { + "description": "Enable or disable interrupt for event ENDEPIN[6]", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPIN7": { + "description": "Enable or disable interrupt for event ENDEPIN[7]", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "EP0DATADONE": { + "description": "Enable or disable interrupt for event EP0DATADONE", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDISOIN": { + "description": "Enable or disable interrupt for event ENDISOIN", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPOUT0": { + "description": "Enable or disable interrupt for event ENDEPOUT[0]", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPOUT1": { + "description": "Enable or disable interrupt for event ENDEPOUT[1]", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPOUT2": { + "description": "Enable or disable interrupt for event ENDEPOUT[2]", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPOUT3": { + "description": "Enable or disable interrupt for event ENDEPOUT[3]", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPOUT4": { + "description": "Enable or disable interrupt for event ENDEPOUT[4]", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPOUT5": { + "description": "Enable or disable interrupt for event ENDEPOUT[5]", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPOUT6": { + "description": "Enable or disable interrupt for event ENDEPOUT[6]", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDEPOUT7": { + "description": "Enable or disable interrupt for event ENDEPOUT[7]", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDISOOUT": { + "description": "Enable or disable interrupt for event ENDISOOUT", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SOF": { + "description": "Enable or disable interrupt for event SOF", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "USBEVENT": { + "description": "Enable or disable interrupt for event USBEVENT", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "EP0SETUP": { + "description": "Enable or disable interrupt for event EP0SETUP", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "EPDATA": { + "description": "Enable or disable interrupt for event EPDATA", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "USBRESET": { + "description": "Write '1' to enable interrupt for event USBRESET", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Write '1' to enable interrupt for event STARTED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN0": { + "description": "Write '1' to enable interrupt for event ENDEPIN[0]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN1": { + "description": "Write '1' to enable interrupt for event ENDEPIN[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN2": { + "description": "Write '1' to enable interrupt for event ENDEPIN[2]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN3": { + "description": "Write '1' to enable interrupt for event ENDEPIN[3]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN4": { + "description": "Write '1' to enable interrupt for event ENDEPIN[4]", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN5": { + "description": "Write '1' to enable interrupt for event ENDEPIN[5]", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN6": { + "description": "Write '1' to enable interrupt for event ENDEPIN[6]", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN7": { + "description": "Write '1' to enable interrupt for event ENDEPIN[7]", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "EP0DATADONE": { + "description": "Write '1' to enable interrupt for event EP0DATADONE", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDISOIN": { + "description": "Write '1' to enable interrupt for event ENDISOIN", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT0": { + "description": "Write '1' to enable interrupt for event ENDEPOUT[0]", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT1": { + "description": "Write '1' to enable interrupt for event ENDEPOUT[1]", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT2": { + "description": "Write '1' to enable interrupt for event ENDEPOUT[2]", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT3": { + "description": "Write '1' to enable interrupt for event ENDEPOUT[3]", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT4": { + "description": "Write '1' to enable interrupt for event ENDEPOUT[4]", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT5": { + "description": "Write '1' to enable interrupt for event ENDEPOUT[5]", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT6": { + "description": "Write '1' to enable interrupt for event ENDEPOUT[6]", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT7": { + "description": "Write '1' to enable interrupt for event ENDEPOUT[7]", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDISOOUT": { + "description": "Write '1' to enable interrupt for event ENDISOOUT", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SOF": { + "description": "Write '1' to enable interrupt for event SOF", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "USBEVENT": { + "description": "Write '1' to enable interrupt for event USBEVENT", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "EP0SETUP": { + "description": "Write '1' to enable interrupt for event EP0SETUP", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "EPDATA": { + "description": "Write '1' to enable interrupt for event EPDATA", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "USBRESET": { + "description": "Write '1' to disable interrupt for event USBRESET", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Write '1' to disable interrupt for event STARTED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN0": { + "description": "Write '1' to disable interrupt for event ENDEPIN[0]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN1": { + "description": "Write '1' to disable interrupt for event ENDEPIN[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN2": { + "description": "Write '1' to disable interrupt for event ENDEPIN[2]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN3": { + "description": "Write '1' to disable interrupt for event ENDEPIN[3]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN4": { + "description": "Write '1' to disable interrupt for event ENDEPIN[4]", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN5": { + "description": "Write '1' to disable interrupt for event ENDEPIN[5]", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN6": { + "description": "Write '1' to disable interrupt for event ENDEPIN[6]", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPIN7": { + "description": "Write '1' to disable interrupt for event ENDEPIN[7]", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "EP0DATADONE": { + "description": "Write '1' to disable interrupt for event EP0DATADONE", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDISOIN": { + "description": "Write '1' to disable interrupt for event ENDISOIN", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT0": { + "description": "Write '1' to disable interrupt for event ENDEPOUT[0]", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT1": { + "description": "Write '1' to disable interrupt for event ENDEPOUT[1]", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT2": { + "description": "Write '1' to disable interrupt for event ENDEPOUT[2]", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT3": { + "description": "Write '1' to disable interrupt for event ENDEPOUT[3]", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT4": { + "description": "Write '1' to disable interrupt for event ENDEPOUT[4]", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT5": { + "description": "Write '1' to disable interrupt for event ENDEPOUT[5]", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT6": { + "description": "Write '1' to disable interrupt for event ENDEPOUT[6]", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDEPOUT7": { + "description": "Write '1' to disable interrupt for event ENDEPOUT[7]", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDISOOUT": { + "description": "Write '1' to disable interrupt for event ENDISOOUT", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SOF": { + "description": "Write '1' to disable interrupt for event SOF", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "USBEVENT": { + "description": "Write '1' to disable interrupt for event USBEVENT", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "EP0SETUP": { + "description": "Write '1' to disable interrupt for event EP0SETUP", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "EPDATA": { + "description": "Write '1' to disable interrupt for event EPDATA", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTCAUSE": { + "description": "Details on what caused the USBEVENT event", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ISOOUTCRC": { + "description": "CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "No error detected", + "value": 0 + }, + "Detected": { + "description": "Error detected", + "value": 1 + } + } + } + } + }, + "SUSPEND": { + "description": "Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear.", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Suspend not detected", + "value": 0 + }, + "Detected": { + "description": "Suspend detected", + "value": 1 + } + } + } + } + }, + "RESUME": { + "description": "Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear.", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "Resume not detected", + "value": 0 + }, + "Detected": { + "description": "Resume detected", + "value": 1 + } + } + } + } + }, + "USBWUALLOWED": { + "description": "USB MAC has been woken up and operational. Write '1' to clear.", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotAllowed": { + "description": "Wake up not allowed", + "value": 0 + }, + "Allowed": { + "description": "Wake up allowed", + "value": 1 + } + } + } + } + }, + "READY": { + "description": "USB device is ready for normal operation. Write '1' to clear.", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDetected": { + "description": "USBEVENT was not issued due to USBD peripheral ready", + "value": 0 + }, + "Ready": { + "description": "USBD peripheral is ready", + "value": 1 + } + } + } + } + } + } + } + }, + "EPSTATUS": { + "description": "Provides information on which endpoint's EasyDMA registers have been captured", + "offset": 1128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPIN0": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPIN1": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPIN2": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPIN3": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPIN4": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPIN5": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPIN6": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPIN7": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPIN8": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPOUT0": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPOUT1": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPOUT2": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPOUT3": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPOUT4": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPOUT5": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPOUT6": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPOUT7": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + }, + "EPOUT8": { + "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoData": { + "description": "EasyDMA registers have not been captured for this endpoint", + "value": 0 + }, + "DataDone": { + "description": "EasyDMA registers have been captured for this endpoint", + "value": 1 + } + } + } + } + } + } + } + }, + "EPDATASTATUS": { + "description": "Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event)", + "offset": 1132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPIN1": { + "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDone": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "DataDone": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPIN2": { + "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDone": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "DataDone": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPIN3": { + "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDone": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "DataDone": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPIN4": { + "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDone": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "DataDone": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPIN5": { + "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDone": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "DataDone": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPIN6": { + "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDone": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "DataDone": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPIN7": { + "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotDone": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "DataDone": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPOUT1": { + "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotStarted": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "Started": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPOUT2": { + "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotStarted": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "Started": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPOUT3": { + "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotStarted": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "Started": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPOUT4": { + "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotStarted": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "Started": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPOUT5": { + "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotStarted": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "Started": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPOUT6": { + "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotStarted": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "Started": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + }, + "EPOUT7": { + "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotStarted": { + "description": "No acknowledged data transfer on this endpoint", + "value": 0 + }, + "Started": { + "description": "Acknowledged data transfer on this endpoint has occurred", + "value": 1 + } + } + } + } + } + } + } + }, + "USBADDR": { + "description": "Device USB address", + "offset": 1136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ADDR": { + "description": "Device USB address", + "offset": 0, + "size": 7 + } + } + } + }, + "BMREQUESTTYPE": { + "description": "SETUP data, byte 0, bmRequestType", + "offset": 1152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RECIPIENT": { + "description": "Data transfer type", + "offset": 0, + "size": 5, + "enum": { + "size": 5, + "children": { + "enum_fields": { + "Device": { + "description": "Device", + "value": 0 + }, + "Interface": { + "description": "Interface", + "value": 1 + }, + "Endpoint": { + "description": "Endpoint", + "value": 2 + }, + "Other": { + "description": "Other", + "value": 3 + } + } + } + } + }, + "TYPE": { + "description": "Data transfer type", + "offset": 5, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Standard": { + "description": "Standard", + "value": 0 + }, + "Class": { + "description": "Class", + "value": 1 + }, + "Vendor": { + "description": "Vendor", + "value": 2 + } + } + } + } + }, + "DIRECTION": { + "description": "Data transfer direction", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "HostToDevice": { + "description": "Host-to-device", + "value": 0 + }, + "DeviceToHost": { + "description": "Device-to-host", + "value": 1 + } + } + } + } + } + } + } + }, + "BREQUEST": { + "description": "SETUP data, byte 1, bRequest", + "offset": 1156, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "BREQUEST": { + "description": "SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values.", + "offset": 0, + "size": 8, + "enum": { + "size": 8, + "children": { + "enum_fields": { + "STD_GET_STATUS": { + "description": "Standard request GET_STATUS", + "value": 0 + }, + "STD_CLEAR_FEATURE": { + "description": "Standard request CLEAR_FEATURE", + "value": 1 + }, + "STD_SET_FEATURE": { + "description": "Standard request SET_FEATURE", + "value": 3 + }, + "STD_SET_ADDRESS": { + "description": "Standard request SET_ADDRESS", + "value": 5 + }, + "STD_GET_DESCRIPTOR": { + "description": "Standard request GET_DESCRIPTOR", + "value": 6 + }, + "STD_SET_DESCRIPTOR": { + "description": "Standard request SET_DESCRIPTOR", + "value": 7 + }, + "STD_GET_CONFIGURATION": { + "description": "Standard request GET_CONFIGURATION", + "value": 8 + }, + "STD_SET_CONFIGURATION": { + "description": "Standard request SET_CONFIGURATION", + "value": 9 + }, + "STD_GET_INTERFACE": { + "description": "Standard request GET_INTERFACE", + "value": 10 + }, + "STD_SET_INTERFACE": { + "description": "Standard request SET_INTERFACE", + "value": 11 + }, + "STD_SYNCH_FRAME": { + "description": "Standard request SYNCH_FRAME", + "value": 12 + } + } + } + } + } + } + } + }, + "WVALUEL": { + "description": "SETUP data, byte 2, LSB of wValue", + "offset": 1160, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WVALUEL": { + "description": "SETUP data, byte 2, LSB of wValue", + "offset": 0, + "size": 8 + } + } + } + }, + "WVALUEH": { + "description": "SETUP data, byte 3, MSB of wValue", + "offset": 1164, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WVALUEH": { + "description": "SETUP data, byte 3, MSB of wValue", + "offset": 0, + "size": 8 + } + } + } + }, + "WINDEXL": { + "description": "SETUP data, byte 4, LSB of wIndex", + "offset": 1168, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WINDEXL": { + "description": "SETUP data, byte 4, LSB of wIndex", + "offset": 0, + "size": 8 + } + } + } + }, + "WINDEXH": { + "description": "SETUP data, byte 5, MSB of wIndex", + "offset": 1172, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WINDEXH": { + "description": "SETUP data, byte 5, MSB of wIndex", + "offset": 0, + "size": 8 + } + } + } + }, + "WLENGTHL": { + "description": "SETUP data, byte 6, LSB of wLength", + "offset": 1176, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WLENGTHL": { + "description": "SETUP data, byte 6, LSB of wLength", + "offset": 0, + "size": 8 + } + } + } + }, + "WLENGTHH": { + "description": "SETUP data, byte 7, MSB of wLength", + "offset": 1180, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WLENGTHH": { + "description": "SETUP data, byte 7, MSB of wLength", + "offset": 0, + "size": 8 + } + } + } + }, + "ENABLE": { + "description": "Enable USB", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable USB", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "USB peripheral is disabled", + "value": 0 + }, + "Enabled": { + "description": "USB peripheral is enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "USBPULLUP": { + "description": "Control of the USB pull-up", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CONNECT": { + "description": "Control of the USB pull-up on the D+ line", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Pull-up is disconnected", + "value": 0 + }, + "Enabled": { + "description": "Pull-up is connected to D+", + "value": 1 + } + } + } + } + } + } + } + }, + "DPDMVALUE": { + "description": "State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing).", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STATE": { + "description": "State D+ and D- lines will be forced into by the DPDMDRIVE task", + "offset": 0, + "size": 5, + "enum": { + "size": 5, + "children": { + "enum_fields": { + "Resume": { + "description": "D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state)", + "value": 1 + }, + "J": { + "description": "D+ forced high, D- forced low (J state)", + "value": 2 + }, + "K": { + "description": "D+ forced low, D- forced high (K state)", + "value": 4 + } + } + } + } + } + } + } + }, + "DTOGGLE": { + "description": "Data toggle control and status", + "offset": 1292, + "size": 32, + "reset_value": 256, + "reset_mask": 4294967295, + "children": { + "fields": { + "EP": { + "description": "Select bulk endpoint number", + "offset": 0, + "size": 3 + }, + "IO": { + "description": "Selects IN or OUT endpoint", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Out": { + "description": "Selects OUT endpoint", + "value": 0 + }, + "In": { + "description": "Selects IN endpoint", + "value": 1 + } + } + } + } + }, + "VALUE": { + "description": "Data toggle value", + "offset": 8, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Nop": { + "description": "No action on data toggle when writing the register with this value", + "value": 0 + }, + "Data0": { + "description": "Data toggle is DATA0 on endpoint set by EP and IO", + "value": 1 + }, + "Data1": { + "description": "Data toggle is DATA1 on endpoint set by EP and IO", + "value": 2 + } + } + } + } + } + } + } + }, + "EPINEN": { + "description": "Endpoint IN enable", + "offset": 1296, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "IN0": { + "description": "Enable IN endpoint 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint IN 0 (no response to IN tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint IN 0 (response to IN tokens)", + "value": 1 + } + } + } + } + }, + "IN1": { + "description": "Enable IN endpoint 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint IN 1 (no response to IN tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint IN 1 (response to IN tokens)", + "value": 1 + } + } + } + } + }, + "IN2": { + "description": "Enable IN endpoint 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint IN 2 (no response to IN tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint IN 2 (response to IN tokens)", + "value": 1 + } + } + } + } + }, + "IN3": { + "description": "Enable IN endpoint 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint IN 3 (no response to IN tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint IN 3 (response to IN tokens)", + "value": 1 + } + } + } + } + }, + "IN4": { + "description": "Enable IN endpoint 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint IN 4 (no response to IN tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint IN 4 (response to IN tokens)", + "value": 1 + } + } + } + } + }, + "IN5": { + "description": "Enable IN endpoint 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint IN 5 (no response to IN tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint IN 5 (response to IN tokens)", + "value": 1 + } + } + } + } + }, + "IN6": { + "description": "Enable IN endpoint 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint IN 6 (no response to IN tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint IN 6 (response to IN tokens)", + "value": 1 + } + } + } + } + }, + "IN7": { + "description": "Enable IN endpoint 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint IN 7 (no response to IN tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint IN 7 (response to IN tokens)", + "value": 1 + } + } + } + } + }, + "ISOIN": { + "description": "Enable ISO IN endpoint", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable ISO IN endpoint 8", + "value": 0 + }, + "Enable": { + "description": "Enable ISO IN endpoint 8", + "value": 1 + } + } + } + } + } + } + } + }, + "EPOUTEN": { + "description": "Endpoint OUT enable", + "offset": 1300, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "OUT0": { + "description": "Enable OUT endpoint 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint OUT 0 (no response to OUT tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint OUT 0 (response to OUT tokens)", + "value": 1 + } + } + } + } + }, + "OUT1": { + "description": "Enable OUT endpoint 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint OUT 1 (no response to OUT tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint OUT 1 (response to OUT tokens)", + "value": 1 + } + } + } + } + }, + "OUT2": { + "description": "Enable OUT endpoint 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint OUT 2 (no response to OUT tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint OUT 2 (response to OUT tokens)", + "value": 1 + } + } + } + } + }, + "OUT3": { + "description": "Enable OUT endpoint 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint OUT 3 (no response to OUT tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint OUT 3 (response to OUT tokens)", + "value": 1 + } + } + } + } + }, + "OUT4": { + "description": "Enable OUT endpoint 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint OUT 4 (no response to OUT tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint OUT 4 (response to OUT tokens)", + "value": 1 + } + } + } + } + }, + "OUT5": { + "description": "Enable OUT endpoint 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint OUT 5 (no response to OUT tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint OUT 5 (response to OUT tokens)", + "value": 1 + } + } + } + } + }, + "OUT6": { + "description": "Enable OUT endpoint 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint OUT 6 (no response to OUT tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint OUT 6 (response to OUT tokens)", + "value": 1 + } + } + } + } + }, + "OUT7": { + "description": "Enable OUT endpoint 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable endpoint OUT 7 (no response to OUT tokens)", + "value": 0 + }, + "Enable": { + "description": "Enable endpoint OUT 7 (response to OUT tokens)", + "value": 1 + } + } + } + } + }, + "ISOOUT": { + "description": "Enable ISO OUT endpoint 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable ISO OUT endpoint 8", + "value": 0 + }, + "Enable": { + "description": "Enable ISO OUT endpoint 8", + "value": 1 + } + } + } + } + } + } + } + }, + "EPSTALL": { + "description": "STALL endpoints", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "EP": { + "description": "Select endpoint number", + "offset": 0, + "size": 3 + }, + "IO": { + "description": "Selects IN or OUT endpoint", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Out": { + "description": "Selects OUT endpoint", + "value": 0 + }, + "In": { + "description": "Selects IN endpoint", + "value": 1 + } + } + } + } + }, + "STALL": { + "description": "Stall selected endpoint", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "UnStall": { + "description": "Don't stall selected endpoint", + "value": 0 + }, + "Stall": { + "description": "Stall selected endpoint", + "value": 1 + } + } + } + } + } + } + } + }, + "ISOSPLIT": { + "description": "Controls the split of ISO buffers", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SPLIT": { + "description": "Controls the split of ISO buffers", + "offset": 0, + "size": 16, + "enum": { + "size": 16, + "children": { + "enum_fields": { + "OneDir": { + "description": "Full buffer dedicated to either iso IN or OUT", + "value": 0 + }, + "HalfIN": { + "description": "Lower half for IN, upper half for OUT", + "value": 128 + } + } + } + } + } + } + } + }, + "FRAMECNTR": { + "description": "Returns the current value of the start of frame counter", + "offset": 1312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FRAMECNTR": { + "description": "Returns the current value of the start of frame counter", + "offset": 0, + "size": 11 + } + } + } + }, + "LOWPOWER": { + "description": "Controls USBD peripheral low power mode during USB suspend", + "offset": 1324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LOWPOWER": { + "description": "Controls USBD peripheral low-power mode during USB suspend", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "ForceNormal": { + "description": "Software must write this value to exit low power mode and before performing a remote wake-up", + "value": 0 + }, + "LowPower": { + "description": "Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral", + "value": 1 + } + } + } + } + } + } + } + }, + "ISOINCONFIG": { + "description": "Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent", + "offset": 1328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RESPONSE": { + "description": "Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoResp": { + "description": "Endpoint does not respond in that case", + "value": 0 + }, + "ZeroData": { + "description": "Endpoint responds with a zero-length data packet in that case", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "NFCT": { + "description": "NFC-A compatible radio", + "children": { + "registers": { + "TASKS_ACTIVATE": { + "description": "Activate NFCT peripheral for incoming and outgoing frames, change state to activated", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_ACTIVATE": { + "description": "Activate NFCT peripheral for incoming and outgoing frames, change state to activated", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_DISABLE": { + "description": "Disable NFCT peripheral", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_DISABLE": { + "description": "Disable NFCT peripheral", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SENSE": { + "description": "Enable NFC sense field mode, change state to sense mode", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SENSE": { + "description": "Enable NFC sense field mode, change state to sense mode", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STARTTX": { + "description": "Start transmission of an outgoing frame, change state to transmit", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTTX": { + "description": "Start transmission of an outgoing frame, change state to transmit", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_ENABLERXDATA": { + "description": "Initializes the EasyDMA for receive.", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_ENABLERXDATA": { + "description": "Initializes the EasyDMA for receive.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_GOIDLE": { + "description": "Force state machine to IDLE state", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_GOIDLE": { + "description": "Force state machine to IDLE state", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_GOSLEEP": { + "description": "Force state machine to SLEEP_A state", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_GOSLEEP": { + "description": "Force state machine to SLEEP_A state", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_READY": { + "description": "The NFCT peripheral is ready to receive and send frames", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_READY": { + "description": "The NFCT peripheral is ready to receive and send frames", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_FIELDDETECTED": { + "description": "Remote NFC field detected", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_FIELDDETECTED": { + "description": "Remote NFC field detected", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_FIELDLOST": { + "description": "Remote NFC field lost", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_FIELDLOST": { + "description": "Remote NFC field lost", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TXFRAMESTART": { + "description": "Marks the start of the first symbol of a transmitted frame", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TXFRAMESTART": { + "description": "Marks the start of the first symbol of a transmitted frame", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TXFRAMEEND": { + "description": "Marks the end of the last transmitted on-air symbol of a frame", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TXFRAMEEND": { + "description": "Marks the end of the last transmitted on-air symbol of a frame", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXFRAMESTART": { + "description": "Marks the end of the first symbol of a received frame", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXFRAMESTART": { + "description": "Marks the end of the first symbol of a received frame", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXFRAMEEND": { + "description": "Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXFRAMEEND": { + "description": "Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ERROR": { + "description": "NFC error reported. The ERRORSTATUS register contains details on the source of the error.", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ERROR": { + "description": "NFC error reported. The ERRORSTATUS register contains details on the source of the error.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXERROR": { + "description": "NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXERROR": { + "description": "NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDRX": { + "description": "RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDRX": { + "description": "RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDTX": { + "description": "Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDTX": { + "description": "Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_AUTOCOLRESSTARTED": { + "description": "Auto collision resolution process has started", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_AUTOCOLRESSTARTED": { + "description": "Auto collision resolution process has started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_COLLISION": { + "description": "NFC auto collision resolution error reported.", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_COLLISION": { + "description": "NFC auto collision resolution error reported.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_SELECTED": { + "description": "NFC auto collision resolution successfully completed", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_SELECTED": { + "description": "NFC auto collision resolution successfully completed", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STARTED": { + "description": "EasyDMA is ready to receive or send frames.", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STARTED": { + "description": "EasyDMA is ready to receive or send frames.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FIELDDETECTED_ACTIVATE": { + "description": "Shortcut between event FIELDDETECTED and task ACTIVATE", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "FIELDLOST_SENSE": { + "description": "Shortcut between event FIELDLOST and task SENSE", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "TXFRAMEEND_ENABLERXDATA": { + "description": "Shortcut between event TXFRAMEEND and task ENABLERXDATA", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Enable or disable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "FIELDDETECTED": { + "description": "Enable or disable interrupt for event FIELDDETECTED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "FIELDLOST": { + "description": "Enable or disable interrupt for event FIELDLOST", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXFRAMESTART": { + "description": "Enable or disable interrupt for event TXFRAMESTART", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXFRAMEEND": { + "description": "Enable or disable interrupt for event TXFRAMEEND", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXFRAMESTART": { + "description": "Enable or disable interrupt for event RXFRAMESTART", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXFRAMEEND": { + "description": "Enable or disable interrupt for event RXFRAMEEND", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Enable or disable interrupt for event ERROR", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RXERROR": { + "description": "Enable or disable interrupt for event RXERROR", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Enable or disable interrupt for event ENDRX", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Enable or disable interrupt for event ENDTX", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "AUTOCOLRESSTARTED": { + "description": "Enable or disable interrupt for event AUTOCOLRESSTARTED", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "COLLISION": { + "description": "Enable or disable interrupt for event COLLISION", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "SELECTED": { + "description": "Enable or disable interrupt for event SELECTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Enable or disable interrupt for event STARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to enable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "FIELDDETECTED": { + "description": "Write '1' to enable interrupt for event FIELDDETECTED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "FIELDLOST": { + "description": "Write '1' to enable interrupt for event FIELDLOST", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXFRAMESTART": { + "description": "Write '1' to enable interrupt for event TXFRAMESTART", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXFRAMEEND": { + "description": "Write '1' to enable interrupt for event TXFRAMEEND", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXFRAMESTART": { + "description": "Write '1' to enable interrupt for event RXFRAMESTART", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXFRAMEEND": { + "description": "Write '1' to enable interrupt for event RXFRAMEEND", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to enable interrupt for event ERROR", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXERROR": { + "description": "Write '1' to enable interrupt for event RXERROR", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to enable interrupt for event ENDRX", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to enable interrupt for event ENDTX", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "AUTOCOLRESSTARTED": { + "description": "Write '1' to enable interrupt for event AUTOCOLRESSTARTED", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COLLISION": { + "description": "Write '1' to enable interrupt for event COLLISION", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SELECTED": { + "description": "Write '1' to enable interrupt for event SELECTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Write '1' to enable interrupt for event STARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to disable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "FIELDDETECTED": { + "description": "Write '1' to disable interrupt for event FIELDDETECTED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "FIELDLOST": { + "description": "Write '1' to disable interrupt for event FIELDLOST", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXFRAMESTART": { + "description": "Write '1' to disable interrupt for event TXFRAMESTART", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXFRAMEEND": { + "description": "Write '1' to disable interrupt for event TXFRAMEEND", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXFRAMESTART": { + "description": "Write '1' to disable interrupt for event RXFRAMESTART", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXFRAMEEND": { + "description": "Write '1' to disable interrupt for event RXFRAMEEND", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Write '1' to disable interrupt for event ERROR", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RXERROR": { + "description": "Write '1' to disable interrupt for event RXERROR", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDRX": { + "description": "Write '1' to disable interrupt for event ENDRX", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDTX": { + "description": "Write '1' to disable interrupt for event ENDTX", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "AUTOCOLRESSTARTED": { + "description": "Write '1' to disable interrupt for event AUTOCOLRESSTARTED", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COLLISION": { + "description": "Write '1' to disable interrupt for event COLLISION", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "SELECTED": { + "description": "Write '1' to disable interrupt for event SELECTED", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STARTED": { + "description": "Write '1' to disable interrupt for event STARTED", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ERRORSTATUS": { + "description": "NFC Error Status register", + "offset": 1028, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRAMEDELAYTIMEOUT": { + "description": "No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX", + "offset": 0, + "size": 1 + } + } + } + }, + "NFCTAGSTATE": { + "description": "NfcTag state register", + "offset": 1040, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "NFCTAGSTATE": { + "description": "NfcTag state", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled or sense", + "value": 0 + }, + "RampUp": { + "description": "RampUp", + "value": 2 + }, + "Idle": { + "description": "Idle", + "value": 3 + }, + "Receive": { + "description": "Receive", + "value": 4 + }, + "FrameDelay": { + "description": "FrameDelay", + "value": 5 + }, + "Transmit": { + "description": "Transmit", + "value": 6 + } + } + } + } + } + } + } + }, + "SLEEPSTATE": { + "description": "Sleep state during automatic collision resolution", + "offset": 1056, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SLEEPSTATE": { + "description": "Reflects the sleep state during automatic collision resolution. Set to IDLE \n by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a \n GOSLEEP task.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Idle": { + "description": "State is IDLE.", + "value": 0 + }, + "SleepA": { + "description": "State is SLEEP_A.", + "value": 1 + } + } + } + } + } + } + } + }, + "FIELDPRESENT": { + "description": "Indicates the presence or not of a valid field", + "offset": 1084, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FIELDPRESENT": { + "description": "Indicates if a valid field is present. Available only in the activated state.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoField": { + "description": "No valid field detected", + "value": 0 + }, + "FieldPresent": { + "description": "Valid field detected", + "value": 1 + } + } + } + } + }, + "LOCKDETECT": { + "description": "Indicates if the low level has locked to the field", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotLocked": { + "description": "Not locked to field", + "value": 0 + }, + "Locked": { + "description": "Locked to field", + "value": 1 + } + } + } + } + } + } + } + }, + "FRAMEDELAYMIN": { + "description": "Minimum frame delay", + "offset": 1284, + "size": 32, + "reset_value": 1152, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRAMEDELAYMIN": { + "description": "Minimum frame delay in number of 13.56 MHz clocks", + "offset": 0, + "size": 16 + } + } + } + }, + "FRAMEDELAYMAX": { + "description": "Maximum frame delay", + "offset": 1288, + "size": 32, + "reset_value": 4096, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRAMEDELAYMAX": { + "description": "Maximum frame delay in number of 13.56 MHz clocks", + "offset": 0, + "size": 20 + } + } + } + }, + "FRAMEDELAYMODE": { + "description": "Configuration register for the Frame Delay Timer", + "offset": 1292, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRAMEDELAYMODE": { + "description": "Configuration register for the Frame Delay Timer", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "FreeRun": { + "description": "Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout.", + "value": 0 + }, + "Window": { + "description": "Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX", + "value": 1 + }, + "ExactVal": { + "description": "Frame is transmitted exactly at FRAMEDELAYMAX", + "value": 2 + }, + "WindowGrid": { + "description": "Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX", + "value": 3 + } + } + } + } + } + } + } + }, + "PACKETPTR": { + "description": "Packet pointer for TXD and RXD data storage in Data RAM", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTR": { + "description": "Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address.", + "offset": 0, + "size": 32 + } + } + } + }, + "MAXLEN": { + "description": "Size of the RAM buffer allocated to TXD and RXD data storage each", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MAXLEN": { + "description": "Size of the RAM buffer allocated to TXD and RXD data storage each", + "offset": 0, + "size": 9 + } + } + } + }, + "NFCID1_LAST": { + "description": "Last NFCID1 part (4, 7 or 10 bytes ID)", + "offset": 1424, + "size": 32, + "reset_value": 25443, + "reset_mask": 4294967295, + "children": { + "fields": { + "NFCID1_Z": { + "description": "NFCID1 byte Z (very last byte sent)", + "offset": 0, + "size": 8 + }, + "NFCID1_Y": { + "description": "NFCID1 byte Y", + "offset": 8, + "size": 8 + }, + "NFCID1_X": { + "description": "NFCID1 byte X", + "offset": 16, + "size": 8 + }, + "NFCID1_W": { + "description": "NFCID1 byte W", + "offset": 24, + "size": 8 + } + } + } + }, + "NFCID1_2ND_LAST": { + "description": "Second last NFCID1 part (7 or 10 bytes ID)", + "offset": 1428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NFCID1_V": { + "description": "NFCID1 byte V", + "offset": 0, + "size": 8 + }, + "NFCID1_U": { + "description": "NFCID1 byte U", + "offset": 8, + "size": 8 + }, + "NFCID1_T": { + "description": "NFCID1 byte T", + "offset": 16, + "size": 8 + } + } + } + }, + "NFCID1_3RD_LAST": { + "description": "Third last NFCID1 part (10 bytes ID)", + "offset": 1432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NFCID1_S": { + "description": "NFCID1 byte S", + "offset": 0, + "size": 8 + }, + "NFCID1_R": { + "description": "NFCID1 byte R", + "offset": 8, + "size": 8 + }, + "NFCID1_Q": { + "description": "NFCID1 byte Q", + "offset": 16, + "size": 8 + } + } + } + }, + "AUTOCOLRESCONFIG": { + "description": "Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled.", + "offset": 1436, + "size": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "Enables/disables auto collision resolution", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Enabled": { + "description": "Auto collision resolution enabled", + "value": 0 + }, + "Disabled": { + "description": "Auto collision resolution disabled", + "value": 1 + } + } + } + } + } + } + } + }, + "SENSRES": { + "description": "NFC-A SENS_RES auto-response settings", + "offset": 1440, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "BITFRAMESDD": { + "description": "Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification", + "offset": 0, + "size": 5, + "enum": { + "size": 5, + "children": { + "enum_fields": { + "SDD00000": { + "description": "SDD pattern 00000", + "value": 0 + }, + "SDD00001": { + "description": "SDD pattern 00001", + "value": 1 + }, + "SDD00010": { + "description": "SDD pattern 00010", + "value": 2 + }, + "SDD00100": { + "description": "SDD pattern 00100", + "value": 4 + }, + "SDD01000": { + "description": "SDD pattern 01000", + "value": 8 + }, + "SDD10000": { + "description": "SDD pattern 10000", + "value": 16 + } + } + } + } + }, + "RFU5": { + "description": "Reserved for future use. Shall be 0.", + "offset": 5, + "size": 1 + }, + "NFCIDSIZE": { + "description": "NFCID1 size. This value is used by the auto collision resolution engine.", + "offset": 6, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "NFCID1Single": { + "description": "NFCID1 size: single (4 bytes)", + "value": 0 + }, + "NFCID1Double": { + "description": "NFCID1 size: double (7 bytes)", + "value": 1 + }, + "NFCID1Triple": { + "description": "NFCID1 size: triple (10 bytes)", + "value": 2 + } + } + } + } + }, + "PLATFCONFIG": { + "description": "Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification", + "offset": 8, + "size": 4 + }, + "RFU74": { + "description": "Reserved for future use. Shall be 0.", + "offset": 12, + "size": 4 + } + } + } + }, + "SELRES": { + "description": "NFC-A SEL_RES auto-response settings", + "offset": 1444, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFU10": { + "description": "Reserved for future use. Shall be 0.", + "offset": 0, + "size": 2 + }, + "CASCADE": { + "description": "Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0)", + "offset": 2, + "size": 1 + }, + "RFU43": { + "description": "Reserved for future use. Shall be 0.", + "offset": 3, + "size": 2 + }, + "PROTOCOL": { + "description": "Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification", + "offset": 5, + "size": 2 + }, + "RFU7": { + "description": "Reserved for future use. Shall be 0.", + "offset": 7, + "size": 1 + } + } + } + } + } + } + }, + "GPIOTE": { + "description": "GPIO Tasks and Events", + "children": { + "registers": { + "TASKS_OUT": { + "description": "Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.", + "offset": 0, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_OUT": { + "description": "Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SET": { + "description": "Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.", + "offset": 48, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SET": { + "description": "Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_CLR": { + "description": "Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.", + "offset": 96, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CLR": { + "description": "Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_IN": { + "description": "Description collection: Event generated from pin specified in CONFIG[n].PSEL", + "offset": 256, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_IN": { + "description": "Event generated from pin specified in CONFIG[n].PSEL", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_PORT": { + "description": "Event generated from multiple input GPIO pins with SENSE mechanism enabled", + "offset": 380, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_PORT": { + "description": "Event generated from multiple input GPIO pins with SENSE mechanism enabled", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IN0": { + "description": "Write '1' to enable interrupt for event IN[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN1": { + "description": "Write '1' to enable interrupt for event IN[1]", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN2": { + "description": "Write '1' to enable interrupt for event IN[2]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN3": { + "description": "Write '1' to enable interrupt for event IN[3]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN4": { + "description": "Write '1' to enable interrupt for event IN[4]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN5": { + "description": "Write '1' to enable interrupt for event IN[5]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN6": { + "description": "Write '1' to enable interrupt for event IN[6]", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN7": { + "description": "Write '1' to enable interrupt for event IN[7]", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PORT": { + "description": "Write '1' to enable interrupt for event PORT", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IN0": { + "description": "Write '1' to disable interrupt for event IN[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN1": { + "description": "Write '1' to disable interrupt for event IN[1]", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN2": { + "description": "Write '1' to disable interrupt for event IN[2]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN3": { + "description": "Write '1' to disable interrupt for event IN[3]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN4": { + "description": "Write '1' to disable interrupt for event IN[4]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN5": { + "description": "Write '1' to disable interrupt for event IN[5]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN6": { + "description": "Write '1' to disable interrupt for event IN[6]", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "IN7": { + "description": "Write '1' to disable interrupt for event IN[7]", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PORT": { + "description": "Write '1' to disable interrupt for event PORT", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event", + "offset": 1296, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "Mode", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.", + "value": 0 + }, + "Event": { + "description": "Event mode", + "value": 1 + }, + "Task": { + "description": "Task mode", + "value": 3 + } + } + } + } + }, + "PSEL": { + "description": "GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event", + "offset": 8, + "size": 5 + }, + "PORT": { + "description": "Port number", + "offset": 13, + "size": 1 + }, + "POLARITY": { + "description": "When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.", + "offset": 16, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "None": { + "description": "Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.", + "value": 0 + }, + "LoToHi": { + "description": "Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.", + "value": 1 + }, + "HiToLo": { + "description": "Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.", + "value": 2 + }, + "Toggle": { + "description": "Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.", + "value": 3 + } + } + } + } + }, + "OUTINIT": { + "description": "When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Low": { + "description": "Task mode: Initial value of pin before task triggering is low", + "value": 0 + }, + "High": { + "description": "Task mode: Initial value of pin before task triggering is high", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "SAADC": { + "description": "Successive approximation register (SAR) analog-to-digital converter", + "children": { + "registers": { + "TASKS_START": { + "description": "Starts the SAADC and prepares the result buffer in RAM", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Starts the SAADC and prepares the result buffer in RAM", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SAMPLE": { + "description": "Takes one SAADC sample", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SAMPLE": { + "description": "Takes one SAADC sample", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stops the SAADC and terminates all on-going conversions", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stops the SAADC and terminates all on-going conversions", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_CALIBRATEOFFSET": { + "description": "Starts offset auto-calibration", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CALIBRATEOFFSET": { + "description": "Starts offset auto-calibration", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STARTED": { + "description": "The SAADC has started", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STARTED": { + "description": "The SAADC has started", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_END": { + "description": "The SAADC has filled up the result buffer", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_END": { + "description": "The SAADC has filled up the result buffer", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_DONE": { + "description": "A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_DONE": { + "description": "A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RESULTDONE": { + "description": "Result ready for transfer to RAM", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RESULTDONE": { + "description": "Result ready for transfer to RAM", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CALIBRATEDONE": { + "description": "Calibration is complete", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CALIBRATEDONE": { + "description": "Calibration is complete", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STOPPED": { + "description": "The SAADC has stopped", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STOPPED": { + "description": "The SAADC has stopped", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Enable or disable interrupt for event STARTED", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Enable or disable interrupt for event END", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "DONE": { + "description": "Enable or disable interrupt for event DONE", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "RESULTDONE": { + "description": "Enable or disable interrupt for event RESULTDONE", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CALIBRATEDONE": { + "description": "Enable or disable interrupt for event CALIBRATEDONE", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Enable or disable interrupt for event STOPPED", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH0LIMITH": { + "description": "Enable or disable interrupt for event CH0LIMITH", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH0LIMITL": { + "description": "Enable or disable interrupt for event CH0LIMITL", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH1LIMITH": { + "description": "Enable or disable interrupt for event CH1LIMITH", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH1LIMITL": { + "description": "Enable or disable interrupt for event CH1LIMITL", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH2LIMITH": { + "description": "Enable or disable interrupt for event CH2LIMITH", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH2LIMITL": { + "description": "Enable or disable interrupt for event CH2LIMITL", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH3LIMITH": { + "description": "Enable or disable interrupt for event CH3LIMITH", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH3LIMITL": { + "description": "Enable or disable interrupt for event CH3LIMITL", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH4LIMITH": { + "description": "Enable or disable interrupt for event CH4LIMITH", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH4LIMITL": { + "description": "Enable or disable interrupt for event CH4LIMITL", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH5LIMITH": { + "description": "Enable or disable interrupt for event CH5LIMITH", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH5LIMITL": { + "description": "Enable or disable interrupt for event CH5LIMITL", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH6LIMITH": { + "description": "Enable or disable interrupt for event CH6LIMITH", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH6LIMITL": { + "description": "Enable or disable interrupt for event CH6LIMITL", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH7LIMITH": { + "description": "Enable or disable interrupt for event CH7LIMITH", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CH7LIMITL": { + "description": "Enable or disable interrupt for event CH7LIMITL", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Write '1' to enable interrupt for event STARTED", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to enable interrupt for event END", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DONE": { + "description": "Write '1' to enable interrupt for event DONE", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RESULTDONE": { + "description": "Write '1' to enable interrupt for event RESULTDONE", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CALIBRATEDONE": { + "description": "Write '1' to enable interrupt for event CALIBRATEDONE", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to enable interrupt for event STOPPED", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH0LIMITH": { + "description": "Write '1' to enable interrupt for event CH0LIMITH", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH0LIMITL": { + "description": "Write '1' to enable interrupt for event CH0LIMITL", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH1LIMITH": { + "description": "Write '1' to enable interrupt for event CH1LIMITH", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH1LIMITL": { + "description": "Write '1' to enable interrupt for event CH1LIMITL", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH2LIMITH": { + "description": "Write '1' to enable interrupt for event CH2LIMITH", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH2LIMITL": { + "description": "Write '1' to enable interrupt for event CH2LIMITL", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH3LIMITH": { + "description": "Write '1' to enable interrupt for event CH3LIMITH", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH3LIMITL": { + "description": "Write '1' to enable interrupt for event CH3LIMITL", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH4LIMITH": { + "description": "Write '1' to enable interrupt for event CH4LIMITH", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH4LIMITL": { + "description": "Write '1' to enable interrupt for event CH4LIMITL", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH5LIMITH": { + "description": "Write '1' to enable interrupt for event CH5LIMITH", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH5LIMITL": { + "description": "Write '1' to enable interrupt for event CH5LIMITL", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH6LIMITH": { + "description": "Write '1' to enable interrupt for event CH6LIMITH", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH6LIMITL": { + "description": "Write '1' to enable interrupt for event CH6LIMITL", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH7LIMITH": { + "description": "Write '1' to enable interrupt for event CH7LIMITH", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH7LIMITL": { + "description": "Write '1' to enable interrupt for event CH7LIMITL", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STARTED": { + "description": "Write '1' to disable interrupt for event STARTED", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "END": { + "description": "Write '1' to disable interrupt for event END", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DONE": { + "description": "Write '1' to disable interrupt for event DONE", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RESULTDONE": { + "description": "Write '1' to disable interrupt for event RESULTDONE", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CALIBRATEDONE": { + "description": "Write '1' to disable interrupt for event CALIBRATEDONE", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to disable interrupt for event STOPPED", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH0LIMITH": { + "description": "Write '1' to disable interrupt for event CH0LIMITH", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH0LIMITL": { + "description": "Write '1' to disable interrupt for event CH0LIMITL", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH1LIMITH": { + "description": "Write '1' to disable interrupt for event CH1LIMITH", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH1LIMITL": { + "description": "Write '1' to disable interrupt for event CH1LIMITL", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH2LIMITH": { + "description": "Write '1' to disable interrupt for event CH2LIMITH", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH2LIMITL": { + "description": "Write '1' to disable interrupt for event CH2LIMITL", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH3LIMITH": { + "description": "Write '1' to disable interrupt for event CH3LIMITH", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH3LIMITL": { + "description": "Write '1' to disable interrupt for event CH3LIMITL", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH4LIMITH": { + "description": "Write '1' to disable interrupt for event CH4LIMITH", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH4LIMITL": { + "description": "Write '1' to disable interrupt for event CH4LIMITL", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH5LIMITH": { + "description": "Write '1' to disable interrupt for event CH5LIMITH", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH5LIMITL": { + "description": "Write '1' to disable interrupt for event CH5LIMITL", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH6LIMITH": { + "description": "Write '1' to disable interrupt for event CH6LIMITH", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH6LIMITL": { + "description": "Write '1' to disable interrupt for event CH6LIMITL", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH7LIMITH": { + "description": "Write '1' to disable interrupt for event CH7LIMITH", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CH7LIMITL": { + "description": "Write '1' to disable interrupt for event CH7LIMITL", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "STATUS": { + "description": "Status", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STATUS": { + "description": "Status", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Ready": { + "description": "SAADC is ready. No on-going conversions.", + "value": 0 + }, + "Busy": { + "description": "SAADC is busy. Conversion in progress.", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable or disable SAADC", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable SAADC", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable SAADC", + "value": 0 + }, + "Enabled": { + "description": "Enable SAADC", + "value": 1 + } + } + } + } + } + } + } + }, + "RESOLUTION": { + "description": "Resolution configuration", + "offset": 1520, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "VAL": { + "description": "Set the resolution", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "8bit": { + "description": "8 bits", + "value": 0 + }, + "10bit": { + "description": "10 bits", + "value": 1 + }, + "12bit": { + "description": "12 bits", + "value": 2 + }, + "14bit": { + "description": "14 bits", + "value": 3 + } + } + } + } + } + } + } + }, + "OVERSAMPLE": { + "description": "Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.", + "offset": 1524, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVERSAMPLE": { + "description": "Oversample control", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Bypass": { + "description": "Bypass oversampling", + "value": 0 + }, + "Over2x": { + "description": "Oversample 2x", + "value": 1 + }, + "Over4x": { + "description": "Oversample 4x", + "value": 2 + }, + "Over8x": { + "description": "Oversample 8x", + "value": 3 + }, + "Over16x": { + "description": "Oversample 16x", + "value": 4 + }, + "Over32x": { + "description": "Oversample 32x", + "value": 5 + }, + "Over64x": { + "description": "Oversample 64x", + "value": 6 + }, + "Over128x": { + "description": "Oversample 128x", + "value": 7 + }, + "Over256x": { + "description": "Oversample 256x", + "value": 8 + } + } + } + } + } + } + } + }, + "SAMPLERATE": { + "description": "Controls normal or continuous sample rate", + "offset": 1528, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC": { + "description": "Capture and compare value. Sample rate is 16 MHz/CC", + "offset": 0, + "size": 11 + }, + "MODE": { + "description": "Select mode for sample rate control", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Task": { + "description": "Rate is controlled from SAMPLE task", + "value": 0 + }, + "Timers": { + "description": "Rate is controlled from local timer (use CC to control the rate)", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "TIMER0": { + "description": "Timer/Counter 0", + "children": { + "registers": { + "TASKS_START": { + "description": "Start Timer", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Start Timer", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stop Timer", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop Timer", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_COUNT": { + "description": "Increment Timer (Counter mode only)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_COUNT": { + "description": "Increment Timer (Counter mode only)", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_CLEAR": { + "description": "Clear time", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CLEAR": { + "description": "Clear time", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SHUTDOWN": { + "description": "Deprecated register - Shut down timer", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SHUTDOWN": { + "description": "Deprecated field - Shut down timer", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_CAPTURE": { + "description": "Description collection: Capture Timer value to CC[n] register", + "offset": 64, + "size": 32, + "count": 6, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CAPTURE": { + "description": "Capture Timer value to CC[n] register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_COMPARE": { + "description": "Description collection: Compare event on CC[n] match", + "offset": 320, + "size": 32, + "count": 6, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_COMPARE": { + "description": "Compare event on CC[n] match", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMPARE0_CLEAR": { + "description": "Shortcut between event COMPARE[0] and task CLEAR", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE1_CLEAR": { + "description": "Shortcut between event COMPARE[1] and task CLEAR", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE2_CLEAR": { + "description": "Shortcut between event COMPARE[2] and task CLEAR", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE3_CLEAR": { + "description": "Shortcut between event COMPARE[3] and task CLEAR", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE4_CLEAR": { + "description": "Shortcut between event COMPARE[4] and task CLEAR", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE5_CLEAR": { + "description": "Shortcut between event COMPARE[5] and task CLEAR", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE0_STOP": { + "description": "Shortcut between event COMPARE[0] and task STOP", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE1_STOP": { + "description": "Shortcut between event COMPARE[1] and task STOP", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE2_STOP": { + "description": "Shortcut between event COMPARE[2] and task STOP", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE3_STOP": { + "description": "Shortcut between event COMPARE[3] and task STOP", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE4_STOP": { + "description": "Shortcut between event COMPARE[4] and task STOP", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "COMPARE5_STOP": { + "description": "Shortcut between event COMPARE[5] and task STOP", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMPARE0": { + "description": "Write '1' to enable interrupt for event COMPARE[0]", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to enable interrupt for event COMPARE[1]", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to enable interrupt for event COMPARE[2]", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to enable interrupt for event COMPARE[3]", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE4": { + "description": "Write '1' to enable interrupt for event COMPARE[4]", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE5": { + "description": "Write '1' to enable interrupt for event COMPARE[5]", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMPARE0": { + "description": "Write '1' to disable interrupt for event COMPARE[0]", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to disable interrupt for event COMPARE[1]", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to disable interrupt for event COMPARE[2]", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to disable interrupt for event COMPARE[3]", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE4": { + "description": "Write '1' to disable interrupt for event COMPARE[4]", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE5": { + "description": "Write '1' to disable interrupt for event COMPARE[5]", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "MODE": { + "description": "Timer mode selection", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "Timer mode", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Timer": { + "description": "Select Timer mode", + "value": 0 + }, + "Counter": { + "description": "Deprecated enumerator - Select Counter mode", + "value": 1 + }, + "LowPowerCounter": { + "description": "Select Low Power Counter mode", + "value": 2 + } + } + } + } + } + } + } + }, + "BITMODE": { + "description": "Configure the number of bits used by the TIMER", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BITMODE": { + "description": "Timer bit width", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "16Bit": { + "description": "16 bit timer bit width", + "value": 0 + }, + "08Bit": { + "description": "8 bit timer bit width", + "value": 1 + }, + "24Bit": { + "description": "24 bit timer bit width", + "value": 2 + }, + "32Bit": { + "description": "32 bit timer bit width", + "value": 3 + } + } + } + } + } + } + } + }, + "PRESCALER": { + "description": "Timer prescaler register", + "offset": 1296, + "size": 32, + "reset_value": 4, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRESCALER": { + "description": "Prescaler value", + "offset": 0, + "size": 4 + } + } + } + }, + "CC": { + "description": "Description collection: Capture/Compare register n", + "offset": 1344, + "size": 32, + "count": 6, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC": { + "description": "Capture/Compare value", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "FPU": { + "description": "FPU", + "children": { + "registers": { + "UNUSED": { + "description": "Unused.", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only" + } + } + } + }, + "I2S": { + "description": "Inter-IC Sound", + "children": { + "registers": { + "TASKS_START": { + "description": "Starts continuous I2S transfer. Also starts MCK generator when this is enabled.", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Starts continuous I2S transfer. Also starts MCK generator when this is enabled.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RXPTRUPD": { + "description": "The RXD.PTR register has been copied to internal double-buffers.\n When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RXPTRUPD": { + "description": "The RXD.PTR register has been copied to internal double-buffers.\n When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STOPPED": { + "description": "I2S transfer stopped.", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STOPPED": { + "description": "I2S transfer stopped.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TXPTRUPD": { + "description": "The TDX.PTR register has been copied to internal double-buffers.\n When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TXPTRUPD": { + "description": "The TDX.PTR register has been copied to internal double-buffers.\n When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXPTRUPD": { + "description": "Enable or disable interrupt for event RXPTRUPD", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Enable or disable interrupt for event STOPPED", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "TXPTRUPD": { + "description": "Enable or disable interrupt for event TXPTRUPD", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXPTRUPD": { + "description": "Write '1' to enable interrupt for event RXPTRUPD", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to enable interrupt for event STOPPED", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXPTRUPD": { + "description": "Write '1' to enable interrupt for event TXPTRUPD", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXPTRUPD": { + "description": "Write '1' to disable interrupt for event RXPTRUPD", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to disable interrupt for event STOPPED", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "TXPTRUPD": { + "description": "Write '1' to disable interrupt for event TXPTRUPD", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable I2S module.", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable I2S module.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "RTC0": { + "description": "Real time counter 0", + "children": { + "registers": { + "TASKS_START": { + "description": "Start RTC COUNTER", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Start RTC COUNTER", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stop RTC COUNTER", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop RTC COUNTER", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_CLEAR": { + "description": "Clear RTC COUNTER", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CLEAR": { + "description": "Clear RTC COUNTER", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_TRIGOVRFLW": { + "description": "Set COUNTER to 0xFFFFF0", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_TRIGOVRFLW": { + "description": "Set COUNTER to 0xFFFFF0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TICK": { + "description": "Event on COUNTER increment", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TICK": { + "description": "Event on COUNTER increment", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_OVRFLW": { + "description": "Event on COUNTER overflow", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_OVRFLW": { + "description": "Event on COUNTER overflow", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_COMPARE": { + "description": "Description collection: Compare event on CC[n] match", + "offset": 320, + "size": 32, + "count": 4, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_COMPARE": { + "description": "Compare event on CC[n] match", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TICK": { + "description": "Write '1' to enable interrupt for event TICK", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "OVRFLW": { + "description": "Write '1' to enable interrupt for event OVRFLW", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE0": { + "description": "Write '1' to enable interrupt for event COMPARE[0]", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to enable interrupt for event COMPARE[1]", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to enable interrupt for event COMPARE[2]", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to enable interrupt for event COMPARE[3]", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TICK": { + "description": "Write '1' to disable interrupt for event TICK", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "OVRFLW": { + "description": "Write '1' to disable interrupt for event OVRFLW", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE0": { + "description": "Write '1' to disable interrupt for event COMPARE[0]", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to disable interrupt for event COMPARE[1]", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to disable interrupt for event COMPARE[2]", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to disable interrupt for event COMPARE[3]", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "EVTEN": { + "description": "Enable or disable event routing", + "offset": 832, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TICK": { + "description": "Enable or disable event routing for event TICK", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Disable", + "value": 1 + } + } + } + } + }, + "OVRFLW": { + "description": "Enable or disable event routing for event OVRFLW", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Disable", + "value": 1 + } + } + } + } + }, + "COMPARE0": { + "description": "Enable or disable event routing for event COMPARE[0]", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Disable", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Enable or disable event routing for event COMPARE[1]", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Disable", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Enable or disable event routing for event COMPARE[2]", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Disable", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Enable or disable event routing for event COMPARE[3]", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Disable", + "value": 1 + } + } + } + } + } + } + } + }, + "EVTENSET": { + "description": "Enable event routing", + "offset": 836, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TICK": { + "description": "Write '1' to enable event routing for event TICK", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "OVRFLW": { + "description": "Write '1' to enable event routing for event OVRFLW", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE0": { + "description": "Write '1' to enable event routing for event COMPARE[0]", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to enable event routing for event COMPARE[1]", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to enable event routing for event COMPARE[2]", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to enable event routing for event COMPARE[3]", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "EVTENCLR": { + "description": "Disable event routing", + "offset": 840, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TICK": { + "description": "Write '1' to disable event routing for event TICK", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "OVRFLW": { + "description": "Write '1' to disable event routing for event OVRFLW", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE0": { + "description": "Write '1' to disable event routing for event COMPARE[0]", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE1": { + "description": "Write '1' to disable event routing for event COMPARE[1]", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE2": { + "description": "Write '1' to disable event routing for event COMPARE[2]", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "COMPARE3": { + "description": "Write '1' to disable event routing for event COMPARE[3]", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "COUNTER": { + "description": "Current COUNTER value", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "COUNTER": { + "description": "Counter value", + "offset": 0, + "size": 24 + } + } + } + }, + "PRESCALER": { + "description": "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRESCALER": { + "description": "Prescaler value", + "offset": 0, + "size": 12 + } + } + } + }, + "CC": { + "description": "Description collection: Compare register n", + "offset": 1344, + "size": 32, + "count": 4, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMPARE": { + "description": "Compare value", + "offset": 0, + "size": 24 + } + } + } + } + } + } + }, + "TEMP": { + "description": "Temperature Sensor", + "children": { + "registers": { + "TASKS_START": { + "description": "Start temperature measurement", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Start temperature measurement", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stop temperature measurement", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop temperature measurement", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_DATARDY": { + "description": "Temperature measurement complete, data ready", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_DATARDY": { + "description": "Temperature measurement complete, data ready", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATARDY": { + "description": "Write '1' to enable interrupt for event DATARDY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATARDY": { + "description": "Write '1' to disable interrupt for event DATARDY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "TEMP": { + "description": "Temperature in degC (0.25deg steps)", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TEMP": { + "description": "Temperature in degC (0.25deg steps)", + "offset": 0, + "size": 32 + } + } + } + }, + "A0": { + "description": "Slope of 1st piece wise linear function", + "offset": 1312, + "size": 32, + "reset_value": 806, + "reset_mask": 4294967295, + "children": { + "fields": { + "A0": { + "description": "Slope of 1st piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "A1": { + "description": "Slope of 2nd piece wise linear function", + "offset": 1316, + "size": 32, + "reset_value": 840, + "reset_mask": 4294967295, + "children": { + "fields": { + "A1": { + "description": "Slope of 2nd piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "A2": { + "description": "Slope of 3rd piece wise linear function", + "offset": 1320, + "size": 32, + "reset_value": 938, + "reset_mask": 4294967295, + "children": { + "fields": { + "A2": { + "description": "Slope of 3rd piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "A3": { + "description": "Slope of 4th piece wise linear function", + "offset": 1324, + "size": 32, + "reset_value": 1038, + "reset_mask": 4294967295, + "children": { + "fields": { + "A3": { + "description": "Slope of 4th piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "A4": { + "description": "Slope of 5th piece wise linear function", + "offset": 1328, + "size": 32, + "reset_value": 1213, + "reset_mask": 4294967295, + "children": { + "fields": { + "A4": { + "description": "Slope of 5th piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "A5": { + "description": "Slope of 6th piece wise linear function", + "offset": 1332, + "size": 32, + "reset_value": 1443, + "reset_mask": 4294967295, + "children": { + "fields": { + "A5": { + "description": "Slope of 6th piece wise linear function", + "offset": 0, + "size": 12 + } + } + } + }, + "B0": { + "description": "y-intercept of 1st piece wise linear function", + "offset": 1344, + "size": 32, + "reset_value": 16367, + "reset_mask": 4294967295, + "children": { + "fields": { + "B0": { + "description": "y-intercept of 1st piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "B1": { + "description": "y-intercept of 2nd piece wise linear function", + "offset": 1348, + "size": 32, + "reset_value": 16318, + "reset_mask": 4294967295, + "children": { + "fields": { + "B1": { + "description": "y-intercept of 2nd piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "B2": { + "description": "y-intercept of 3rd piece wise linear function", + "offset": 1352, + "size": 32, + "reset_value": 16318, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2": { + "description": "y-intercept of 3rd piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "B3": { + "description": "y-intercept of 4th piece wise linear function", + "offset": 1356, + "size": 32, + "reset_value": 18, + "reset_mask": 4294967295, + "children": { + "fields": { + "B3": { + "description": "y-intercept of 4th piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "B4": { + "description": "y-intercept of 5th piece wise linear function", + "offset": 1360, + "size": 32, + "reset_value": 292, + "reset_mask": 4294967295, + "children": { + "fields": { + "B4": { + "description": "y-intercept of 5th piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "B5": { + "description": "y-intercept of 6th piece wise linear function", + "offset": 1364, + "size": 32, + "reset_value": 636, + "reset_mask": 4294967295, + "children": { + "fields": { + "B5": { + "description": "y-intercept of 6th piece wise linear function", + "offset": 0, + "size": 14 + } + } + } + }, + "T0": { + "description": "End point of 1st piece wise linear function", + "offset": 1376, + "size": 32, + "reset_value": 226, + "reset_mask": 4294967295, + "children": { + "fields": { + "T0": { + "description": "End point of 1st piece wise linear function", + "offset": 0, + "size": 8 + } + } + } + }, + "T1": { + "description": "End point of 2nd piece wise linear function", + "offset": 1380, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "T1": { + "description": "End point of 2nd piece wise linear function", + "offset": 0, + "size": 8 + } + } + } + }, + "T2": { + "description": "End point of 3rd piece wise linear function", + "offset": 1384, + "size": 32, + "reset_value": 25, + "reset_mask": 4294967295, + "children": { + "fields": { + "T2": { + "description": "End point of 3rd piece wise linear function", + "offset": 0, + "size": 8 + } + } + } + }, + "T3": { + "description": "End point of 4th piece wise linear function", + "offset": 1388, + "size": 32, + "reset_value": 60, + "reset_mask": 4294967295, + "children": { + "fields": { + "T3": { + "description": "End point of 4th piece wise linear function", + "offset": 0, + "size": 8 + } + } + } + }, + "T4": { + "description": "End point of 5th piece wise linear function", + "offset": 1392, + "size": 32, + "reset_value": 80, + "reset_mask": 4294967295, + "children": { + "fields": { + "T4": { + "description": "End point of 5th piece wise linear function", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "RNG": { + "description": "Random Number Generator", + "children": { + "registers": { + "TASKS_START": { + "description": "Task starting the random number generator", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Task starting the random number generator", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Task stopping the random number generator", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Task stopping the random number generator", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_VALRDY": { + "description": "Event being generated for every new random number written to the VALUE register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_VALRDY": { + "description": "Event being generated for every new random number written to the VALUE register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VALRDY_STOP": { + "description": "Shortcut between event VALRDY and task STOP", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VALRDY": { + "description": "Write '1' to enable interrupt for event VALRDY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VALRDY": { + "description": "Write '1' to disable interrupt for event VALRDY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DERCEN": { + "description": "Bias correction", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disabled", + "value": 0 + }, + "Enabled": { + "description": "Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "VALUE": { + "description": "Output random number", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "VALUE": { + "description": "Generated random number", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "ECB": { + "description": "AES ECB Mode Encryption", + "children": { + "registers": { + "TASKS_STARTECB": { + "description": "Start ECB block encrypt", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STARTECB": { + "description": "Start ECB block encrypt", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOPECB": { + "description": "Abort a possible executing ECB operation", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOPECB": { + "description": "Abort a possible executing ECB operation", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDECB": { + "description": "ECB block encrypt complete", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDECB": { + "description": "ECB block encrypt complete", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ERRORECB": { + "description": "ECB block encrypt aborted because of a STOPECB task or due to an error", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ERRORECB": { + "description": "ECB block encrypt aborted because of a STOPECB task or due to an error", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDECB": { + "description": "Write '1' to enable interrupt for event ENDECB", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERRORECB": { + "description": "Write '1' to enable interrupt for event ERRORECB", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDECB": { + "description": "Write '1' to disable interrupt for event ENDECB", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERRORECB": { + "description": "Write '1' to disable interrupt for event ERRORECB", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ECBDATAPTR": { + "description": "ECB block encrypt memory pointers", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ECBDATAPTR": { + "description": "Pointer to the ECB data structure (see Table 1 ECB data structure overview)", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "AAR": { + "description": "Accelerated Address Resolver", + "children": { + "registers": { + "TASKS_START": { + "description": "Start resolving addresses based on IRKs specified in the IRK data structure", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Start resolving addresses based on IRKs specified in the IRK data structure", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stop resolving addresses", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop resolving addresses", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_END": { + "description": "Address resolution procedure complete", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_END": { + "description": "Address resolution procedure complete", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_RESOLVED": { + "description": "Address resolved", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_RESOLVED": { + "description": "Address resolved", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_NOTRESOLVED": { + "description": "Address not resolved", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_NOTRESOLVED": { + "description": "Address not resolved", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END": { + "description": "Write '1' to enable interrupt for event END", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RESOLVED": { + "description": "Write '1' to enable interrupt for event RESOLVED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NOTRESOLVED": { + "description": "Write '1' to enable interrupt for event NOTRESOLVED", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "END": { + "description": "Write '1' to disable interrupt for event END", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "RESOLVED": { + "description": "Write '1' to disable interrupt for event RESOLVED", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "NOTRESOLVED": { + "description": "Write '1' to disable interrupt for event NOTRESOLVED", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "STATUS": { + "description": "Resolution status", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STATUS": { + "description": "The IRK that was used last time an address was resolved", + "offset": 0, + "size": 4 + } + } + } + }, + "ENABLE": { + "description": "Enable AAR", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable AAR", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 3 + } + } + } + } + } + } + } + }, + "NIRK": { + "description": "Number of IRKs", + "offset": 1284, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "NIRK": { + "description": "Number of Identity root keys available in the IRK data structure", + "offset": 0, + "size": 5 + } + } + } + }, + "IRKPTR": { + "description": "Pointer to IRK data structure", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IRKPTR": { + "description": "Pointer to the IRK data structure", + "offset": 0, + "size": 32 + } + } + } + }, + "ADDRPTR": { + "description": "Pointer to the resolvable address", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRPTR": { + "description": "Pointer to the resolvable address (6-bytes)", + "offset": 0, + "size": 32 + } + } + } + }, + "SCRATCHPTR": { + "description": "Pointer to data area used for temporary storage", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SCRATCHPTR": { + "description": "Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved.", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "CCM": { + "description": "AES CCM Mode Encryption", + "children": { + "registers": { + "TASKS_KSGEN": { + "description": "Start generation of key-stream. This operation will stop by itself when completed.", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_KSGEN": { + "description": "Start generation of key-stream. This operation will stop by itself when completed.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_CRYPT": { + "description": "Start encryption/decryption. This operation will stop by itself when completed.", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_CRYPT": { + "description": "Start encryption/decryption. This operation will stop by itself when completed.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stop encryption/decryption", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop encryption/decryption", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_RATEOVERRIDE": { + "description": "Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_RATEOVERRIDE": { + "description": "Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDKSGEN": { + "description": "Key-stream generation complete", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDKSGEN": { + "description": "Key-stream generation complete", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ENDCRYPT": { + "description": "Encrypt/decrypt complete", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ENDCRYPT": { + "description": "Encrypt/decrypt complete", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ERROR": { + "description": "Deprecated register - CCM error event", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ERROR": { + "description": "Deprecated field - CCM error event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDKSGEN_CRYPT": { + "description": "Shortcut between event ENDKSGEN and task CRYPT", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDKSGEN": { + "description": "Write '1' to enable interrupt for event ENDKSGEN", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDCRYPT": { + "description": "Write '1' to enable interrupt for event ENDCRYPT", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Deprecated intsetfield - Write '1' to enable interrupt for event ERROR", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDKSGEN": { + "description": "Write '1' to disable interrupt for event ENDKSGEN", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ENDCRYPT": { + "description": "Write '1' to disable interrupt for event ENDCRYPT", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ERROR": { + "description": "Deprecated intclrfield - Write '1' to disable interrupt for event ERROR", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "MICSTATUS": { + "description": "MIC check result", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "MICSTATUS": { + "description": "The result of the MIC check performed during the previous decryption operation", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "CheckFailed": { + "description": "MIC check failed", + "value": 0 + }, + "CheckPassed": { + "description": "MIC check passed", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable CCM", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 2 + } + } + } + } + } + } + } + }, + "MODE": { + "description": "Operation mode", + "offset": 1284, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Encryption": { + "description": "AES CCM packet encryption mode", + "value": 0 + }, + "Decryption": { + "description": "AES CCM packet decryption mode", + "value": 1 + } + } + } + } + }, + "DATARATE": { + "description": "Radio data rate that the CCM shall run synchronous with", + "offset": 16, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "1Mbit": { + "description": "1 Mbps", + "value": 0 + }, + "2Mbit": { + "description": "2 Mbps", + "value": 1 + }, + "125Kbps": { + "description": "125 Kbps", + "value": 2 + }, + "500Kbps": { + "description": "500 Kbps", + "value": 3 + } + } + } + } + }, + "LENGTH": { + "description": "Packet length configuration", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Default": { + "description": "Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated.", + "value": 0 + }, + "Extended": { + "description": "Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated.", + "value": 1 + } + } + } + } + } + } + } + }, + "CNFPTR": { + "description": "Pointer to data structure holding AES key and NONCE vector", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNFPTR": { + "description": "Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)", + "offset": 0, + "size": 32 + } + } + } + }, + "INPTR": { + "description": "Input pointer", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INPTR": { + "description": "Input pointer", + "offset": 0, + "size": 32 + } + } + } + }, + "OUTPTR": { + "description": "Output pointer", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OUTPTR": { + "description": "Output pointer", + "offset": 0, + "size": 32 + } + } + } + }, + "SCRATCHPTR": { + "description": "Pointer to data area used for temporary storage", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SCRATCHPTR": { + "description": "Pointer to a scratch data area used for temporary storage during key-stream generation,\n MIC generation and encryption/decryption.", + "offset": 0, + "size": 32 + } + } + } + }, + "MAXPACKETSIZE": { + "description": "Length of key-stream generated when MODE.LENGTH = Extended.", + "offset": 1304, + "size": 32, + "reset_value": 251, + "reset_mask": 4294967295, + "children": { + "fields": { + "MAXPACKETSIZE": { + "description": "Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted.", + "offset": 0, + "size": 8 + } + } + } + }, + "RATEOVERRIDE": { + "description": "Data rate override setting.", + "offset": 1308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RATEOVERRIDE": { + "description": "Data rate override setting.", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "1Mbit": { + "description": "1 Mbps", + "value": 0 + }, + "2Mbit": { + "description": "2 Mbps", + "value": 1 + }, + "125Kbps": { + "description": "125 Kbps", + "value": 2 + }, + "500Kbps": { + "description": "500 Kbps", + "value": 3 + } + } + } + } + } + } + } + } + } + } + }, + "WDT": { + "description": "Watchdog Timer", + "children": { + "registers": { + "TASKS_START": { + "description": "Start the watchdog", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Start the watchdog", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TIMEOUT": { + "description": "Watchdog timeout", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TIMEOUT": { + "description": "Watchdog timeout", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIMEOUT": { + "description": "Write '1' to enable interrupt for event TIMEOUT", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIMEOUT": { + "description": "Write '1' to disable interrupt for event TIMEOUT", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "RUNSTATUS": { + "description": "Run status", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RUNSTATUS": { + "description": "Indicates whether or not the watchdog is running", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotRunning": { + "description": "Watchdog not running", + "value": 0 + }, + "Running": { + "description": "Watchdog is running", + "value": 1 + } + } + } + } + } + } + } + }, + "REQSTATUS": { + "description": "Request status", + "offset": 1028, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RR0": { + "description": "Request status for RR[0] register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[0] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[0] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR1": { + "description": "Request status for RR[1] register", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[1] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[1] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR2": { + "description": "Request status for RR[2] register", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[2] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[2] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR3": { + "description": "Request status for RR[3] register", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[3] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[3] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR4": { + "description": "Request status for RR[4] register", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[4] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[4] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR5": { + "description": "Request status for RR[5] register", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[5] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[5] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR6": { + "description": "Request status for RR[6] register", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[6] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[6] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + }, + "RR7": { + "description": "Request status for RR[7] register", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "DisabledOrRequested": { + "description": "RR[7] register is not enabled, or are already requesting reload", + "value": 0 + }, + "EnabledAndUnrequested": { + "description": "RR[7] register is enabled, and are not yet requesting reload", + "value": 1 + } + } + } + } + } + } + } + }, + "CRV": { + "description": "Counter reload value", + "offset": 1284, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRV": { + "description": "Counter reload value in number of cycles of the 32.768 kHz clock", + "offset": 0, + "size": 32 + } + } + } + }, + "RREN": { + "description": "Enable register for reload request registers", + "offset": 1288, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "RR0": { + "description": "Enable or disable RR[0] register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[0] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[0] register", + "value": 1 + } + } + } + } + }, + "RR1": { + "description": "Enable or disable RR[1] register", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[1] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[1] register", + "value": 1 + } + } + } + } + }, + "RR2": { + "description": "Enable or disable RR[2] register", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[2] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[2] register", + "value": 1 + } + } + } + } + }, + "RR3": { + "description": "Enable or disable RR[3] register", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[3] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[3] register", + "value": 1 + } + } + } + } + }, + "RR4": { + "description": "Enable or disable RR[4] register", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[4] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[4] register", + "value": 1 + } + } + } + } + }, + "RR5": { + "description": "Enable or disable RR[5] register", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[5] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[5] register", + "value": 1 + } + } + } + } + }, + "RR6": { + "description": "Enable or disable RR[6] register", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[6] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[6] register", + "value": 1 + } + } + } + } + }, + "RR7": { + "description": "Enable or disable RR[7] register", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable RR[7] register", + "value": 0 + }, + "Enabled": { + "description": "Enable RR[7] register", + "value": 1 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1292, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLEEP": { + "description": "Configure the watchdog to either be paused, or kept running, while the CPU is sleeping", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Pause": { + "description": "Pause watchdog while the CPU is sleeping", + "value": 0 + }, + "Run": { + "description": "Keep the watchdog running while the CPU is sleeping", + "value": 1 + } + } + } + } + }, + "HALT": { + "description": "Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Pause": { + "description": "Pause watchdog while the CPU is halted by the debugger", + "value": 0 + }, + "Run": { + "description": "Keep the watchdog running while the CPU is halted by the debugger", + "value": 1 + } + } + } + } + } + } + } + }, + "RR": { + "description": "Description collection: Reload request n", + "offset": 1536, + "size": 32, + "count": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "RR": { + "description": "Reload request register", + "offset": 0, + "size": 32, + "enum": { + "size": 32, + "children": { + "enum_fields": { + "Reload": { + "description": "Value to request a reload of the watchdog timer", + "value": 1850885685 + } + } + } + } + } + } + } + } + } + } + }, + "MWU": { + "description": "Memory Watch Unit", + "children": { + "registers": { + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION0WA": { + "description": "Enable or disable interrupt for event REGION0WA", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION0RA": { + "description": "Enable or disable interrupt for event REGION0RA", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION1WA": { + "description": "Enable or disable interrupt for event REGION1WA", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION1RA": { + "description": "Enable or disable interrupt for event REGION1RA", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION2WA": { + "description": "Enable or disable interrupt for event REGION2WA", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION2RA": { + "description": "Enable or disable interrupt for event REGION2RA", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION3WA": { + "description": "Enable or disable interrupt for event REGION3WA", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION3RA": { + "description": "Enable or disable interrupt for event REGION3RA", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "PREGION0WA": { + "description": "Enable or disable interrupt for event PREGION0WA", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "PREGION0RA": { + "description": "Enable or disable interrupt for event PREGION0RA", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "PREGION1WA": { + "description": "Enable or disable interrupt for event PREGION1WA", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "PREGION1RA": { + "description": "Enable or disable interrupt for event PREGION1RA", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION0WA": { + "description": "Write '1' to enable interrupt for event REGION0WA", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION0RA": { + "description": "Write '1' to enable interrupt for event REGION0RA", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION1WA": { + "description": "Write '1' to enable interrupt for event REGION1WA", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION1RA": { + "description": "Write '1' to enable interrupt for event REGION1RA", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION2WA": { + "description": "Write '1' to enable interrupt for event REGION2WA", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION2RA": { + "description": "Write '1' to enable interrupt for event REGION2RA", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION3WA": { + "description": "Write '1' to enable interrupt for event REGION3WA", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION3RA": { + "description": "Write '1' to enable interrupt for event REGION3RA", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION0WA": { + "description": "Write '1' to enable interrupt for event PREGION0WA", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION0RA": { + "description": "Write '1' to enable interrupt for event PREGION0RA", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION1WA": { + "description": "Write '1' to enable interrupt for event PREGION1WA", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION1RA": { + "description": "Write '1' to enable interrupt for event PREGION1RA", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION0WA": { + "description": "Write '1' to disable interrupt for event REGION0WA", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION0RA": { + "description": "Write '1' to disable interrupt for event REGION0RA", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION1WA": { + "description": "Write '1' to disable interrupt for event REGION1WA", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION1RA": { + "description": "Write '1' to disable interrupt for event REGION1RA", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION2WA": { + "description": "Write '1' to disable interrupt for event REGION2WA", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION2RA": { + "description": "Write '1' to disable interrupt for event REGION2RA", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION3WA": { + "description": "Write '1' to disable interrupt for event REGION3WA", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION3RA": { + "description": "Write '1' to disable interrupt for event REGION3RA", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION0WA": { + "description": "Write '1' to disable interrupt for event PREGION0WA", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION0RA": { + "description": "Write '1' to disable interrupt for event PREGION0RA", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION1WA": { + "description": "Write '1' to disable interrupt for event PREGION1WA", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION1RA": { + "description": "Write '1' to disable interrupt for event PREGION1RA", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "NMIEN": { + "description": "Enable or disable interrupt", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION0WA": { + "description": "Enable or disable interrupt for event REGION0WA", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION0RA": { + "description": "Enable or disable interrupt for event REGION0RA", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION1WA": { + "description": "Enable or disable interrupt for event REGION1WA", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION1RA": { + "description": "Enable or disable interrupt for event REGION1RA", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION2WA": { + "description": "Enable or disable interrupt for event REGION2WA", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION2RA": { + "description": "Enable or disable interrupt for event REGION2RA", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION3WA": { + "description": "Enable or disable interrupt for event REGION3WA", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "REGION3RA": { + "description": "Enable or disable interrupt for event REGION3RA", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "PREGION0WA": { + "description": "Enable or disable interrupt for event PREGION0WA", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "PREGION0RA": { + "description": "Enable or disable interrupt for event PREGION0RA", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "PREGION1WA": { + "description": "Enable or disable interrupt for event PREGION1WA", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "PREGION1RA": { + "description": "Enable or disable interrupt for event PREGION1RA", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "NMIENSET": { + "description": "Enable interrupt", + "offset": 804, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION0WA": { + "description": "Write '1' to enable interrupt for event REGION0WA", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION0RA": { + "description": "Write '1' to enable interrupt for event REGION0RA", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION1WA": { + "description": "Write '1' to enable interrupt for event REGION1WA", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION1RA": { + "description": "Write '1' to enable interrupt for event REGION1RA", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION2WA": { + "description": "Write '1' to enable interrupt for event REGION2WA", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION2RA": { + "description": "Write '1' to enable interrupt for event REGION2RA", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION3WA": { + "description": "Write '1' to enable interrupt for event REGION3WA", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION3RA": { + "description": "Write '1' to enable interrupt for event REGION3RA", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION0WA": { + "description": "Write '1' to enable interrupt for event PREGION0WA", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION0RA": { + "description": "Write '1' to enable interrupt for event PREGION0RA", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION1WA": { + "description": "Write '1' to enable interrupt for event PREGION1WA", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION1RA": { + "description": "Write '1' to enable interrupt for event PREGION1RA", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "NMIENCLR": { + "description": "Disable interrupt", + "offset": 808, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION0WA": { + "description": "Write '1' to disable interrupt for event REGION0WA", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION0RA": { + "description": "Write '1' to disable interrupt for event REGION0RA", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION1WA": { + "description": "Write '1' to disable interrupt for event REGION1WA", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION1RA": { + "description": "Write '1' to disable interrupt for event REGION1RA", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION2WA": { + "description": "Write '1' to disable interrupt for event REGION2WA", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION2RA": { + "description": "Write '1' to disable interrupt for event REGION2RA", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION3WA": { + "description": "Write '1' to disable interrupt for event REGION3WA", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REGION3RA": { + "description": "Write '1' to disable interrupt for event REGION3RA", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION0WA": { + "description": "Write '1' to disable interrupt for event PREGION0WA", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION0RA": { + "description": "Write '1' to disable interrupt for event PREGION0RA", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION1WA": { + "description": "Write '1' to disable interrupt for event PREGION1WA", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "PREGION1RA": { + "description": "Write '1' to disable interrupt for event PREGION1RA", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "REGIONEN": { + "description": "Enable/disable regions watch", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RGN0WA": { + "description": "Enable/disable write access watch in region[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN0RA": { + "description": "Enable/disable read access watch in region[0]", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN1WA": { + "description": "Enable/disable write access watch in region[1]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN1RA": { + "description": "Enable/disable read access watch in region[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN2WA": { + "description": "Enable/disable write access watch in region[2]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN2RA": { + "description": "Enable/disable read access watch in region[2]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN3WA": { + "description": "Enable/disable write access watch in region[3]", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this region", + "value": 1 + } + } + } + } + }, + "RGN3RA": { + "description": "Enable/disable read access watch in region[3]", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this region", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this region", + "value": 1 + } + } + } + } + }, + "PRGN0WA": { + "description": "Enable/disable write access watch in PREGION[0]", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this PREGION", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this PREGION", + "value": 1 + } + } + } + } + }, + "PRGN0RA": { + "description": "Enable/disable read access watch in PREGION[0]", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this PREGION", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this PREGION", + "value": 1 + } + } + } + } + }, + "PRGN1WA": { + "description": "Enable/disable write access watch in PREGION[1]", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable write access watch in this PREGION", + "value": 0 + }, + "Enable": { + "description": "Enable write access watch in this PREGION", + "value": 1 + } + } + } + } + }, + "PRGN1RA": { + "description": "Enable/disable read access watch in PREGION[1]", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disable": { + "description": "Disable read access watch in this PREGION", + "value": 0 + }, + "Enable": { + "description": "Enable read access watch in this PREGION", + "value": 1 + } + } + } + } + } + } + } + }, + "REGIONENSET": { + "description": "Enable regions watch", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RGN0WA": { + "description": "Enable write access watch in region[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN0RA": { + "description": "Enable read access watch in region[0]", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN1WA": { + "description": "Enable write access watch in region[1]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN1RA": { + "description": "Enable read access watch in region[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN2WA": { + "description": "Enable write access watch in region[2]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN2RA": { + "description": "Enable read access watch in region[2]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN3WA": { + "description": "Enable write access watch in region[3]", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN3RA": { + "description": "Enable read access watch in region[3]", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "PRGN0WA": { + "description": "Enable write access watch in PREGION[0]", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN0RA": { + "description": "Enable read access watch in PREGION[0]", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN1WA": { + "description": "Enable write access watch in PREGION[1]", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN1RA": { + "description": "Enable read access watch in PREGION[1]", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "REGIONENCLR": { + "description": "Disable regions watch", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RGN0WA": { + "description": "Disable write access watch in region[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN0RA": { + "description": "Disable read access watch in region[0]", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN1WA": { + "description": "Disable write access watch in region[1]", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN1RA": { + "description": "Disable read access watch in region[1]", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN2WA": { + "description": "Disable write access watch in region[2]", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN2RA": { + "description": "Disable read access watch in region[2]", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN3WA": { + "description": "Disable write access watch in region[3]", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "RGN3RA": { + "description": "Disable read access watch in region[3]", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this region is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this region is enabled", + "value": 1 + } + } + } + } + }, + "PRGN0WA": { + "description": "Disable write access watch in PREGION[0]", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN0RA": { + "description": "Disable read access watch in PREGION[0]", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN1WA": { + "description": "Disable write access watch in PREGION[1]", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Write access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Write access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + }, + "PRGN1RA": { + "description": "Disable read access watch in PREGION[1]", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read access watch in this PREGION is disabled", + "value": 0 + }, + "Enabled": { + "description": "Read access watch in this PREGION is enabled", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "QDEC": { + "description": "Quadrature Decoder", + "children": { + "registers": { + "TASKS_START": { + "description": "Task starting the quadrature decoder", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Task starting the quadrature decoder", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Task stopping the quadrature decoder", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Task stopping the quadrature decoder", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_READCLRACC": { + "description": "Read and clear ACC and ACCDBL", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_READCLRACC": { + "description": "Read and clear ACC and ACCDBL", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_RDCLRACC": { + "description": "Read and clear ACC", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_RDCLRACC": { + "description": "Read and clear ACC", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_RDCLRDBL": { + "description": "Read and clear ACCDBL", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_RDCLRDBL": { + "description": "Read and clear ACCDBL", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_SAMPLERDY": { + "description": "Event being generated for every new sample value written to the SAMPLE register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_SAMPLERDY": { + "description": "Event being generated for every new sample value written to the SAMPLE register", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_REPORTRDY": { + "description": "Non-null report ready", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_REPORTRDY": { + "description": "Non-null report ready", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_ACCOF": { + "description": "ACC or ACCDBL register overflow", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_ACCOF": { + "description": "ACC or ACCDBL register overflow", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_DBLRDY": { + "description": "Double displacement(s) detected", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_DBLRDY": { + "description": "Double displacement(s) detected", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_STOPPED": { + "description": "QDEC has been stopped", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_STOPPED": { + "description": "QDEC has been stopped", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REPORTRDY_READCLRACC": { + "description": "Shortcut between event REPORTRDY and task READCLRACC", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "SAMPLERDY_STOP": { + "description": "Shortcut between event SAMPLERDY and task STOP", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "REPORTRDY_RDCLRACC": { + "description": "Shortcut between event REPORTRDY and task RDCLRACC", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "REPORTRDY_STOP": { + "description": "Shortcut between event REPORTRDY and task STOP", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DBLRDY_RDCLRDBL": { + "description": "Shortcut between event DBLRDY and task RDCLRDBL", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DBLRDY_STOP": { + "description": "Shortcut between event DBLRDY and task STOP", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "SAMPLERDY_READCLRACC": { + "description": "Shortcut between event SAMPLERDY and task READCLRACC", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SAMPLERDY": { + "description": "Write '1' to enable interrupt for event SAMPLERDY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REPORTRDY": { + "description": "Write '1' to enable interrupt for event REPORTRDY", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ACCOF": { + "description": "Write '1' to enable interrupt for event ACCOF", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DBLRDY": { + "description": "Write '1' to enable interrupt for event DBLRDY", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to enable interrupt for event STOPPED", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SAMPLERDY": { + "description": "Write '1' to disable interrupt for event SAMPLERDY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "REPORTRDY": { + "description": "Write '1' to disable interrupt for event REPORTRDY", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "ACCOF": { + "description": "Write '1' to disable interrupt for event ACCOF", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DBLRDY": { + "description": "Write '1' to disable interrupt for event DBLRDY", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "STOPPED": { + "description": "Write '1' to disable interrupt for event STOPPED", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable the quadrature decoder", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable the quadrature decoder", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "LEDPOL": { + "description": "LED output pin polarity", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEDPOL": { + "description": "LED output pin polarity", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "ActiveLow": { + "description": "Led active on output pin low", + "value": 0 + }, + "ActiveHigh": { + "description": "Led active on output pin high", + "value": 1 + } + } + } + } + } + } + } + }, + "SAMPLEPER": { + "description": "Sample period", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SAMPLEPER": { + "description": "Sample period. The SAMPLE register will be updated for every new sample", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "128us": { + "description": "128 us", + "value": 0 + }, + "256us": { + "description": "256 us", + "value": 1 + }, + "512us": { + "description": "512 us", + "value": 2 + }, + "1024us": { + "description": "1024 us", + "value": 3 + }, + "2048us": { + "description": "2048 us", + "value": 4 + }, + "4096us": { + "description": "4096 us", + "value": 5 + }, + "8192us": { + "description": "8192 us", + "value": 6 + }, + "16384us": { + "description": "16384 us", + "value": 7 + }, + "32ms": { + "description": "32768 us", + "value": 8 + }, + "65ms": { + "description": "65536 us", + "value": 9 + }, + "131ms": { + "description": "131072 us", + "value": 10 + } + } + } + } + } + } + } + }, + "SAMPLE": { + "description": "Motion sample value", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SAMPLE": { + "description": "Last motion sample", + "offset": 0, + "size": 32 + } + } + } + }, + "REPORTPER": { + "description": "Number of samples to be taken before REPORTRDY and DBLRDY events can be generated", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REPORTPER": { + "description": "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "10Smpl": { + "description": "10 samples / report", + "value": 0 + }, + "40Smpl": { + "description": "40 samples / report", + "value": 1 + }, + "80Smpl": { + "description": "80 samples / report", + "value": 2 + }, + "120Smpl": { + "description": "120 samples / report", + "value": 3 + }, + "160Smpl": { + "description": "160 samples / report", + "value": 4 + }, + "200Smpl": { + "description": "200 samples / report", + "value": 5 + }, + "240Smpl": { + "description": "240 samples / report", + "value": 6 + }, + "280Smpl": { + "description": "280 samples / report", + "value": 7 + }, + "1Smpl": { + "description": "1 sample / report", + "value": 8 + } + } + } + } + } + } + } + }, + "ACC": { + "description": "Register accumulating the valid transitions", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACC": { + "description": "Register accumulating all valid samples (not double transition) read from the SAMPLE register", + "offset": 0, + "size": 32 + } + } + } + }, + "ACCREAD": { + "description": "Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACCREAD": { + "description": "Snapshot of the ACC register.", + "offset": 0, + "size": 32 + } + } + } + }, + "DBFEN": { + "description": "Enable input debounce filters", + "offset": 1320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBFEN": { + "description": "Enable input debounce filters", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Debounce input filters disabled", + "value": 0 + }, + "Enabled": { + "description": "Debounce input filters enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "LEDPRE": { + "description": "Time period the LED is switched ON prior to sampling", + "offset": 1344, + "size": 32, + "reset_value": 16, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEDPRE": { + "description": "Period in us the LED is switched on prior to sampling", + "offset": 0, + "size": 9 + } + } + } + }, + "ACCDBL": { + "description": "Register accumulating the number of detected double transitions", + "offset": 1348, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACCDBL": { + "description": "Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).", + "offset": 0, + "size": 4 + } + } + } + }, + "ACCDBLREAD": { + "description": "Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task", + "offset": 1352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACCDBLREAD": { + "description": "Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered.", + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "COMP": { + "description": "Comparator", + "children": { + "registers": { + "TASKS_START": { + "description": "Start comparator", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Start comparator", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stop comparator", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop comparator", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SAMPLE": { + "description": "Sample comparator value", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SAMPLE": { + "description": "Sample comparator value", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_READY": { + "description": "COMP is ready and output is valid", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_READY": { + "description": "COMP is ready and output is valid", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_DOWN": { + "description": "Downward crossing", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_DOWN": { + "description": "Downward crossing", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_UP": { + "description": "Upward crossing", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_UP": { + "description": "Upward crossing", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CROSS": { + "description": "Downward or upward crossing", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CROSS": { + "description": "Downward or upward crossing", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY_SAMPLE": { + "description": "Shortcut between event READY and task SAMPLE", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "READY_STOP": { + "description": "Shortcut between event READY and task STOP", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DOWN_STOP": { + "description": "Shortcut between event DOWN and task STOP", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "UP_STOP": { + "description": "Shortcut between event UP and task STOP", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "CROSS_STOP": { + "description": "Shortcut between event CROSS and task STOP", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Enable or disable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "DOWN": { + "description": "Enable or disable interrupt for event DOWN", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "UP": { + "description": "Enable or disable interrupt for event UP", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + }, + "CROSS": { + "description": "Enable or disable interrupt for event CROSS", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to enable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DOWN": { + "description": "Write '1' to enable interrupt for event DOWN", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "UP": { + "description": "Write '1' to enable interrupt for event UP", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CROSS": { + "description": "Write '1' to enable interrupt for event CROSS", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to disable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DOWN": { + "description": "Write '1' to disable interrupt for event DOWN", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "UP": { + "description": "Write '1' to disable interrupt for event UP", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CROSS": { + "description": "Write '1' to disable interrupt for event CROSS", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "RESULT": { + "description": "Compare result", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RESULT": { + "description": "Result of last compare. Decision point SAMPLE task.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Below": { + "description": "Input voltage is below the threshold (VIN+ < VIN-)", + "value": 0 + }, + "Above": { + "description": "Input voltage is above the threshold (VIN+ > VIN-)", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "COMP enable", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable COMP", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 2 + } + } + } + } + } + } + } + }, + "PSEL": { + "description": "Pin select", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSEL": { + "description": "Analog pin select", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "AnalogInput0": { + "description": "AIN0 selected as analog input", + "value": 0 + }, + "AnalogInput1": { + "description": "AIN1 selected as analog input", + "value": 1 + }, + "AnalogInput2": { + "description": "AIN2 selected as analog input", + "value": 2 + }, + "AnalogInput3": { + "description": "AIN3 selected as analog input", + "value": 3 + }, + "AnalogInput4": { + "description": "AIN4 selected as analog input", + "value": 4 + }, + "AnalogInput5": { + "description": "AIN5 selected as analog input", + "value": 5 + }, + "AnalogInput6": { + "description": "AIN6 selected as analog input", + "value": 6 + }, + "AnalogInput7": { + "description": "AIN7 selected as analog input", + "value": 7 + } + } + } + } + } + } + } + }, + "REFSEL": { + "description": "Reference source select for single-ended mode", + "offset": 1288, + "size": 32, + "reset_value": 4, + "reset_mask": 4294967295, + "children": { + "fields": { + "REFSEL": { + "description": "Reference select", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "Int1V2": { + "description": "VREF = internal 1.2 V reference (VDD >= 1.7 V)", + "value": 0 + }, + "Int1V8": { + "description": "VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)", + "value": 1 + }, + "Int2V4": { + "description": "VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)", + "value": 2 + }, + "VDD": { + "description": "VREF = VDD", + "value": 4 + }, + "ARef": { + "description": "VREF = AREF (VDD >= VREF >= AREFMIN)", + "value": 5 + } + } + } + } + } + } + } + }, + "EXTREFSEL": { + "description": "External reference select", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTREFSEL": { + "description": "External analog reference select", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "AnalogReference0": { + "description": "Use AIN0 as external analog reference", + "value": 0 + }, + "AnalogReference1": { + "description": "Use AIN1 as external analog reference", + "value": 1 + }, + "AnalogReference2": { + "description": "Use AIN2 as external analog reference", + "value": 2 + }, + "AnalogReference3": { + "description": "Use AIN3 as external analog reference", + "value": 3 + }, + "AnalogReference4": { + "description": "Use AIN4 as external analog reference", + "value": 4 + }, + "AnalogReference5": { + "description": "Use AIN5 as external analog reference", + "value": 5 + }, + "AnalogReference6": { + "description": "Use AIN6 as external analog reference", + "value": 6 + }, + "AnalogReference7": { + "description": "Use AIN7 as external analog reference", + "value": 7 + } + } + } + } + } + } + } + }, + "TH": { + "description": "Threshold configuration for hysteresis unit", + "offset": 1328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "THDOWN": { + "description": "VDOWN = (THDOWN+1)/64*VREF", + "offset": 0, + "size": 6 + }, + "THUP": { + "description": "VUP = (THUP+1)/64*VREF", + "offset": 8, + "size": 6 + } + } + } + }, + "MODE": { + "description": "Mode configuration", + "offset": 1332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SP": { + "description": "Speed and power modes", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Low": { + "description": "Low-power mode", + "value": 0 + }, + "Normal": { + "description": "Normal mode", + "value": 1 + }, + "High": { + "description": "High-speed mode", + "value": 2 + } + } + } + } + }, + "MAIN": { + "description": "Main operation modes", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "SE": { + "description": "Single-ended mode", + "value": 0 + }, + "Diff": { + "description": "Differential mode", + "value": 1 + } + } + } + } + } + } + } + }, + "HYST": { + "description": "Comparator hysteresis enable", + "offset": 1336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HYST": { + "description": "Comparator hysteresis", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoHyst": { + "description": "Comparator hysteresis disabled", + "value": 0 + }, + "Hyst50mV": { + "description": "Comparator hysteresis enabled", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "LPCOMP": { + "description": "Low Power Comparator", + "children": { + "registers": { + "TASKS_START": { + "description": "Start comparator", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_START": { + "description": "Start comparator", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_STOP": { + "description": "Stop comparator", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_STOP": { + "description": "Stop comparator", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "TASKS_SAMPLE": { + "description": "Sample comparator value", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_SAMPLE": { + "description": "Sample comparator value", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_READY": { + "description": "LPCOMP is ready and output is valid", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_READY": { + "description": "LPCOMP is ready and output is valid", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_DOWN": { + "description": "Downward crossing", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_DOWN": { + "description": "Downward crossing", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_UP": { + "description": "Upward crossing", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_UP": { + "description": "Upward crossing", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_CROSS": { + "description": "Downward or upward crossing", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_CROSS": { + "description": "Downward or upward crossing", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "SHORTS": { + "description": "Shortcuts between local events and tasks", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY_SAMPLE": { + "description": "Shortcut between event READY and task SAMPLE", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "READY_STOP": { + "description": "Shortcut between event READY and task STOP", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "DOWN_STOP": { + "description": "Shortcut between event DOWN and task STOP", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "UP_STOP": { + "description": "Shortcut between event UP and task STOP", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + }, + "CROSS_STOP": { + "description": "Shortcut between event CROSS and task STOP", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable shortcut", + "value": 0 + }, + "Enabled": { + "description": "Enable shortcut", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENSET": { + "description": "Enable interrupt", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to enable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DOWN": { + "description": "Write '1' to enable interrupt for event DOWN", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "UP": { + "description": "Write '1' to enable interrupt for event UP", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CROSS": { + "description": "Write '1' to enable interrupt for event CROSS", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "INTENCLR": { + "description": "Disable interrupt", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "READY": { + "description": "Write '1' to disable interrupt for event READY", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "DOWN": { + "description": "Write '1' to disable interrupt for event DOWN", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "UP": { + "description": "Write '1' to disable interrupt for event UP", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + }, + "CROSS": { + "description": "Write '1' to disable interrupt for event CROSS", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: Disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: Enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "RESULT": { + "description": "Compare result", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RESULT": { + "description": "Result of last compare. Decision point SAMPLE task.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Below": { + "description": "Input voltage is below the reference threshold (VIN+ < VIN-).", + "value": 0 + }, + "Above": { + "description": "Input voltage is above the reference threshold (VIN+ > VIN-).", + "value": 1 + } + } + } + } + } + } + } + }, + "ENABLE": { + "description": "Enable LPCOMP", + "offset": 1280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Enable or disable LPCOMP", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable", + "value": 0 + }, + "Enabled": { + "description": "Enable", + "value": 1 + } + } + } + } + } + } + } + }, + "PSEL": { + "description": "Input pin select", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSEL": { + "description": "Analog pin select", + "offset": 0, + "size": 3, + "enum": { + "size": 3, + "children": { + "enum_fields": { + "AnalogInput0": { + "description": "AIN0 selected as analog input", + "value": 0 + }, + "AnalogInput1": { + "description": "AIN1 selected as analog input", + "value": 1 + }, + "AnalogInput2": { + "description": "AIN2 selected as analog input", + "value": 2 + }, + "AnalogInput3": { + "description": "AIN3 selected as analog input", + "value": 3 + }, + "AnalogInput4": { + "description": "AIN4 selected as analog input", + "value": 4 + }, + "AnalogInput5": { + "description": "AIN5 selected as analog input", + "value": 5 + }, + "AnalogInput6": { + "description": "AIN6 selected as analog input", + "value": 6 + }, + "AnalogInput7": { + "description": "AIN7 selected as analog input", + "value": 7 + } + } + } + } + } + } + } + }, + "REFSEL": { + "description": "Reference select", + "offset": 1288, + "size": 32, + "reset_value": 4, + "reset_mask": 4294967295, + "children": { + "fields": { + "REFSEL": { + "description": "Reference select", + "offset": 0, + "size": 4, + "enum": { + "size": 4, + "children": { + "enum_fields": { + "Ref1_8Vdd": { + "description": "VDD * 1/8 selected as reference", + "value": 0 + }, + "Ref2_8Vdd": { + "description": "VDD * 2/8 selected as reference", + "value": 1 + }, + "Ref3_8Vdd": { + "description": "VDD * 3/8 selected as reference", + "value": 2 + }, + "Ref4_8Vdd": { + "description": "VDD * 4/8 selected as reference", + "value": 3 + }, + "Ref5_8Vdd": { + "description": "VDD * 5/8 selected as reference", + "value": 4 + }, + "Ref6_8Vdd": { + "description": "VDD * 6/8 selected as reference", + "value": 5 + }, + "Ref7_8Vdd": { + "description": "VDD * 7/8 selected as reference", + "value": 6 + }, + "ARef": { + "description": "External analog reference selected", + "value": 7 + }, + "Ref1_16Vdd": { + "description": "VDD * 1/16 selected as reference", + "value": 8 + }, + "Ref3_16Vdd": { + "description": "VDD * 3/16 selected as reference", + "value": 9 + }, + "Ref5_16Vdd": { + "description": "VDD * 5/16 selected as reference", + "value": 10 + }, + "Ref7_16Vdd": { + "description": "VDD * 7/16 selected as reference", + "value": 11 + }, + "Ref9_16Vdd": { + "description": "VDD * 9/16 selected as reference", + "value": 12 + }, + "Ref11_16Vdd": { + "description": "VDD * 11/16 selected as reference", + "value": 13 + }, + "Ref13_16Vdd": { + "description": "VDD * 13/16 selected as reference", + "value": 14 + }, + "Ref15_16Vdd": { + "description": "VDD * 15/16 selected as reference", + "value": 15 + } + } + } + } + } + } + } + }, + "EXTREFSEL": { + "description": "External reference select", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTREFSEL": { + "description": "External analog reference select", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "AnalogReference0": { + "description": "Use AIN0 as external analog reference", + "value": 0 + }, + "AnalogReference1": { + "description": "Use AIN1 as external analog reference", + "value": 1 + } + } + } + } + } + } + } + }, + "ANADETECT": { + "description": "Analog detect configuration", + "offset": 1312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ANADETECT": { + "description": "Analog detect configuration", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Cross": { + "description": "Generate ANADETECT on crossing, both upward crossing and downward crossing", + "value": 0 + }, + "Up": { + "description": "Generate ANADETECT on upward crossing only", + "value": 1 + }, + "Down": { + "description": "Generate ANADETECT on downward crossing only", + "value": 2 + } + } + } + } + } + } + } + }, + "HYST": { + "description": "Comparator hysteresis enable", + "offset": 1336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HYST": { + "description": "Comparator hysteresis enable", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Comparator hysteresis disabled", + "value": 0 + }, + "Enabled": { + "description": "Comparator hysteresis enabled", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "EGU0": { + "description": "Event Generator Unit 0", + "children": { + "registers": { + "TASKS_TRIGGER": { + "description": "Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event", + "offset": 0, + "size": 32, + "count": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TASKS_TRIGGER": { + "description": "Trigger n for triggering the corresponding TRIGGERED[n] event", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Trigger": { + "description": "Trigger task", + "value": 1 + } + } + } + } + } + } + } + }, + "EVENTS_TRIGGERED": { + "description": "Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task", + "offset": 256, + "size": 32, + "count": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVENTS_TRIGGERED": { + "description": "Event number n generated by triggering the corresponding TRIGGER[n] task", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NotGenerated": { + "description": "Event not generated", + "value": 0 + }, + "Generated": { + "description": "Event generated", + "value": 1 + } + } + } + } + } + } + } + }, + "INTEN": { + "description": "Enable or disable interrupt", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TRIGGERED0": { + "description": "Enable or disable interrupt for event TRIGGERED[0]", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + 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1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH9": { + "description": "Enable or disable channel 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH10": { + "description": "Enable or disable channel 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH11": { + "description": "Enable or disable channel 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH12": { + "description": "Enable or disable channel 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH13": { + "description": "Enable or disable channel 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH14": { + "description": "Enable or disable channel 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH15": { + "description": "Enable or disable channel 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH16": { + "description": "Enable or disable channel 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH17": { + "description": "Enable or disable channel 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH18": { + "description": "Enable or disable channel 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH19": { + "description": "Enable or disable channel 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH20": { + "description": "Enable or disable channel 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH21": { + "description": "Enable or disable channel 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH22": { + "description": "Enable or disable channel 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH23": { + "description": "Enable or disable channel 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH24": { + "description": "Enable or disable channel 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH25": { + "description": "Enable or disable channel 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH26": { + "description": "Enable or disable channel 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH27": { + "description": "Enable or disable channel 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH28": { + "description": "Enable or disable channel 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH29": { + "description": "Enable or disable channel 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH30": { + "description": "Enable or disable channel 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + }, + "CH31": { + "description": "Enable or disable channel 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable channel", + "value": 0 + }, + "Enabled": { + "description": "Enable channel", + "value": 1 + } + } + } + } + } + } + } + }, + "CHENSET": { + "description": "Channel enable set register", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH0": { + "description": "Channel 0 enable set register. Writing '0' has no effect", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH1": { + "description": "Channel 1 enable set register. Writing '0' has no effect", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH2": { + "description": "Channel 2 enable set register. Writing '0' has no effect", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH3": { + "description": "Channel 3 enable set register. Writing '0' has no effect", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH4": { + "description": "Channel 4 enable set register. Writing '0' has no effect", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH5": { + "description": "Channel 5 enable set register. Writing '0' has no effect", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH6": { + "description": "Channel 6 enable set register. Writing '0' has no effect", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH7": { + "description": "Channel 7 enable set register. Writing '0' has no effect", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH8": { + "description": "Channel 8 enable set register. Writing '0' has no effect", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH9": { + "description": "Channel 9 enable set register. Writing '0' has no effect", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH10": { + "description": "Channel 10 enable set register. Writing '0' has no effect", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH11": { + "description": "Channel 11 enable set register. Writing '0' has no effect", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH12": { + "description": "Channel 12 enable set register. Writing '0' has no effect", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH13": { + "description": "Channel 13 enable set register. Writing '0' has no effect", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH14": { + "description": "Channel 14 enable set register. Writing '0' has no effect", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH15": { + "description": "Channel 15 enable set register. Writing '0' has no effect", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH16": { + "description": "Channel 16 enable set register. Writing '0' has no effect", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH17": { + "description": "Channel 17 enable set register. Writing '0' has no effect", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH18": { + "description": "Channel 18 enable set register. Writing '0' has no effect", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH19": { + "description": "Channel 19 enable set register. Writing '0' has no effect", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH20": { + "description": "Channel 20 enable set register. Writing '0' has no effect", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH21": { + "description": "Channel 21 enable set register. Writing '0' has no effect", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH22": { + "description": "Channel 22 enable set register. Writing '0' has no effect", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH23": { + "description": "Channel 23 enable set register. Writing '0' has no effect", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH24": { + "description": "Channel 24 enable set register. Writing '0' has no effect", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH25": { + "description": "Channel 25 enable set register. Writing '0' has no effect", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH26": { + "description": "Channel 26 enable set register. Writing '0' has no effect", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH27": { + "description": "Channel 27 enable set register. Writing '0' has no effect", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH28": { + "description": "Channel 28 enable set register. Writing '0' has no effect", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH29": { + "description": "Channel 29 enable set register. Writing '0' has no effect", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH30": { + "description": "Channel 30 enable set register. Writing '0' has no effect", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH31": { + "description": "Channel 31 enable set register. Writing '0' has no effect", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "CHENCLR": { + "description": "Channel enable clear register", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH0": { + "description": "Channel 0 enable clear register. Writing '0' has no effect", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH1": { + "description": "Channel 1 enable clear register. Writing '0' has no effect", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH2": { + "description": "Channel 2 enable clear register. Writing '0' has no effect", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH3": { + "description": "Channel 3 enable clear register. Writing '0' has no effect", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH4": { + "description": "Channel 4 enable clear register. Writing '0' has no effect", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH5": { + "description": "Channel 5 enable clear register. Writing '0' has no effect", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH6": { + "description": "Channel 6 enable clear register. Writing '0' has no effect", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH7": { + "description": "Channel 7 enable clear register. Writing '0' has no effect", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH8": { + "description": "Channel 8 enable clear register. Writing '0' has no effect", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH9": { + "description": "Channel 9 enable clear register. Writing '0' has no effect", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH10": { + "description": "Channel 10 enable clear register. Writing '0' has no effect", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH11": { + "description": "Channel 11 enable clear register. Writing '0' has no effect", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH12": { + "description": "Channel 12 enable clear register. Writing '0' has no effect", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH13": { + "description": "Channel 13 enable clear register. Writing '0' has no effect", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH14": { + "description": "Channel 14 enable clear register. Writing '0' has no effect", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH15": { + "description": "Channel 15 enable clear register. Writing '0' has no effect", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH16": { + "description": "Channel 16 enable clear register. Writing '0' has no effect", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH17": { + "description": "Channel 17 enable clear register. Writing '0' has no effect", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH18": { + "description": "Channel 18 enable clear register. Writing '0' has no effect", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH19": { + "description": "Channel 19 enable clear register. Writing '0' has no effect", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH20": { + "description": "Channel 20 enable clear register. Writing '0' has no effect", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH21": { + "description": "Channel 21 enable clear register. Writing '0' has no effect", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH22": { + "description": "Channel 22 enable clear register. Writing '0' has no effect", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH23": { + "description": "Channel 23 enable clear register. Writing '0' has no effect", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH24": { + "description": "Channel 24 enable clear register. Writing '0' has no effect", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH25": { + "description": "Channel 25 enable clear register. Writing '0' has no effect", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH26": { + "description": "Channel 26 enable clear register. Writing '0' has no effect", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH27": { + "description": "Channel 27 enable clear register. Writing '0' has no effect", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH28": { + "description": "Channel 28 enable clear register. Writing '0' has no effect", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH29": { + "description": "Channel 29 enable clear register. Writing '0' has no effect", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH30": { + "description": "Channel 30 enable clear register. Writing '0' has no effect", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + }, + "CH31": { + "description": "Channel 31 enable clear register. Writing '0' has no effect", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Read: channel disabled", + "value": 0 + }, + "Enabled": { + "description": "Read: channel enabled", + "value": 1 + } + } + } + } + } + } + } + }, + "CHG": { + "description": "Description collection: Channel group n", + "offset": 2048, + "size": 32, + "count": 6, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH0": { + "description": "Include or exclude channel 0", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH1": { + "description": "Include or exclude channel 1", + "offset": 1, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH2": { + "description": "Include or exclude channel 2", + "offset": 2, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH3": { + "description": "Include or exclude channel 3", + "offset": 3, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH4": { + "description": "Include or exclude channel 4", + "offset": 4, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH5": { + "description": "Include or exclude channel 5", + "offset": 5, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH6": { + "description": "Include or exclude channel 6", + "offset": 6, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH7": { + "description": "Include or exclude channel 7", + "offset": 7, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH8": { + "description": "Include or exclude channel 8", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH9": { + "description": "Include or exclude channel 9", + "offset": 9, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH10": { + "description": "Include or exclude channel 10", + "offset": 10, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH11": { + "description": "Include or exclude channel 11", + "offset": 11, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH12": { + "description": "Include or exclude channel 12", + "offset": 12, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH13": { + "description": "Include or exclude channel 13", + "offset": 13, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH14": { + "description": "Include or exclude channel 14", + "offset": 14, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH15": { + "description": "Include or exclude channel 15", + "offset": 15, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH16": { + "description": "Include or exclude channel 16", + "offset": 16, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH17": { + "description": "Include or exclude channel 17", + "offset": 17, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH18": { + "description": "Include or exclude channel 18", + "offset": 18, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH19": { + "description": "Include or exclude channel 19", + "offset": 19, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH20": { + "description": "Include or exclude channel 20", + "offset": 20, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH21": { + "description": "Include or exclude channel 21", + "offset": 21, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH22": { + "description": "Include or exclude channel 22", + "offset": 22, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH23": { + "description": "Include or exclude channel 23", + "offset": 23, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH24": { + "description": "Include or exclude channel 24", + "offset": 24, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH25": { + "description": "Include or exclude channel 25", + "offset": 25, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH26": { + "description": "Include or exclude channel 26", + "offset": 26, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH27": { + "description": "Include or exclude channel 27", + "offset": 27, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH28": { + "description": "Include or exclude channel 28", + "offset": 28, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH29": { + "description": "Include or exclude channel 29", + "offset": 29, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH30": { + "description": "Include or exclude channel 30", + "offset": 30, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + }, + "CH31": { + "description": "Include or exclude channel 31", + "offset": 31, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Excluded": { + "description": "Exclude", + "value": 0 + }, + "Included": { + "description": "Include", + "value": 1 + } + } + } + } + } + } + } + } + } + } + }, + "NVMC": { + "description": "Non Volatile Memory Controller", + "children": { + "registers": { + "READY": { + "description": "Ready flag", + "offset": 1024, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "READY": { + "description": "NVMC is ready or busy", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Busy": { + "description": "NVMC is busy (on-going write or erase operation)", + "value": 0 + }, + "Ready": { + "description": "NVMC is ready", + "value": 1 + } + } + } + } + } + } + } + }, + "READYNEXT": { + "description": "Ready flag", + "offset": 1032, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "READYNEXT": { + "description": "NVMC can accept a new write operation", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Busy": { + "description": "NVMC cannot accept any write operation", + "value": 0 + }, + "Ready": { + "description": "NVMC is ready", + "value": 1 + } + } + } + } + } + } + } + }, + "CONFIG": { + "description": "Configuration register", + "offset": 1284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WEN": { + "description": "Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.", + "offset": 0, + "size": 2, + "enum": { + "size": 2, + "children": { + "enum_fields": { + "Ren": { + "description": "Read only access", + "value": 0 + }, + "Wen": { + "description": "Write enabled", + "value": 1 + }, + "Een": { + "description": "Erase enabled", + "value": 2 + } + } + } + } + } + } + } + }, + "ERASEPAGE": { + "description": "Register for erasing a page in code area", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ERASEPAGE": { + "description": "Register for starting erase of a page in code area", + "offset": 0, + "size": 32 + } + } + } + }, + "ERASEPCR1": { + "description": "Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE.", + "offset": 1288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ERASEPCR1": { + "description": "Register for erasing a page in code area. Equivalent to ERASEPAGE.", + "offset": 0, + "size": 32 + } + } + } + }, + "ERASEALL": { + "description": "Register for erasing all non-volatile user memory", + "offset": 1292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ERASEALL": { + "description": "Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoOperation": { + "description": "No operation", + "value": 0 + }, + "Erase": { + "description": "Start chip erase", + "value": 1 + } + } + } + } + } + } + } + }, + "ERASEPCR0": { + "description": "Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE.", + "offset": 1296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ERASEPCR0": { + "description": "Register for starting erase of a page in code area. Equivalent to ERASEPAGE.", + "offset": 0, + "size": 32 + } + } + } + }, + "ERASEUICR": { + "description": "Register for erasing user information configuration registers", + "offset": 1300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ERASEUICR": { + "description": "Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "NoOperation": { + "description": "No operation", + "value": 0 + }, + "Erase": { + "description": "Start erase of UICR", + "value": 1 + } + } + } + } + } + } + } + }, + "ERASEPAGEPARTIAL": { + "description": "Register for partial erase of a page in code area", + "offset": 1304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ERASEPAGEPARTIAL": { + "description": "Register for starting partial erase of a page in code area", + "offset": 0, + "size": 32 + } + } + } + }, + "ERASEPAGEPARTIALCFG": { + "description": "Register for partial erase configuration", + "offset": 1308, + "size": 32, + "reset_value": 10, + "reset_mask": 4294967295, + "children": { + "fields": { + "DURATION": { + "description": "Duration of the partial erase in milliseconds", + "offset": 0, + "size": 7 + } + } + } + }, + "ICACHECNF": { + "description": "I-code cache configuration register.", + "offset": 1344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CACHEEN": { + "description": "Cache enable", + "offset": 0, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable cache. Invalidates all cache entries.", + "value": 0 + }, + "Enabled": { + "description": "Enable cache", + "value": 1 + } + } + } + } + }, + "CACHEPROFEN": { + "description": "Cache profiling enable", + "offset": 8, + "size": 1, + "enum": { + "size": 1, + "children": { + "enum_fields": { + "Disabled": { + "description": "Disable cache profiling", + "value": 0 + }, + "Enabled": { + "description": "Enable cache profiling", + "value": 1 + } + } + } + } + } + } + } + }, + "IHIT": { + "description": "I-code cache hit counter.", + "offset": 1352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HITS": { + "description": "Number of cache hits", + "offset": 0, + "size": 32 + } + } + } + }, + "IMISS": { + "description": "I-code cache miss counter.", + "offset": 1356, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MISSES": { + "description": "Number of cache misses", + "offset": 0, + "size": 32 + } + } + } + } + } + } + } + } + }, + "devices": { + "nrf52840": { + "arch": "cortex_m4", + "description": "nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller ", + "properties": { + "cpu.nvic_prio_bits": "3", + "cpu.mpu": "1", + "cpu.fpu": "1", + "cpu.revision": "r0p1", + "cpu.vendor_systick_config": "0", + "license": "\nCopyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\\n\n\\n\nRedistribution and use in source and binary forms, with or without\\n\nmodification, are permitted provided that the following conditions are met:\\n\n\\n\n1. Redistributions of source code must retain the above copyright notice, this\\n\n list of conditions and the following disclaimer.\\n\n\\n\n2. Redistributions in binary form must reproduce the above copyright\\n\n notice, this list of conditions and the following disclaimer in the\\n\n documentation and/or other materials provided with the distribution.\\n\n\\n\n3. Neither the name of Nordic Semiconductor ASA nor the names of its\\n\n contributors may be used to endorse or promote products derived from this\\n\n software without specific prior written permission.\\n\n\\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\\n\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\\n\nIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\\n\nARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\\n\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\\n\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\\n\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\\n\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\\n\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\\n\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\\n\nPOSSIBILITY OF SUCH DAMAGE.\\n\n ", + "cpu.name": "CM4", + "cpu.endian": "little" + }, + "children": { + "interrupts": { + "MemManageFault": { + "index": -12 + }, + "BusFault": { + "index": -11 + }, + "UsageFault": { + "index": -10 + }, + "DebugMonitor": { + "index": -4 + }, + "NMI": { + "index": -14 + }, + "HardFault": { + "index": -13 + }, + "SVCall": { + "index": -5 + }, + "PendSV": { + "index": -2 + }, + "SysTick": { + "index": -1 + }, + "POWER_CLOCK": { + "index": 0 + }, + "RADIO": { + "index": 1 + }, + "UARTE0_UART0": { + "index": 2 + }, + "SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0": { + "index": 3 + }, + "SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1": { + "index": 4 + }, + "NFCT": { + "index": 5 + }, + "GPIOTE": { + "index": 6 + }, + "SAADC": { + "index": 7 + }, + "TIMER0": { + "index": 8 + }, + "TIMER1": { + "index": 9 + }, + "TIMER2": { + "index": 10 + }, + "RTC0": { + "index": 11 + }, + "TEMP": { + "index": 12 + }, + "RNG": { + "index": 13 + }, + "ECB": { + "index": 14 + }, + "CCM_AAR": { + "index": 15 + }, + "WDT": { + "index": 16 + }, + "RTC1": { + "index": 17 + }, + "QDEC": { + "index": 18 + }, + "COMP_LPCOMP": { + "index": 19 + }, + "SWI0_EGU0": { + "index": 20 + }, + "SWI1_EGU1": { + "index": 21 + }, + "SWI2_EGU2": { + "index": 22 + }, + "SWI3_EGU3": { + "index": 23 + }, + "SWI4_EGU4": { + "index": 24 + }, + "SWI5_EGU5": { + "index": 25 + }, + "TIMER3": { + "index": 26 + }, + "TIMER4": { + "index": 27 + }, + "PWM0": { + "index": 28 + }, + "PDM": { + "index": 29 + }, + "MWU": { + "index": 32 + }, + "PWM1": { + "index": 33 + }, + "PWM2": { + "index": 34 + }, + "SPIM2_SPIS2_SPI2": { + "index": 35 + }, + "RTC2": { + "index": 36 + }, + "I2S": { + "index": 37 + }, + "FPU": { + "index": 38 + }, + "USBD": { + "index": 39 + }, + "UARTE1": { + "index": 40 + }, + "QSPI": { + "index": 41 + }, + "CRYPTOCELL": { + "index": 42 + }, + "PWM3": { + "index": 45 + }, + "SPIM3": { + "index": 47 + } + }, + "peripheral_instances": { + "SysTick": { + "offset": 3758153744, + "type": "types.peripherals.SCS.children.register_groups.SysTick" + }, + "FICR": { + "description": "Factory information configuration registers", + "offset": 268435456, + "type": "types.peripherals.FICR" + }, + "UICR": { + "description": "User information configuration registers", + "offset": 268439552, + "type": "types.peripherals.UICR" + }, + "CLOCK": { + "description": "Clock control", + "offset": 1073741824, + "type": "types.peripherals.CLOCK" + }, + "POWER": { + "description": "Power control", + "offset": 1073741824, + "type": "types.peripherals.POWER" + }, + "P0": { + "description": "GPIO Port 1", + "offset": 1342177280, + "type": "types.peripherals.P0" + }, + "P1": { + "description": "GPIO Port 2", + "offset": 1342178048, + "type": "types.peripherals.P0" + }, + "RADIO": { + "description": "2.4 GHz radio", + "offset": 1073745920, + "type": "types.peripherals.RADIO" + }, + "UART0": { + "description": "Universal Asynchronous Receiver/Transmitter", + "offset": 1073750016, + "type": "types.peripherals.UART0" + }, + "UARTE0": { + "description": "UART with EasyDMA 0", + "offset": 1073750016, + "type": "types.peripherals.UARTE0" + }, + "SPI0": { + "description": "Serial Peripheral Interface 0", + "offset": 1073754112, + "type": "types.peripherals.SPI0" + }, + "SPIM0": { + "description": "Serial Peripheral Interface Master with EasyDMA 0", + "offset": 1073754112, + "type": "types.peripherals.SPIM0" + }, + "SPIS0": { + "description": "SPI Slave 0", + "offset": 1073754112, + "type": "types.peripherals.SPIS0" + }, + "TWI0": { + "description": "I2C compatible Two-Wire Interface 0", + "offset": 1073754112, + "type": "types.peripherals.TWI0" + }, + "TWIM0": { + "description": "I2C compatible Two-Wire Master Interface with EasyDMA 0", + "offset": 1073754112, + "type": "types.peripherals.TWIM0" + }, + "TWIS0": { + "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 0", + "offset": 1073754112, + "type": "types.peripherals.TWIS0" + }, + "SPI1": { + "description": "Serial Peripheral Interface 1", + "offset": 1073758208, + "type": "types.peripherals.SPI0" + }, + "SPIM1": { + "description": "Serial Peripheral Interface Master with EasyDMA 1", + "offset": 1073758208, + "type": "types.peripherals.SPIM0" + }, + "SPIS1": { + "description": "SPI Slave 1", + "offset": 1073758208, + "type": "types.peripherals.SPIS0" + }, + "TWI1": { + "description": "I2C compatible Two-Wire Interface 1", + "offset": 1073758208, + "type": "types.peripherals.TWI0" + }, + "TWIM1": { + "description": "I2C compatible Two-Wire Master Interface with EasyDMA 1", + "offset": 1073758208, + "type": "types.peripherals.TWIM0" + }, + "TWIS1": { + "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 1", + "offset": 1073758208, + "type": "types.peripherals.TWIS0" + }, + "NFCT": { + "description": "NFC-A compatible radio", + "offset": 1073762304, + "type": "types.peripherals.NFCT" + }, + "GPIOTE": { + "description": "GPIO Tasks and Events", + "offset": 1073766400, + "type": "types.peripherals.GPIOTE" + }, + "SAADC": { + "description": "Successive approximation register (SAR) analog-to-digital converter", + "offset": 1073770496, + "type": "types.peripherals.SAADC" + }, + "TIMER0": { + "description": "Timer/Counter 0", + "offset": 1073774592, + "type": "types.peripherals.TIMER0" + }, + "TIMER1": { + "description": "Timer/Counter 1", + "offset": 1073778688, + "type": "types.peripherals.TIMER0" + }, + "TIMER2": { + "description": "Timer/Counter 2", + "offset": 1073782784, + "type": "types.peripherals.TIMER0" + }, + "RTC0": { + "description": "Real time counter 0", + "offset": 1073786880, + "type": "types.peripherals.RTC0" + }, + "TEMP": { + "description": "Temperature Sensor", + "offset": 1073790976, + "type": "types.peripherals.TEMP" + }, + "RNG": { + "description": "Random Number Generator", + "offset": 1073795072, + "type": "types.peripherals.RNG" + }, + "ECB": { + "description": "AES ECB Mode Encryption", + "offset": 1073799168, + "type": "types.peripherals.ECB" + }, + "AAR": { + "description": "Accelerated Address Resolver", + "offset": 1073803264, + "type": "types.peripherals.AAR" + }, + "CCM": { + "description": "AES CCM Mode Encryption", + "offset": 1073803264, + "type": "types.peripherals.CCM" + }, + "WDT": { + "description": "Watchdog Timer", + "offset": 1073807360, + "type": "types.peripherals.WDT" + }, + "RTC1": { + "description": "Real time counter 1", + "offset": 1073811456, + "type": "types.peripherals.RTC0" + }, + "QDEC": { + "description": "Quadrature Decoder", + "offset": 1073815552, + "type": "types.peripherals.QDEC" + }, + "COMP": { + "description": "Comparator", + "offset": 1073819648, + "type": "types.peripherals.COMP" + }, + "LPCOMP": { + "description": "Low Power Comparator", + "offset": 1073819648, + "type": "types.peripherals.LPCOMP" + }, + "EGU0": { + "description": "Event Generator Unit 0", + "offset": 1073823744, + "type": "types.peripherals.EGU0" + }, + "SWI0": { + "description": "Software interrupt 0", + "offset": 1073823744, + "type": "types.peripherals.SWI0" + }, + "EGU1": { + "description": "Event Generator Unit 1", + "offset": 1073827840, + "type": "types.peripherals.EGU0" + }, + "SWI1": { + "description": "Software interrupt 1", + "offset": 1073827840, + "type": "types.peripherals.SWI0" + }, + "EGU2": { + "description": "Event Generator Unit 2", + "offset": 1073831936, + "type": "types.peripherals.EGU0" + }, + "SWI2": { + "description": "Software interrupt 2", + "offset": 1073831936, + "type": "types.peripherals.SWI0" + }, + "EGU3": { + "description": "Event Generator Unit 3", + "offset": 1073836032, + "type": "types.peripherals.EGU0" + }, + "SWI3": { + "description": "Software interrupt 3", + "offset": 1073836032, + "type": "types.peripherals.SWI0" + }, + "EGU4": { + "description": "Event Generator Unit 4", + "offset": 1073840128, + "type": "types.peripherals.EGU0" + }, + "SWI4": { + "description": "Software interrupt 4", + "offset": 1073840128, + "type": "types.peripherals.SWI0" + }, + "EGU5": { + "description": "Event Generator Unit 5", + "offset": 1073844224, + "type": "types.peripherals.EGU0" + }, + "SWI5": { + "description": "Software interrupt 5", + "offset": 1073844224, + "type": "types.peripherals.SWI0" + }, + "TIMER3": { + "description": "Timer/Counter 3", + "offset": 1073848320, + "type": "types.peripherals.TIMER0" + }, + "TIMER4": { + "description": "Timer/Counter 4", + "offset": 1073852416, + "type": "types.peripherals.TIMER0" + }, + "PWM0": { + "description": "Pulse width modulation unit 0", + "offset": 1073856512, + "type": "types.peripherals.PWM0" + }, + "PDM": { + "description": "Pulse Density Modulation (Digital Microphone) Interface", + "offset": 1073860608, + "type": "types.peripherals.PDM" + }, + "ACL": { + "description": "Access control lists", + "offset": 1073864704, + "type": "types.peripherals.ACL" + }, + "NVMC": { + "description": "Non Volatile Memory Controller", + "offset": 1073864704, + "type": "types.peripherals.NVMC" + }, + "PPI": { + "description": "Programmable Peripheral Interconnect", + "offset": 1073868800, + "type": "types.peripherals.PPI" + }, + "MWU": { + "description": "Memory Watch Unit", + "offset": 1073872896, + "type": "types.peripherals.MWU" + }, + "PWM1": { + "description": "Pulse width modulation unit 1", + "offset": 1073876992, + "type": "types.peripherals.PWM0" + }, + "PWM2": { + "description": "Pulse width modulation unit 2", + "offset": 1073881088, + "type": "types.peripherals.PWM0" + }, + "SPI2": { + "description": "Serial Peripheral Interface 2", + "offset": 1073885184, + "type": "types.peripherals.SPI0" + }, + "SPIM2": { + "description": "Serial Peripheral Interface Master with EasyDMA 2", + "offset": 1073885184, + "type": "types.peripherals.SPIM0" + }, + "SPIS2": { + "description": "SPI Slave 2", + "offset": 1073885184, + "type": "types.peripherals.SPIS0" + }, + "RTC2": { + "description": "Real time counter 2", + "offset": 1073889280, + "type": "types.peripherals.RTC0" + }, + "I2S": { + "description": "Inter-IC Sound", + "offset": 1073893376, + "type": "types.peripherals.I2S" + }, + "FPU": { + "description": "FPU", + "offset": 1073897472, + "type": "types.peripherals.FPU" + }, + "USBD": { + "description": "Universal serial bus device", + "offset": 1073901568, + "type": "types.peripherals.USBD" + }, + "UARTE1": { + "description": "UART with EasyDMA 1", + "offset": 1073905664, + "type": "types.peripherals.UARTE0" + }, + "QSPI": { + "description": "External flash interface", + "offset": 1073909760, + "type": "types.peripherals.QSPI" + }, + "CC_HOST_RGF": { + "description": "CRYPTOCELL HOST_RGF interface", + "offset": 1342349312, + "type": "types.peripherals.CC_HOST_RGF" + }, + "CRYPTOCELL": { + "description": "ARM TrustZone CryptoCell register interface", + "offset": 1342349312, + "type": "types.peripherals.CRYPTOCELL" + }, + "PWM3": { + "description": "Pulse width modulation unit 3", + "offset": 1073926144, + "type": "types.peripherals.PWM0" + }, + "SPIM3": { + "description": "Serial Peripheral Interface Master with EasyDMA 3", + "offset": 1073934336, + "type": "types.peripherals.SPIM0" + } + } + } + } + } +} \ No newline at end of file diff --git a/src/chips/nrf52840.zig b/src/chips/nrf52840.zig new file mode 100644 index 0000000..8c1ffa2 --- /dev/null +++ b/src/chips/nrf52840.zig @@ -0,0 +1,21782 @@ +const micro = @import("microzig"); +const mmio = micro.mmio; + +pub const devices = struct { + /// nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + pub const nrf52840 = struct { + pub const properties = struct { + pub const @"cpu.nvic_prio_bits" = "3"; + pub const @"cpu.mpu" = "1"; + pub const @"cpu.fpu" = "1"; + pub const @"cpu.revision" = "r0p1"; + pub const @"cpu.vendor_systick_config" = "0"; + pub const license = + \\ + \\Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n + \\\n + \\Redistribution and use in source and binary forms, with or without\n + \\modification, are permitted provided that the following conditions are met:\n + \\\n + \\1. Redistributions of source code must retain the above copyright notice, this\n + \\ list of conditions and the following disclaimer.\n + \\\n + \\2. Redistributions in binary form must reproduce the above copyright\n + \\ notice, this list of conditions and the following disclaimer in the\n + \\ documentation and/or other materials provided with the distribution.\n + \\\n + \\3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + \\ contributors may be used to endorse or promote products derived from this\n + \\ software without specific prior written permission.\n + \\\n + \\THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n + \\AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n + \\IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n + \\ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n + \\LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n + \\CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n + \\SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n + \\INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n + \\CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n + \\ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n + \\POSSIBILITY OF SUCH DAMAGE.\n + \\ + ; + pub const @"cpu.name" = "CM4"; + pub const @"cpu.endian" = "little"; + }; + + pub const VectorTable = extern struct { + const Handler = micro.interrupt.Handler; + const unhandled = micro.interrupt.unhandled; + + initial_stack_pointer: u32, + Reset: Handler = unhandled, + NMI: Handler = unhandled, + HardFault: Handler = unhandled, + MemManageFault: Handler = unhandled, + BusFault: Handler = unhandled, + UsageFault: Handler = unhandled, + reserved5: [4]u32 = undefined, + SVCall: Handler = unhandled, + DebugMonitor: Handler = unhandled, + reserved11: [1]u32 = undefined, + PendSV: Handler = unhandled, + SysTick: Handler = unhandled, + POWER_CLOCK: Handler = unhandled, + RADIO: Handler = unhandled, + UARTE0_UART0: Handler = unhandled, + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: Handler = unhandled, + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: Handler = unhandled, + NFCT: Handler = unhandled, + GPIOTE: Handler = unhandled, + SAADC: Handler = unhandled, + TIMER0: Handler = unhandled, + TIMER1: Handler = unhandled, + TIMER2: Handler = unhandled, + RTC0: Handler = unhandled, + TEMP: Handler = unhandled, + RNG: Handler = unhandled, + ECB: Handler = unhandled, + CCM_AAR: Handler = unhandled, + WDT: Handler = unhandled, + RTC1: Handler = unhandled, + QDEC: Handler = unhandled, + COMP_LPCOMP: Handler = unhandled, + SWI0_EGU0: Handler = unhandled, + SWI1_EGU1: Handler = unhandled, + SWI2_EGU2: Handler = unhandled, + SWI3_EGU3: Handler = unhandled, + SWI4_EGU4: Handler = unhandled, + SWI5_EGU5: Handler = unhandled, + TIMER3: Handler = unhandled, + TIMER4: Handler = unhandled, + PWM0: Handler = unhandled, + PDM: Handler = unhandled, + reserved44: [2]u32 = undefined, + MWU: Handler = unhandled, + PWM1: Handler = unhandled, + PWM2: Handler = unhandled, + SPIM2_SPIS2_SPI2: Handler = unhandled, + RTC2: Handler = unhandled, + I2S: Handler = unhandled, + FPU: Handler = unhandled, + USBD: Handler = unhandled, + UARTE1: Handler = unhandled, + QSPI: Handler = unhandled, + CRYPTOCELL: Handler = unhandled, + reserved57: [2]u32 = undefined, + PWM3: Handler = unhandled, + reserved60: [1]u32 = undefined, + SPIM3: Handler = unhandled, + }; + + pub const peripherals = struct { + /// Factory information configuration registers + pub const FICR = @intToPtr(*volatile types.peripherals.FICR, 0x10000000); + /// User information configuration registers + pub const UICR = @intToPtr(*volatile types.peripherals.UICR, 0x10001000); + /// Clock control + pub const CLOCK = @intToPtr(*volatile types.peripherals.CLOCK, 0x40000000); + /// Power control + pub const POWER = @intToPtr(*volatile types.peripherals.POWER, 0x40000000); + /// 2.4 GHz radio + pub const RADIO = @intToPtr(*volatile types.peripherals.RADIO, 0x40001000); + /// Universal Asynchronous Receiver/Transmitter + pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x40002000); + /// UART with EasyDMA 0 + pub const UARTE0 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40002000); + /// Serial Peripheral Interface 0 + pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003000); + /// Serial Peripheral Interface Master with EasyDMA 0 + pub const SPIM0 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40003000); + /// SPI Slave 0 + pub const SPIS0 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40003000); + /// I2C compatible Two-Wire Interface 0 + pub const TWI0 = @intToPtr(*volatile types.peripherals.TWI0, 0x40003000); + /// I2C compatible Two-Wire Master Interface with EasyDMA 0 + pub const TWIM0 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40003000); + /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 + pub const TWIS0 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40003000); + /// Serial Peripheral Interface 1 + pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40004000); + /// Serial Peripheral Interface Master with EasyDMA 1 + pub const SPIM1 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40004000); + /// SPI Slave 1 + pub const SPIS1 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40004000); + /// I2C compatible Two-Wire Interface 1 + pub const TWI1 = @intToPtr(*volatile types.peripherals.TWI0, 0x40004000); + /// I2C compatible Two-Wire Master Interface with EasyDMA 1 + pub const TWIM1 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40004000); + /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 + pub const TWIS1 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40004000); + /// NFC-A compatible radio + pub const NFCT = @intToPtr(*volatile types.peripherals.NFCT, 0x40005000); + /// GPIO Tasks and Events + pub const GPIOTE = @intToPtr(*volatile types.peripherals.GPIOTE, 0x40006000); + /// Successive approximation register (SAR) analog-to-digital converter + pub const SAADC = @intToPtr(*volatile types.peripherals.SAADC, 0x40007000); + /// Timer/Counter 0 + pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40008000); + /// Timer/Counter 1 + pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40009000); + /// Timer/Counter 2 + pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4000a000); + /// Real time counter 0 + pub const RTC0 = @intToPtr(*volatile types.peripherals.RTC0, 0x4000b000); + /// Temperature Sensor + pub const TEMP = @intToPtr(*volatile types.peripherals.TEMP, 0x4000c000); + /// Random Number Generator + pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x4000d000); + /// AES ECB Mode Encryption + pub const ECB = @intToPtr(*volatile types.peripherals.ECB, 0x4000e000); + /// Accelerated Address Resolver + pub const AAR = @intToPtr(*volatile types.peripherals.AAR, 0x4000f000); + /// AES CCM Mode Encryption + pub const CCM = @intToPtr(*volatile types.peripherals.CCM, 0x4000f000); + /// Watchdog Timer + pub const WDT = @intToPtr(*volatile types.peripherals.WDT, 0x40010000); + /// Real time counter 1 + pub const RTC1 = @intToPtr(*volatile types.peripherals.RTC0, 0x40011000); + /// Quadrature Decoder + pub const QDEC = @intToPtr(*volatile types.peripherals.QDEC, 0x40012000); + /// Comparator + pub const COMP = @intToPtr(*volatile types.peripherals.COMP, 0x40013000); + /// Low Power Comparator + pub const LPCOMP = @intToPtr(*volatile types.peripherals.LPCOMP, 0x40013000); + /// Event Generator Unit 0 + pub const EGU0 = @intToPtr(*volatile types.peripherals.EGU0, 0x40014000); + /// Software interrupt 0 + pub const SWI0 = @intToPtr(*volatile types.peripherals.SWI0, 0x40014000); + /// Event Generator Unit 1 + pub const EGU1 = @intToPtr(*volatile types.peripherals.EGU0, 0x40015000); + /// Software interrupt 1 + pub const SWI1 = @intToPtr(*volatile types.peripherals.SWI0, 0x40015000); + /// Event Generator Unit 2 + pub const EGU2 = @intToPtr(*volatile types.peripherals.EGU0, 0x40016000); + /// Software interrupt 2 + pub const SWI2 = @intToPtr(*volatile types.peripherals.SWI0, 0x40016000); + /// Event Generator Unit 3 + pub const EGU3 = @intToPtr(*volatile types.peripherals.EGU0, 0x40017000); + /// Software interrupt 3 + pub const SWI3 = @intToPtr(*volatile types.peripherals.SWI0, 0x40017000); + /// Event Generator Unit 4 + pub const EGU4 = @intToPtr(*volatile types.peripherals.EGU0, 0x40018000); + /// Software interrupt 4 + pub const SWI4 = @intToPtr(*volatile types.peripherals.SWI0, 0x40018000); + /// Event Generator Unit 5 + pub const EGU5 = @intToPtr(*volatile types.peripherals.EGU0, 0x40019000); + /// Software interrupt 5 + pub const SWI5 = @intToPtr(*volatile types.peripherals.SWI0, 0x40019000); + /// Timer/Counter 3 + pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001a000); + /// Timer/Counter 4 + pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001b000); + /// Pulse width modulation unit 0 + pub const PWM0 = @intToPtr(*volatile types.peripherals.PWM0, 0x4001c000); + /// Pulse Density Modulation (Digital Microphone) Interface + pub const PDM = @intToPtr(*volatile types.peripherals.PDM, 0x4001d000); + /// Access control lists + pub const ACL = @intToPtr(*volatile types.peripherals.ACL, 0x4001e000); + /// Non Volatile Memory Controller + pub const NVMC = @intToPtr(*volatile types.peripherals.NVMC, 0x4001e000); + /// Programmable Peripheral Interconnect + pub const PPI = @intToPtr(*volatile types.peripherals.PPI, 0x4001f000); + /// Memory Watch Unit + pub const MWU = @intToPtr(*volatile types.peripherals.MWU, 0x40020000); + /// Pulse width modulation unit 1 + pub const PWM1 = @intToPtr(*volatile types.peripherals.PWM0, 0x40021000); + /// Pulse width modulation unit 2 + pub const PWM2 = @intToPtr(*volatile types.peripherals.PWM0, 0x40022000); + /// Serial Peripheral Interface 2 + pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40023000); + /// Serial Peripheral Interface Master with EasyDMA 2 + pub const SPIM2 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40023000); + /// SPI Slave 2 + pub const SPIS2 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40023000); + /// Real time counter 2 + pub const RTC2 = @intToPtr(*volatile types.peripherals.RTC0, 0x40024000); + /// Inter-IC Sound + pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x40025000); + /// FPU + pub const FPU = @intToPtr(*volatile types.peripherals.FPU, 0x40026000); + /// Universal serial bus device + pub const USBD = @intToPtr(*volatile types.peripherals.USBD, 0x40027000); + /// UART with EasyDMA 1 + pub const UARTE1 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40028000); + /// External flash interface + pub const QSPI = @intToPtr(*volatile types.peripherals.QSPI, 0x40029000); + /// Pulse width modulation unit 3 + pub const PWM3 = @intToPtr(*volatile types.peripherals.PWM0, 0x4002d000); + /// Serial Peripheral Interface Master with EasyDMA 3 + pub const SPIM3 = @intToPtr(*volatile types.peripherals.SPIM0, 0x4002f000); + /// GPIO Port 1 + pub const P0 = @intToPtr(*volatile types.peripherals.P0, 0x50000000); + /// GPIO Port 2 + pub const P1 = @intToPtr(*volatile types.peripherals.P0, 0x50000300); + /// CRYPTOCELL HOST_RGF interface + pub const CC_HOST_RGF = @intToPtr(*volatile types.peripherals.CC_HOST_RGF, 0x5002a000); + /// ARM TrustZone CryptoCell register interface + pub const CRYPTOCELL = @intToPtr(*volatile types.peripherals.CRYPTOCELL, 0x5002a000); + /// System Tick Timer + pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010); + }; + }; +}; + +pub const types = struct { + pub const peripherals = struct { + /// System Control Space + pub const SCS = struct { + /// System Tick Timer + pub const SysTick = extern struct { + /// SysTick Control and Status Register + CTRL: mmio.Mmio(packed struct(u32) { + ENABLE: u1, + TICKINT: u1, + CLKSOURCE: u1, + reserved16: u13, + COUNTFLAG: u1, + padding: u15, + }), + /// SysTick Reload Value Register + LOAD: mmio.Mmio(packed struct(u32) { + RELOAD: u24, + padding: u8, + }), + /// SysTick Current Value Register + VAL: mmio.Mmio(packed struct(u32) { + CURRENT: u24, + padding: u8, + }), + /// SysTick Calibration Register + CALIB: mmio.Mmio(packed struct(u32) { + TENMS: u24, + reserved30: u6, + SKEW: u1, + NOREF: u1, + }), + }; + }; + + /// Factory information configuration registers + pub const FICR = extern struct { + reserved16: [16]u8, + /// Code memory page size + CODEPAGESIZE: mmio.Mmio(packed struct(u32) { + /// Code memory page size + CODEPAGESIZE: u32, + }), + /// Code memory size + CODESIZE: mmio.Mmio(packed struct(u32) { + /// Code memory size in number of pages + CODESIZE: u32, + }), + reserved96: [72]u8, + /// Description collection: Device identifier + DEVICEID: [2]mmio.Mmio(packed struct(u32) { + /// 64 bit unique device identifier + DEVICEID: u32, + }), + reserved128: [24]u8, + /// Description collection: Encryption root, word n + ER: [4]mmio.Mmio(packed struct(u32) { + /// Encryption root, word n + ER: u32, + }), + /// Description collection: Identity Root, word n + IR: [4]mmio.Mmio(packed struct(u32) { + /// Identity Root, word n + IR: u32, + }), + /// Device address type + DEVICEADDRTYPE: mmio.Mmio(packed struct(u32) { + /// Device address type + DEVICEADDRTYPE: packed union { + raw: u1, + value: enum(u1) { + /// Public address + Public = 0x0, + /// Random address + Random = 0x1, + }, + }, + padding: u31, + }), + /// Description collection: Device address n + DEVICEADDR: [2]mmio.Mmio(packed struct(u32) { + /// 48 bit device address + DEVICEADDR: u32, + }), + reserved848: [676]u8, + /// Description collection: Production test signature n + PRODTEST: [3]mmio.Mmio(packed struct(u32) { + /// Production test signature n + PRODTEST: packed union { + raw: u32, + value: enum(u32) { + /// Production tests done + Done = 0xbb42319f, + /// Production tests not done + NotDone = 0xffffffff, + _, + }, + }, + }), + }; + + /// User information configuration registers + pub const UICR = extern struct { + reserved20: [20]u8, + /// Description collection: Reserved for Nordic firmware design + NRFFW: [13]mmio.Mmio(packed struct(u32) { + /// Reserved for Nordic firmware design + NRFFW: u32, + }), + reserved80: [8]u8, + /// Description collection: Reserved for Nordic hardware design + NRFHW: [12]mmio.Mmio(packed struct(u32) { + /// Reserved for Nordic hardware design + NRFHW: u32, + }), + /// Description collection: Reserved for customer + CUSTOMER: [32]mmio.Mmio(packed struct(u32) { + /// Reserved for customer + CUSTOMER: u32, + }), + reserved512: [256]u8, + /// Description collection: Mapping of the nRESET function (see POWER chapter for details) + PSELRESET: [2]mmio.Mmio(packed struct(u32) { + /// GPIO pin number onto which nRESET is exposed + PIN: u5, + /// Port number onto which nRESET is exposed + PORT: u1, + reserved31: u25, + /// Connection + CONNECT: packed union { + raw: u1, + value: enum(u1) { + /// Disconnect + Disconnected = 0x1, + /// Connect + Connected = 0x0, + }, + }, + }), + /// Access port protection + APPROTECT: mmio.Mmio(packed struct(u32) { + /// Enable or disable access port protection. + PALL: packed union { + raw: u8, + value: enum(u8) { + /// Disable + Disabled = 0xff, + /// Enable + Enabled = 0x0, + _, + }, + }, + padding: u24, + }), + /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + NFCPINS: mmio.Mmio(packed struct(u32) { + /// Setting of pins dedicated to NFC functionality + PROTECT: packed union { + raw: u1, + value: enum(u1) { + /// Operation as GPIO pins. Same protection as normal GPIO pins + Disabled = 0x0, + /// Operation as NFC antenna pins. Configures the protection for NFC operation + NFC = 0x1, + }, + }, + padding: u31, + }), + /// Processor debug control + DEBUGCTRL: mmio.Mmio(packed struct(u32) { + /// Configure CPU non-intrusive debug features + CPUNIDEN: packed union { + raw: u8, + value: enum(u8) { + /// Enable CPU ITM and ETM functionality (default behavior) + Enabled = 0xff, + /// Disable CPU ITM and ETM functionality + Disabled = 0x0, + _, + }, + }, + /// Configure CPU flash patch and breakpoint (FPB) unit behavior + CPUFPBEN: packed union { + raw: u8, + value: enum(u8) { + /// Enable CPU FPB unit (default behavior) + Enabled = 0xff, + /// Disable CPU FPB unit. Writes into the FPB registers will be ignored. + Disabled = 0x0, + _, + }, + }, + padding: u16, + }), + reserved772: [240]u8, + /// GPIO reference voltage / external output supply voltage in high voltage mode + REGOUT0: mmio.Mmio(packed struct(u32) { + /// Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. + VOUT: packed union { + raw: u3, + value: enum(u3) { + /// 1.8 V + @"1V8" = 0x0, + /// 2.1 V + @"2V1" = 0x1, + /// 2.4 V + @"2V4" = 0x2, + /// 2.7 V + @"2V7" = 0x3, + /// 3.0 V + @"3V0" = 0x4, + /// 3.3 V + @"3V3" = 0x5, + /// Default voltage: 1.8 V + DEFAULT = 0x7, + _, + }, + }, + padding: u29, + }), + }; + + /// Clock control + pub const CLOCK = extern struct { + /// Start HFXO crystal oscillator + TASKS_HFCLKSTART: mmio.Mmio(packed struct(u32) { + /// Start HFXO crystal oscillator + TASKS_HFCLKSTART: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop HFXO crystal oscillator + TASKS_HFCLKSTOP: mmio.Mmio(packed struct(u32) { + /// Stop HFXO crystal oscillator + TASKS_HFCLKSTOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start LFCLK + TASKS_LFCLKSTART: mmio.Mmio(packed struct(u32) { + /// Start LFCLK + TASKS_LFCLKSTART: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop LFCLK + TASKS_LFCLKSTOP: mmio.Mmio(packed struct(u32) { + /// Stop LFCLK + TASKS_LFCLKSTOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start calibration of LFRC + TASKS_CAL: mmio.Mmio(packed struct(u32) { + /// Start calibration of LFRC + TASKS_CAL: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start calibration timer + TASKS_CTSTART: mmio.Mmio(packed struct(u32) { + /// Start calibration timer + TASKS_CTSTART: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop calibration timer + TASKS_CTSTOP: mmio.Mmio(packed struct(u32) { + /// Stop calibration timer + TASKS_CTSTOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [228]u8, + /// HFXO crystal oscillator started + EVENTS_HFCLKSTARTED: mmio.Mmio(packed struct(u32) { + /// HFXO crystal oscillator started + EVENTS_HFCLKSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// LFCLK started + EVENTS_LFCLKSTARTED: mmio.Mmio(packed struct(u32) { + /// LFCLK started + EVENTS_LFCLKSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved268: [4]u8, + /// Calibration of LFRC completed + EVENTS_DONE: mmio.Mmio(packed struct(u32) { + /// Calibration of LFRC completed + EVENTS_DONE: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Calibration timer timeout + EVENTS_CTTO: mmio.Mmio(packed struct(u32) { + /// Calibration timer timeout + EVENTS_CTTO: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved296: [20]u8, + /// Calibration timer has been started and is ready to process new tasks + EVENTS_CTSTARTED: mmio.Mmio(packed struct(u32) { + /// Calibration timer has been started and is ready to process new tasks + EVENTS_CTSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Calibration timer has been stopped and is ready to process new tasks + EVENTS_CTSTOPPED: mmio.Mmio(packed struct(u32) { + /// Calibration timer has been stopped and is ready to process new tasks + EVENTS_CTSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved772: [468]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event HFCLKSTARTED + HFCLKSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event LFCLKSTARTED + LFCLKSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved3: u1, + /// Write '1' to enable interrupt for event DONE + DONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CTTO + CTTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u5, + /// Write '1' to enable interrupt for event CTSTARTED + CTSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CTSTOPPED + CTSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u20, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event HFCLKSTARTED + HFCLKSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event LFCLKSTARTED + LFCLKSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved3: u1, + /// Write '1' to disable interrupt for event DONE + DONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CTTO + CTTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u5, + /// Write '1' to disable interrupt for event CTSTARTED + CTSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CTSTOPPED + CTSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u20, + }), + reserved1032: [252]u8, + /// Status indicating that HFCLKSTART task has been triggered + HFCLKRUN: mmio.Mmio(packed struct(u32) { + /// HFCLKSTART task triggered or not + STATUS: packed union { + raw: u1, + value: enum(u1) { + /// Task not triggered + NotTriggered = 0x0, + /// Task triggered + Triggered = 0x1, + }, + }, + padding: u31, + }), + /// HFCLK status + HFCLKSTAT: mmio.Mmio(packed struct(u32) { + /// Source of HFCLK + SRC: packed union { + raw: u1, + value: enum(u1) { + /// 64 MHz internal oscillator (HFINT) + RC = 0x0, + /// 64 MHz crystal oscillator (HFXO) + Xtal = 0x1, + }, + }, + reserved16: u15, + /// HFCLK state + STATE: packed union { + raw: u1, + value: enum(u1) { + /// HFCLK not running + NotRunning = 0x0, + /// HFCLK running + Running = 0x1, + }, + }, + padding: u15, + }), + reserved1044: [4]u8, + /// Status indicating that LFCLKSTART task has been triggered + LFCLKRUN: mmio.Mmio(packed struct(u32) { + /// LFCLKSTART task triggered or not + STATUS: packed union { + raw: u1, + value: enum(u1) { + /// Task not triggered + NotTriggered = 0x0, + /// Task triggered + Triggered = 0x1, + }, + }, + padding: u31, + }), + /// LFCLK status + LFCLKSTAT: mmio.Mmio(packed struct(u32) { + /// Source of LFCLK + SRC: packed union { + raw: u2, + value: enum(u2) { + /// 32.768 kHz RC oscillator (LFRC) + RC = 0x0, + /// 32.768 kHz crystal oscillator (LFXO) + Xtal = 0x1, + /// 32.768 kHz synthesized from HFCLK (LFSYNT) + Synth = 0x2, + _, + }, + }, + reserved16: u14, + /// LFCLK state + STATE: packed union { + raw: u1, + value: enum(u1) { + /// LFCLK not running + NotRunning = 0x0, + /// LFCLK running + Running = 0x1, + }, + }, + padding: u15, + }), + /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + LFCLKSRCCOPY: mmio.Mmio(packed struct(u32) { + /// Clock source + SRC: packed union { + raw: u2, + value: enum(u2) { + /// 32.768 kHz RC oscillator (LFRC) + RC = 0x0, + /// 32.768 kHz crystal oscillator (LFXO) + Xtal = 0x1, + /// 32.768 kHz synthesized from HFCLK (LFSYNT) + Synth = 0x2, + _, + }, + }, + padding: u30, + }), + reserved1304: [248]u8, + /// Clock source for the LFCLK + LFCLKSRC: mmio.Mmio(packed struct(u32) { + /// Clock source + SRC: packed union { + raw: u2, + value: enum(u2) { + /// 32.768 kHz RC oscillator (LFRC) + RC = 0x0, + /// 32.768 kHz crystal oscillator (LFXO) + Xtal = 0x1, + /// 32.768 kHz synthesized from HFCLK (LFSYNT) + Synth = 0x2, + _, + }, + }, + reserved16: u14, + /// Enable or disable bypass of LFCLK crystal oscillator with external clock source + BYPASS: packed union { + raw: u1, + value: enum(u1) { + /// Disable (use with Xtal or low-swing external source) + Disabled = 0x0, + /// Enable (use with rail-to-rail external source) + Enabled = 0x1, + }, + }, + /// Enable or disable external source for LFCLK + EXTERNAL: packed union { + raw: u1, + value: enum(u1) { + /// Disable external source (use with Xtal) + Disabled = 0x0, + /// Enable use of external source instead of Xtal (SRC needs to be set to Xtal) + Enabled = 0x1, + }, + }, + padding: u14, + }), + reserved1320: [12]u8, + /// HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. + HFXODEBOUNCE: mmio.Mmio(packed struct(u32) { + /// HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. + HFXODEBOUNCE: packed union { + raw: u8, + value: enum(u8) { + /// 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. + Db256us = 0x10, + /// 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. + Db1024us = 0x40, + _, + }, + }, + padding: u24, + }), + reserved1336: [12]u8, + /// Calibration timer interval + CTIV: mmio.Mmio(packed struct(u32) { + /// Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. + CTIV: u7, + padding: u25, + }), + reserved1372: [32]u8, + /// Clocking options for the trace port debug interface + TRACECONFIG: mmio.Mmio(packed struct(u32) { + /// Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. + TRACEPORTSPEED: packed union { + raw: u2, + value: enum(u2) { + /// 32 MHz trace port clock (TRACECLK = 16 MHz) + @"32MHz" = 0x0, + /// 16 MHz trace port clock (TRACECLK = 8 MHz) + @"16MHz" = 0x1, + /// 8 MHz trace port clock (TRACECLK = 4 MHz) + @"8MHz" = 0x2, + /// 4 MHz trace port clock (TRACECLK = 2 MHz) + @"4MHz" = 0x3, + }, + }, + reserved16: u14, + /// Pin multiplexing of trace signals. See pin assignment chapter for more details. + TRACEMUX: packed union { + raw: u2, + value: enum(u2) { + /// No trace signals routed to pins. All pins can be used as regular GPIOs. + GPIO = 0x0, + /// SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. + Serial = 0x1, + /// All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. + Parallel = 0x2, + _, + }, + }, + padding: u14, + }), + reserved1460: [84]u8, + /// LFRC mode configuration + LFRCMODE: mmio.Mmio(packed struct(u32) { + /// Set LFRC mode + MODE: packed union { + raw: u1, + value: enum(u1) { + /// Normal mode + Normal = 0x0, + /// Ultra-low power mode (ULP) + ULP = 0x1, + }, + }, + reserved16: u15, + /// Active LFRC mode. This field is read only. + STATUS: packed union { + raw: u1, + value: enum(u1) { + /// Normal mode + Normal = 0x0, + /// Ultra-low power mode (ULP) + ULP = 0x1, + }, + }, + padding: u15, + }), + }; + + /// Power control + pub const POWER = extern struct { + reserved120: [120]u8, + /// Enable Constant Latency mode + TASKS_CONSTLAT: mmio.Mmio(packed struct(u32) { + /// Enable Constant Latency mode + TASKS_CONSTLAT: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Enable Low-power mode (variable latency) + TASKS_LOWPWR: mmio.Mmio(packed struct(u32) { + /// Enable Low-power mode (variable latency) + TASKS_LOWPWR: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved264: [136]u8, + /// Power failure warning + EVENTS_POFWARN: mmio.Mmio(packed struct(u32) { + /// Power failure warning + EVENTS_POFWARN: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved276: [8]u8, + /// CPU entered WFI/WFE sleep + EVENTS_SLEEPENTER: mmio.Mmio(packed struct(u32) { + /// CPU entered WFI/WFE sleep + EVENTS_SLEEPENTER: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// CPU exited WFI/WFE sleep + EVENTS_SLEEPEXIT: mmio.Mmio(packed struct(u32) { + /// CPU exited WFI/WFE sleep + EVENTS_SLEEPEXIT: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Voltage supply detected on VBUS + EVENTS_USBDETECTED: mmio.Mmio(packed struct(u32) { + /// Voltage supply detected on VBUS + EVENTS_USBDETECTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Voltage supply removed from VBUS + EVENTS_USBREMOVED: mmio.Mmio(packed struct(u32) { + /// Voltage supply removed from VBUS + EVENTS_USBREMOVED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// USB 3.3 V supply ready + EVENTS_USBPWRRDY: mmio.Mmio(packed struct(u32) { + /// USB 3.3 V supply ready + EVENTS_USBPWRRDY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved772: [476]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Write '1' to enable interrupt for event POFWARN + POFWARN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved5: u2, + /// Write '1' to enable interrupt for event SLEEPENTER + SLEEPENTER: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event SLEEPEXIT + SLEEPEXIT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event USBDETECTED + USBDETECTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event USBREMOVED + USBREMOVED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event USBPWRRDY + USBPWRRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u22, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Write '1' to disable interrupt for event POFWARN + POFWARN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved5: u2, + /// Write '1' to disable interrupt for event SLEEPENTER + SLEEPENTER: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event SLEEPEXIT + SLEEPEXIT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event USBDETECTED + USBDETECTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event USBREMOVED + USBREMOVED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event USBPWRRDY + USBPWRRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u22, + }), + reserved1024: [244]u8, + /// Reset reason + RESETREAS: mmio.Mmio(packed struct(u32) { + /// Reset from pin-reset detected + RESETPIN: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset from watchdog detected + DOG: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset from soft reset detected + SREQ: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset from CPU lock-up detected + LOCKUP: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + reserved16: u12, + /// Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO + OFF: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP + LPCOMP: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode + DIF: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset due to wake up from System OFF mode by NFC field detect + NFC: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + /// Reset due to wake up from System OFF mode by VBUS rising into valid range + VBUS: packed union { + raw: u1, + value: enum(u1) { + /// Not detected + NotDetected = 0x0, + /// Detected + Detected = 0x1, + }, + }, + padding: u11, + }), + reserved1064: [36]u8, + /// Deprecated register - RAM status register + RAMSTATUS: mmio.Mmio(packed struct(u32) { + /// RAM block 0 is on or off/powering up + RAMBLOCK0: packed union { + raw: u1, + value: enum(u1) { + /// Off + Off = 0x0, + /// On + On = 0x1, + }, + }, + /// RAM block 1 is on or off/powering up + RAMBLOCK1: packed union { + raw: u1, + value: enum(u1) { + /// Off + Off = 0x0, + /// On + On = 0x1, + }, + }, + /// RAM block 2 is on or off/powering up + RAMBLOCK2: packed union { + raw: u1, + value: enum(u1) { + /// Off + Off = 0x0, + /// On + On = 0x1, + }, + }, + /// RAM block 3 is on or off/powering up + RAMBLOCK3: packed union { + raw: u1, + value: enum(u1) { + /// Off + Off = 0x0, + /// On + On = 0x1, + }, + }, + padding: u28, + }), + reserved1080: [12]u8, + /// USB supply status + USBREGSTATUS: mmio.Mmio(packed struct(u32) { + /// VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) + VBUSDETECT: packed union { + raw: u1, + value: enum(u1) { + /// VBUS voltage below valid threshold + NoVbus = 0x0, + /// VBUS voltage above valid threshold + VbusPresent = 0x1, + }, + }, + /// USB supply output settling time elapsed + OUTPUTRDY: packed union { + raw: u1, + value: enum(u1) { + /// USBREG output settling time not elapsed + NotReady = 0x0, + /// USBREG output settling time elapsed (same information as USBPWRRDY event) + Ready = 0x1, + }, + }, + padding: u30, + }), + reserved1280: [196]u8, + /// System OFF register + SYSTEMOFF: mmio.Mmio(packed struct(u32) { + /// Enable System OFF mode + SYSTEMOFF: packed union { + raw: u1, + value: enum(u1) { + /// Enable System OFF mode + Enter = 0x1, + _, + }, + }, + padding: u31, + }), + reserved1296: [12]u8, + /// Power-fail comparator configuration + POFCON: mmio.Mmio(packed struct(u32) { + /// Enable or disable power failure warning + POF: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. + THRESHOLD: packed union { + raw: u4, + value: enum(u4) { + /// Set threshold to 1.7 V + V17 = 0x4, + /// Set threshold to 1.8 V + V18 = 0x5, + /// Set threshold to 1.9 V + V19 = 0x6, + /// Set threshold to 2.0 V + V20 = 0x7, + /// Set threshold to 2.1 V + V21 = 0x8, + /// Set threshold to 2.2 V + V22 = 0x9, + /// Set threshold to 2.3 V + V23 = 0xa, + /// Set threshold to 2.4 V + V24 = 0xb, + /// Set threshold to 2.5 V + V25 = 0xc, + /// Set threshold to 2.6 V + V26 = 0xd, + /// Set threshold to 2.7 V + V27 = 0xe, + /// Set threshold to 2.8 V + V28 = 0xf, + _, + }, + }, + reserved8: u3, + /// Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). + THRESHOLDVDDH: packed union { + raw: u4, + value: enum(u4) { + /// Set threshold to 2.7 V + V27 = 0x0, + /// Set threshold to 2.8 V + V28 = 0x1, + /// Set threshold to 2.9 V + V29 = 0x2, + /// Set threshold to 3.0 V + V30 = 0x3, + /// Set threshold to 3.1 V + V31 = 0x4, + /// Set threshold to 3.2 V + V32 = 0x5, + /// Set threshold to 3.3 V + V33 = 0x6, + /// Set threshold to 3.4 V + V34 = 0x7, + /// Set threshold to 3.5 V + V35 = 0x8, + /// Set threshold to 3.6 V + V36 = 0x9, + /// Set threshold to 3.7 V + V37 = 0xa, + /// Set threshold to 3.8 V + V38 = 0xb, + /// Set threshold to 3.9 V + V39 = 0xc, + /// Set threshold to 4.0 V + V40 = 0xd, + /// Set threshold to 4.1 V + V41 = 0xe, + /// Set threshold to 4.2 V + V42 = 0xf, + }, + }, + padding: u20, + }), + reserved1308: [8]u8, + /// General purpose retention register + GPREGRET: mmio.Mmio(packed struct(u32) { + /// General purpose retention register + GPREGRET: u8, + padding: u24, + }), + /// General purpose retention register + GPREGRET2: mmio.Mmio(packed struct(u32) { + /// General purpose retention register + GPREGRET: u8, + padding: u24, + }), + reserved1400: [84]u8, + /// Enable DC/DC converter for REG1 stage + DCDCEN: mmio.Mmio(packed struct(u32) { + /// Enable DC/DC converter for REG1 stage. + DCDCEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1408: [4]u8, + /// Enable DC/DC converter for REG0 stage + DCDCEN0: mmio.Mmio(packed struct(u32) { + /// Enable DC/DC converter for REG0 stage. + DCDCEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1600: [188]u8, + /// Main supply status + MAINREGSTATUS: mmio.Mmio(packed struct(u32) { + /// Main supply status + MAINREGSTATUS: packed union { + raw: u1, + value: enum(u1) { + /// Normal voltage mode. Voltage supplied on VDD. + Normal = 0x0, + /// High voltage mode. Voltage supplied on VDDH. + High = 0x1, + }, + }, + padding: u31, + }), + }; + + /// GPIO Port 1 + pub const P0 = extern struct { + reserved1284: [1284]u8, + /// Write GPIO port + OUT: mmio.Mmio(packed struct(u32) { + /// Pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + /// Pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Pin driver is low + Low = 0x0, + /// Pin driver is high + High = 0x1, + }, + }, + }), + /// Set individual bits in GPIO port + OUTSET: mmio.Mmio(packed struct(u32) { + /// Pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + }), + /// Clear individual bits in GPIO port + OUTCLR: mmio.Mmio(packed struct(u32) { + /// Pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + /// Pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin driver is low + Low = 0x0, + /// Read: pin driver is high + High = 0x1, + }, + }, + }), + /// Read GPIO port + IN: mmio.Mmio(packed struct(u32) { + /// Pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + /// Pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Pin input is low + Low = 0x0, + /// Pin input is high + High = 0x1, + }, + }, + }), + /// Direction of GPIO pins + DIR: mmio.Mmio(packed struct(u32) { + /// Pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + /// Pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Pin set as input + Input = 0x0, + /// Pin set as output + Output = 0x1, + }, + }, + }), + /// DIR set register + DIRSET: mmio.Mmio(packed struct(u32) { + /// Set as output pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as output pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + }), + /// DIR clear register + DIRCLR: mmio.Mmio(packed struct(u32) { + /// Set as input pin 0 + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 1 + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 2 + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 3 + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 4 + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 5 + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 6 + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 7 + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 8 + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 9 + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 10 + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 11 + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 12 + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 13 + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 14 + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 15 + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 16 + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 17 + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 18 + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 19 + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 20 + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 21 + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 22 + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 23 + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 24 + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 25 + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 26 + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 27 + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 28 + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 29 + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 30 + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + /// Set as input pin 31 + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Read: pin set as input + Input = 0x0, + /// Read: pin set as output + Output = 0x1, + }, + }, + }), + /// Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + LATCH: mmio.Mmio(packed struct(u32) { + /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + PIN0: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + PIN1: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + PIN2: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + PIN3: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + PIN4: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + PIN5: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + PIN6: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + PIN7: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + PIN8: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + PIN9: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + PIN10: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + PIN11: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + PIN12: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + PIN13: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + PIN14: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + PIN15: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + PIN16: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + PIN17: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + PIN18: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + PIN19: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + PIN20: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + PIN21: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + PIN22: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + PIN23: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + PIN24: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + PIN25: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + PIN26: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + PIN27: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + PIN28: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + PIN29: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + PIN30: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + /// Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + PIN31: packed union { + raw: u1, + value: enum(u1) { + /// Criteria has not been met + NotLatched = 0x0, + /// Criteria has been met + Latched = 0x1, + }, + }, + }), + /// Select between default DETECT signal behaviour and LDETECT mode + DETECTMODE: mmio.Mmio(packed struct(u32) { + /// Select between default DETECT signal behaviour and LDETECT mode + DETECTMODE: packed union { + raw: u1, + value: enum(u1) { + /// DETECT directly connected to PIN DETECT signals + Default = 0x0, + /// Use the latched LDETECT behaviour + LDETECT = 0x1, + }, + }, + padding: u31, + }), + reserved1792: [472]u8, + /// Description collection: Configuration of GPIO pins + PIN_CNF: [32]mmio.Mmio(packed struct(u32) { + /// Pin direction. Same physical register as DIR register + DIR: packed union { + raw: u1, + value: enum(u1) { + /// Configure pin as an input pin + Input = 0x0, + /// Configure pin as an output pin + Output = 0x1, + }, + }, + /// Connect or disconnect input buffer + INPUT: packed union { + raw: u1, + value: enum(u1) { + /// Connect input buffer + Connect = 0x0, + /// Disconnect input buffer + Disconnect = 0x1, + }, + }, + /// Pull configuration + PULL: packed union { + raw: u2, + value: enum(u2) { + /// No pull + Disabled = 0x0, + /// Pull down on pin + Pulldown = 0x1, + /// Pull up on pin + Pullup = 0x3, + _, + }, + }, + reserved8: u4, + /// Drive configuration + DRIVE: packed union { + raw: u3, + value: enum(u3) { + /// Standard '0', standard '1' + S0S1 = 0x0, + /// High drive '0', standard '1' + H0S1 = 0x1, + /// Standard '0', high drive '1' + S0H1 = 0x2, + /// High drive '0', high 'drive '1'' + H0H1 = 0x3, + /// Disconnect '0' standard '1' (normally used for wired-or connections) + D0S1 = 0x4, + /// Disconnect '0', high drive '1' (normally used for wired-or connections) + D0H1 = 0x5, + /// Standard '0'. disconnect '1' (normally used for wired-and connections) + S0D1 = 0x6, + /// High drive '0', disconnect '1' (normally used for wired-and connections) + H0D1 = 0x7, + }, + }, + reserved16: u5, + /// Pin sensing mechanism + SENSE: packed union { + raw: u2, + value: enum(u2) { + /// Disabled + Disabled = 0x0, + /// Sense for high level + High = 0x2, + /// Sense for low level + Low = 0x3, + _, + }, + }, + padding: u14, + }), + }; + + /// Access control lists + pub const ACL = struct {}; + + /// 2.4 GHz radio + pub const RADIO = extern struct { + /// Enable RADIO in TX mode + TASKS_TXEN: mmio.Mmio(packed struct(u32) { + /// Enable RADIO in TX mode + TASKS_TXEN: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Enable RADIO in RX mode + TASKS_RXEN: mmio.Mmio(packed struct(u32) { + /// Enable RADIO in RX mode + TASKS_RXEN: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start RADIO + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Start RADIO + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop RADIO + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop RADIO + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Disable RADIO + TASKS_DISABLE: mmio.Mmio(packed struct(u32) { + /// Disable RADIO + TASKS_DISABLE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start the RSSI and take one single sample of the receive signal strength + TASKS_RSSISTART: mmio.Mmio(packed struct(u32) { + /// Start the RSSI and take one single sample of the receive signal strength + TASKS_RSSISTART: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop the RSSI measurement + TASKS_RSSISTOP: mmio.Mmio(packed struct(u32) { + /// Stop the RSSI measurement + TASKS_RSSISTOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start the bit counter + TASKS_BCSTART: mmio.Mmio(packed struct(u32) { + /// Start the bit counter + TASKS_BCSTART: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop the bit counter + TASKS_BCSTOP: mmio.Mmio(packed struct(u32) { + /// Stop the bit counter + TASKS_BCSTOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start the energy detect measurement used in IEEE 802.15.4 mode + TASKS_EDSTART: mmio.Mmio(packed struct(u32) { + /// Start the energy detect measurement used in IEEE 802.15.4 mode + TASKS_EDSTART: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop the energy detect measurement + TASKS_EDSTOP: mmio.Mmio(packed struct(u32) { + /// Stop the energy detect measurement + TASKS_EDSTOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start the clear channel assessment used in IEEE 802.15.4 mode + TASKS_CCASTART: mmio.Mmio(packed struct(u32) { + /// Start the clear channel assessment used in IEEE 802.15.4 mode + TASKS_CCASTART: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop the clear channel assessment + TASKS_CCASTOP: mmio.Mmio(packed struct(u32) { + /// Stop the clear channel assessment + TASKS_CCASTOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [204]u8, + /// RADIO has ramped up and is ready to be started + EVENTS_READY: mmio.Mmio(packed struct(u32) { + /// RADIO has ramped up and is ready to be started + EVENTS_READY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Address sent or received + EVENTS_ADDRESS: mmio.Mmio(packed struct(u32) { + /// Address sent or received + EVENTS_ADDRESS: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Packet payload sent or received + EVENTS_PAYLOAD: mmio.Mmio(packed struct(u32) { + /// Packet payload sent or received + EVENTS_PAYLOAD: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Packet sent or received + EVENTS_END: mmio.Mmio(packed struct(u32) { + /// Packet sent or received + EVENTS_END: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// RADIO has been disabled + EVENTS_DISABLED: mmio.Mmio(packed struct(u32) { + /// RADIO has been disabled + EVENTS_DISABLED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// A device address match occurred on the last received packet + EVENTS_DEVMATCH: mmio.Mmio(packed struct(u32) { + /// A device address match occurred on the last received packet + EVENTS_DEVMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// No device address match occurred on the last received packet + EVENTS_DEVMISS: mmio.Mmio(packed struct(u32) { + /// No device address match occurred on the last received packet + EVENTS_DEVMISS: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Sampling of receive signal strength complete + EVENTS_RSSIEND: mmio.Mmio(packed struct(u32) { + /// Sampling of receive signal strength complete + EVENTS_RSSIEND: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved296: [8]u8, + /// Bit counter reached bit count value + EVENTS_BCMATCH: mmio.Mmio(packed struct(u32) { + /// Bit counter reached bit count value + EVENTS_BCMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved304: [4]u8, + /// Packet received with CRC ok + EVENTS_CRCOK: mmio.Mmio(packed struct(u32) { + /// Packet received with CRC ok + EVENTS_CRCOK: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Packet received with CRC error + EVENTS_CRCERROR: mmio.Mmio(packed struct(u32) { + /// Packet received with CRC error + EVENTS_CRCERROR: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// IEEE 802.15.4 length field received + EVENTS_FRAMESTART: mmio.Mmio(packed struct(u32) { + /// IEEE 802.15.4 length field received + EVENTS_FRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + EVENTS_EDEND: mmio.Mmio(packed struct(u32) { + /// Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + EVENTS_EDEND: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// The sampling of energy detection has stopped + EVENTS_EDSTOPPED: mmio.Mmio(packed struct(u32) { + /// The sampling of energy detection has stopped + EVENTS_EDSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Wireless medium in idle - clear to send + EVENTS_CCAIDLE: mmio.Mmio(packed struct(u32) { + /// Wireless medium in idle - clear to send + EVENTS_CCAIDLE: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Wireless medium busy - do not send + EVENTS_CCABUSY: mmio.Mmio(packed struct(u32) { + /// Wireless medium busy - do not send + EVENTS_CCABUSY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// The CCA has stopped + EVENTS_CCASTOPPED: mmio.Mmio(packed struct(u32) { + /// The CCA has stopped + EVENTS_CCASTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + EVENTS_RATEBOOST: mmio.Mmio(packed struct(u32) { + /// Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + EVENTS_RATEBOOST: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// RADIO has ramped up and is ready to be started TX path + EVENTS_TXREADY: mmio.Mmio(packed struct(u32) { + /// RADIO has ramped up and is ready to be started TX path + EVENTS_TXREADY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// RADIO has ramped up and is ready to be started RX path + EVENTS_RXREADY: mmio.Mmio(packed struct(u32) { + /// RADIO has ramped up and is ready to be started RX path + EVENTS_RXREADY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// MAC header match found + EVENTS_MHRMATCH: mmio.Mmio(packed struct(u32) { + /// MAC header match found + EVENTS_MHRMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved360: [8]u8, + /// Preamble indicator. + EVENTS_SYNC: mmio.Mmio(packed struct(u32) { + /// Preamble indicator. + EVENTS_SYNC: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. + EVENTS_PHYEND: mmio.Mmio(packed struct(u32) { + /// Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. + EVENTS_PHYEND: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [144]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between event READY and task START + READY_START: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event END and task DISABLE + END_DISABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event DISABLED and task TXEN + DISABLED_TXEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event DISABLED and task RXEN + DISABLED_RXEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event ADDRESS and task RSSISTART + ADDRESS_RSSISTART: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event END and task START + END_START: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event ADDRESS and task BCSTART + ADDRESS_BCSTART: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + reserved8: u1, + /// Shortcut between event DISABLED and task RSSISTOP + DISABLED_RSSISTOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + reserved11: u2, + /// Shortcut between event RXREADY and task CCASTART + RXREADY_CCASTART: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event CCAIDLE and task TXEN + CCAIDLE_TXEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event CCABUSY and task DISABLE + CCABUSY_DISABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event FRAMESTART and task BCSTART + FRAMESTART_BCSTART: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event READY and task EDSTART + READY_EDSTART: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event EDEND and task DISABLE + EDEND_DISABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event CCAIDLE and task STOP + CCAIDLE_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event TXREADY and task START + TXREADY_START: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event RXREADY and task START + RXREADY_START: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event PHYEND and task DISABLE + PHYEND_DISABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event PHYEND and task START + PHYEND_START: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u10, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ADDRESS + ADDRESS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event PAYLOAD + PAYLOAD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event DISABLED + DISABLED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event DEVMATCH + DEVMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event DEVMISS + DEVMISS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event RSSIEND + RSSIEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u2, + /// Write '1' to enable interrupt for event BCMATCH + BCMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved12: u1, + /// Write '1' to enable interrupt for event CRCOK + CRCOK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CRCERROR + CRCERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event FRAMESTART + FRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event EDEND + EDEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event EDSTOPPED + EDSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CCAIDLE + CCAIDLE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CCABUSY + CCABUSY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CCASTOPPED + CCASTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event RATEBOOST + RATEBOOST: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TXREADY + TXREADY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event RXREADY + RXREADY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event MHRMATCH + MHRMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved26: u2, + /// Write '1' to enable interrupt for event SYNC + SYNC: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event PHYEND + PHYEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ADDRESS + ADDRESS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event PAYLOAD + PAYLOAD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event DISABLED + DISABLED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event DEVMATCH + DEVMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event DEVMISS + DEVMISS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event RSSIEND + RSSIEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u2, + /// Write '1' to disable interrupt for event BCMATCH + BCMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved12: u1, + /// Write '1' to disable interrupt for event CRCOK + CRCOK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CRCERROR + CRCERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event FRAMESTART + FRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event EDEND + EDEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event EDSTOPPED + EDSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CCAIDLE + CCAIDLE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CCABUSY + CCABUSY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CCASTOPPED + CCASTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event RATEBOOST + RATEBOOST: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TXREADY + TXREADY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event RXREADY + RXREADY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event MHRMATCH + MHRMATCH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved26: u2, + /// Write '1' to disable interrupt for event SYNC + SYNC: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event PHYEND + PHYEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + reserved1024: [244]u8, + /// CRC status + CRCSTATUS: mmio.Mmio(packed struct(u32) { + /// CRC status of packet received + CRCSTATUS: packed union { + raw: u1, + value: enum(u1) { + /// Packet received with CRC error + CRCError = 0x0, + /// Packet received with CRC ok + CRCOk = 0x1, + }, + }, + padding: u31, + }), + reserved1032: [4]u8, + /// Received address + RXMATCH: mmio.Mmio(packed struct(u32) { + /// Received address + RXMATCH: u3, + padding: u29, + }), + /// CRC field of previously received packet + RXCRC: mmio.Mmio(packed struct(u32) { + /// CRC field of previously received packet + RXCRC: u24, + padding: u8, + }), + /// Device address match index + DAI: mmio.Mmio(packed struct(u32) { + /// Device address match index + DAI: u3, + padding: u29, + }), + /// Payload status + PDUSTAT: mmio.Mmio(packed struct(u32) { + /// Status on payload length vs. PCNF1.MAXLEN + PDUSTAT: packed union { + raw: u1, + value: enum(u1) { + /// Payload less than PCNF1.MAXLEN + LessThan = 0x0, + /// Payload greater than PCNF1.MAXLEN + GreaterThan = 0x1, + }, + }, + /// Status on what rate packet is received with in Long Range + CISTAT: packed union { + raw: u2, + value: enum(u2) { + /// Frame is received at 125kbps + LR125kbit = 0x0, + /// Frame is received at 500kbps + LR500kbit = 0x1, + _, + }, + }, + padding: u29, + }), + reserved1284: [236]u8, + /// Packet pointer + PACKETPTR: mmio.Mmio(packed struct(u32) { + /// Packet pointer + PACKETPTR: u32, + }), + /// Frequency + FREQUENCY: mmio.Mmio(packed struct(u32) { + /// Radio channel frequency + FREQUENCY: u7, + reserved8: u1, + /// Channel map selection. + MAP: packed union { + raw: u1, + value: enum(u1) { + /// Channel map between 2400 MHZ .. 2500 MHz + Default = 0x0, + /// Channel map between 2360 MHZ .. 2460 MHz + Low = 0x1, + }, + }, + padding: u23, + }), + /// Output power + TXPOWER: mmio.Mmio(packed struct(u32) { + /// RADIO output power + TXPOWER: packed union { + raw: u8, + value: enum(u8) { + /// +8 dBm + Pos8dBm = 0x8, + /// +7 dBm + Pos7dBm = 0x7, + /// +6 dBm + Pos6dBm = 0x6, + /// +5 dBm + Pos5dBm = 0x5, + /// +4 dBm + Pos4dBm = 0x4, + /// +3 dBm + Pos3dBm = 0x3, + /// +2 dBm + Pos2dBm = 0x2, + /// 0 dBm + @"0dBm" = 0x0, + /// -4 dBm + Neg4dBm = 0xfc, + /// -8 dBm + Neg8dBm = 0xf8, + /// -12 dBm + Neg12dBm = 0xf4, + /// -16 dBm + Neg16dBm = 0xf0, + /// -20 dBm + Neg20dBm = 0xec, + /// Deprecated enumerator - -40 dBm + Neg30dBm = 0xe2, + /// -40 dBm + Neg40dBm = 0xd8, + _, + }, + }, + padding: u24, + }), + /// Data rate and modulation + MODE: mmio.Mmio(packed struct(u32) { + /// Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. + MODE: packed union { + raw: u4, + value: enum(u4) { + /// 1 Mbit/s Nordic proprietary radio mode + Nrf_1Mbit = 0x0, + /// 2 Mbit/s Nordic proprietary radio mode + Nrf_2Mbit = 0x1, + /// 1 Mbit/s BLE + Ble_1Mbit = 0x3, + /// 2 Mbit/s BLE + Ble_2Mbit = 0x4, + /// Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX + Ble_LR125Kbit = 0x5, + /// Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX + Ble_LR500Kbit = 0x6, + /// IEEE 802.15.4-2006 250 kbit/s + Ieee802154_250Kbit = 0xf, + _, + }, + }, + padding: u28, + }), + /// Packet configuration register 0 + PCNF0: mmio.Mmio(packed struct(u32) { + /// Length on air of LENGTH field in number of bits. + LFLEN: u4, + reserved8: u4, + /// Length on air of S0 field in number of bytes. + S0LEN: u1, + reserved16: u7, + /// Length on air of S1 field in number of bits. + S1LEN: u4, + /// Include or exclude S1 field in RAM + S1INCL: packed union { + raw: u1, + value: enum(u1) { + /// Include S1 field in RAM only if S1LEN > 0 + Automatic = 0x0, + /// Always include S1 field in RAM independent of S1LEN + Include = 0x1, + }, + }, + reserved22: u1, + /// Length of code indicator - long range + CILEN: u2, + /// Length of preamble on air. Decision point: TASKS_START task + PLEN: packed union { + raw: u2, + value: enum(u2) { + /// 8-bit preamble + @"8bit" = 0x0, + /// 16-bit preamble + @"16bit" = 0x1, + /// 32-bit zero preamble - used for IEEE 802.15.4 + @"32bitZero" = 0x2, + /// Preamble - used for BLE long range + LongRange = 0x3, + }, + }, + /// Indicates if LENGTH field contains CRC or not + CRCINC: packed union { + raw: u1, + value: enum(u1) { + /// LENGTH does not contain CRC + Exclude = 0x0, + /// LENGTH includes CRC + Include = 0x1, + }, + }, + reserved29: u2, + /// Length of TERM field in Long Range operation + TERMLEN: u2, + padding: u1, + }), + /// Packet configuration register 1 + PCNF1: mmio.Mmio(packed struct(u32) { + /// Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + MAXLEN: u8, + /// Static length in number of bytes + STATLEN: u8, + /// Base address length in number of bytes + BALEN: u3, + reserved24: u5, + /// On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. + ENDIAN: packed union { + raw: u1, + value: enum(u1) { + /// Least significant bit on air first + Little = 0x0, + /// Most significant bit on air first + Big = 0x1, + }, + }, + /// Enable or disable packet whitening + WHITEEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u6, + }), + /// Base address 0 + BASE0: mmio.Mmio(packed struct(u32) { + /// Base address 0 + BASE0: u32, + }), + /// Base address 1 + BASE1: mmio.Mmio(packed struct(u32) { + /// Base address 1 + BASE1: u32, + }), + /// Prefixes bytes for logical addresses 0-3 + PREFIX0: mmio.Mmio(packed struct(u32) { + /// Address prefix 0. + AP0: u8, + /// Address prefix 1. + AP1: u8, + /// Address prefix 2. + AP2: u8, + /// Address prefix 3. + AP3: u8, + }), + /// Prefixes bytes for logical addresses 4-7 + PREFIX1: mmio.Mmio(packed struct(u32) { + /// Address prefix 4. + AP4: u8, + /// Address prefix 5. + AP5: u8, + /// Address prefix 6. + AP6: u8, + /// Address prefix 7. + AP7: u8, + }), + /// Transmit address select + TXADDRESS: mmio.Mmio(packed struct(u32) { + /// Transmit address select + TXADDRESS: u3, + padding: u29, + }), + /// Receive address select + RXADDRESSES: mmio.Mmio(packed struct(u32) { + /// Enable or disable reception on logical address 0. + ADDR0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 1. + ADDR1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 2. + ADDR2: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 3. + ADDR3: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 4. + ADDR4: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 5. + ADDR5: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 6. + ADDR6: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable reception on logical address 7. + ADDR7: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u24, + }), + /// CRC configuration + CRCCNF: mmio.Mmio(packed struct(u32) { + /// CRC length in number of bytes. + LEN: packed union { + raw: u2, + value: enum(u2) { + /// CRC length is zero and CRC calculation is disabled + Disabled = 0x0, + /// CRC length is one byte and CRC calculation is enabled + One = 0x1, + /// CRC length is two bytes and CRC calculation is enabled + Two = 0x2, + /// CRC length is three bytes and CRC calculation is enabled + Three = 0x3, + }, + }, + reserved8: u6, + /// Include or exclude packet address field out of CRC calculation. + SKIPADDR: packed union { + raw: u2, + value: enum(u2) { + /// CRC calculation includes address field + Include = 0x0, + /// CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + Skip = 0x1, + /// CRC calculation as per 802.15.4 standard. Starting at first byte after length field. + Ieee802154 = 0x2, + _, + }, + }, + padding: u22, + }), + /// CRC polynomial + CRCPOLY: mmio.Mmio(packed struct(u32) { + /// CRC polynomial + CRCPOLY: u24, + padding: u8, + }), + /// CRC initial value + CRCINIT: mmio.Mmio(packed struct(u32) { + /// CRC initial value + CRCINIT: u24, + padding: u8, + }), + reserved1348: [4]u8, + /// Interframe spacing in us + TIFS: mmio.Mmio(packed struct(u32) { + /// Interframe spacing in us + TIFS: u10, + padding: u22, + }), + /// RSSI sample + RSSISAMPLE: mmio.Mmio(packed struct(u32) { + /// RSSI sample + RSSISAMPLE: u7, + padding: u25, + }), + reserved1360: [4]u8, + /// Current radio state + STATE: mmio.Mmio(packed struct(u32) { + /// Current radio state + STATE: packed union { + raw: u4, + value: enum(u4) { + /// RADIO is in the Disabled state + Disabled = 0x0, + /// RADIO is in the RXRU state + RxRu = 0x1, + /// RADIO is in the RXIDLE state + RxIdle = 0x2, + /// RADIO is in the RX state + Rx = 0x3, + /// RADIO is in the RXDISABLED state + RxDisable = 0x4, + /// RADIO is in the TXRU state + TxRu = 0x9, + /// RADIO is in the TXIDLE state + TxIdle = 0xa, + /// RADIO is in the TX state + Tx = 0xb, + /// RADIO is in the TXDISABLED state + TxDisable = 0xc, + _, + }, + }, + padding: u28, + }), + /// Data whitening initial value + DATAWHITEIV: mmio.Mmio(packed struct(u32) { + /// Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + DATAWHITEIV: u7, + padding: u25, + }), + reserved1376: [8]u8, + /// Bit counter compare + BCC: mmio.Mmio(packed struct(u32) { + /// Bit counter compare + BCC: u32, + }), + reserved1536: [156]u8, + /// Description collection: Device address base segment n + DAB: [8]mmio.Mmio(packed struct(u32) { + /// Device address base segment n + DAB: u32, + }), + /// Description collection: Device address prefix n + DAP: [8]mmio.Mmio(packed struct(u32) { + /// Device address prefix n + DAP: u16, + padding: u16, + }), + /// Device address match configuration + DACNF: mmio.Mmio(packed struct(u32) { + /// Enable or disable device address matching using device address 0 + ENA0: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 1 + ENA1: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 2 + ENA2: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 3 + ENA3: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 4 + ENA4: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 5 + ENA5: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 6 + ENA6: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable device address matching using device address 7 + ENA7: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// TxAdd for device address 0 + TXADD0: u1, + /// TxAdd for device address 1 + TXADD1: u1, + /// TxAdd for device address 2 + TXADD2: u1, + /// TxAdd for device address 3 + TXADD3: u1, + /// TxAdd for device address 4 + TXADD4: u1, + /// TxAdd for device address 5 + TXADD5: u1, + /// TxAdd for device address 6 + TXADD6: u1, + /// TxAdd for device address 7 + TXADD7: u1, + padding: u16, + }), + /// Search pattern configuration + MHRMATCHCONF: mmio.Mmio(packed struct(u32) { + /// Search pattern configuration + MHRMATCHCONF: u32, + }), + /// Pattern mask + MHRMATCHMAS: mmio.Mmio(packed struct(u32) { + /// Pattern mask + MHRMATCHMAS: u32, + }), + reserved1616: [4]u8, + /// Radio mode configuration register 0 + MODECNF0: mmio.Mmio(packed struct(u32) { + /// Radio ramp-up time + RU: packed union { + raw: u1, + value: enum(u1) { + /// Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 + Default = 0x0, + /// Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information + Fast = 0x1, + }, + }, + reserved8: u7, + /// Default TX value + DTX: packed union { + raw: u2, + value: enum(u2) { + /// Transmit '1' + B1 = 0x0, + /// Transmit '0' + B0 = 0x1, + /// Transmit center frequency + Center = 0x2, + _, + }, + }, + padding: u22, + }), + reserved1632: [12]u8, + /// IEEE 802.15.4 start of frame delimiter + SFD: mmio.Mmio(packed struct(u32) { + /// IEEE 802.15.4 start of frame delimiter + SFD: u8, + padding: u24, + }), + /// IEEE 802.15.4 energy detect loop count + EDCNT: mmio.Mmio(packed struct(u32) { + /// IEEE 802.15.4 energy detect loop count + EDCNT: u21, + padding: u11, + }), + /// IEEE 802.15.4 energy detect level + EDSAMPLE: mmio.Mmio(packed struct(u32) { + /// IEEE 802.15.4 energy detect level + EDLVL: u8, + padding: u24, + }), + /// IEEE 802.15.4 clear channel assessment control + CCACTRL: mmio.Mmio(packed struct(u32) { + /// CCA mode of operation + CCAMODE: packed union { + raw: u3, + value: enum(u3) { + /// Energy above threshold + EdMode = 0x0, + /// Carrier seen + CarrierMode = 0x1, + /// Energy above threshold AND carrier seen + CarrierAndEdMode = 0x2, + /// Energy above threshold OR carrier seen + CarrierOrEdMode = 0x3, + /// Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + EdModeTest1 = 0x4, + _, + }, + }, + reserved8: u5, + /// CCA energy busy threshold. Used in all the CCA modes except CarrierMode. + CCAEDTHRES: u8, + /// CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. + CCACORRTHRES: u8, + /// Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. + CCACORRCNT: u8, + }), + reserved4092: [2444]u8, + /// Peripheral power control + POWER: mmio.Mmio(packed struct(u32) { + /// Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + POWER: packed union { + raw: u1, + value: enum(u1) { + /// Peripheral is powered off + Disabled = 0x0, + /// Peripheral is powered on + Enabled = 0x1, + }, + }, + padding: u31, + }), + }; + + /// Universal Asynchronous Receiver/Transmitter + pub const UART0 = extern struct { + /// Start UART receiver + TASKS_STARTRX: mmio.Mmio(packed struct(u32) { + /// Start UART receiver + TASKS_STARTRX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop UART receiver + TASKS_STOPRX: mmio.Mmio(packed struct(u32) { + /// Stop UART receiver + TASKS_STOPRX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start UART transmitter + TASKS_STARTTX: mmio.Mmio(packed struct(u32) { + /// Start UART transmitter + TASKS_STARTTX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop UART transmitter + TASKS_STOPTX: mmio.Mmio(packed struct(u32) { + /// Stop UART transmitter + TASKS_STOPTX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved28: [12]u8, + /// Suspend UART + TASKS_SUSPEND: mmio.Mmio(packed struct(u32) { + /// Suspend UART + TASKS_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [224]u8, + /// CTS is activated (set low). Clear To Send. + EVENTS_CTS: mmio.Mmio(packed struct(u32) { + /// CTS is activated (set low). Clear To Send. + EVENTS_CTS: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// CTS is deactivated (set high). Not Clear To Send. + EVENTS_NCTS: mmio.Mmio(packed struct(u32) { + /// CTS is deactivated (set high). Not Clear To Send. + EVENTS_NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Data received in RXD + EVENTS_RXDRDY: mmio.Mmio(packed struct(u32) { + /// Data received in RXD + EVENTS_RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved284: [16]u8, + /// Data sent from TXD + EVENTS_TXDRDY: mmio.Mmio(packed struct(u32) { + /// Data sent from TXD + EVENTS_TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved292: [4]u8, + /// Error detected + EVENTS_ERROR: mmio.Mmio(packed struct(u32) { + /// Error detected + EVENTS_ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved324: [28]u8, + /// Receiver timeout + EVENTS_RXTO: mmio.Mmio(packed struct(u32) { + /// Receiver timeout + EVENTS_RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [184]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Shortcut between event CTS and task STARTRX + CTS_STARTRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event NCTS and task STOPRX + NCTS_STOPRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event CTS + CTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event NCTS + NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event RXDRDY + RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u4, + /// Write '1' to enable interrupt for event TXDRDY + TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u1, + /// Write '1' to enable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved17: u7, + /// Write '1' to enable interrupt for event RXTO + RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u14, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event CTS + CTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event NCTS + NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event RXDRDY + RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u4, + /// Write '1' to disable interrupt for event TXDRDY + TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u1, + /// Write '1' to disable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved17: u7, + /// Write '1' to disable interrupt for event RXTO + RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u14, + }), + reserved1152: [372]u8, + /// Error source + ERRORSRC: mmio.Mmio(packed struct(u32) { + /// Overrun error + OVERRUN: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Parity error + PARITY: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Framing error occurred + FRAMING: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Break condition + BREAK: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + padding: u28, + }), + reserved1280: [124]u8, + /// Enable UART + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable UART + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable UART + Disabled = 0x0, + /// Enable UART + Enabled = 0x4, + _, + }, + }, + padding: u28, + }), + reserved1304: [20]u8, + /// RXD register + RXD: mmio.Mmio(packed struct(u32) { + /// RX data received in previous transfers, double buffered + RXD: u8, + padding: u24, + }), + /// TXD register + TXD: mmio.Mmio(packed struct(u32) { + /// TX data to be transferred + TXD: u8, + padding: u24, + }), + reserved1316: [4]u8, + /// Baud rate. Accuracy depends on the HFCLK source selected. + BAUDRATE: mmio.Mmio(packed struct(u32) { + /// Baud rate + BAUDRATE: packed union { + raw: u32, + value: enum(u32) { + /// 1200 baud (actual rate: 1205) + Baud1200 = 0x4f000, + /// 2400 baud (actual rate: 2396) + Baud2400 = 0x9d000, + /// 4800 baud (actual rate: 4808) + Baud4800 = 0x13b000, + /// 9600 baud (actual rate: 9598) + Baud9600 = 0x275000, + /// 14400 baud (actual rate: 14414) + Baud14400 = 0x3b0000, + /// 19200 baud (actual rate: 19208) + Baud19200 = 0x4ea000, + /// 28800 baud (actual rate: 28829) + Baud28800 = 0x75f000, + /// 31250 baud + Baud31250 = 0x800000, + /// 38400 baud (actual rate: 38462) + Baud38400 = 0x9d5000, + /// 56000 baud (actual rate: 55944) + Baud56000 = 0xe50000, + /// 57600 baud (actual rate: 57762) + Baud57600 = 0xebf000, + /// 76800 baud (actual rate: 76923) + Baud76800 = 0x13a9000, + /// 115200 baud (actual rate: 115942) + Baud115200 = 0x1d7e000, + /// 230400 baud (actual rate: 231884) + Baud230400 = 0x3afb000, + /// 250000 baud + Baud250000 = 0x4000000, + /// 460800 baud (actual rate: 470588) + Baud460800 = 0x75f7000, + /// 921600 baud (actual rate: 941176) + Baud921600 = 0xebed000, + /// 1Mega baud + Baud1M = 0x10000000, + _, + }, + }, + }), + reserved1388: [68]u8, + /// Configuration of parity and hardware flow control + CONFIG: mmio.Mmio(packed struct(u32) { + /// Hardware flow control + HWFC: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Parity + PARITY: packed union { + raw: u3, + value: enum(u3) { + /// Exclude parity bit + Excluded = 0x0, + /// Include parity bit + Included = 0x7, + _, + }, + }, + /// Stop bits + STOP: packed union { + raw: u1, + value: enum(u1) { + /// One stop bit + One = 0x0, + /// Two stop bits + Two = 0x1, + }, + }, + padding: u27, + }), + }; + + /// UART with EasyDMA 0 + pub const UARTE0 = extern struct { + /// Start UART receiver + TASKS_STARTRX: mmio.Mmio(packed struct(u32) { + /// Start UART receiver + TASKS_STARTRX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop UART receiver + TASKS_STOPRX: mmio.Mmio(packed struct(u32) { + /// Stop UART receiver + TASKS_STOPRX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start UART transmitter + TASKS_STARTTX: mmio.Mmio(packed struct(u32) { + /// Start UART transmitter + TASKS_STARTTX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop UART transmitter + TASKS_STOPTX: mmio.Mmio(packed struct(u32) { + /// Stop UART transmitter + TASKS_STOPTX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved44: [28]u8, + /// Flush RX FIFO into RX buffer + TASKS_FLUSHRX: mmio.Mmio(packed struct(u32) { + /// Flush RX FIFO into RX buffer + TASKS_FLUSHRX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [208]u8, + /// CTS is activated (set low). Clear To Send. + EVENTS_CTS: mmio.Mmio(packed struct(u32) { + /// CTS is activated (set low). Clear To Send. + EVENTS_CTS: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// CTS is deactivated (set high). Not Clear To Send. + EVENTS_NCTS: mmio.Mmio(packed struct(u32) { + /// CTS is deactivated (set high). Not Clear To Send. + EVENTS_NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Data received in RXD (but potentially not yet transferred to Data RAM) + EVENTS_RXDRDY: mmio.Mmio(packed struct(u32) { + /// Data received in RXD (but potentially not yet transferred to Data RAM) + EVENTS_RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved272: [4]u8, + /// Receive buffer is filled up + EVENTS_ENDRX: mmio.Mmio(packed struct(u32) { + /// Receive buffer is filled up + EVENTS_ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved284: [8]u8, + /// Data sent from TXD + EVENTS_TXDRDY: mmio.Mmio(packed struct(u32) { + /// Data sent from TXD + EVENTS_TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Last TX byte transmitted + EVENTS_ENDTX: mmio.Mmio(packed struct(u32) { + /// Last TX byte transmitted + EVENTS_ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Error detected + EVENTS_ERROR: mmio.Mmio(packed struct(u32) { + /// Error detected + EVENTS_ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved324: [28]u8, + /// Receiver timeout + EVENTS_RXTO: mmio.Mmio(packed struct(u32) { + /// Receiver timeout + EVENTS_RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved332: [4]u8, + /// UART receiver has started + EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) { + /// UART receiver has started + EVENTS_RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// UART transmitter has started + EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) { + /// UART transmitter has started + EVENTS_TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved344: [4]u8, + /// Transmitter stopped + EVENTS_TXSTOPPED: mmio.Mmio(packed struct(u32) { + /// Transmitter stopped + EVENTS_TXSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [164]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Shortcut between event ENDRX and task STARTRX + ENDRX_STARTRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event ENDRX and task STOPRX + ENDRX_STOPRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u25, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for event CTS + CTS: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event NCTS + NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event RXDRDY + RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved4: u1, + /// Enable or disable interrupt for event ENDRX + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved7: u2, + /// Enable or disable interrupt for event TXDRDY + TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDTX + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved17: u7, + /// Enable or disable interrupt for event RXTO + RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved19: u1, + /// Enable or disable interrupt for event RXSTARTED + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TXSTARTED + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved22: u1, + /// Enable or disable interrupt for event TXSTOPPED + TXSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u9, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event CTS + CTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event NCTS + NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event RXDRDY + RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u1, + /// Write '1' to enable interrupt for event ENDRX + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u2, + /// Write '1' to enable interrupt for event TXDRDY + TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDTX + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved17: u7, + /// Write '1' to enable interrupt for event RXTO + RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u1, + /// Write '1' to enable interrupt for event RXSTARTED + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TXSTARTED + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved22: u1, + /// Write '1' to enable interrupt for event TXSTOPPED + TXSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u9, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event CTS + CTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event NCTS + NCTS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event RXDRDY + RXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u1, + /// Write '1' to disable interrupt for event ENDRX + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u2, + /// Write '1' to disable interrupt for event TXDRDY + TXDRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDTX + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved17: u7, + /// Write '1' to disable interrupt for event RXTO + RXTO: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u1, + /// Write '1' to disable interrupt for event RXSTARTED + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TXSTARTED + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved22: u1, + /// Write '1' to disable interrupt for event TXSTOPPED + TXSTOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u9, + }), + reserved1152: [372]u8, + /// Error source Note : this register is read / write one to clear. + ERRORSRC: mmio.Mmio(packed struct(u32) { + /// Overrun error + OVERRUN: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Parity error + PARITY: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Framing error occurred + FRAMING: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// Break condition + BREAK: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + padding: u28, + }), + reserved1280: [124]u8, + /// Enable UART + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable UARTE + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable UARTE + Disabled = 0x0, + /// Enable UARTE + Enabled = 0x8, + _, + }, + }, + padding: u28, + }), + reserved1316: [32]u8, + /// Baud rate. Accuracy depends on the HFCLK source selected. + BAUDRATE: mmio.Mmio(packed struct(u32) { + /// Baud rate + BAUDRATE: packed union { + raw: u32, + value: enum(u32) { + /// 1200 baud (actual rate: 1205) + Baud1200 = 0x4f000, + /// 2400 baud (actual rate: 2396) + Baud2400 = 0x9d000, + /// 4800 baud (actual rate: 4808) + Baud4800 = 0x13b000, + /// 9600 baud (actual rate: 9598) + Baud9600 = 0x275000, + /// 14400 baud (actual rate: 14401) + Baud14400 = 0x3af000, + /// 19200 baud (actual rate: 19208) + Baud19200 = 0x4ea000, + /// 28800 baud (actual rate: 28777) + Baud28800 = 0x75c000, + /// 31250 baud + Baud31250 = 0x800000, + /// 38400 baud (actual rate: 38369) + Baud38400 = 0x9d0000, + /// 56000 baud (actual rate: 55944) + Baud56000 = 0xe50000, + /// 57600 baud (actual rate: 57554) + Baud57600 = 0xeb0000, + /// 76800 baud (actual rate: 76923) + Baud76800 = 0x13a9000, + /// 115200 baud (actual rate: 115108) + Baud115200 = 0x1d60000, + /// 230400 baud (actual rate: 231884) + Baud230400 = 0x3b00000, + /// 250000 baud + Baud250000 = 0x4000000, + /// 460800 baud (actual rate: 457143) + Baud460800 = 0x7400000, + /// 921600 baud (actual rate: 941176) + Baud921600 = 0xf000000, + /// 1Mega baud + Baud1M = 0x10000000, + _, + }, + }, + }), + reserved1388: [68]u8, + /// Configuration of parity and hardware flow control + CONFIG: mmio.Mmio(packed struct(u32) { + /// Hardware flow control + HWFC: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Parity + PARITY: packed union { + raw: u3, + value: enum(u3) { + /// Exclude parity bit + Excluded = 0x0, + /// Include even parity bit + Included = 0x7, + _, + }, + }, + /// Stop bits + STOP: packed union { + raw: u1, + value: enum(u1) { + /// One stop bit + One = 0x0, + /// Two stop bits + Two = 0x1, + }, + }, + padding: u27, + }), + }; + + /// Serial Peripheral Interface 0 + pub const SPI0 = extern struct { + reserved264: [264]u8, + /// TXD byte sent and RXD byte received + EVENTS_READY: mmio.Mmio(packed struct(u32) { + /// TXD byte sent and RXD byte received + EVENTS_READY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved772: [504]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Write '1' to enable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Write '1' to disable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + reserved1280: [500]u8, + /// Enable SPI + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable SPI + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable SPI + Disabled = 0x0, + /// Enable SPI + Enabled = 0x1, + _, + }, + }, + padding: u28, + }), + reserved1304: [20]u8, + /// RXD register + RXD: mmio.Mmio(packed struct(u32) { + /// RX data received. Double buffered + RXD: u8, + padding: u24, + }), + /// TXD register + TXD: mmio.Mmio(packed struct(u32) { + /// TX data to send. Double buffered + TXD: u8, + padding: u24, + }), + reserved1316: [4]u8, + /// SPI frequency. Accuracy depends on the HFCLK source selected. + FREQUENCY: mmio.Mmio(packed struct(u32) { + /// SPI master data rate + FREQUENCY: packed union { + raw: u32, + value: enum(u32) { + /// 125 kbps + K125 = 0x2000000, + /// 250 kbps + K250 = 0x4000000, + /// 500 kbps + K500 = 0x8000000, + /// 1 Mbps + M1 = 0x10000000, + /// 2 Mbps + M2 = 0x20000000, + /// 4 Mbps + M4 = 0x40000000, + /// 8 Mbps + M8 = 0x80000000, + _, + }, + }, + }), + reserved1364: [44]u8, + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Bit order + ORDER: packed union { + raw: u1, + value: enum(u1) { + /// Most significant bit shifted out first + MsbFirst = 0x0, + /// Least significant bit shifted out first + LsbFirst = 0x1, + }, + }, + /// Serial clock (SCK) phase + CPHA: packed union { + raw: u1, + value: enum(u1) { + /// Sample on leading edge of clock, shift serial data on trailing edge + Leading = 0x0, + /// Sample on trailing edge of clock, shift serial data on leading edge + Trailing = 0x1, + }, + }, + /// Serial clock (SCK) polarity + CPOL: packed union { + raw: u1, + value: enum(u1) { + /// Active high + ActiveHigh = 0x0, + /// Active low + ActiveLow = 0x1, + }, + }, + padding: u29, + }), + }; + + /// Serial Peripheral Interface Master with EasyDMA 0 + pub const SPIM0 = extern struct { + reserved16: [16]u8, + /// Start SPI transaction + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Start SPI transaction + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop SPI transaction + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop SPI transaction + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved28: [4]u8, + /// Suspend SPI transaction + TASKS_SUSPEND: mmio.Mmio(packed struct(u32) { + /// Suspend SPI transaction + TASKS_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Resume SPI transaction + TASKS_RESUME: mmio.Mmio(packed struct(u32) { + /// Resume SPI transaction + TASKS_RESUME: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved260: [224]u8, + /// SPI transaction has stopped + EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { + /// SPI transaction has stopped + EVENTS_STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved272: [8]u8, + /// End of RXD buffer reached + EVENTS_ENDRX: mmio.Mmio(packed struct(u32) { + /// End of RXD buffer reached + EVENTS_ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved280: [4]u8, + /// End of RXD buffer and TXD buffer reached + EVENTS_END: mmio.Mmio(packed struct(u32) { + /// End of RXD buffer and TXD buffer reached + EVENTS_END: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved288: [4]u8, + /// End of TXD buffer reached + EVENTS_ENDTX: mmio.Mmio(packed struct(u32) { + /// End of TXD buffer reached + EVENTS_ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved332: [40]u8, + /// Transaction started + EVENTS_STARTED: mmio.Mmio(packed struct(u32) { + /// Transaction started + EVENTS_STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [176]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + reserved17: u17, + /// Shortcut between event END and task START + END_START: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u14, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to enable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u2, + /// Write '1' to enable interrupt for event ENDRX + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved6: u1, + /// Write '1' to enable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved8: u1, + /// Write '1' to enable interrupt for event ENDTX + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u10, + /// Write '1' to enable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u2, + /// Write '1' to disable interrupt for event ENDRX + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved6: u1, + /// Write '1' to disable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved8: u1, + /// Write '1' to disable interrupt for event ENDTX + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u10, + /// Write '1' to disable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + reserved1024: [244]u8, + /// Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. + STALLSTAT: mmio.Mmio(packed struct(u32) { + /// Stall status for EasyDMA RAM reads + TX: packed union { + raw: u1, + value: enum(u1) { + /// No stall + NOSTALL = 0x0, + /// A stall has occurred + STALL = 0x1, + }, + }, + /// Stall status for EasyDMA RAM writes + RX: packed union { + raw: u1, + value: enum(u1) { + /// No stall + NOSTALL = 0x0, + /// A stall has occurred + STALL = 0x1, + }, + }, + padding: u30, + }), + reserved1280: [252]u8, + /// Enable SPIM + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable SPIM + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable SPIM + Disabled = 0x0, + /// Enable SPIM + Enabled = 0x7, + _, + }, + }, + padding: u28, + }), + reserved1316: [32]u8, + /// SPI frequency. Accuracy depends on the HFCLK source selected. + FREQUENCY: mmio.Mmio(packed struct(u32) { + /// SPI master data rate + FREQUENCY: packed union { + raw: u32, + value: enum(u32) { + /// 125 kbps + K125 = 0x2000000, + /// 250 kbps + K250 = 0x4000000, + /// 500 kbps + K500 = 0x8000000, + /// 1 Mbps + M1 = 0x10000000, + /// 2 Mbps + M2 = 0x20000000, + /// 4 Mbps + M4 = 0x40000000, + /// 8 Mbps + M8 = 0x80000000, + /// 16 Mbps + M16 = 0xa000000, + /// 32 Mbps + M32 = 0x14000000, + _, + }, + }, + }), + reserved1364: [44]u8, + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Bit order + ORDER: packed union { + raw: u1, + value: enum(u1) { + /// Most significant bit shifted out first + MsbFirst = 0x0, + /// Least significant bit shifted out first + LsbFirst = 0x1, + }, + }, + /// Serial clock (SCK) phase + CPHA: packed union { + raw: u1, + value: enum(u1) { + /// Sample on leading edge of clock, shift serial data on trailing edge + Leading = 0x0, + /// Sample on trailing edge of clock, shift serial data on leading edge + Trailing = 0x1, + }, + }, + /// Serial clock (SCK) polarity + CPOL: packed union { + raw: u1, + value: enum(u1) { + /// Active high + ActiveHigh = 0x0, + /// Active low + ActiveLow = 0x1, + }, + }, + padding: u29, + }), + reserved1384: [16]u8, + /// Polarity of CSN output + CSNPOL: mmio.Mmio(packed struct(u32) { + /// Polarity of CSN output + CSNPOL: packed union { + raw: u1, + value: enum(u1) { + /// Active low (idle state high) + LOW = 0x0, + /// Active high (idle state low) + HIGH = 0x1, + }, + }, + padding: u31, + }), + /// Pin select for DCX signal + PSELDCX: mmio.Mmio(packed struct(u32) { + /// Pin number + PIN: u5, + /// Port number + PORT: u1, + reserved31: u25, + /// Connection + CONNECT: packed union { + raw: u1, + value: enum(u1) { + /// Disconnect + Disconnected = 0x1, + /// Connect + Connected = 0x0, + }, + }, + }), + /// DCX configuration + DCXCNT: mmio.Mmio(packed struct(u32) { + /// This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + DCXCNT: u4, + padding: u28, + }), + reserved1472: [76]u8, + /// Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + ORC: mmio.Mmio(packed struct(u32) { + /// Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + ORC: u8, + padding: u24, + }), + }; + + /// SPI Slave 0 + pub const SPIS0 = extern struct { + reserved36: [36]u8, + /// Acquire SPI semaphore + TASKS_ACQUIRE: mmio.Mmio(packed struct(u32) { + /// Acquire SPI semaphore + TASKS_ACQUIRE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Release SPI semaphore, enabling the SPI slave to acquire it + TASKS_RELEASE: mmio.Mmio(packed struct(u32) { + /// Release SPI semaphore, enabling the SPI slave to acquire it + TASKS_RELEASE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved260: [216]u8, + /// Granted transaction completed + EVENTS_END: mmio.Mmio(packed struct(u32) { + /// Granted transaction completed + EVENTS_END: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved272: [8]u8, + /// End of RXD buffer reached + EVENTS_ENDRX: mmio.Mmio(packed struct(u32) { + /// End of RXD buffer reached + EVENTS_ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved296: [20]u8, + /// Semaphore acquired + EVENTS_ACQUIRED: mmio.Mmio(packed struct(u32) { + /// Semaphore acquired + EVENTS_ACQUIRED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [212]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Shortcut between event END and task ACQUIRE + END_ACQUIRE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u29, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to enable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u2, + /// Write '1' to enable interrupt for event ENDRX + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u5, + /// Write '1' to enable interrupt for event ACQUIRED + ACQUIRED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u21, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to disable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved4: u2, + /// Write '1' to disable interrupt for event ENDRX + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u5, + /// Write '1' to disable interrupt for event ACQUIRED + ACQUIRED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u21, + }), + reserved1024: [244]u8, + /// Semaphore status register + SEMSTAT: mmio.Mmio(packed struct(u32) { + /// Semaphore status + SEMSTAT: packed union { + raw: u2, + value: enum(u2) { + /// Semaphore is free + Free = 0x0, + /// Semaphore is assigned to CPU + CPU = 0x1, + /// Semaphore is assigned to SPI slave + SPIS = 0x2, + /// Semaphore is assigned to SPI but a handover to the CPU is pending + CPUPending = 0x3, + }, + }, + padding: u30, + }), + reserved1088: [60]u8, + /// Status from last transaction + STATUS: mmio.Mmio(packed struct(u32) { + /// TX buffer over-read detected, and prevented + OVERREAD: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// RX buffer overflow detected, and prevented + OVERFLOW: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + padding: u30, + }), + reserved1280: [188]u8, + /// Enable SPI slave + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable SPI slave + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable SPI slave + Disabled = 0x0, + /// Enable SPI slave + Enabled = 0x2, + _, + }, + }, + padding: u28, + }), + reserved1364: [80]u8, + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Bit order + ORDER: packed union { + raw: u1, + value: enum(u1) { + /// Most significant bit shifted out first + MsbFirst = 0x0, + /// Least significant bit shifted out first + LsbFirst = 0x1, + }, + }, + /// Serial clock (SCK) phase + CPHA: packed union { + raw: u1, + value: enum(u1) { + /// Sample on leading edge of clock, shift serial data on trailing edge + Leading = 0x0, + /// Sample on trailing edge of clock, shift serial data on leading edge + Trailing = 0x1, + }, + }, + /// Serial clock (SCK) polarity + CPOL: packed union { + raw: u1, + value: enum(u1) { + /// Active high + ActiveHigh = 0x0, + /// Active low + ActiveLow = 0x1, + }, + }, + padding: u29, + }), + reserved1372: [4]u8, + /// Default character. Character clocked out in case of an ignored transaction. + DEF: mmio.Mmio(packed struct(u32) { + /// Default character. Character clocked out in case of an ignored transaction. + DEF: u8, + padding: u24, + }), + reserved1472: [96]u8, + /// Over-read character + ORC: mmio.Mmio(packed struct(u32) { + /// Over-read character. Character clocked out after an over-read of the transmit buffer. + ORC: u8, + padding: u24, + }), + }; + + /// I2C compatible Two-Wire Interface 0 + pub const TWI0 = extern struct { + /// Start TWI receive sequence + TASKS_STARTRX: mmio.Mmio(packed struct(u32) { + /// Start TWI receive sequence + TASKS_STARTRX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved8: [4]u8, + /// Start TWI transmit sequence + TASKS_STARTTX: mmio.Mmio(packed struct(u32) { + /// Start TWI transmit sequence + TASKS_STARTTX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved20: [8]u8, + /// Stop TWI transaction + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop TWI transaction + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved28: [4]u8, + /// Suspend TWI transaction + TASKS_SUSPEND: mmio.Mmio(packed struct(u32) { + /// Suspend TWI transaction + TASKS_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Resume TWI transaction + TASKS_RESUME: mmio.Mmio(packed struct(u32) { + /// Resume TWI transaction + TASKS_RESUME: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved260: [224]u8, + /// TWI stopped + EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { + /// TWI stopped + EVENTS_STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// TWI RXD byte received + EVENTS_RXDREADY: mmio.Mmio(packed struct(u32) { + /// TWI RXD byte received + EVENTS_RXDREADY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved284: [16]u8, + /// TWI TXD byte sent + EVENTS_TXDSENT: mmio.Mmio(packed struct(u32) { + /// TWI TXD byte sent + EVENTS_TXDSENT: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved292: [4]u8, + /// TWI error + EVENTS_ERROR: mmio.Mmio(packed struct(u32) { + /// TWI error + EVENTS_ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved312: [16]u8, + /// TWI byte boundary, generated before each byte that is sent or received + EVENTS_BB: mmio.Mmio(packed struct(u32) { + /// TWI byte boundary, generated before each byte that is sent or received + EVENTS_BB: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved328: [12]u8, + /// TWI entered the suspended state + EVENTS_SUSPENDED: mmio.Mmio(packed struct(u32) { + /// TWI entered the suspended state + EVENTS_SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [180]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between event BB and task SUSPEND + BB_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event BB and task STOP + BB_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u30, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to enable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event RXDREADY + RXDREADY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u4, + /// Write '1' to enable interrupt for event TXDSENT + TXDSENT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u1, + /// Write '1' to enable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved14: u4, + /// Write '1' to enable interrupt for event BB + BB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u3, + /// Write '1' to enable interrupt for event SUSPENDED + SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u13, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event RXDREADY + RXDREADY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved7: u4, + /// Write '1' to disable interrupt for event TXDSENT + TXDSENT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u1, + /// Write '1' to disable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved14: u4, + /// Write '1' to disable interrupt for event BB + BB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u3, + /// Write '1' to disable interrupt for event SUSPENDED + SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u13, + }), + reserved1220: [440]u8, + /// Error source + ERRORSRC: mmio.Mmio(packed struct(u32) { + /// Overrun error + OVERRUN: packed union { + raw: u1, + value: enum(u1) { + /// Read: no overrun occured + NotPresent = 0x0, + /// Read: overrun occured + Present = 0x1, + }, + }, + /// NACK received after sending the address (write '1' to clear) + ANACK: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: packed union { + raw: u1, + value: enum(u1) { + /// Read: error not present + NotPresent = 0x0, + /// Read: error present + Present = 0x1, + }, + }, + padding: u29, + }), + reserved1280: [56]u8, + /// Enable TWI + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable TWI + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable TWI + Disabled = 0x0, + /// Enable TWI + Enabled = 0x5, + _, + }, + }, + padding: u28, + }), + reserved1304: [20]u8, + /// RXD register + RXD: mmio.Mmio(packed struct(u32) { + /// RXD register + RXD: u8, + padding: u24, + }), + /// TXD register + TXD: mmio.Mmio(packed struct(u32) { + /// TXD register + TXD: u8, + padding: u24, + }), + reserved1316: [4]u8, + /// TWI frequency. Accuracy depends on the HFCLK source selected. + FREQUENCY: mmio.Mmio(packed struct(u32) { + /// TWI master clock frequency + FREQUENCY: packed union { + raw: u32, + value: enum(u32) { + /// 100 kbps + K100 = 0x1980000, + /// 250 kbps + K250 = 0x4000000, + /// 400 kbps (actual rate 410.256 kbps) + K400 = 0x6680000, + _, + }, + }, + }), + reserved1416: [96]u8, + /// Address used in the TWI transfer + ADDRESS: mmio.Mmio(packed struct(u32) { + /// Address used in the TWI transfer + ADDRESS: u7, + padding: u25, + }), + }; + + /// I2C compatible Two-Wire Master Interface with EasyDMA 0 + pub const TWIM0 = extern struct { + /// Start TWI receive sequence + TASKS_STARTRX: mmio.Mmio(packed struct(u32) { + /// Start TWI receive sequence + TASKS_STARTRX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved8: [4]u8, + /// Start TWI transmit sequence + TASKS_STARTTX: mmio.Mmio(packed struct(u32) { + /// Start TWI transmit sequence + TASKS_STARTTX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved20: [8]u8, + /// Stop TWI transaction. Must be issued while the TWI master is not suspended. + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop TWI transaction. Must be issued while the TWI master is not suspended. + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved28: [4]u8, + /// Suspend TWI transaction + TASKS_SUSPEND: mmio.Mmio(packed struct(u32) { + /// Suspend TWI transaction + TASKS_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Resume TWI transaction + TASKS_RESUME: mmio.Mmio(packed struct(u32) { + /// Resume TWI transaction + TASKS_RESUME: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved260: [224]u8, + /// TWI stopped + EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { + /// TWI stopped + EVENTS_STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved292: [28]u8, + /// TWI error + EVENTS_ERROR: mmio.Mmio(packed struct(u32) { + /// TWI error + EVENTS_ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved328: [32]u8, + /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + EVENTS_SUSPENDED: mmio.Mmio(packed struct(u32) { + /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + EVENTS_SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Receive sequence started + EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) { + /// Receive sequence started + EVENTS_RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Transmit sequence started + EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) { + /// Transmit sequence started + EVENTS_TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved348: [8]u8, + /// Byte boundary, starting to receive the last byte + EVENTS_LASTRX: mmio.Mmio(packed struct(u32) { + /// Byte boundary, starting to receive the last byte + EVENTS_LASTRX: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Byte boundary, starting to transmit the last byte + EVENTS_LASTTX: mmio.Mmio(packed struct(u32) { + /// Byte boundary, starting to transmit the last byte + EVENTS_LASTTX: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [156]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + reserved7: u7, + /// Shortcut between event LASTTX and task STARTRX + LASTTX_STARTRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event LASTTX and task SUSPEND + LASTTX_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event LASTTX and task STOP + LASTTX_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event LASTRX and task STARTTX + LASTRX_STARTTX: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event LASTRX and task SUSPEND + LASTRX_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event LASTRX and task STOP + LASTRX_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u19, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Enable or disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Enable or disable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved18: u8, + /// Enable or disable interrupt for event SUSPENDED + SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event RXSTARTED + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TXSTARTED + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved23: u2, + /// Enable or disable interrupt for event LASTRX + LASTRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event LASTTX + LASTTX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u7, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to enable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Write '1' to enable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u8, + /// Write '1' to enable interrupt for event SUSPENDED + SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event RXSTARTED + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TXSTARTED + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved23: u2, + /// Write '1' to enable interrupt for event LASTRX + LASTRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event LASTTX + LASTTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u7, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Write '1' to disable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u8, + /// Write '1' to disable interrupt for event SUSPENDED + SUSPENDED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event RXSTARTED + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TXSTARTED + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved23: u2, + /// Write '1' to disable interrupt for event LASTRX + LASTRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event LASTTX + LASTTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u7, + }), + reserved1220: [440]u8, + /// Error source + ERRORSRC: mmio.Mmio(packed struct(u32) { + /// Overrun error + OVERRUN: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotReceived = 0x0, + /// Error occurred + Received = 0x1, + }, + }, + /// NACK received after sending the address (write '1' to clear) + ANACK: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotReceived = 0x0, + /// Error occurred + Received = 0x1, + }, + }, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotReceived = 0x0, + /// Error occurred + Received = 0x1, + }, + }, + padding: u29, + }), + reserved1280: [56]u8, + /// Enable TWIM + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable TWIM + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable TWIM + Disabled = 0x0, + /// Enable TWIM + Enabled = 0x6, + _, + }, + }, + padding: u28, + }), + reserved1316: [32]u8, + /// TWI frequency. Accuracy depends on the HFCLK source selected. + FREQUENCY: mmio.Mmio(packed struct(u32) { + /// TWI master clock frequency + FREQUENCY: packed union { + raw: u32, + value: enum(u32) { + /// 100 kbps + K100 = 0x1980000, + /// 250 kbps + K250 = 0x4000000, + /// 400 kbps + K400 = 0x6400000, + _, + }, + }, + }), + reserved1416: [96]u8, + /// Address used in the TWI transfer + ADDRESS: mmio.Mmio(packed struct(u32) { + /// Address used in the TWI transfer + ADDRESS: u7, + padding: u25, + }), + }; + + /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 + pub const TWIS0 = extern struct { + reserved20: [20]u8, + /// Stop TWI transaction + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop TWI transaction + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved28: [4]u8, + /// Suspend TWI transaction + TASKS_SUSPEND: mmio.Mmio(packed struct(u32) { + /// Suspend TWI transaction + TASKS_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Resume TWI transaction + TASKS_RESUME: mmio.Mmio(packed struct(u32) { + /// Resume TWI transaction + TASKS_RESUME: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved48: [12]u8, + /// Prepare the TWI slave to respond to a write command + TASKS_PREPARERX: mmio.Mmio(packed struct(u32) { + /// Prepare the TWI slave to respond to a write command + TASKS_PREPARERX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Prepare the TWI slave to respond to a read command + TASKS_PREPARETX: mmio.Mmio(packed struct(u32) { + /// Prepare the TWI slave to respond to a read command + TASKS_PREPARETX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved260: [204]u8, + /// TWI stopped + EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { + /// TWI stopped + EVENTS_STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved292: [28]u8, + /// TWI error + EVENTS_ERROR: mmio.Mmio(packed struct(u32) { + /// TWI error + EVENTS_ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved332: [36]u8, + /// Receive sequence started + EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) { + /// Receive sequence started + EVENTS_RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Transmit sequence started + EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) { + /// Transmit sequence started + EVENTS_TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved356: [16]u8, + /// Write command received + EVENTS_WRITE: mmio.Mmio(packed struct(u32) { + /// Write command received + EVENTS_WRITE: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Read command received + EVENTS_READ: mmio.Mmio(packed struct(u32) { + /// Read command received + EVENTS_READ: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [148]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// Shortcut between event WRITE and task SUSPEND + WRITE_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event READ and task SUSPEND + READ_SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u17, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Enable or disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Enable or disable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved19: u9, + /// Enable or disable interrupt for event RXSTARTED + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TXSTARTED + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved25: u4, + /// Enable or disable interrupt for event WRITE + WRITE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event READ + READ: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u5, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to enable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Write '1' to enable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u9, + /// Write '1' to enable interrupt for event RXSTARTED + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TXSTARTED + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved25: u4, + /// Write '1' to enable interrupt for event WRITE + WRITE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event READ + READ: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u5, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved9: u7, + /// Write '1' to disable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved19: u9, + /// Write '1' to disable interrupt for event RXSTARTED + RXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TXSTARTED + TXSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved25: u4, + /// Write '1' to disable interrupt for event WRITE + WRITE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event READ + READ: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u5, + }), + reserved1232: [452]u8, + /// Error source + ERRORSRC: mmio.Mmio(packed struct(u32) { + /// RX buffer overflow detected, and prevented + OVERFLOW: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotDetected = 0x0, + /// Error occurred + Detected = 0x1, + }, + }, + reserved2: u1, + /// NACK sent after receiving a data byte + DNACK: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotReceived = 0x0, + /// Error occurred + Received = 0x1, + }, + }, + /// TX buffer over-read detected, and prevented + OVERREAD: packed union { + raw: u1, + value: enum(u1) { + /// Error did not occur + NotDetected = 0x0, + /// Error occurred + Detected = 0x1, + }, + }, + padding: u28, + }), + /// Status register indicating which address had a match + MATCH: mmio.Mmio(packed struct(u32) { + /// Which of the addresses in {ADDRESS} matched the incoming address + MATCH: u1, + padding: u31, + }), + reserved1280: [40]u8, + /// Enable TWIS + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable TWIS + ENABLE: packed union { + raw: u4, + value: enum(u4) { + /// Disable TWIS + Disabled = 0x0, + /// Enable TWIS + Enabled = 0x9, + _, + }, + }, + padding: u28, + }), + reserved1416: [132]u8, + /// Description collection: TWI slave address n + ADDRESS: [2]mmio.Mmio(packed struct(u32) { + /// TWI slave address + ADDRESS: u7, + padding: u25, + }), + reserved1428: [4]u8, + /// Configuration register for the address match mechanism + CONFIG: mmio.Mmio(packed struct(u32) { + /// Enable or disable address matching on ADDRESS[0] + ADDRESS0: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + /// Enable or disable address matching on ADDRESS[1] + ADDRESS1: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + padding: u30, + }), + reserved1472: [40]u8, + /// Over-read character. Character sent out in case of an over-read of the transmit buffer. + ORC: mmio.Mmio(packed struct(u32) { + /// Over-read character. Character sent out in case of an over-read of the transmit buffer. + ORC: u8, + padding: u24, + }), + }; + + /// Pulse Density Modulation (Digital Microphone) Interface + pub const PDM = extern struct { + /// Starts continuous PDM transfer + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Starts continuous PDM transfer + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stops PDM transfer + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stops PDM transfer + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [248]u8, + /// PDM transfer has started + EVENTS_STARTED: mmio.Mmio(packed struct(u32) { + /// PDM transfer has started + EVENTS_STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// PDM transfer has finished + EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { + /// PDM transfer has finished + EVENTS_STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + EVENTS_END: mmio.Mmio(packed struct(u32) { + /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + EVENTS_END: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved768: [500]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u29, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + reserved1280: [500]u8, + /// PDM module enable register + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable PDM module + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// PDM clock generator control + PDMCLKCTRL: mmio.Mmio(packed struct(u32) { + /// PDM_CLK frequency + FREQ: packed union { + raw: u32, + value: enum(u32) { + /// PDM_CLK = 32 MHz / 32 = 1.000 MHz + @"1000K" = 0x8000000, + /// PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + Default = 0x8400000, + /// PDM_CLK = 32 MHz / 30 = 1.067 MHz + @"1067K" = 0x8800000, + /// PDM_CLK = 32 MHz / 26 = 1.231 MHz + @"1231K" = 0x9800000, + /// PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + @"1280K" = 0xa000000, + /// PDM_CLK = 32 MHz / 24 = 1.333 MHz + @"1333K" = 0xa800000, + _, + }, + }, + }), + /// Defines the routing of the connected PDM microphones' signals + MODE: mmio.Mmio(packed struct(u32) { + /// Mono or stereo operation + OPERATION: packed union { + raw: u1, + value: enum(u1) { + /// Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] + Stereo = 0x0, + /// Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] + Mono = 0x1, + }, + }, + /// Defines on which PDM_CLK edge Left (or mono) is sampled + EDGE: packed union { + raw: u1, + value: enum(u1) { + /// Left (or mono) is sampled on falling edge of PDM_CLK + LeftFalling = 0x0, + /// Left (or mono) is sampled on rising edge of PDM_CLK + LeftRising = 0x1, + }, + }, + padding: u30, + }), + reserved1304: [12]u8, + /// Left output gain adjustment + GAINL: mmio.Mmio(packed struct(u32) { + /// Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + GAINL: packed union { + raw: u7, + value: enum(u7) { + /// -20dB gain adjustment (minimum) + MinGain = 0x0, + /// 0dB gain adjustment + DefaultGain = 0x28, + /// +20dB gain adjustment (maximum) + MaxGain = 0x50, + _, + }, + }, + padding: u25, + }), + /// Right output gain adjustment + GAINR: mmio.Mmio(packed struct(u32) { + /// Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + GAINR: packed union { + raw: u7, + value: enum(u7) { + /// -20dB gain adjustment (minimum) + MinGain = 0x0, + /// 0dB gain adjustment + DefaultGain = 0x28, + /// +20dB gain adjustment (maximum) + MaxGain = 0x50, + _, + }, + }, + padding: u25, + }), + /// Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + RATIO: mmio.Mmio(packed struct(u32) { + /// Selects the ratio between PDM_CLK and output sample rate + RATIO: packed union { + raw: u1, + value: enum(u1) { + /// Ratio of 64 + Ratio64 = 0x0, + /// Ratio of 80 + Ratio80 = 0x1, + }, + }, + padding: u31, + }), + }; + + /// ARM TrustZone CryptoCell register interface + pub const CRYPTOCELL = extern struct { + reserved1280: [1280]u8, + /// Enable CRYPTOCELL subsystem + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable the CRYPTOCELL subsystem + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// CRYPTOCELL subsystem disabled + Disabled = 0x0, + /// CRYPTOCELL subsystem enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + }; + + /// CRYPTOCELL HOST_RGF interface + pub const CC_HOST_RGF = extern struct { + reserved6712: [6712]u8, + /// AES hardware key select + HOST_CRYPTOKEY_SEL: mmio.Mmio(packed struct(u32) { + /// Select the source of the HW key that is used by the AES engine + HOST_CRYPTOKEY_SEL: packed union { + raw: u2, + value: enum(u2) { + /// Use device root key K_DR from CRYPTOCELL AO power domain + K_DR = 0x0, + /// Use hard-coded RTL key K_PRTL + K_PRTL = 0x1, + /// Use provided session key + Session = 0x2, + _, + }, + }, + padding: u30, + }), + reserved6732: [16]u8, + /// This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + HOST_IOT_KPRTL_LOCK: mmio.Mmio(packed struct(u32) { + /// This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + HOST_IOT_KPRTL_LOCK: packed union { + raw: u1, + value: enum(u1) { + /// K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL + Disabled = 0x0, + /// K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. + HOST_IOT_KDR0: mmio.Mmio(packed struct(u32) { + /// Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain + HOST_IOT_KDR0: u32, + }), + /// This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + HOST_IOT_KDR1: mmio.Mmio(packed struct(u32) { + /// K_DR bits 63:32 + HOST_IOT_KDR1: u32, + }), + /// This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + HOST_IOT_KDR2: mmio.Mmio(packed struct(u32) { + /// K_DR bits 95:64 + HOST_IOT_KDR2: u32, + }), + /// This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + HOST_IOT_KDR3: mmio.Mmio(packed struct(u32) { + /// K_DR bits 127:96 + HOST_IOT_KDR3: u32, + }), + /// Controls lifecycle state (LCS) for CRYPTOCELL subsystem + HOST_IOT_LCS: mmio.Mmio(packed struct(u32) { + /// Lifecycle state value. This field is write-once per reset. + LCS: packed union { + raw: u3, + value: enum(u3) { + /// CC310 operates in debug mode + Debug = 0x0, + /// CC310 operates in secure mode + Secure = 0x2, + _, + }, + }, + reserved8: u5, + /// This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset + LCS_IS_VALID: packed union { + raw: u1, + value: enum(u1) { + /// A valid LCS is not yet retained in the CRYPTOCELL AO power domain + Invalid = 0x0, + /// A valid LCS is successfully retained in the CRYPTOCELL AO power domain + Valid = 0x1, + }, + }, + padding: u23, + }), + }; + + /// External flash interface + pub const QSPI = extern struct { + /// Activate QSPI interface + TASKS_ACTIVATE: mmio.Mmio(packed struct(u32) { + /// Activate QSPI interface + TASKS_ACTIVATE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start transfer from external flash memory to internal RAM + TASKS_READSTART: mmio.Mmio(packed struct(u32) { + /// Start transfer from external flash memory to internal RAM + TASKS_READSTART: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start transfer from internal RAM to external flash memory + TASKS_WRITESTART: mmio.Mmio(packed struct(u32) { + /// Start transfer from internal RAM to external flash memory + TASKS_WRITESTART: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start external flash memory erase operation + TASKS_ERASESTART: mmio.Mmio(packed struct(u32) { + /// Start external flash memory erase operation + TASKS_ERASESTART: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Deactivate QSPI interface + TASKS_DEACTIVATE: mmio.Mmio(packed struct(u32) { + /// Deactivate QSPI interface + TASKS_DEACTIVATE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [236]u8, + /// QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + EVENTS_READY: mmio.Mmio(packed struct(u32) { + /// QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + EVENTS_READY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved768: [508]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1280: [500]u8, + /// Enable QSPI peripheral and acquire the pins selected in PSELn registers + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable QSPI + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable QSPI + Disabled = 0x0, + /// Enable QSPI + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1344: [60]u8, + /// Address offset into the external memory for Execute in Place operation. + XIPOFFSET: mmio.Mmio(packed struct(u32) { + /// Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. + XIPOFFSET: u32, + }), + /// Interface configuration. + IFCONFIG0: mmio.Mmio(packed struct(u32) { + /// Configure number of data lines and opcode used for reading. + READOC: packed union { + raw: u3, + value: enum(u3) { + /// Single data line SPI. FAST_READ (opcode 0x0B). + FASTREAD = 0x0, + /// Dual data line SPI. READ2O (opcode 0x3B). + READ2O = 0x1, + /// Dual data line SPI. READ2IO (opcode 0xBB). + READ2IO = 0x2, + /// Quad data line SPI. READ4O (opcode 0x6B). + READ4O = 0x3, + /// Quad data line SPI. READ4IO (opcode 0xEB). + READ4IO = 0x4, + _, + }, + }, + /// Configure number of data lines and opcode used for writing. + WRITEOC: packed union { + raw: u3, + value: enum(u3) { + /// Single data line SPI. PP (opcode 0x02). + PP = 0x0, + /// Dual data line SPI. PP2O (opcode 0xA2). + PP2O = 0x1, + /// Quad data line SPI. PP4O (opcode 0x32). + PP4O = 0x2, + /// Quad data line SPI. PP4IO (opcode 0x38). + PP4IO = 0x3, + _, + }, + }, + /// Addressing mode. + ADDRMODE: packed union { + raw: u1, + value: enum(u1) { + /// 24-bit addressing. + @"24BIT" = 0x0, + /// 32-bit addressing. + @"32BIT" = 0x1, + }, + }, + /// Enable deep power-down mode (DPM) feature. + DPMENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable DPM feature. + Disable = 0x0, + /// Enable DPM feature. + Enable = 0x1, + }, + }, + reserved12: u4, + /// Page size for commands PP, PP2O, PP4O and PP4IO. + PPSIZE: packed union { + raw: u1, + value: enum(u1) { + /// 256 bytes. + @"256Bytes" = 0x0, + /// 512 bytes. + @"512Bytes" = 0x1, + }, + }, + padding: u19, + }), + reserved1536: [184]u8, + /// Interface configuration. + IFCONFIG1: mmio.Mmio(packed struct(u32) { + /// Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). + SCKDELAY: u8, + reserved24: u16, + /// Enter/exit deep power-down mode (DPM) for external flash memory. + DPMEN: packed union { + raw: u1, + value: enum(u1) { + /// Exit DPM. + Exit = 0x0, + /// Enter DPM. + Enter = 0x1, + }, + }, + /// Select SPI mode. + SPIMODE: packed union { + raw: u1, + value: enum(u1) { + /// Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). + MODE0 = 0x0, + /// Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). + MODE3 = 0x1, + }, + }, + reserved28: u2, + /// SCK frequency is given as 32 MHz / (SCKFREQ + 1). + SCKFREQ: u4, + }), + /// Status register. + STATUS: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Deep power-down mode (DPM) status of external flash. + DPM: packed union { + raw: u1, + value: enum(u1) { + /// External flash is not in DPM. + Disabled = 0x0, + /// External flash is in DPM. + Enabled = 0x1, + }, + }, + /// Ready status. + READY: packed union { + raw: u1, + value: enum(u1) { + /// QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. + READY = 0x1, + /// QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. + BUSY = 0x0, + }, + }, + reserved24: u20, + /// Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. + SREG: u8, + }), + reserved1556: [12]u8, + /// Set the duration required to enter/exit deep power-down mode (DPM). + DPMDUR: mmio.Mmio(packed struct(u32) { + /// Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. + ENTER: u16, + /// Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. + EXIT: u16, + }), + reserved1572: [12]u8, + /// Extended address configuration. + ADDRCONF: mmio.Mmio(packed struct(u32) { + /// Opcode that enters the 32-bit addressing mode. + OPCODE: u8, + /// Byte 0 following opcode. + BYTE0: u8, + /// Byte 1 following byte 0. + BYTE1: u8, + /// Extended addressing mode. + MODE: packed union { + raw: u2, + value: enum(u2) { + /// Do not send any instruction. + NoInstr = 0x0, + /// Send opcode. + Opcode = 0x1, + /// Send opcode, byte0. + OpByte0 = 0x2, + /// Send opcode, byte0, byte1. + All = 0x3, + }, + }, + /// Wait for write complete before sending command. + WIPWAIT: packed union { + raw: u1, + value: enum(u1) { + /// No wait. + Disable = 0x0, + /// Wait. + Enable = 0x1, + }, + }, + /// Send WREN (write enable opcode 0x06) before instruction. + WREN: packed union { + raw: u1, + value: enum(u1) { + /// Do not send WREN. + Disable = 0x0, + /// Send WREN. + Enable = 0x1, + }, + }, + padding: u4, + }), + reserved1588: [12]u8, + /// Custom instruction configuration register. + CINSTRCONF: mmio.Mmio(packed struct(u32) { + /// Opcode of Custom instruction. + OPCODE: u8, + /// Length of custom instruction in number of bytes. + LENGTH: packed union { + raw: u4, + value: enum(u4) { + /// Send opcode only. + @"1B" = 0x1, + /// Send opcode, CINSTRDAT0.BYTE0. + @"2B" = 0x2, + /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. + @"3B" = 0x3, + /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. + @"4B" = 0x4, + /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. + @"5B" = 0x5, + /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. + @"6B" = 0x6, + /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. + @"7B" = 0x7, + /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. + @"8B" = 0x8, + /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. + @"9B" = 0x9, + _, + }, + }, + /// Level of the IO2 pin (if connected) during transmission of custom instruction. + LIO2: u1, + /// Level of the IO3 pin (if connected) during transmission of custom instruction. + LIO3: u1, + /// Wait for write complete before sending command. + WIPWAIT: packed union { + raw: u1, + value: enum(u1) { + /// No wait. + Disable = 0x0, + /// Wait. + Enable = 0x1, + }, + }, + /// Send WREN (write enable opcode 0x06) before instruction. + WREN: packed union { + raw: u1, + value: enum(u1) { + /// Do not send WREN. + Disable = 0x0, + /// Send WREN. + Enable = 0x1, + }, + }, + /// Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. + LFEN: packed union { + raw: u1, + value: enum(u1) { + /// Long frame mode disabled + Disable = 0x0, + /// Long frame mode enabled + Enable = 0x1, + }, + }, + /// Stop (finalize) long frame transaction + LFSTOP: packed union { + raw: u1, + value: enum(u1) { + /// Stop + Stop = 0x1, + _, + }, + }, + padding: u14, + }), + /// Custom instruction data register 0. + CINSTRDAT0: mmio.Mmio(packed struct(u32) { + /// Data byte 0 + BYTE0: u8, + /// Data byte 1 + BYTE1: u8, + /// Data byte 2 + BYTE2: u8, + /// Data byte 3 + BYTE3: u8, + }), + /// Custom instruction data register 1. + CINSTRDAT1: mmio.Mmio(packed struct(u32) { + /// Data byte 4 + BYTE4: u8, + /// Data byte 5 + BYTE5: u8, + /// Data byte 6 + BYTE6: u8, + /// Data byte 7 + BYTE7: u8, + }), + /// SPI interface timing. + IFTIMING: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. + RXDELAY: u3, + padding: u21, + }), + }; + + /// Pulse width modulation unit 0 + pub const PWM0 = extern struct { + reserved4: [4]u8, + /// Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + TASKS_SEQSTART: [2]mmio.Mmio(packed struct(u32) { + /// Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + TASKS_SEQSTART: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + TASKS_NEXTSTEP: mmio.Mmio(packed struct(u32) { + /// Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + TASKS_NEXTSTEP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved260: [240]u8, + /// Response to STOP task, emitted when PWM pulses are no longer generated + EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { + /// Response to STOP task, emitted when PWM pulses are no longer generated + EVENTS_STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Description collection: First PWM period started on sequence n + EVENTS_SEQSTARTED: [2]mmio.Mmio(packed struct(u32) { + /// First PWM period started on sequence n + EVENTS_SEQSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + EVENTS_SEQEND: [2]mmio.Mmio(packed struct(u32) { + /// Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + EVENTS_SEQEND: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Emitted at the end of each PWM period + EVENTS_PWMPERIODEND: mmio.Mmio(packed struct(u32) { + /// Emitted at the end of each PWM period + EVENTS_PWMPERIODEND: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Concatenated sequences have been played the amount of times defined in LOOP.CNT + EVENTS_LOOPSDONE: mmio.Mmio(packed struct(u32) { + /// Concatenated sequences have been played the amount of times defined in LOOP.CNT + EVENTS_LOOPSDONE: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [224]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between event SEQEND[0] and task STOP + SEQEND0_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event SEQEND[1] and task STOP + SEQEND1_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event LOOPSDONE and task SEQSTART[0] + LOOPSDONE_SEQSTART0: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event LOOPSDONE and task SEQSTART[1] + LOOPSDONE_SEQSTART1: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event LOOPSDONE and task STOP + LOOPSDONE_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Enable or disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event SEQSTARTED[0] + SEQSTARTED0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event SEQSTARTED[1] + SEQSTARTED1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event SEQEND[0] + SEQEND0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event SEQEND[1] + SEQEND1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event PWMPERIODEND + PWMPERIODEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event LOOPSDONE + LOOPSDONE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u24, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to enable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event SEQSTARTED[0] + SEQSTARTED0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event SEQSTARTED[1] + SEQSTARTED1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event SEQEND[0] + SEQEND0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event SEQEND[1] + SEQEND1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event PWMPERIODEND + PWMPERIODEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event LOOPSDONE + LOOPSDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u24, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event SEQSTARTED[0] + SEQSTARTED0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event SEQSTARTED[1] + SEQSTARTED1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event SEQEND[0] + SEQEND0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event SEQEND[1] + SEQEND1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event PWMPERIODEND + PWMPERIODEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event LOOPSDONE + LOOPSDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u24, + }), + reserved1280: [500]u8, + /// PWM module enable register + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable PWM module + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Selects operating mode of the wave counter + MODE: mmio.Mmio(packed struct(u32) { + /// Selects up mode or up-and-down mode for the counter + UPDOWN: packed union { + raw: u1, + value: enum(u1) { + /// Up counter, edge-aligned PWM duty cycle + Up = 0x0, + /// Up and down counter, center-aligned PWM duty cycle + UpAndDown = 0x1, + }, + }, + padding: u31, + }), + /// Value up to which the pulse generator counter counts + COUNTERTOP: mmio.Mmio(packed struct(u32) { + /// Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + COUNTERTOP: u15, + padding: u17, + }), + /// Configuration for PWM_CLK + PRESCALER: mmio.Mmio(packed struct(u32) { + /// Prescaler of PWM_CLK + PRESCALER: packed union { + raw: u3, + value: enum(u3) { + /// Divide by 1 (16 MHz) + DIV_1 = 0x0, + /// Divide by 2 (8 MHz) + DIV_2 = 0x1, + /// Divide by 4 (4 MHz) + DIV_4 = 0x2, + /// Divide by 8 (2 MHz) + DIV_8 = 0x3, + /// Divide by 16 (1 MHz) + DIV_16 = 0x4, + /// Divide by 32 (500 kHz) + DIV_32 = 0x5, + /// Divide by 64 (250 kHz) + DIV_64 = 0x6, + /// Divide by 128 (125 kHz) + DIV_128 = 0x7, + }, + }, + padding: u29, + }), + /// Configuration of the decoder + DECODER: mmio.Mmio(packed struct(u32) { + /// How a sequence is read from RAM and spread to the compare register + LOAD: packed union { + raw: u2, + value: enum(u2) { + /// 1st half word (16-bit) used in all PWM channels 0..3 + Common = 0x0, + /// 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + Grouped = 0x1, + /// 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + Individual = 0x2, + /// 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + WaveForm = 0x3, + }, + }, + reserved8: u6, + /// Selects source for advancing the active sequence + MODE: packed union { + raw: u1, + value: enum(u1) { + /// SEQ[n].REFRESH is used to determine loading internal compare registers + RefreshCount = 0x0, + /// NEXTSTEP task causes a new value to be loaded to internal compare registers + NextStep = 0x1, + }, + }, + padding: u23, + }), + /// Number of playbacks of a loop + LOOP: mmio.Mmio(packed struct(u32) { + /// Number of playbacks of pattern cycles + CNT: packed union { + raw: u16, + value: enum(u16) { + /// Looping disabled (stop at the end of the sequence) + Disabled = 0x0, + _, + }, + }, + padding: u16, + }), + }; + + /// Universal serial bus device + pub const USBD = extern struct { + reserved4: [4]u8, + /// Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + TASKS_STARTEPIN: [8]mmio.Mmio(packed struct(u32) { + /// Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + TASKS_STARTEPIN: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + TASKS_STARTISOIN: mmio.Mmio(packed struct(u32) { + /// Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + TASKS_STARTISOIN: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + TASKS_STARTEPOUT: [8]mmio.Mmio(packed struct(u32) { + /// Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + TASKS_STARTEPOUT: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + TASKS_STARTISOOUT: mmio.Mmio(packed struct(u32) { + /// Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + TASKS_STARTISOOUT: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Allows OUT data stage on control endpoint 0 + TASKS_EP0RCVOUT: mmio.Mmio(packed struct(u32) { + /// Allows OUT data stage on control endpoint 0 + TASKS_EP0RCVOUT: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Allows status stage on control endpoint 0 + TASKS_EP0STATUS: mmio.Mmio(packed struct(u32) { + /// Allows status stage on control endpoint 0 + TASKS_EP0STATUS: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stalls data and status stage on control endpoint 0 + TASKS_EP0STALL: mmio.Mmio(packed struct(u32) { + /// Stalls data and status stage on control endpoint 0 + TASKS_EP0STALL: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Forces D+ and D- lines into the state defined in the DPDMVALUE register + TASKS_DPDMDRIVE: mmio.Mmio(packed struct(u32) { + /// Forces D+ and D- lines into the state defined in the DPDMVALUE register + TASKS_DPDMDRIVE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stops forcing D+ and D- lines into any state (USB engine takes control) + TASKS_DPDMNODRIVE: mmio.Mmio(packed struct(u32) { + /// Stops forcing D+ and D- lines into any state (USB engine takes control) + TASKS_DPDMNODRIVE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [160]u8, + /// Signals that a USB reset condition has been detected on USB lines + EVENTS_USBRESET: mmio.Mmio(packed struct(u32) { + /// Signals that a USB reset condition has been detected on USB lines + EVENTS_USBRESET: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + EVENTS_STARTED: mmio.Mmio(packed struct(u32) { + /// Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + EVENTS_STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + EVENTS_ENDEPIN: [8]mmio.Mmio(packed struct(u32) { + /// The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + EVENTS_ENDEPIN: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// An acknowledged data transfer has taken place on the control endpoint + EVENTS_EP0DATADONE: mmio.Mmio(packed struct(u32) { + /// An acknowledged data transfer has taken place on the control endpoint + EVENTS_EP0DATADONE: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. + EVENTS_ENDISOIN: mmio.Mmio(packed struct(u32) { + /// The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. + EVENTS_ENDISOIN: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + EVENTS_ENDEPOUT: [8]mmio.Mmio(packed struct(u32) { + /// The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + EVENTS_ENDEPOUT: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. + EVENTS_ENDISOOUT: mmio.Mmio(packed struct(u32) { + /// The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. + EVENTS_ENDISOOUT: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Signals that a SOF (start of frame) condition has been detected on USB lines + EVENTS_SOF: mmio.Mmio(packed struct(u32) { + /// Signals that a SOF (start of frame) condition has been detected on USB lines + EVENTS_SOF: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + EVENTS_USBEVENT: mmio.Mmio(packed struct(u32) { + /// An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + EVENTS_USBEVENT: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// A valid SETUP token has been received (and acknowledged) on the control endpoint + EVENTS_EP0SETUP: mmio.Mmio(packed struct(u32) { + /// A valid SETUP token has been received (and acknowledged) on the control endpoint + EVENTS_EP0SETUP: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + EVENTS_EPDATA: mmio.Mmio(packed struct(u32) { + /// A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + EVENTS_EPDATA: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [156]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between event EP0DATADONE and task STARTEPIN[0] + EP0DATADONE_STARTEPIN0: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event EP0DATADONE and task STARTEPOUT[0] + EP0DATADONE_STARTEPOUT0: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event EP0DATADONE and task EP0STATUS + EP0DATADONE_EP0STATUS: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event ENDEPOUT[0] and task EP0STATUS + ENDEPOUT0_EP0STATUS: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event ENDEPOUT[0] and task EP0RCVOUT + ENDEPOUT0_EP0RCVOUT: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for event USBRESET + USBRESET: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPIN[0] + ENDEPIN0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPIN[1] + ENDEPIN1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPIN[2] + ENDEPIN2: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPIN[3] + ENDEPIN3: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPIN[4] + ENDEPIN4: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPIN[5] + ENDEPIN5: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPIN[6] + ENDEPIN6: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPIN[7] + ENDEPIN7: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event EP0DATADONE + EP0DATADONE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDISOIN + ENDISOIN: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPOUT[0] + ENDEPOUT0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPOUT[1] + ENDEPOUT1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPOUT[2] + ENDEPOUT2: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPOUT[3] + ENDEPOUT3: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPOUT[4] + ENDEPOUT4: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPOUT[5] + ENDEPOUT5: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPOUT[6] + ENDEPOUT6: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDEPOUT[7] + ENDEPOUT7: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDISOOUT + ENDISOOUT: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event SOF + SOF: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event USBEVENT + USBEVENT: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event EP0SETUP + EP0SETUP: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event EPDATA + EPDATA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u7, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event USBRESET + USBRESET: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPIN[0] + ENDEPIN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPIN[1] + ENDEPIN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPIN[2] + ENDEPIN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPIN[3] + ENDEPIN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPIN[4] + ENDEPIN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPIN[5] + ENDEPIN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPIN[6] + ENDEPIN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPIN[7] + ENDEPIN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event EP0DATADONE + EP0DATADONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDISOIN + ENDISOIN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPOUT[0] + ENDEPOUT0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPOUT[1] + ENDEPOUT1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPOUT[2] + ENDEPOUT2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPOUT[3] + ENDEPOUT3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPOUT[4] + ENDEPOUT4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPOUT[5] + ENDEPOUT5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPOUT[6] + ENDEPOUT6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDEPOUT[7] + ENDEPOUT7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDISOOUT + ENDISOOUT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event SOF + SOF: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event USBEVENT + USBEVENT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event EP0SETUP + EP0SETUP: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event EPDATA + EPDATA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u7, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event USBRESET + USBRESET: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPIN[0] + ENDEPIN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPIN[1] + ENDEPIN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPIN[2] + ENDEPIN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPIN[3] + ENDEPIN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPIN[4] + ENDEPIN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPIN[5] + ENDEPIN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPIN[6] + ENDEPIN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPIN[7] + ENDEPIN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event EP0DATADONE + EP0DATADONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDISOIN + ENDISOIN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPOUT[0] + ENDEPOUT0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPOUT[1] + ENDEPOUT1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPOUT[2] + ENDEPOUT2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPOUT[3] + ENDEPOUT3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPOUT[4] + ENDEPOUT4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPOUT[5] + ENDEPOUT5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPOUT[6] + ENDEPOUT6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDEPOUT[7] + ENDEPOUT7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDISOOUT + ENDISOOUT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event SOF + SOF: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event USBEVENT + USBEVENT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event EP0SETUP + EP0SETUP: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event EPDATA + EPDATA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u7, + }), + reserved1024: [244]u8, + /// Details on what caused the USBEVENT event + EVENTCAUSE: mmio.Mmio(packed struct(u32) { + /// CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. + ISOOUTCRC: packed union { + raw: u1, + value: enum(u1) { + /// No error detected + NotDetected = 0x0, + /// Error detected + Detected = 0x1, + }, + }, + reserved8: u7, + /// Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. + SUSPEND: packed union { + raw: u1, + value: enum(u1) { + /// Suspend not detected + NotDetected = 0x0, + /// Suspend detected + Detected = 0x1, + }, + }, + /// Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. + RESUME: packed union { + raw: u1, + value: enum(u1) { + /// Resume not detected + NotDetected = 0x0, + /// Resume detected + Detected = 0x1, + }, + }, + /// USB MAC has been woken up and operational. Write '1' to clear. + USBWUALLOWED: packed union { + raw: u1, + value: enum(u1) { + /// Wake up not allowed + NotAllowed = 0x0, + /// Wake up allowed + Allowed = 0x1, + }, + }, + /// USB device is ready for normal operation. Write '1' to clear. + READY: packed union { + raw: u1, + value: enum(u1) { + /// USBEVENT was not issued due to USBD peripheral ready + NotDetected = 0x0, + /// USBD peripheral is ready + Ready = 0x1, + }, + }, + padding: u20, + }), + reserved1128: [100]u8, + /// Provides information on which endpoint's EasyDMA registers have been captured + EPSTATUS: mmio.Mmio(packed struct(u32) { + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPIN0: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPIN1: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPIN2: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPIN3: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPIN4: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPIN5: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPIN6: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPIN7: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPIN8: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + reserved16: u7, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPOUT0: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPOUT1: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPOUT2: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPOUT3: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPOUT4: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPOUT5: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPOUT6: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPOUT7: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. + EPOUT8: packed union { + raw: u1, + value: enum(u1) { + /// EasyDMA registers have not been captured for this endpoint + NoData = 0x0, + /// EasyDMA registers have been captured for this endpoint + DataDone = 0x1, + }, + }, + padding: u7, + }), + /// Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) + EPDATASTATUS: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. + EPIN1: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotDone = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + DataDone = 0x1, + }, + }, + /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. + EPIN2: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotDone = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + DataDone = 0x1, + }, + }, + /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. + EPIN3: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotDone = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + DataDone = 0x1, + }, + }, + /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. + EPIN4: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotDone = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + DataDone = 0x1, + }, + }, + /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. + EPIN5: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotDone = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + DataDone = 0x1, + }, + }, + /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. + EPIN6: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotDone = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + DataDone = 0x1, + }, + }, + /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. + EPIN7: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotDone = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + DataDone = 0x1, + }, + }, + reserved17: u9, + /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + EPOUT1: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotStarted = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + Started = 0x1, + }, + }, + /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + EPOUT2: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotStarted = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + Started = 0x1, + }, + }, + /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + EPOUT3: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotStarted = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + Started = 0x1, + }, + }, + /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + EPOUT4: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotStarted = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + Started = 0x1, + }, + }, + /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + EPOUT5: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotStarted = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + Started = 0x1, + }, + }, + /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + EPOUT6: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotStarted = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + Started = 0x1, + }, + }, + /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + EPOUT7: packed union { + raw: u1, + value: enum(u1) { + /// No acknowledged data transfer on this endpoint + NotStarted = 0x0, + /// Acknowledged data transfer on this endpoint has occurred + Started = 0x1, + }, + }, + padding: u8, + }), + /// Device USB address + USBADDR: mmio.Mmio(packed struct(u32) { + /// Device USB address + ADDR: u7, + padding: u25, + }), + reserved1152: [12]u8, + /// SETUP data, byte 0, bmRequestType + BMREQUESTTYPE: mmio.Mmio(packed struct(u32) { + /// Data transfer type + RECIPIENT: packed union { + raw: u5, + value: enum(u5) { + /// Device + Device = 0x0, + /// Interface + Interface = 0x1, + /// Endpoint + Endpoint = 0x2, + /// Other + Other = 0x3, + _, + }, + }, + /// Data transfer type + TYPE: packed union { + raw: u2, + value: enum(u2) { + /// Standard + Standard = 0x0, + /// Class + Class = 0x1, + /// Vendor + Vendor = 0x2, + _, + }, + }, + /// Data transfer direction + DIRECTION: packed union { + raw: u1, + value: enum(u1) { + /// Host-to-device + HostToDevice = 0x0, + /// Device-to-host + DeviceToHost = 0x1, + }, + }, + padding: u24, + }), + /// SETUP data, byte 1, bRequest + BREQUEST: mmio.Mmio(packed struct(u32) { + /// SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. + BREQUEST: packed union { + raw: u8, + value: enum(u8) { + /// Standard request GET_STATUS + STD_GET_STATUS = 0x0, + /// Standard request CLEAR_FEATURE + STD_CLEAR_FEATURE = 0x1, + /// Standard request SET_FEATURE + STD_SET_FEATURE = 0x3, + /// Standard request SET_ADDRESS + STD_SET_ADDRESS = 0x5, + /// Standard request GET_DESCRIPTOR + STD_GET_DESCRIPTOR = 0x6, + /// Standard request SET_DESCRIPTOR + STD_SET_DESCRIPTOR = 0x7, + /// Standard request GET_CONFIGURATION + STD_GET_CONFIGURATION = 0x8, + /// Standard request SET_CONFIGURATION + STD_SET_CONFIGURATION = 0x9, + /// Standard request GET_INTERFACE + STD_GET_INTERFACE = 0xa, + /// Standard request SET_INTERFACE + STD_SET_INTERFACE = 0xb, + /// Standard request SYNCH_FRAME + STD_SYNCH_FRAME = 0xc, + _, + }, + }, + padding: u24, + }), + /// SETUP data, byte 2, LSB of wValue + WVALUEL: mmio.Mmio(packed struct(u32) { + /// SETUP data, byte 2, LSB of wValue + WVALUEL: u8, + padding: u24, + }), + /// SETUP data, byte 3, MSB of wValue + WVALUEH: mmio.Mmio(packed struct(u32) { + /// SETUP data, byte 3, MSB of wValue + WVALUEH: u8, + padding: u24, + }), + /// SETUP data, byte 4, LSB of wIndex + WINDEXL: mmio.Mmio(packed struct(u32) { + /// SETUP data, byte 4, LSB of wIndex + WINDEXL: u8, + padding: u24, + }), + /// SETUP data, byte 5, MSB of wIndex + WINDEXH: mmio.Mmio(packed struct(u32) { + /// SETUP data, byte 5, MSB of wIndex + WINDEXH: u8, + padding: u24, + }), + /// SETUP data, byte 6, LSB of wLength + WLENGTHL: mmio.Mmio(packed struct(u32) { + /// SETUP data, byte 6, LSB of wLength + WLENGTHL: u8, + padding: u24, + }), + /// SETUP data, byte 7, MSB of wLength + WLENGTHH: mmio.Mmio(packed struct(u32) { + /// SETUP data, byte 7, MSB of wLength + WLENGTHH: u8, + padding: u24, + }), + reserved1280: [96]u8, + /// Enable USB + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable USB + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// USB peripheral is disabled + Disabled = 0x0, + /// USB peripheral is enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Control of the USB pull-up + USBPULLUP: mmio.Mmio(packed struct(u32) { + /// Control of the USB pull-up on the D+ line + CONNECT: packed union { + raw: u1, + value: enum(u1) { + /// Pull-up is disconnected + Disabled = 0x0, + /// Pull-up is connected to D+ + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). + DPDMVALUE: mmio.Mmio(packed struct(u32) { + /// State D+ and D- lines will be forced into by the DPDMDRIVE task + STATE: packed union { + raw: u5, + value: enum(u5) { + /// D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) + Resume = 0x1, + /// D+ forced high, D- forced low (J state) + J = 0x2, + /// D+ forced low, D- forced high (K state) + K = 0x4, + _, + }, + }, + padding: u27, + }), + /// Data toggle control and status + DTOGGLE: mmio.Mmio(packed struct(u32) { + /// Select bulk endpoint number + EP: u3, + reserved7: u4, + /// Selects IN or OUT endpoint + IO: packed union { + raw: u1, + value: enum(u1) { + /// Selects OUT endpoint + Out = 0x0, + /// Selects IN endpoint + In = 0x1, + }, + }, + /// Data toggle value + VALUE: packed union { + raw: u2, + value: enum(u2) { + /// No action on data toggle when writing the register with this value + Nop = 0x0, + /// Data toggle is DATA0 on endpoint set by EP and IO + Data0 = 0x1, + /// Data toggle is DATA1 on endpoint set by EP and IO + Data1 = 0x2, + _, + }, + }, + padding: u22, + }), + /// Endpoint IN enable + EPINEN: mmio.Mmio(packed struct(u32) { + /// Enable IN endpoint 0 + IN0: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint IN 0 (no response to IN tokens) + Disable = 0x0, + /// Enable endpoint IN 0 (response to IN tokens) + Enable = 0x1, + }, + }, + /// Enable IN endpoint 1 + IN1: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint IN 1 (no response to IN tokens) + Disable = 0x0, + /// Enable endpoint IN 1 (response to IN tokens) + Enable = 0x1, + }, + }, + /// Enable IN endpoint 2 + IN2: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint IN 2 (no response to IN tokens) + Disable = 0x0, + /// Enable endpoint IN 2 (response to IN tokens) + Enable = 0x1, + }, + }, + /// Enable IN endpoint 3 + IN3: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint IN 3 (no response to IN tokens) + Disable = 0x0, + /// Enable endpoint IN 3 (response to IN tokens) + Enable = 0x1, + }, + }, + /// Enable IN endpoint 4 + IN4: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint IN 4 (no response to IN tokens) + Disable = 0x0, + /// Enable endpoint IN 4 (response to IN tokens) + Enable = 0x1, + }, + }, + /// Enable IN endpoint 5 + IN5: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint IN 5 (no response to IN tokens) + Disable = 0x0, + /// Enable endpoint IN 5 (response to IN tokens) + Enable = 0x1, + }, + }, + /// Enable IN endpoint 6 + IN6: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint IN 6 (no response to IN tokens) + Disable = 0x0, + /// Enable endpoint IN 6 (response to IN tokens) + Enable = 0x1, + }, + }, + /// Enable IN endpoint 7 + IN7: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint IN 7 (no response to IN tokens) + Disable = 0x0, + /// Enable endpoint IN 7 (response to IN tokens) + Enable = 0x1, + }, + }, + /// Enable ISO IN endpoint + ISOIN: packed union { + raw: u1, + value: enum(u1) { + /// Disable ISO IN endpoint 8 + Disable = 0x0, + /// Enable ISO IN endpoint 8 + Enable = 0x1, + }, + }, + padding: u23, + }), + /// Endpoint OUT enable + EPOUTEN: mmio.Mmio(packed struct(u32) { + /// Enable OUT endpoint 0 + OUT0: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint OUT 0 (no response to OUT tokens) + Disable = 0x0, + /// Enable endpoint OUT 0 (response to OUT tokens) + Enable = 0x1, + }, + }, + /// Enable OUT endpoint 1 + OUT1: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint OUT 1 (no response to OUT tokens) + Disable = 0x0, + /// Enable endpoint OUT 1 (response to OUT tokens) + Enable = 0x1, + }, + }, + /// Enable OUT endpoint 2 + OUT2: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint OUT 2 (no response to OUT tokens) + Disable = 0x0, + /// Enable endpoint OUT 2 (response to OUT tokens) + Enable = 0x1, + }, + }, + /// Enable OUT endpoint 3 + OUT3: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint OUT 3 (no response to OUT tokens) + Disable = 0x0, + /// Enable endpoint OUT 3 (response to OUT tokens) + Enable = 0x1, + }, + }, + /// Enable OUT endpoint 4 + OUT4: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint OUT 4 (no response to OUT tokens) + Disable = 0x0, + /// Enable endpoint OUT 4 (response to OUT tokens) + Enable = 0x1, + }, + }, + /// Enable OUT endpoint 5 + OUT5: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint OUT 5 (no response to OUT tokens) + Disable = 0x0, + /// Enable endpoint OUT 5 (response to OUT tokens) + Enable = 0x1, + }, + }, + /// Enable OUT endpoint 6 + OUT6: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint OUT 6 (no response to OUT tokens) + Disable = 0x0, + /// Enable endpoint OUT 6 (response to OUT tokens) + Enable = 0x1, + }, + }, + /// Enable OUT endpoint 7 + OUT7: packed union { + raw: u1, + value: enum(u1) { + /// Disable endpoint OUT 7 (no response to OUT tokens) + Disable = 0x0, + /// Enable endpoint OUT 7 (response to OUT tokens) + Enable = 0x1, + }, + }, + /// Enable ISO OUT endpoint 8 + ISOOUT: packed union { + raw: u1, + value: enum(u1) { + /// Disable ISO OUT endpoint 8 + Disable = 0x0, + /// Enable ISO OUT endpoint 8 + Enable = 0x1, + }, + }, + padding: u23, + }), + /// STALL endpoints + EPSTALL: mmio.Mmio(packed struct(u32) { + /// Select endpoint number + EP: u3, + reserved7: u4, + /// Selects IN or OUT endpoint + IO: packed union { + raw: u1, + value: enum(u1) { + /// Selects OUT endpoint + Out = 0x0, + /// Selects IN endpoint + In = 0x1, + }, + }, + /// Stall selected endpoint + STALL: packed union { + raw: u1, + value: enum(u1) { + /// Don't stall selected endpoint + UnStall = 0x0, + /// Stall selected endpoint + Stall = 0x1, + }, + }, + padding: u23, + }), + /// Controls the split of ISO buffers + ISOSPLIT: mmio.Mmio(packed struct(u32) { + /// Controls the split of ISO buffers + SPLIT: packed union { + raw: u16, + value: enum(u16) { + /// Full buffer dedicated to either iso IN or OUT + OneDir = 0x0, + /// Lower half for IN, upper half for OUT + HalfIN = 0x80, + _, + }, + }, + padding: u16, + }), + /// Returns the current value of the start of frame counter + FRAMECNTR: mmio.Mmio(packed struct(u32) { + /// Returns the current value of the start of frame counter + FRAMECNTR: u11, + padding: u21, + }), + reserved1324: [8]u8, + /// Controls USBD peripheral low power mode during USB suspend + LOWPOWER: mmio.Mmio(packed struct(u32) { + /// Controls USBD peripheral low-power mode during USB suspend + LOWPOWER: packed union { + raw: u1, + value: enum(u1) { + /// Software must write this value to exit low power mode and before performing a remote wake-up + ForceNormal = 0x0, + /// Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral + LowPower = 0x1, + }, + }, + padding: u31, + }), + /// Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + ISOINCONFIG: mmio.Mmio(packed struct(u32) { + /// Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + RESPONSE: packed union { + raw: u1, + value: enum(u1) { + /// Endpoint does not respond in that case + NoResp = 0x0, + /// Endpoint responds with a zero-length data packet in that case + ZeroData = 0x1, + }, + }, + padding: u31, + }), + }; + + /// NFC-A compatible radio + pub const NFCT = extern struct { + /// Activate NFCT peripheral for incoming and outgoing frames, change state to activated + TASKS_ACTIVATE: mmio.Mmio(packed struct(u32) { + /// Activate NFCT peripheral for incoming and outgoing frames, change state to activated + TASKS_ACTIVATE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Disable NFCT peripheral + TASKS_DISABLE: mmio.Mmio(packed struct(u32) { + /// Disable NFCT peripheral + TASKS_DISABLE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Enable NFC sense field mode, change state to sense mode + TASKS_SENSE: mmio.Mmio(packed struct(u32) { + /// Enable NFC sense field mode, change state to sense mode + TASKS_SENSE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start transmission of an outgoing frame, change state to transmit + TASKS_STARTTX: mmio.Mmio(packed struct(u32) { + /// Start transmission of an outgoing frame, change state to transmit + TASKS_STARTTX: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved28: [12]u8, + /// Initializes the EasyDMA for receive. + TASKS_ENABLERXDATA: mmio.Mmio(packed struct(u32) { + /// Initializes the EasyDMA for receive. + TASKS_ENABLERXDATA: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved36: [4]u8, + /// Force state machine to IDLE state + TASKS_GOIDLE: mmio.Mmio(packed struct(u32) { + /// Force state machine to IDLE state + TASKS_GOIDLE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Force state machine to SLEEP_A state + TASKS_GOSLEEP: mmio.Mmio(packed struct(u32) { + /// Force state machine to SLEEP_A state + TASKS_GOSLEEP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [212]u8, + /// The NFCT peripheral is ready to receive and send frames + EVENTS_READY: mmio.Mmio(packed struct(u32) { + /// The NFCT peripheral is ready to receive and send frames + EVENTS_READY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Remote NFC field detected + EVENTS_FIELDDETECTED: mmio.Mmio(packed struct(u32) { + /// Remote NFC field detected + EVENTS_FIELDDETECTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Remote NFC field lost + EVENTS_FIELDLOST: mmio.Mmio(packed struct(u32) { + /// Remote NFC field lost + EVENTS_FIELDLOST: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Marks the start of the first symbol of a transmitted frame + EVENTS_TXFRAMESTART: mmio.Mmio(packed struct(u32) { + /// Marks the start of the first symbol of a transmitted frame + EVENTS_TXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Marks the end of the last transmitted on-air symbol of a frame + EVENTS_TXFRAMEEND: mmio.Mmio(packed struct(u32) { + /// Marks the end of the last transmitted on-air symbol of a frame + EVENTS_TXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Marks the end of the first symbol of a received frame + EVENTS_RXFRAMESTART: mmio.Mmio(packed struct(u32) { + /// Marks the end of the first symbol of a received frame + EVENTS_RXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + EVENTS_RXFRAMEEND: mmio.Mmio(packed struct(u32) { + /// Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + EVENTS_RXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// NFC error reported. The ERRORSTATUS register contains details on the source of the error. + EVENTS_ERROR: mmio.Mmio(packed struct(u32) { + /// NFC error reported. The ERRORSTATUS register contains details on the source of the error. + EVENTS_ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved296: [8]u8, + /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + EVENTS_RXERROR: mmio.Mmio(packed struct(u32) { + /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + EVENTS_RXERROR: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + EVENTS_ENDRX: mmio.Mmio(packed struct(u32) { + /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + EVENTS_ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + EVENTS_ENDTX: mmio.Mmio(packed struct(u32) { + /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + EVENTS_ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved312: [4]u8, + /// Auto collision resolution process has started + EVENTS_AUTOCOLRESSTARTED: mmio.Mmio(packed struct(u32) { + /// Auto collision resolution process has started + EVENTS_AUTOCOLRESSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved328: [12]u8, + /// NFC auto collision resolution error reported. + EVENTS_COLLISION: mmio.Mmio(packed struct(u32) { + /// NFC auto collision resolution error reported. + EVENTS_COLLISION: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// NFC auto collision resolution successfully completed + EVENTS_SELECTED: mmio.Mmio(packed struct(u32) { + /// NFC auto collision resolution successfully completed + EVENTS_SELECTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// EasyDMA is ready to receive or send frames. + EVENTS_STARTED: mmio.Mmio(packed struct(u32) { + /// EasyDMA is ready to receive or send frames. + EVENTS_STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [172]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between event FIELDDETECTED and task ACTIVATE + FIELDDETECTED_ACTIVATE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event FIELDLOST and task SENSE + FIELDLOST_SENSE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + reserved5: u3, + /// Shortcut between event TXFRAMEEND and task ENABLERXDATA + TXFRAMEEND_ENABLERXDATA: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u26, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event FIELDDETECTED + FIELDDETECTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event FIELDLOST + FIELDLOST: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TXFRAMESTART + TXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TXFRAMEEND + TXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event RXFRAMESTART + RXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event RXFRAMEEND + RXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved10: u2, + /// Enable or disable interrupt for event RXERROR + RXERROR: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDRX + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event ENDTX + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved14: u1, + /// Enable or disable interrupt for event AUTOCOLRESSTARTED + AUTOCOLRESSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved18: u3, + /// Enable or disable interrupt for event COLLISION + COLLISION: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event SELECTED + SELECTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u11, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event FIELDDETECTED + FIELDDETECTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event FIELDLOST + FIELDLOST: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TXFRAMESTART + TXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TXFRAMEEND + TXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event RXFRAMESTART + RXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event RXFRAMEEND + RXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u2, + /// Write '1' to enable interrupt for event RXERROR + RXERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDRX + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDTX + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved14: u1, + /// Write '1' to enable interrupt for event AUTOCOLRESSTARTED + AUTOCOLRESSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u3, + /// Write '1' to enable interrupt for event COLLISION + COLLISION: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event SELECTED + SELECTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u11, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event FIELDDETECTED + FIELDDETECTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event FIELDLOST + FIELDLOST: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TXFRAMESTART + TXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TXFRAMEEND + TXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event RXFRAMESTART + RXFRAMESTART: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event RXFRAMEEND + RXFRAMEEND: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved10: u2, + /// Write '1' to disable interrupt for event RXERROR + RXERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDRX + ENDRX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDTX + ENDTX: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved14: u1, + /// Write '1' to disable interrupt for event AUTOCOLRESSTARTED + AUTOCOLRESSTARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved18: u3, + /// Write '1' to disable interrupt for event COLLISION + COLLISION: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event SELECTED + SELECTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u11, + }), + reserved1028: [248]u8, + /// NFC Error Status register + ERRORSTATUS: mmio.Mmio(packed struct(u32) { + /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + FRAMEDELAYTIMEOUT: u1, + padding: u31, + }), + reserved1040: [8]u8, + /// NfcTag state register + NFCTAGSTATE: mmio.Mmio(packed struct(u32) { + /// NfcTag state + NFCTAGSTATE: packed union { + raw: u3, + value: enum(u3) { + /// Disabled or sense + Disabled = 0x0, + /// RampUp + RampUp = 0x2, + /// Idle + Idle = 0x3, + /// Receive + Receive = 0x4, + /// FrameDelay + FrameDelay = 0x5, + /// Transmit + Transmit = 0x6, + _, + }, + }, + padding: u29, + }), + reserved1056: [12]u8, + /// Sleep state during automatic collision resolution + SLEEPSTATE: mmio.Mmio(packed struct(u32) { + /// Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. + SLEEPSTATE: packed union { + raw: u1, + value: enum(u1) { + /// State is IDLE. + Idle = 0x0, + /// State is SLEEP_A. + SleepA = 0x1, + }, + }, + padding: u31, + }), + reserved1084: [24]u8, + /// Indicates the presence or not of a valid field + FIELDPRESENT: mmio.Mmio(packed struct(u32) { + /// Indicates if a valid field is present. Available only in the activated state. + FIELDPRESENT: packed union { + raw: u1, + value: enum(u1) { + /// No valid field detected + NoField = 0x0, + /// Valid field detected + FieldPresent = 0x1, + }, + }, + /// Indicates if the low level has locked to the field + LOCKDETECT: packed union { + raw: u1, + value: enum(u1) { + /// Not locked to field + NotLocked = 0x0, + /// Locked to field + Locked = 0x1, + }, + }, + padding: u30, + }), + reserved1284: [196]u8, + /// Minimum frame delay + FRAMEDELAYMIN: mmio.Mmio(packed struct(u32) { + /// Minimum frame delay in number of 13.56 MHz clocks + FRAMEDELAYMIN: u16, + padding: u16, + }), + /// Maximum frame delay + FRAMEDELAYMAX: mmio.Mmio(packed struct(u32) { + /// Maximum frame delay in number of 13.56 MHz clocks + FRAMEDELAYMAX: u20, + padding: u12, + }), + /// Configuration register for the Frame Delay Timer + FRAMEDELAYMODE: mmio.Mmio(packed struct(u32) { + /// Configuration register for the Frame Delay Timer + FRAMEDELAYMODE: packed union { + raw: u2, + value: enum(u2) { + /// Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + FreeRun = 0x0, + /// Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + Window = 0x1, + /// Frame is transmitted exactly at FRAMEDELAYMAX + ExactVal = 0x2, + /// Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + WindowGrid = 0x3, + }, + }, + padding: u30, + }), + /// Packet pointer for TXD and RXD data storage in Data RAM + PACKETPTR: mmio.Mmio(packed struct(u32) { + /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. + PTR: u32, + }), + /// Size of the RAM buffer allocated to TXD and RXD data storage each + MAXLEN: mmio.Mmio(packed struct(u32) { + /// Size of the RAM buffer allocated to TXD and RXD data storage each + MAXLEN: u9, + padding: u23, + }), + reserved1424: [120]u8, + /// Last NFCID1 part (4, 7 or 10 bytes ID) + NFCID1_LAST: mmio.Mmio(packed struct(u32) { + /// NFCID1 byte Z (very last byte sent) + NFCID1_Z: u8, + /// NFCID1 byte Y + NFCID1_Y: u8, + /// NFCID1 byte X + NFCID1_X: u8, + /// NFCID1 byte W + NFCID1_W: u8, + }), + /// Second last NFCID1 part (7 or 10 bytes ID) + NFCID1_2ND_LAST: mmio.Mmio(packed struct(u32) { + /// NFCID1 byte V + NFCID1_V: u8, + /// NFCID1 byte U + NFCID1_U: u8, + /// NFCID1 byte T + NFCID1_T: u8, + padding: u8, + }), + /// Third last NFCID1 part (10 bytes ID) + NFCID1_3RD_LAST: mmio.Mmio(packed struct(u32) { + /// NFCID1 byte S + NFCID1_S: u8, + /// NFCID1 byte R + NFCID1_R: u8, + /// NFCID1 byte Q + NFCID1_Q: u8, + padding: u8, + }), + /// Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. + AUTOCOLRESCONFIG: mmio.Mmio(packed struct(u32) { + /// Enables/disables auto collision resolution + MODE: packed union { + raw: u1, + value: enum(u1) { + /// Auto collision resolution enabled + Enabled = 0x0, + /// Auto collision resolution disabled + Disabled = 0x1, + }, + }, + padding: u31, + }), + /// NFC-A SENS_RES auto-response settings + SENSRES: mmio.Mmio(packed struct(u32) { + /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + BITFRAMESDD: packed union { + raw: u5, + value: enum(u5) { + /// SDD pattern 00000 + SDD00000 = 0x0, + /// SDD pattern 00001 + SDD00001 = 0x1, + /// SDD pattern 00010 + SDD00010 = 0x2, + /// SDD pattern 00100 + SDD00100 = 0x4, + /// SDD pattern 01000 + SDD01000 = 0x8, + /// SDD pattern 10000 + SDD10000 = 0x10, + _, + }, + }, + /// Reserved for future use. Shall be 0. + RFU5: u1, + /// NFCID1 size. This value is used by the auto collision resolution engine. + NFCIDSIZE: packed union { + raw: u2, + value: enum(u2) { + /// NFCID1 size: single (4 bytes) + NFCID1Single = 0x0, + /// NFCID1 size: double (7 bytes) + NFCID1Double = 0x1, + /// NFCID1 size: triple (10 bytes) + NFCID1Triple = 0x2, + _, + }, + }, + /// Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + PLATFCONFIG: u4, + /// Reserved for future use. Shall be 0. + RFU74: u4, + padding: u16, + }), + /// NFC-A SEL_RES auto-response settings + SELRES: mmio.Mmio(packed struct(u32) { + /// Reserved for future use. Shall be 0. + RFU10: u2, + /// Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) + CASCADE: u1, + /// Reserved for future use. Shall be 0. + RFU43: u2, + /// Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + PROTOCOL: u2, + /// Reserved for future use. Shall be 0. + RFU7: u1, + padding: u24, + }), + }; + + /// GPIO Tasks and Events + pub const GPIOTE = extern struct { + /// Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + TASKS_OUT: [8]mmio.Mmio(packed struct(u32) { + /// Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + TASKS_OUT: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved48: [16]u8, + /// Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + TASKS_SET: [8]mmio.Mmio(packed struct(u32) { + /// Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + TASKS_SET: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved96: [16]u8, + /// Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + TASKS_CLR: [8]mmio.Mmio(packed struct(u32) { + /// Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + TASKS_CLR: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [128]u8, + /// Description collection: Event generated from pin specified in CONFIG[n].PSEL + EVENTS_IN: [8]mmio.Mmio(packed struct(u32) { + /// Event generated from pin specified in CONFIG[n].PSEL + EVENTS_IN: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved380: [92]u8, + /// Event generated from multiple input GPIO pins with SENSE mechanism enabled + EVENTS_PORT: mmio.Mmio(packed struct(u32) { + /// Event generated from multiple input GPIO pins with SENSE mechanism enabled + EVENTS_PORT: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved772: [388]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event IN[0] + IN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event IN[1] + IN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event IN[2] + IN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event IN[3] + IN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event IN[4] + IN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event IN[5] + IN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event IN[6] + IN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event IN[7] + IN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved31: u23, + /// Write '1' to enable interrupt for event PORT + PORT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event IN[0] + IN0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event IN[1] + IN1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event IN[2] + IN2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event IN[3] + IN3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event IN[4] + IN4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event IN[5] + IN5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event IN[6] + IN6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event IN[7] + IN7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved31: u23, + /// Write '1' to disable interrupt for event PORT + PORT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + }), + reserved1296: [516]u8, + /// Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + CONFIG: [8]mmio.Mmio(packed struct(u32) { + /// Mode + MODE: packed union { + raw: u2, + value: enum(u2) { + /// Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + Disabled = 0x0, + /// Event mode + Event = 0x1, + /// Task mode + Task = 0x3, + _, + }, + }, + reserved8: u6, + /// GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + PSEL: u5, + /// Port number + PORT: u1, + reserved16: u2, + /// When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + POLARITY: packed union { + raw: u2, + value: enum(u2) { + /// Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + None = 0x0, + /// Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + LoToHi = 0x1, + /// Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + HiToLo = 0x2, + /// Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + Toggle = 0x3, + }, + }, + reserved20: u2, + /// When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + OUTINIT: packed union { + raw: u1, + value: enum(u1) { + /// Task mode: Initial value of pin before task triggering is low + Low = 0x0, + /// Task mode: Initial value of pin before task triggering is high + High = 0x1, + }, + }, + padding: u11, + }), + }; + + /// Successive approximation register (SAR) analog-to-digital converter + pub const SAADC = extern struct { + /// Starts the SAADC and prepares the result buffer in RAM + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Starts the SAADC and prepares the result buffer in RAM + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Takes one SAADC sample + TASKS_SAMPLE: mmio.Mmio(packed struct(u32) { + /// Takes one SAADC sample + TASKS_SAMPLE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stops the SAADC and terminates all on-going conversions + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stops the SAADC and terminates all on-going conversions + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Starts offset auto-calibration + TASKS_CALIBRATEOFFSET: mmio.Mmio(packed struct(u32) { + /// Starts offset auto-calibration + TASKS_CALIBRATEOFFSET: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [240]u8, + /// The SAADC has started + EVENTS_STARTED: mmio.Mmio(packed struct(u32) { + /// The SAADC has started + EVENTS_STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// The SAADC has filled up the result buffer + EVENTS_END: mmio.Mmio(packed struct(u32) { + /// The SAADC has filled up the result buffer + EVENTS_END: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. + EVENTS_DONE: mmio.Mmio(packed struct(u32) { + /// A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. + EVENTS_DONE: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Result ready for transfer to RAM + EVENTS_RESULTDONE: mmio.Mmio(packed struct(u32) { + /// Result ready for transfer to RAM + EVENTS_RESULTDONE: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Calibration is complete + EVENTS_CALIBRATEDONE: mmio.Mmio(packed struct(u32) { + /// Calibration is complete + EVENTS_CALIBRATEDONE: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// The SAADC has stopped + EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { + /// The SAADC has stopped + EVENTS_STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved768: [488]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event DONE + DONE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event RESULTDONE + RESULTDONE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CALIBRATEDONE + CALIBRATEDONE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH0LIMITH + CH0LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH0LIMITL + CH0LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH1LIMITH + CH1LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH1LIMITL + CH1LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH2LIMITH + CH2LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH2LIMITL + CH2LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH3LIMITH + CH3LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH3LIMITL + CH3LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH4LIMITH + CH4LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH4LIMITL + CH4LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH5LIMITH + CH5LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH5LIMITL + CH5LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH6LIMITH + CH6LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH6LIMITL + CH6LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH7LIMITH + CH7LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CH7LIMITL + CH7LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u10, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event DONE + DONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event RESULTDONE + RESULTDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CALIBRATEDONE + CALIBRATEDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH0LIMITH + CH0LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH0LIMITL + CH0LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH1LIMITH + CH1LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH1LIMITL + CH1LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH2LIMITH + CH2LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH2LIMITL + CH2LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH3LIMITH + CH3LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH3LIMITL + CH3LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH4LIMITH + CH4LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH4LIMITL + CH4LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH5LIMITH + CH5LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH5LIMITL + CH5LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH6LIMITH + CH6LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH6LIMITL + CH6LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH7LIMITH + CH7LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CH7LIMITL + CH7LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u10, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event STARTED + STARTED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event DONE + DONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event RESULTDONE + RESULTDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CALIBRATEDONE + CALIBRATEDONE: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH0LIMITH + CH0LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH0LIMITL + CH0LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH1LIMITH + CH1LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH1LIMITL + CH1LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH2LIMITH + CH2LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH2LIMITL + CH2LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH3LIMITH + CH3LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH3LIMITL + CH3LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH4LIMITH + CH4LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH4LIMITL + CH4LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH5LIMITH + CH5LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH5LIMITL + CH5LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH6LIMITH + CH6LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH6LIMITL + CH6LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH7LIMITH + CH7LIMITH: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CH7LIMITL + CH7LIMITL: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u10, + }), + reserved1024: [244]u8, + /// Status + STATUS: mmio.Mmio(packed struct(u32) { + /// Status + STATUS: packed union { + raw: u1, + value: enum(u1) { + /// SAADC is ready. No on-going conversions. + Ready = 0x0, + /// SAADC is busy. Conversion in progress. + Busy = 0x1, + }, + }, + padding: u31, + }), + reserved1280: [252]u8, + /// Enable or disable SAADC + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable SAADC + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable SAADC + Disabled = 0x0, + /// Enable SAADC + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1520: [236]u8, + /// Resolution configuration + RESOLUTION: mmio.Mmio(packed struct(u32) { + /// Set the resolution + VAL: packed union { + raw: u3, + value: enum(u3) { + /// 8 bits + @"8bit" = 0x0, + /// 10 bits + @"10bit" = 0x1, + /// 12 bits + @"12bit" = 0x2, + /// 14 bits + @"14bit" = 0x3, + _, + }, + }, + padding: u29, + }), + /// Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + OVERSAMPLE: mmio.Mmio(packed struct(u32) { + /// Oversample control + OVERSAMPLE: packed union { + raw: u4, + value: enum(u4) { + /// Bypass oversampling + Bypass = 0x0, + /// Oversample 2x + Over2x = 0x1, + /// Oversample 4x + Over4x = 0x2, + /// Oversample 8x + Over8x = 0x3, + /// Oversample 16x + Over16x = 0x4, + /// Oversample 32x + Over32x = 0x5, + /// Oversample 64x + Over64x = 0x6, + /// Oversample 128x + Over128x = 0x7, + /// Oversample 256x + Over256x = 0x8, + _, + }, + }, + padding: u28, + }), + /// Controls normal or continuous sample rate + SAMPLERATE: mmio.Mmio(packed struct(u32) { + /// Capture and compare value. Sample rate is 16 MHz/CC + CC: u11, + reserved12: u1, + /// Select mode for sample rate control + MODE: packed union { + raw: u1, + value: enum(u1) { + /// Rate is controlled from SAMPLE task + Task = 0x0, + /// Rate is controlled from local timer (use CC to control the rate) + Timers = 0x1, + }, + }, + padding: u19, + }), + }; + + /// Timer/Counter 0 + pub const TIMER0 = extern struct { + /// Start Timer + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Start Timer + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop Timer + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop Timer + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Increment Timer (Counter mode only) + TASKS_COUNT: mmio.Mmio(packed struct(u32) { + /// Increment Timer (Counter mode only) + TASKS_COUNT: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Clear time + TASKS_CLEAR: mmio.Mmio(packed struct(u32) { + /// Clear time + TASKS_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Deprecated register - Shut down timer + TASKS_SHUTDOWN: mmio.Mmio(packed struct(u32) { + /// Deprecated field - Shut down timer + TASKS_SHUTDOWN: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved64: [44]u8, + /// Description collection: Capture Timer value to CC[n] register + TASKS_CAPTURE: [6]mmio.Mmio(packed struct(u32) { + /// Capture Timer value to CC[n] register + TASKS_CAPTURE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved320: [232]u8, + /// Description collection: Compare event on CC[n] match + EVENTS_COMPARE: [6]mmio.Mmio(packed struct(u32) { + /// Compare event on CC[n] match + EVENTS_COMPARE: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [168]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between event COMPARE[0] and task CLEAR + COMPARE0_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event COMPARE[1] and task CLEAR + COMPARE1_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event COMPARE[2] and task CLEAR + COMPARE2_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event COMPARE[3] and task CLEAR + COMPARE3_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event COMPARE[4] and task CLEAR + COMPARE4_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event COMPARE[5] and task CLEAR + COMPARE5_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + reserved8: u2, + /// Shortcut between event COMPARE[0] and task STOP + COMPARE0_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event COMPARE[1] and task STOP + COMPARE1_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event COMPARE[2] and task STOP + COMPARE2_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event COMPARE[3] and task STOP + COMPARE3_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event COMPARE[4] and task STOP + COMPARE4_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event COMPARE[5] and task STOP + COMPARE5_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u18, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Write '1' to enable interrupt for event COMPARE[0] + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event COMPARE[1] + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event COMPARE[2] + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event COMPARE[3] + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event COMPARE[4] + COMPARE4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event COMPARE[5] + COMPARE5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u10, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Write '1' to disable interrupt for event COMPARE[0] + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event COMPARE[1] + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event COMPARE[2] + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event COMPARE[3] + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event COMPARE[4] + COMPARE4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event COMPARE[5] + COMPARE5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u10, + }), + reserved1284: [504]u8, + /// Timer mode selection + MODE: mmio.Mmio(packed struct(u32) { + /// Timer mode + MODE: packed union { + raw: u2, + value: enum(u2) { + /// Select Timer mode + Timer = 0x0, + /// Deprecated enumerator - Select Counter mode + Counter = 0x1, + /// Select Low Power Counter mode + LowPowerCounter = 0x2, + _, + }, + }, + padding: u30, + }), + /// Configure the number of bits used by the TIMER + BITMODE: mmio.Mmio(packed struct(u32) { + /// Timer bit width + BITMODE: packed union { + raw: u2, + value: enum(u2) { + /// 16 bit timer bit width + @"16Bit" = 0x0, + /// 8 bit timer bit width + @"08Bit" = 0x1, + /// 24 bit timer bit width + @"24Bit" = 0x2, + /// 32 bit timer bit width + @"32Bit" = 0x3, + }, + }, + padding: u30, + }), + reserved1296: [4]u8, + /// Timer prescaler register + PRESCALER: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PRESCALER: u4, + padding: u28, + }), + reserved1344: [44]u8, + /// Description collection: Capture/Compare register n + CC: [6]mmio.Mmio(packed struct(u32) { + /// Capture/Compare value + CC: u32, + }), + }; + + /// FPU + pub const FPU = extern struct { + /// Unused. + UNUSED: u32, + }; + + /// Inter-IC Sound + pub const I2S = extern struct { + /// Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved260: [252]u8, + /// The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + EVENTS_RXPTRUPD: mmio.Mmio(packed struct(u32) { + /// The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + EVENTS_RXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// I2S transfer stopped. + EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { + /// I2S transfer stopped. + EVENTS_STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved276: [8]u8, + /// The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + EVENTS_TXPTRUPD: mmio.Mmio(packed struct(u32) { + /// The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + EVENTS_TXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved768: [488]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Enable or disable interrupt for event RXPTRUPD + RXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved5: u2, + /// Enable or disable interrupt for event TXPTRUPD + TXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u26, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to enable interrupt for event RXPTRUPD + RXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved5: u2, + /// Write '1' to enable interrupt for event TXPTRUPD + TXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u26, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Write '1' to disable interrupt for event RXPTRUPD + RXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved5: u2, + /// Write '1' to disable interrupt for event TXPTRUPD + TXPTRUPD: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u26, + }), + reserved1280: [500]u8, + /// Enable I2S module. + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable I2S module. + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + }; + + /// Real time counter 0 + pub const RTC0 = extern struct { + /// Start RTC COUNTER + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Start RTC COUNTER + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop RTC COUNTER + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop RTC COUNTER + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Clear RTC COUNTER + TASKS_CLEAR: mmio.Mmio(packed struct(u32) { + /// Clear RTC COUNTER + TASKS_CLEAR: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Set COUNTER to 0xFFFFF0 + TASKS_TRIGOVRFLW: mmio.Mmio(packed struct(u32) { + /// Set COUNTER to 0xFFFFF0 + TASKS_TRIGOVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [240]u8, + /// Event on COUNTER increment + EVENTS_TICK: mmio.Mmio(packed struct(u32) { + /// Event on COUNTER increment + EVENTS_TICK: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Event on COUNTER overflow + EVENTS_OVRFLW: mmio.Mmio(packed struct(u32) { + /// Event on COUNTER overflow + EVENTS_OVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved320: [56]u8, + /// Description collection: Compare event on CC[n] match + EVENTS_COMPARE: [4]mmio.Mmio(packed struct(u32) { + /// Compare event on CC[n] match + EVENTS_COMPARE: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved772: [436]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event TICK + TICK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event OVRFLW + OVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved16: u14, + /// Write '1' to enable interrupt for event COMPARE[0] + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event COMPARE[1] + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event COMPARE[2] + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event COMPARE[3] + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event TICK + TICK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event OVRFLW + OVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved16: u14, + /// Write '1' to disable interrupt for event COMPARE[0] + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event COMPARE[1] + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event COMPARE[2] + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event COMPARE[3] + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + reserved832: [52]u8, + /// Enable or disable event routing + EVTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable event routing for event TICK + TICK: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Disable + Enabled = 0x1, + }, + }, + /// Enable or disable event routing for event OVRFLW + OVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Disable + Enabled = 0x1, + }, + }, + reserved16: u14, + /// Enable or disable event routing for event COMPARE[0] + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Disable + Enabled = 0x1, + }, + }, + /// Enable or disable event routing for event COMPARE[1] + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Disable + Enabled = 0x1, + }, + }, + /// Enable or disable event routing for event COMPARE[2] + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Disable + Enabled = 0x1, + }, + }, + /// Enable or disable event routing for event COMPARE[3] + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Disable + Enabled = 0x1, + }, + }, + padding: u12, + }), + /// Enable event routing + EVTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable event routing for event TICK + TICK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable event routing for event OVRFLW + OVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved16: u14, + /// Write '1' to enable event routing for event COMPARE[0] + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable event routing for event COMPARE[1] + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable event routing for event COMPARE[2] + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable event routing for event COMPARE[3] + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + /// Disable event routing + EVTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable event routing for event TICK + TICK: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable event routing for event OVRFLW + OVRFLW: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved16: u14, + /// Write '1' to disable event routing for event COMPARE[0] + COMPARE0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable event routing for event COMPARE[1] + COMPARE1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable event routing for event COMPARE[2] + COMPARE2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable event routing for event COMPARE[3] + COMPARE3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u12, + }), + reserved1284: [440]u8, + /// Current COUNTER value + COUNTER: mmio.Mmio(packed struct(u32) { + /// Counter value + COUNTER: u24, + padding: u8, + }), + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + PRESCALER: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PRESCALER: u12, + padding: u20, + }), + reserved1344: [52]u8, + /// Description collection: Compare register n + CC: [4]mmio.Mmio(packed struct(u32) { + /// Compare value + COMPARE: u24, + padding: u8, + }), + }; + + /// Temperature Sensor + pub const TEMP = extern struct { + /// Start temperature measurement + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Start temperature measurement + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop temperature measurement + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop temperature measurement + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [248]u8, + /// Temperature measurement complete, data ready + EVENTS_DATARDY: mmio.Mmio(packed struct(u32) { + /// Temperature measurement complete, data ready + EVENTS_DATARDY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved772: [512]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event DATARDY + DATARDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event DATARDY + DATARDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1288: [508]u8, + /// Temperature in degC (0.25deg steps) + TEMP: mmio.Mmio(packed struct(u32) { + /// Temperature in degC (0.25deg steps) + TEMP: u32, + }), + reserved1312: [20]u8, + /// Slope of 1st piece wise linear function + A0: mmio.Mmio(packed struct(u32) { + /// Slope of 1st piece wise linear function + A0: u12, + padding: u20, + }), + /// Slope of 2nd piece wise linear function + A1: mmio.Mmio(packed struct(u32) { + /// Slope of 2nd piece wise linear function + A1: u12, + padding: u20, + }), + /// Slope of 3rd piece wise linear function + A2: mmio.Mmio(packed struct(u32) { + /// Slope of 3rd piece wise linear function + A2: u12, + padding: u20, + }), + /// Slope of 4th piece wise linear function + A3: mmio.Mmio(packed struct(u32) { + /// Slope of 4th piece wise linear function + A3: u12, + padding: u20, + }), + /// Slope of 5th piece wise linear function + A4: mmio.Mmio(packed struct(u32) { + /// Slope of 5th piece wise linear function + A4: u12, + padding: u20, + }), + /// Slope of 6th piece wise linear function + A5: mmio.Mmio(packed struct(u32) { + /// Slope of 6th piece wise linear function + A5: u12, + padding: u20, + }), + reserved1344: [8]u8, + /// y-intercept of 1st piece wise linear function + B0: mmio.Mmio(packed struct(u32) { + /// y-intercept of 1st piece wise linear function + B0: u14, + padding: u18, + }), + /// y-intercept of 2nd piece wise linear function + B1: mmio.Mmio(packed struct(u32) { + /// y-intercept of 2nd piece wise linear function + B1: u14, + padding: u18, + }), + /// y-intercept of 3rd piece wise linear function + B2: mmio.Mmio(packed struct(u32) { + /// y-intercept of 3rd piece wise linear function + B2: u14, + padding: u18, + }), + /// y-intercept of 4th piece wise linear function + B3: mmio.Mmio(packed struct(u32) { + /// y-intercept of 4th piece wise linear function + B3: u14, + padding: u18, + }), + /// y-intercept of 5th piece wise linear function + B4: mmio.Mmio(packed struct(u32) { + /// y-intercept of 5th piece wise linear function + B4: u14, + padding: u18, + }), + /// y-intercept of 6th piece wise linear function + B5: mmio.Mmio(packed struct(u32) { + /// y-intercept of 6th piece wise linear function + B5: u14, + padding: u18, + }), + reserved1376: [8]u8, + /// End point of 1st piece wise linear function + T0: mmio.Mmio(packed struct(u32) { + /// End point of 1st piece wise linear function + T0: u8, + padding: u24, + }), + /// End point of 2nd piece wise linear function + T1: mmio.Mmio(packed struct(u32) { + /// End point of 2nd piece wise linear function + T1: u8, + padding: u24, + }), + /// End point of 3rd piece wise linear function + T2: mmio.Mmio(packed struct(u32) { + /// End point of 3rd piece wise linear function + T2: u8, + padding: u24, + }), + /// End point of 4th piece wise linear function + T3: mmio.Mmio(packed struct(u32) { + /// End point of 4th piece wise linear function + T3: u8, + padding: u24, + }), + /// End point of 5th piece wise linear function + T4: mmio.Mmio(packed struct(u32) { + /// End point of 5th piece wise linear function + T4: u8, + padding: u24, + }), + }; + + /// Random Number Generator + pub const RNG = extern struct { + /// Task starting the random number generator + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Task starting the random number generator + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Task stopping the random number generator + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Task stopping the random number generator + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [248]u8, + /// Event being generated for every new random number written to the VALUE register + EVENTS_VALRDY: mmio.Mmio(packed struct(u32) { + /// Event being generated for every new random number written to the VALUE register + EVENTS_VALRDY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [252]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between event VALRDY and task STOP + VALRDY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event VALRDY + VALRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event VALRDY + VALRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1284: [504]u8, + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Bias correction + DERCEN: packed union { + raw: u1, + value: enum(u1) { + /// Disabled + Disabled = 0x0, + /// Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Output random number + VALUE: mmio.Mmio(packed struct(u32) { + /// Generated random number + VALUE: u8, + padding: u24, + }), + }; + + /// AES ECB Mode Encryption + pub const ECB = extern struct { + /// Start ECB block encrypt + TASKS_STARTECB: mmio.Mmio(packed struct(u32) { + /// Start ECB block encrypt + TASKS_STARTECB: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Abort a possible executing ECB operation + TASKS_STOPECB: mmio.Mmio(packed struct(u32) { + /// Abort a possible executing ECB operation + TASKS_STOPECB: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [248]u8, + /// ECB block encrypt complete + EVENTS_ENDECB: mmio.Mmio(packed struct(u32) { + /// ECB block encrypt complete + EVENTS_ENDECB: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// ECB block encrypt aborted because of a STOPECB task or due to an error + EVENTS_ERRORECB: mmio.Mmio(packed struct(u32) { + /// ECB block encrypt aborted because of a STOPECB task or due to an error + EVENTS_ERRORECB: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved772: [508]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event ENDECB + ENDECB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ERRORECB + ERRORECB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u30, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event ENDECB + ENDECB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ERRORECB + ERRORECB: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u30, + }), + reserved1284: [504]u8, + /// ECB block encrypt memory pointers + ECBDATAPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to the ECB data structure (see Table 1 ECB data structure overview) + ECBDATAPTR: u32, + }), + }; + + /// Accelerated Address Resolver + pub const AAR = extern struct { + /// Start resolving addresses based on IRKs specified in the IRK data structure + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Start resolving addresses based on IRKs specified in the IRK data structure + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved8: [4]u8, + /// Stop resolving addresses + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop resolving addresses + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [244]u8, + /// Address resolution procedure complete + EVENTS_END: mmio.Mmio(packed struct(u32) { + /// Address resolution procedure complete + EVENTS_END: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Address resolved + EVENTS_RESOLVED: mmio.Mmio(packed struct(u32) { + /// Address resolved + EVENTS_RESOLVED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Address not resolved + EVENTS_NOTRESOLVED: mmio.Mmio(packed struct(u32) { + /// Address not resolved + EVENTS_NOTRESOLVED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved772: [504]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event RESOLVED + RESOLVED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event NOTRESOLVED + NOTRESOLVED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event END + END: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event RESOLVED + RESOLVED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event NOTRESOLVED + NOTRESOLVED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + reserved1024: [244]u8, + /// Resolution status + STATUS: mmio.Mmio(packed struct(u32) { + /// The IRK that was used last time an address was resolved + STATUS: u4, + padding: u28, + }), + reserved1280: [252]u8, + /// Enable AAR + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable AAR + ENABLE: packed union { + raw: u2, + value: enum(u2) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x3, + _, + }, + }, + padding: u30, + }), + /// Number of IRKs + NIRK: mmio.Mmio(packed struct(u32) { + /// Number of Identity root keys available in the IRK data structure + NIRK: u5, + padding: u27, + }), + /// Pointer to IRK data structure + IRKPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to the IRK data structure + IRKPTR: u32, + }), + reserved1296: [4]u8, + /// Pointer to the resolvable address + ADDRPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to the resolvable address (6-bytes) + ADDRPTR: u32, + }), + /// Pointer to data area used for temporary storage + SCRATCHPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. + SCRATCHPTR: u32, + }), + }; + + /// AES CCM Mode Encryption + pub const CCM = extern struct { + /// Start generation of key-stream. This operation will stop by itself when completed. + TASKS_KSGEN: mmio.Mmio(packed struct(u32) { + /// Start generation of key-stream. This operation will stop by itself when completed. + TASKS_KSGEN: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Start encryption/decryption. This operation will stop by itself when completed. + TASKS_CRYPT: mmio.Mmio(packed struct(u32) { + /// Start encryption/decryption. This operation will stop by itself when completed. + TASKS_CRYPT: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop encryption/decryption + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop encryption/decryption + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + TASKS_RATEOVERRIDE: mmio.Mmio(packed struct(u32) { + /// Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + TASKS_RATEOVERRIDE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [240]u8, + /// Key-stream generation complete + EVENTS_ENDKSGEN: mmio.Mmio(packed struct(u32) { + /// Key-stream generation complete + EVENTS_ENDKSGEN: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Encrypt/decrypt complete + EVENTS_ENDCRYPT: mmio.Mmio(packed struct(u32) { + /// Encrypt/decrypt complete + EVENTS_ENDCRYPT: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Deprecated register - CCM error event + EVENTS_ERROR: mmio.Mmio(packed struct(u32) { + /// Deprecated field - CCM error event + EVENTS_ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [244]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between event ENDKSGEN and task CRYPT + ENDKSGEN_CRYPT: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event ENDKSGEN + ENDKSGEN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ENDCRYPT + ENDCRYPT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Deprecated intsetfield - Write '1' to enable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event ENDKSGEN + ENDKSGEN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ENDCRYPT + ENDCRYPT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Deprecated intclrfield - Write '1' to disable interrupt for event ERROR + ERROR: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u29, + }), + reserved1024: [244]u8, + /// MIC check result + MICSTATUS: mmio.Mmio(packed struct(u32) { + /// The result of the MIC check performed during the previous decryption operation + MICSTATUS: packed union { + raw: u1, + value: enum(u1) { + /// MIC check failed + CheckFailed = 0x0, + /// MIC check passed + CheckPassed = 0x1, + }, + }, + padding: u31, + }), + reserved1280: [252]u8, + /// Enable + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable CCM + ENABLE: packed union { + raw: u2, + value: enum(u2) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x2, + _, + }, + }, + padding: u30, + }), + /// Operation mode + MODE: mmio.Mmio(packed struct(u32) { + /// The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + MODE: packed union { + raw: u1, + value: enum(u1) { + /// AES CCM packet encryption mode + Encryption = 0x0, + /// AES CCM packet decryption mode + Decryption = 0x1, + }, + }, + reserved16: u15, + /// Radio data rate that the CCM shall run synchronous with + DATARATE: packed union { + raw: u2, + value: enum(u2) { + /// 1 Mbps + @"1Mbit" = 0x0, + /// 2 Mbps + @"2Mbit" = 0x1, + /// 125 Kbps + @"125Kbps" = 0x2, + /// 500 Kbps + @"500Kbps" = 0x3, + }, + }, + reserved24: u6, + /// Packet length configuration + LENGTH: packed union { + raw: u1, + value: enum(u1) { + /// Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. + Default = 0x0, + /// Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. + Extended = 0x1, + }, + }, + padding: u7, + }), + /// Pointer to data structure holding AES key and NONCE vector + CNFPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + CNFPTR: u32, + }), + /// Input pointer + INPTR: mmio.Mmio(packed struct(u32) { + /// Input pointer + INPTR: u32, + }), + /// Output pointer + OUTPTR: mmio.Mmio(packed struct(u32) { + /// Output pointer + OUTPTR: u32, + }), + /// Pointer to data area used for temporary storage + SCRATCHPTR: mmio.Mmio(packed struct(u32) { + /// Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. + SCRATCHPTR: u32, + }), + /// Length of key-stream generated when MODE.LENGTH = Extended. + MAXPACKETSIZE: mmio.Mmio(packed struct(u32) { + /// Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + MAXPACKETSIZE: u8, + padding: u24, + }), + /// Data rate override setting. + RATEOVERRIDE: mmio.Mmio(packed struct(u32) { + /// Data rate override setting. + RATEOVERRIDE: packed union { + raw: u2, + value: enum(u2) { + /// 1 Mbps + @"1Mbit" = 0x0, + /// 2 Mbps + @"2Mbit" = 0x1, + /// 125 Kbps + @"125Kbps" = 0x2, + /// 500 Kbps + @"500Kbps" = 0x3, + }, + }, + padding: u30, + }), + }; + + /// Watchdog Timer + pub const WDT = extern struct { + /// Start the watchdog + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Start the watchdog + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [252]u8, + /// Watchdog timeout + EVENTS_TIMEOUT: mmio.Mmio(packed struct(u32) { + /// Watchdog timeout + EVENTS_TIMEOUT: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved772: [512]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event TIMEOUT + TIMEOUT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event TIMEOUT + TIMEOUT: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1024: [244]u8, + /// Run status + RUNSTATUS: mmio.Mmio(packed struct(u32) { + /// Indicates whether or not the watchdog is running + RUNSTATUS: packed union { + raw: u1, + value: enum(u1) { + /// Watchdog not running + NotRunning = 0x0, + /// Watchdog is running + Running = 0x1, + }, + }, + padding: u31, + }), + /// Request status + REQSTATUS: mmio.Mmio(packed struct(u32) { + /// Request status for RR[0] register + RR0: packed union { + raw: u1, + value: enum(u1) { + /// RR[0] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[0] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[1] register + RR1: packed union { + raw: u1, + value: enum(u1) { + /// RR[1] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[1] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[2] register + RR2: packed union { + raw: u1, + value: enum(u1) { + /// RR[2] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[2] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[3] register + RR3: packed union { + raw: u1, + value: enum(u1) { + /// RR[3] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[3] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[4] register + RR4: packed union { + raw: u1, + value: enum(u1) { + /// RR[4] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[4] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[5] register + RR5: packed union { + raw: u1, + value: enum(u1) { + /// RR[5] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[5] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[6] register + RR6: packed union { + raw: u1, + value: enum(u1) { + /// RR[6] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[6] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + /// Request status for RR[7] register + RR7: packed union { + raw: u1, + value: enum(u1) { + /// RR[7] register is not enabled, or are already requesting reload + DisabledOrRequested = 0x0, + /// RR[7] register is enabled, and are not yet requesting reload + EnabledAndUnrequested = 0x1, + }, + }, + padding: u24, + }), + reserved1284: [252]u8, + /// Counter reload value + CRV: mmio.Mmio(packed struct(u32) { + /// Counter reload value in number of cycles of the 32.768 kHz clock + CRV: u32, + }), + /// Enable register for reload request registers + RREN: mmio.Mmio(packed struct(u32) { + /// Enable or disable RR[0] register + RR0: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[0] register + Disabled = 0x0, + /// Enable RR[0] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[1] register + RR1: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[1] register + Disabled = 0x0, + /// Enable RR[1] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[2] register + RR2: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[2] register + Disabled = 0x0, + /// Enable RR[2] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[3] register + RR3: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[3] register + Disabled = 0x0, + /// Enable RR[3] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[4] register + RR4: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[4] register + Disabled = 0x0, + /// Enable RR[4] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[5] register + RR5: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[5] register + Disabled = 0x0, + /// Enable RR[5] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[6] register + RR6: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[6] register + Disabled = 0x0, + /// Enable RR[6] register + Enabled = 0x1, + }, + }, + /// Enable or disable RR[7] register + RR7: packed union { + raw: u1, + value: enum(u1) { + /// Disable RR[7] register + Disabled = 0x0, + /// Enable RR[7] register + Enabled = 0x1, + }, + }, + padding: u24, + }), + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + SLEEP: packed union { + raw: u1, + value: enum(u1) { + /// Pause watchdog while the CPU is sleeping + Pause = 0x0, + /// Keep the watchdog running while the CPU is sleeping + Run = 0x1, + }, + }, + reserved3: u2, + /// Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + HALT: packed union { + raw: u1, + value: enum(u1) { + /// Pause watchdog while the CPU is halted by the debugger + Pause = 0x0, + /// Keep the watchdog running while the CPU is halted by the debugger + Run = 0x1, + }, + }, + padding: u28, + }), + reserved1536: [240]u8, + /// Description collection: Reload request n + RR: [8]mmio.Mmio(packed struct(u32) { + /// Reload request register + RR: packed union { + raw: u32, + value: enum(u32) { + /// Value to request a reload of the watchdog timer + Reload = 0x6e524635, + _, + }, + }, + }), + }; + + /// Memory Watch Unit + pub const MWU = extern struct { + reserved768: [768]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for event REGION0WA + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION0RA + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION1WA + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION1RA + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION2WA + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION2RA + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION3WA + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION3RA + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Enable or disable interrupt for event PREGION0WA + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event PREGION0RA + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event PREGION1WA + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event PREGION1RA + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u4, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event REGION0WA + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION0RA + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION1WA + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION1RA + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION2WA + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION2RA + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION3WA + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION3RA + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Write '1' to enable interrupt for event PREGION0WA + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event PREGION0RA + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event PREGION1WA + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event PREGION1RA + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event REGION0WA + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION0RA + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION1WA + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION1RA + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION2WA + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION2RA + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION3WA + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION3RA + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Write '1' to disable interrupt for event PREGION0WA + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event PREGION0RA + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event PREGION1WA + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event PREGION1RA + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + reserved800: [20]u8, + /// Enable or disable interrupt + NMIEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for event REGION0WA + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION0RA + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION1WA + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION1RA + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION2WA + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION2RA + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION3WA + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event REGION3RA + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Enable or disable interrupt for event PREGION0WA + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event PREGION0RA + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event PREGION1WA + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event PREGION1RA + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u4, + }), + /// Enable interrupt + NMIENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event REGION0WA + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION0RA + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION1WA + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION1RA + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION2WA + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION2RA + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION3WA + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REGION3RA + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Write '1' to enable interrupt for event PREGION0WA + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event PREGION0RA + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event PREGION1WA + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event PREGION1RA + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + /// Disable interrupt + NMIENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event REGION0WA + REGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION0RA + REGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION1WA + REGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION1RA + REGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION2WA + REGION2WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION2RA + REGION2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION3WA + REGION3WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REGION3RA + REGION3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Write '1' to disable interrupt for event PREGION0WA + PREGION0WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event PREGION0RA + PREGION0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event PREGION1WA + PREGION1WA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event PREGION1RA + PREGION1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + reserved1296: [484]u8, + /// Enable/disable regions watch + REGIONEN: mmio.Mmio(packed struct(u32) { + /// Enable/disable write access watch in region[0] + RGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this region + Disable = 0x0, + /// Enable write access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in region[0] + RGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this region + Disable = 0x0, + /// Enable read access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable write access watch in region[1] + RGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this region + Disable = 0x0, + /// Enable write access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in region[1] + RGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this region + Disable = 0x0, + /// Enable read access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable write access watch in region[2] + RGN2WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this region + Disable = 0x0, + /// Enable write access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in region[2] + RGN2RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this region + Disable = 0x0, + /// Enable read access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable write access watch in region[3] + RGN3WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this region + Disable = 0x0, + /// Enable write access watch in this region + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in region[3] + RGN3RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this region + Disable = 0x0, + /// Enable read access watch in this region + Enable = 0x1, + }, + }, + reserved24: u16, + /// Enable/disable write access watch in PREGION[0] + PRGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this PREGION + Disable = 0x0, + /// Enable write access watch in this PREGION + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in PREGION[0] + PRGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this PREGION + Disable = 0x0, + /// Enable read access watch in this PREGION + Enable = 0x1, + }, + }, + /// Enable/disable write access watch in PREGION[1] + PRGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Disable write access watch in this PREGION + Disable = 0x0, + /// Enable write access watch in this PREGION + Enable = 0x1, + }, + }, + /// Enable/disable read access watch in PREGION[1] + PRGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Disable read access watch in this PREGION + Disable = 0x0, + /// Enable read access watch in this PREGION + Enable = 0x1, + }, + }, + padding: u4, + }), + /// Enable regions watch + REGIONENSET: mmio.Mmio(packed struct(u32) { + /// Enable write access watch in region[0] + RGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in region[0] + RGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable write access watch in region[1] + RGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in region[1] + RGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable write access watch in region[2] + RGN2WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in region[2] + RGN2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable write access watch in region[3] + RGN3WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in region[3] + RGN3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Enable write access watch in PREGION[0] + PRGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this PREGION is disabled + Disabled = 0x0, + /// Write access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in PREGION[0] + PRGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this PREGION is disabled + Disabled = 0x0, + /// Read access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Enable write access watch in PREGION[1] + PRGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this PREGION is disabled + Disabled = 0x0, + /// Write access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Enable read access watch in PREGION[1] + PRGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this PREGION is disabled + Disabled = 0x0, + /// Read access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + /// Disable regions watch + REGIONENCLR: mmio.Mmio(packed struct(u32) { + /// Disable write access watch in region[0] + RGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in region[0] + RGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable write access watch in region[1] + RGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in region[1] + RGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable write access watch in region[2] + RGN2WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in region[2] + RGN2RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable write access watch in region[3] + RGN3WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this region is disabled + Disabled = 0x0, + /// Write access watch in this region is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in region[3] + RGN3RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this region is disabled + Disabled = 0x0, + /// Read access watch in this region is enabled + Enabled = 0x1, + }, + }, + reserved24: u16, + /// Disable write access watch in PREGION[0] + PRGN0WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this PREGION is disabled + Disabled = 0x0, + /// Write access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in PREGION[0] + PRGN0RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this PREGION is disabled + Disabled = 0x0, + /// Read access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Disable write access watch in PREGION[1] + PRGN1WA: packed union { + raw: u1, + value: enum(u1) { + /// Write access watch in this PREGION is disabled + Disabled = 0x0, + /// Write access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + /// Disable read access watch in PREGION[1] + PRGN1RA: packed union { + raw: u1, + value: enum(u1) { + /// Read access watch in this PREGION is disabled + Disabled = 0x0, + /// Read access watch in this PREGION is enabled + Enabled = 0x1, + }, + }, + padding: u4, + }), + }; + + /// Quadrature Decoder + pub const QDEC = extern struct { + /// Task starting the quadrature decoder + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Task starting the quadrature decoder + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Task stopping the quadrature decoder + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Task stopping the quadrature decoder + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Read and clear ACC and ACCDBL + TASKS_READCLRACC: mmio.Mmio(packed struct(u32) { + /// Read and clear ACC and ACCDBL + TASKS_READCLRACC: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Read and clear ACC + TASKS_RDCLRACC: mmio.Mmio(packed struct(u32) { + /// Read and clear ACC + TASKS_RDCLRACC: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Read and clear ACCDBL + TASKS_RDCLRDBL: mmio.Mmio(packed struct(u32) { + /// Read and clear ACCDBL + TASKS_RDCLRDBL: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [236]u8, + /// Event being generated for every new sample value written to the SAMPLE register + EVENTS_SAMPLERDY: mmio.Mmio(packed struct(u32) { + /// Event being generated for every new sample value written to the SAMPLE register + EVENTS_SAMPLERDY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Non-null report ready + EVENTS_REPORTRDY: mmio.Mmio(packed struct(u32) { + /// Non-null report ready + EVENTS_REPORTRDY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// ACC or ACCDBL register overflow + EVENTS_ACCOF: mmio.Mmio(packed struct(u32) { + /// ACC or ACCDBL register overflow + EVENTS_ACCOF: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Double displacement(s) detected + EVENTS_DBLRDY: mmio.Mmio(packed struct(u32) { + /// Double displacement(s) detected + EVENTS_DBLRDY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// QDEC has been stopped + EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { + /// QDEC has been stopped + EVENTS_STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [236]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between event REPORTRDY and task READCLRACC + REPORTRDY_READCLRACC: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event SAMPLERDY and task STOP + SAMPLERDY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event REPORTRDY and task RDCLRACC + REPORTRDY_RDCLRACC: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event REPORTRDY and task STOP + REPORTRDY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event DBLRDY and task RDCLRDBL + DBLRDY_RDCLRDBL: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event DBLRDY and task STOP + DBLRDY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event SAMPLERDY and task READCLRACC + SAMPLERDY_READCLRACC: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u25, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event SAMPLERDY + SAMPLERDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event REPORTRDY + REPORTRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event ACCOF + ACCOF: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event DBLRDY + DBLRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u27, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event SAMPLERDY + SAMPLERDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event REPORTRDY + REPORTRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event ACCOF + ACCOF: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event DBLRDY + DBLRDY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event STOPPED + STOPPED: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved1280: [500]u8, + /// Enable the quadrature decoder + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable the quadrature decoder + ENABLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u31, + }), + /// LED output pin polarity + LEDPOL: mmio.Mmio(packed struct(u32) { + /// LED output pin polarity + LEDPOL: packed union { + raw: u1, + value: enum(u1) { + /// Led active on output pin low + ActiveLow = 0x0, + /// Led active on output pin high + ActiveHigh = 0x1, + }, + }, + padding: u31, + }), + /// Sample period + SAMPLEPER: mmio.Mmio(packed struct(u32) { + /// Sample period. The SAMPLE register will be updated for every new sample + SAMPLEPER: packed union { + raw: u4, + value: enum(u4) { + /// 128 us + @"128us" = 0x0, + /// 256 us + @"256us" = 0x1, + /// 512 us + @"512us" = 0x2, + /// 1024 us + @"1024us" = 0x3, + /// 2048 us + @"2048us" = 0x4, + /// 4096 us + @"4096us" = 0x5, + /// 8192 us + @"8192us" = 0x6, + /// 16384 us + @"16384us" = 0x7, + /// 32768 us + @"32ms" = 0x8, + /// 65536 us + @"65ms" = 0x9, + /// 131072 us + @"131ms" = 0xa, + _, + }, + }, + padding: u28, + }), + /// Motion sample value + SAMPLE: mmio.Mmio(packed struct(u32) { + /// Last motion sample + SAMPLE: u32, + }), + /// Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + REPORTPER: mmio.Mmio(packed struct(u32) { + /// Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + REPORTPER: packed union { + raw: u4, + value: enum(u4) { + /// 10 samples / report + @"10Smpl" = 0x0, + /// 40 samples / report + @"40Smpl" = 0x1, + /// 80 samples / report + @"80Smpl" = 0x2, + /// 120 samples / report + @"120Smpl" = 0x3, + /// 160 samples / report + @"160Smpl" = 0x4, + /// 200 samples / report + @"200Smpl" = 0x5, + /// 240 samples / report + @"240Smpl" = 0x6, + /// 280 samples / report + @"280Smpl" = 0x7, + /// 1 sample / report + @"1Smpl" = 0x8, + _, + }, + }, + padding: u28, + }), + /// Register accumulating the valid transitions + ACC: mmio.Mmio(packed struct(u32) { + /// Register accumulating all valid samples (not double transition) read from the SAMPLE register + ACC: u32, + }), + /// Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + ACCREAD: mmio.Mmio(packed struct(u32) { + /// Snapshot of the ACC register. + ACCREAD: u32, + }), + reserved1320: [12]u8, + /// Enable input debounce filters + DBFEN: mmio.Mmio(packed struct(u32) { + /// Enable input debounce filters + DBFEN: packed union { + raw: u1, + value: enum(u1) { + /// Debounce input filters disabled + Disabled = 0x0, + /// Debounce input filters enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + reserved1344: [20]u8, + /// Time period the LED is switched ON prior to sampling + LEDPRE: mmio.Mmio(packed struct(u32) { + /// Period in us the LED is switched on prior to sampling + LEDPRE: u9, + padding: u23, + }), + /// Register accumulating the number of detected double transitions + ACCDBL: mmio.Mmio(packed struct(u32) { + /// Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + ACCDBL: u4, + padding: u28, + }), + /// Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + ACCDBLREAD: mmio.Mmio(packed struct(u32) { + /// Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + ACCDBLREAD: u4, + padding: u28, + }), + }; + + /// Comparator + pub const COMP = extern struct { + /// Start comparator + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Start comparator + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop comparator + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop comparator + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Sample comparator value + TASKS_SAMPLE: mmio.Mmio(packed struct(u32) { + /// Sample comparator value + TASKS_SAMPLE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [244]u8, + /// COMP is ready and output is valid + EVENTS_READY: mmio.Mmio(packed struct(u32) { + /// COMP is ready and output is valid + EVENTS_READY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Downward crossing + EVENTS_DOWN: mmio.Mmio(packed struct(u32) { + /// Downward crossing + EVENTS_DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Upward crossing + EVENTS_UP: mmio.Mmio(packed struct(u32) { + /// Upward crossing + EVENTS_UP: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Downward or upward crossing + EVENTS_CROSS: mmio.Mmio(packed struct(u32) { + /// Downward or upward crossing + EVENTS_CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [240]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between event READY and task SAMPLE + READY_SAMPLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event READY and task STOP + READY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event DOWN and task STOP + DOWN_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event UP and task STOP + UP_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event CROSS and task STOP + CROSS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved768: [252]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event DOWN + DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event UP + UP: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event CROSS + CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u28, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event DOWN + DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event UP + UP: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CROSS + CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u28, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event DOWN + DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event UP + UP: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CROSS + CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u28, + }), + reserved1024: [244]u8, + /// Compare result + RESULT: mmio.Mmio(packed struct(u32) { + /// Result of last compare. Decision point SAMPLE task. + RESULT: packed union { + raw: u1, + value: enum(u1) { + /// Input voltage is below the threshold (VIN+ < VIN-) + Below = 0x0, + /// Input voltage is above the threshold (VIN+ > VIN-) + Above = 0x1, + }, + }, + padding: u31, + }), + reserved1280: [252]u8, + /// COMP enable + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable COMP + ENABLE: packed union { + raw: u2, + value: enum(u2) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x2, + _, + }, + }, + padding: u30, + }), + /// Pin select + PSEL: mmio.Mmio(packed struct(u32) { + /// Analog pin select + PSEL: packed union { + raw: u3, + value: enum(u3) { + /// AIN0 selected as analog input + AnalogInput0 = 0x0, + /// AIN1 selected as analog input + AnalogInput1 = 0x1, + /// AIN2 selected as analog input + AnalogInput2 = 0x2, + /// AIN3 selected as analog input + AnalogInput3 = 0x3, + /// AIN4 selected as analog input + AnalogInput4 = 0x4, + /// AIN5 selected as analog input + AnalogInput5 = 0x5, + /// AIN6 selected as analog input + AnalogInput6 = 0x6, + /// AIN7 selected as analog input + AnalogInput7 = 0x7, + }, + }, + padding: u29, + }), + /// Reference source select for single-ended mode + REFSEL: mmio.Mmio(packed struct(u32) { + /// Reference select + REFSEL: packed union { + raw: u3, + value: enum(u3) { + /// VREF = internal 1.2 V reference (VDD >= 1.7 V) + Int1V2 = 0x0, + /// VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) + Int1V8 = 0x1, + /// VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) + Int2V4 = 0x2, + /// VREF = VDD + VDD = 0x4, + /// VREF = AREF (VDD >= VREF >= AREFMIN) + ARef = 0x5, + _, + }, + }, + padding: u29, + }), + /// External reference select + EXTREFSEL: mmio.Mmio(packed struct(u32) { + /// External analog reference select + EXTREFSEL: packed union { + raw: u3, + value: enum(u3) { + /// Use AIN0 as external analog reference + AnalogReference0 = 0x0, + /// Use AIN1 as external analog reference + AnalogReference1 = 0x1, + /// Use AIN2 as external analog reference + AnalogReference2 = 0x2, + /// Use AIN3 as external analog reference + AnalogReference3 = 0x3, + /// Use AIN4 as external analog reference + AnalogReference4 = 0x4, + /// Use AIN5 as external analog reference + AnalogReference5 = 0x5, + /// Use AIN6 as external analog reference + AnalogReference6 = 0x6, + /// Use AIN7 as external analog reference + AnalogReference7 = 0x7, + }, + }, + padding: u29, + }), + reserved1328: [32]u8, + /// Threshold configuration for hysteresis unit + TH: mmio.Mmio(packed struct(u32) { + /// VDOWN = (THDOWN+1)/64*VREF + THDOWN: u6, + reserved8: u2, + /// VUP = (THUP+1)/64*VREF + THUP: u6, + padding: u18, + }), + /// Mode configuration + MODE: mmio.Mmio(packed struct(u32) { + /// Speed and power modes + SP: packed union { + raw: u2, + value: enum(u2) { + /// Low-power mode + Low = 0x0, + /// Normal mode + Normal = 0x1, + /// High-speed mode + High = 0x2, + _, + }, + }, + reserved8: u6, + /// Main operation modes + MAIN: packed union { + raw: u1, + value: enum(u1) { + /// Single-ended mode + SE = 0x0, + /// Differential mode + Diff = 0x1, + }, + }, + padding: u23, + }), + /// Comparator hysteresis enable + HYST: mmio.Mmio(packed struct(u32) { + /// Comparator hysteresis + HYST: packed union { + raw: u1, + value: enum(u1) { + /// Comparator hysteresis disabled + NoHyst = 0x0, + /// Comparator hysteresis enabled + Hyst50mV = 0x1, + }, + }, + padding: u31, + }), + }; + + /// Low Power Comparator + pub const LPCOMP = extern struct { + /// Start comparator + TASKS_START: mmio.Mmio(packed struct(u32) { + /// Start comparator + TASKS_START: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Stop comparator + TASKS_STOP: mmio.Mmio(packed struct(u32) { + /// Stop comparator + TASKS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + /// Sample comparator value + TASKS_SAMPLE: mmio.Mmio(packed struct(u32) { + /// Sample comparator value + TASKS_SAMPLE: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [244]u8, + /// LPCOMP is ready and output is valid + EVENTS_READY: mmio.Mmio(packed struct(u32) { + /// LPCOMP is ready and output is valid + EVENTS_READY: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Downward crossing + EVENTS_DOWN: mmio.Mmio(packed struct(u32) { + /// Downward crossing + EVENTS_DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Upward crossing + EVENTS_UP: mmio.Mmio(packed struct(u32) { + /// Upward crossing + EVENTS_UP: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + /// Downward or upward crossing + EVENTS_CROSS: mmio.Mmio(packed struct(u32) { + /// Downward or upward crossing + EVENTS_CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved512: [240]u8, + /// Shortcuts between local events and tasks + SHORTS: mmio.Mmio(packed struct(u32) { + /// Shortcut between event READY and task SAMPLE + READY_SAMPLE: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event READY and task STOP + READY_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event DOWN and task STOP + DOWN_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event UP and task STOP + UP_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + /// Shortcut between event CROSS and task STOP + CROSS_STOP: packed union { + raw: u1, + value: enum(u1) { + /// Disable shortcut + Disabled = 0x0, + /// Enable shortcut + Enabled = 0x1, + }, + }, + padding: u27, + }), + reserved772: [256]u8, + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event DOWN + DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event UP + UP: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event CROSS + CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u28, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event READY + READY: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event DOWN + DOWN: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event UP + UP: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event CROSS + CROSS: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u28, + }), + reserved1024: [244]u8, + /// Compare result + RESULT: mmio.Mmio(packed struct(u32) { + /// Result of last compare. Decision point SAMPLE task. + RESULT: packed union { + raw: u1, + value: enum(u1) { + /// Input voltage is below the reference threshold (VIN+ < VIN-). + Below = 0x0, + /// Input voltage is above the reference threshold (VIN+ > VIN-). + Above = 0x1, + }, + }, + padding: u31, + }), + reserved1280: [252]u8, + /// Enable LPCOMP + ENABLE: mmio.Mmio(packed struct(u32) { + /// Enable or disable LPCOMP + ENABLE: packed union { + raw: u2, + value: enum(u2) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + _, + }, + }, + padding: u30, + }), + /// Input pin select + PSEL: mmio.Mmio(packed struct(u32) { + /// Analog pin select + PSEL: packed union { + raw: u3, + value: enum(u3) { + /// AIN0 selected as analog input + AnalogInput0 = 0x0, + /// AIN1 selected as analog input + AnalogInput1 = 0x1, + /// AIN2 selected as analog input + AnalogInput2 = 0x2, + /// AIN3 selected as analog input + AnalogInput3 = 0x3, + /// AIN4 selected as analog input + AnalogInput4 = 0x4, + /// AIN5 selected as analog input + AnalogInput5 = 0x5, + /// AIN6 selected as analog input + AnalogInput6 = 0x6, + /// AIN7 selected as analog input + AnalogInput7 = 0x7, + }, + }, + padding: u29, + }), + /// Reference select + REFSEL: mmio.Mmio(packed struct(u32) { + /// Reference select + REFSEL: packed union { + raw: u4, + value: enum(u4) { + /// VDD * 1/8 selected as reference + Ref1_8Vdd = 0x0, + /// VDD * 2/8 selected as reference + Ref2_8Vdd = 0x1, + /// VDD * 3/8 selected as reference + Ref3_8Vdd = 0x2, + /// VDD * 4/8 selected as reference + Ref4_8Vdd = 0x3, + /// VDD * 5/8 selected as reference + Ref5_8Vdd = 0x4, + /// VDD * 6/8 selected as reference + Ref6_8Vdd = 0x5, + /// VDD * 7/8 selected as reference + Ref7_8Vdd = 0x6, + /// External analog reference selected + ARef = 0x7, + /// VDD * 1/16 selected as reference + Ref1_16Vdd = 0x8, + /// VDD * 3/16 selected as reference + Ref3_16Vdd = 0x9, + /// VDD * 5/16 selected as reference + Ref5_16Vdd = 0xa, + /// VDD * 7/16 selected as reference + Ref7_16Vdd = 0xb, + /// VDD * 9/16 selected as reference + Ref9_16Vdd = 0xc, + /// VDD * 11/16 selected as reference + Ref11_16Vdd = 0xd, + /// VDD * 13/16 selected as reference + Ref13_16Vdd = 0xe, + /// VDD * 15/16 selected as reference + Ref15_16Vdd = 0xf, + }, + }, + padding: u28, + }), + /// External reference select + EXTREFSEL: mmio.Mmio(packed struct(u32) { + /// External analog reference select + EXTREFSEL: packed union { + raw: u1, + value: enum(u1) { + /// Use AIN0 as external analog reference + AnalogReference0 = 0x0, + /// Use AIN1 as external analog reference + AnalogReference1 = 0x1, + }, + }, + padding: u31, + }), + reserved1312: [16]u8, + /// Analog detect configuration + ANADETECT: mmio.Mmio(packed struct(u32) { + /// Analog detect configuration + ANADETECT: packed union { + raw: u2, + value: enum(u2) { + /// Generate ANADETECT on crossing, both upward crossing and downward crossing + Cross = 0x0, + /// Generate ANADETECT on upward crossing only + Up = 0x1, + /// Generate ANADETECT on downward crossing only + Down = 0x2, + _, + }, + }, + padding: u30, + }), + reserved1336: [20]u8, + /// Comparator hysteresis enable + HYST: mmio.Mmio(packed struct(u32) { + /// Comparator hysteresis enable + HYST: packed union { + raw: u1, + value: enum(u1) { + /// Comparator hysteresis disabled + Disabled = 0x0, + /// Comparator hysteresis enabled + Enabled = 0x1, + }, + }, + padding: u31, + }), + }; + + /// Event Generator Unit 0 + pub const EGU0 = extern struct { + /// Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + TASKS_TRIGGER: [16]mmio.Mmio(packed struct(u32) { + /// Trigger n for triggering the corresponding TRIGGERED[n] event + TASKS_TRIGGER: packed union { + raw: u1, + value: enum(u1) { + /// Trigger task + Trigger = 0x1, + _, + }, + }, + padding: u31, + }), + reserved256: [192]u8, + /// Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + EVENTS_TRIGGERED: [16]mmio.Mmio(packed struct(u32) { + /// Event number n generated by triggering the corresponding TRIGGER[n] task + EVENTS_TRIGGERED: packed union { + raw: u1, + value: enum(u1) { + /// Event not generated + NotGenerated = 0x0, + /// Event generated + Generated = 0x1, + }, + }, + padding: u31, + }), + reserved768: [448]u8, + /// Enable or disable interrupt + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable interrupt for event TRIGGERED[0] + TRIGGERED0: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[1] + TRIGGERED1: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[2] + TRIGGERED2: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[3] + TRIGGERED3: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[4] + TRIGGERED4: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[5] + TRIGGERED5: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[6] + TRIGGERED6: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[7] + TRIGGERED7: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[8] + TRIGGERED8: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[9] + TRIGGERED9: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[10] + TRIGGERED10: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[11] + TRIGGERED11: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[12] + TRIGGERED12: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[13] + TRIGGERED13: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[14] + TRIGGERED14: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + /// Enable or disable interrupt for event TRIGGERED[15] + TRIGGERED15: packed union { + raw: u1, + value: enum(u1) { + /// Disable + Disabled = 0x0, + /// Enable + Enabled = 0x1, + }, + }, + padding: u16, + }), + /// Enable interrupt + INTENSET: mmio.Mmio(packed struct(u32) { + /// Write '1' to enable interrupt for event TRIGGERED[0] + TRIGGERED0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[1] + TRIGGERED1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[2] + TRIGGERED2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[3] + TRIGGERED3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[4] + TRIGGERED4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[5] + TRIGGERED5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[6] + TRIGGERED6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[7] + TRIGGERED7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[8] + TRIGGERED8: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[9] + TRIGGERED9: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[10] + TRIGGERED10: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[11] + TRIGGERED11: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[12] + TRIGGERED12: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[13] + TRIGGERED13: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[14] + TRIGGERED14: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to enable interrupt for event TRIGGERED[15] + TRIGGERED15: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u16, + }), + /// Disable interrupt + INTENCLR: mmio.Mmio(packed struct(u32) { + /// Write '1' to disable interrupt for event TRIGGERED[0] + TRIGGERED0: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[1] + TRIGGERED1: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[2] + TRIGGERED2: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[3] + TRIGGERED3: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[4] + TRIGGERED4: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[5] + TRIGGERED5: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[6] + TRIGGERED6: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[7] + TRIGGERED7: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[8] + TRIGGERED8: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[9] + TRIGGERED9: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[10] + TRIGGERED10: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[11] + TRIGGERED11: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[12] + TRIGGERED12: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[13] + TRIGGERED13: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[14] + TRIGGERED14: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + /// Write '1' to disable interrupt for event TRIGGERED[15] + TRIGGERED15: packed union { + raw: u1, + value: enum(u1) { + /// Read: Disabled + Disabled = 0x0, + /// Read: Enabled + Enabled = 0x1, + }, + }, + padding: u16, + }), + }; + + /// Software interrupt 0 + pub const SWI0 = extern struct { + /// Unused. + UNUSED: u32, + }; + + /// Programmable Peripheral Interconnect + pub const PPI = extern struct { + reserved1280: [1280]u8, + /// Channel enable register + CHEN: mmio.Mmio(packed struct(u32) { + /// Enable or disable channel 0 + CH0: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 1 + CH1: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 2 + CH2: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 3 + CH3: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 4 + CH4: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 5 + CH5: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 6 + CH6: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 7 + CH7: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 8 + CH8: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 9 + CH9: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 10 + CH10: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 11 + CH11: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 12 + CH12: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 13 + CH13: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 14 + CH14: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 15 + CH15: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 16 + CH16: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 17 + CH17: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 18 + CH18: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 19 + CH19: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 20 + CH20: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 21 + CH21: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 22 + CH22: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 23 + CH23: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 24 + CH24: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 25 + CH25: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 26 + CH26: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 27 + CH27: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 28 + CH28: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 29 + CH29: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 30 + CH30: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + /// Enable or disable channel 31 + CH31: packed union { + raw: u1, + value: enum(u1) { + /// Disable channel + Disabled = 0x0, + /// Enable channel + Enabled = 0x1, + }, + }, + }), + /// Channel enable set register + CHENSET: mmio.Mmio(packed struct(u32) { + /// Channel 0 enable set register. Writing '0' has no effect + CH0: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 1 enable set register. Writing '0' has no effect + CH1: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 2 enable set register. Writing '0' has no effect + CH2: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 3 enable set register. Writing '0' has no effect + CH3: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 4 enable set register. Writing '0' has no effect + CH4: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 5 enable set register. Writing '0' has no effect + CH5: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 6 enable set register. Writing '0' has no effect + CH6: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 7 enable set register. Writing '0' has no effect + CH7: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 8 enable set register. Writing '0' has no effect + CH8: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 9 enable set register. Writing '0' has no effect + CH9: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 10 enable set register. Writing '0' has no effect + CH10: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 11 enable set register. Writing '0' has no effect + CH11: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 12 enable set register. Writing '0' has no effect + CH12: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 13 enable set register. Writing '0' has no effect + CH13: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 14 enable set register. Writing '0' has no effect + CH14: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 15 enable set register. Writing '0' has no effect + CH15: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 16 enable set register. Writing '0' has no effect + CH16: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 17 enable set register. Writing '0' has no effect + CH17: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 18 enable set register. Writing '0' has no effect + CH18: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 19 enable set register. Writing '0' has no effect + CH19: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 20 enable set register. Writing '0' has no effect + CH20: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 21 enable set register. Writing '0' has no effect + CH21: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 22 enable set register. Writing '0' has no effect + CH22: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 23 enable set register. Writing '0' has no effect + CH23: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 24 enable set register. Writing '0' has no effect + CH24: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 25 enable set register. Writing '0' has no effect + CH25: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 26 enable set register. Writing '0' has no effect + CH26: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 27 enable set register. Writing '0' has no effect + CH27: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 28 enable set register. Writing '0' has no effect + CH28: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 29 enable set register. Writing '0' has no effect + CH29: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 30 enable set register. Writing '0' has no effect + CH30: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 31 enable set register. Writing '0' has no effect + CH31: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + }), + /// Channel enable clear register + CHENCLR: mmio.Mmio(packed struct(u32) { + /// Channel 0 enable clear register. Writing '0' has no effect + CH0: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 1 enable clear register. Writing '0' has no effect + CH1: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 2 enable clear register. Writing '0' has no effect + CH2: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 3 enable clear register. Writing '0' has no effect + CH3: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 4 enable clear register. Writing '0' has no effect + CH4: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 5 enable clear register. Writing '0' has no effect + CH5: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 6 enable clear register. Writing '0' has no effect + CH6: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 7 enable clear register. Writing '0' has no effect + CH7: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 8 enable clear register. Writing '0' has no effect + CH8: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 9 enable clear register. Writing '0' has no effect + CH9: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 10 enable clear register. Writing '0' has no effect + CH10: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 11 enable clear register. Writing '0' has no effect + CH11: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 12 enable clear register. Writing '0' has no effect + CH12: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 13 enable clear register. Writing '0' has no effect + CH13: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 14 enable clear register. Writing '0' has no effect + CH14: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 15 enable clear register. Writing '0' has no effect + CH15: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 16 enable clear register. Writing '0' has no effect + CH16: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 17 enable clear register. Writing '0' has no effect + CH17: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 18 enable clear register. Writing '0' has no effect + CH18: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 19 enable clear register. Writing '0' has no effect + CH19: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 20 enable clear register. Writing '0' has no effect + CH20: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 21 enable clear register. Writing '0' has no effect + CH21: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 22 enable clear register. Writing '0' has no effect + CH22: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 23 enable clear register. Writing '0' has no effect + CH23: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 24 enable clear register. Writing '0' has no effect + CH24: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 25 enable clear register. Writing '0' has no effect + CH25: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 26 enable clear register. Writing '0' has no effect + CH26: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 27 enable clear register. Writing '0' has no effect + CH27: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 28 enable clear register. Writing '0' has no effect + CH28: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 29 enable clear register. Writing '0' has no effect + CH29: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 30 enable clear register. Writing '0' has no effect + CH30: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + /// Channel 31 enable clear register. Writing '0' has no effect + CH31: packed union { + raw: u1, + value: enum(u1) { + /// Read: channel disabled + Disabled = 0x0, + /// Read: channel enabled + Enabled = 0x1, + }, + }, + }), + reserved2048: [756]u8, + /// Description collection: Channel group n + CHG: [6]mmio.Mmio(packed struct(u32) { + /// Include or exclude channel 0 + CH0: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 1 + CH1: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 2 + CH2: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 3 + CH3: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 4 + CH4: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 5 + CH5: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 6 + CH6: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 7 + CH7: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 8 + CH8: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 9 + CH9: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 10 + CH10: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 11 + CH11: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 12 + CH12: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 13 + CH13: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 14 + CH14: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 15 + CH15: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 16 + CH16: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 17 + CH17: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 18 + CH18: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 19 + CH19: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 20 + CH20: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 21 + CH21: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 22 + CH22: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 23 + CH23: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 24 + CH24: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 25 + CH25: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 26 + CH26: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 27 + CH27: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 28 + CH28: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 29 + CH29: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 30 + CH30: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + /// Include or exclude channel 31 + CH31: packed union { + raw: u1, + value: enum(u1) { + /// Exclude + Excluded = 0x0, + /// Include + Included = 0x1, + }, + }, + }), + }; + + /// Non Volatile Memory Controller + pub const NVMC = extern struct { + reserved1024: [1024]u8, + /// Ready flag + READY: mmio.Mmio(packed struct(u32) { + /// NVMC is ready or busy + READY: packed union { + raw: u1, + value: enum(u1) { + /// NVMC is busy (on-going write or erase operation) + Busy = 0x0, + /// NVMC is ready + Ready = 0x1, + }, + }, + padding: u31, + }), + reserved1032: [4]u8, + /// Ready flag + READYNEXT: mmio.Mmio(packed struct(u32) { + /// NVMC can accept a new write operation + READYNEXT: packed union { + raw: u1, + value: enum(u1) { + /// NVMC cannot accept any write operation + Busy = 0x0, + /// NVMC is ready + Ready = 0x1, + }, + }, + padding: u31, + }), + reserved1284: [248]u8, + /// Configuration register + CONFIG: mmio.Mmio(packed struct(u32) { + /// Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + WEN: packed union { + raw: u2, + value: enum(u2) { + /// Read only access + Ren = 0x0, + /// Write enabled + Wen = 0x1, + /// Erase enabled + Een = 0x2, + _, + }, + }, + padding: u30, + }), + /// Register for erasing a page in code area + ERASEPAGE: mmio.Mmio(packed struct(u32) { + /// Register for starting erase of a page in code area + ERASEPAGE: u32, + }), + /// Register for erasing all non-volatile user memory + ERASEALL: mmio.Mmio(packed struct(u32) { + /// Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + ERASEALL: packed union { + raw: u1, + value: enum(u1) { + /// No operation + NoOperation = 0x0, + /// Start chip erase + Erase = 0x1, + }, + }, + padding: u31, + }), + /// Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + ERASEPCR0: mmio.Mmio(packed struct(u32) { + /// Register for starting erase of a page in code area. Equivalent to ERASEPAGE. + ERASEPCR0: u32, + }), + /// Register for erasing user information configuration registers + ERASEUICR: mmio.Mmio(packed struct(u32) { + /// Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. + ERASEUICR: packed union { + raw: u1, + value: enum(u1) { + /// No operation + NoOperation = 0x0, + /// Start erase of UICR + Erase = 0x1, + }, + }, + padding: u31, + }), + /// Register for partial erase of a page in code area + ERASEPAGEPARTIAL: mmio.Mmio(packed struct(u32) { + /// Register for starting partial erase of a page in code area + ERASEPAGEPARTIAL: u32, + }), + /// Register for partial erase configuration + ERASEPAGEPARTIALCFG: mmio.Mmio(packed struct(u32) { + /// Duration of the partial erase in milliseconds + DURATION: u7, + padding: u25, + }), + reserved1344: [32]u8, + /// I-code cache configuration register. + ICACHECNF: mmio.Mmio(packed struct(u32) { + /// Cache enable + CACHEEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable cache. Invalidates all cache entries. + Disabled = 0x0, + /// Enable cache + Enabled = 0x1, + }, + }, + reserved8: u7, + /// Cache profiling enable + CACHEPROFEN: packed union { + raw: u1, + value: enum(u1) { + /// Disable cache profiling + Disabled = 0x0, + /// Enable cache profiling + Enabled = 0x1, + }, + }, + padding: u23, + }), + reserved1352: [4]u8, + /// I-code cache hit counter. + IHIT: mmio.Mmio(packed struct(u32) { + /// Number of cache hits + HITS: u32, + }), + /// I-code cache miss counter. + IMISS: mmio.Mmio(packed struct(u32) { + /// Number of cache misses + MISSES: u32, + }), + }; + }; +}; diff --git a/test/nrf52840.robot b/test/nrf52840.robot new file mode 100644 index 0000000..28c77fe --- /dev/null +++ b/test/nrf52840.robot @@ -0,0 +1,10 @@ +*** Settings *** +Suite Setup Setup +Suite Teardown Teardown +Test Teardown Test Teardown +Resource ${RENODEKEYWORDS} + +*** Test Cases *** +Should Print Help + ${x}= Execute Command help + Should Contain ${x} Available commands: diff --git a/test/programs/minimal.zig b/test/programs/minimal.zig new file mode 100644 index 0000000..5258ce3 --- /dev/null +++ b/test/programs/minimal.zig @@ -0,0 +1,5 @@ +const micro = @import("microzig"); + +pub fn main() void { + // This function will contain the application logic. +} From 470cd86348977833936a477bccded645743ff444 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 18 Feb 2023 12:01:58 -0500 Subject: [PATCH 02/20] add microzig submodule and buildkite pipeline file (#1) --- .buildkite/pipeline.yml | 6 ++++++ .gitmodules | 3 +++ deps/microzig | 1 + 3 files changed, 10 insertions(+) create mode 100644 .buildkite/pipeline.yml create mode 100644 .gitmodules create mode 160000 deps/microzig diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml new file mode 100644 index 0000000..5fd8795 --- /dev/null +++ b/.buildkite/pipeline.yml @@ -0,0 +1,6 @@ +steps: + - group: Build and Test + steps: + - command: zig build + - label: 🔨 Test + command: renode-test test/nrf52840.robot diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..32e895c --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "deps/microzig"] + path = deps/microzig + url = https://github.com/ZigEmbeddedGroup/microzig.git diff --git a/deps/microzig b/deps/microzig new file mode 160000 index 0000000..97ca549 --- /dev/null +++ b/deps/microzig @@ -0,0 +1 @@ +Subproject commit 97ca5497da0f22d025e18bced9311efed088d893 From 49c61c7e1417c013612c26b52c175df16722cc2b Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 20 Feb 2023 11:11:42 -0800 Subject: [PATCH 03/20] update microzig (#2) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 97ca549..831cfff 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 97ca5497da0f22d025e18bced9311efed088d893 +Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec From 39245b48ac1dea7f070fdbd50ddecaa73fb5bc45 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 24 Feb 2023 09:12:42 -0800 Subject: [PATCH 04/20] Update microzig (#3) * update microzig * update paths and for loops --------- Co-authored-by: mattnite --- build.zig | 2 +- deps/microzig | 2 +- src/chips.zig | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/build.zig b/build.zig index 4039838..d659002 100644 --- a/build.zig +++ b/build.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const microzig = @import("deps/microzig/src/main.zig"); +const microzig = @import("deps/microzig/build.zig"); const chips = @import("src/chips.zig"); pub fn build(b: *std.build.Builder) void { diff --git a/deps/microzig b/deps/microzig index 831cfff..11214ed 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec +Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732 diff --git a/src/chips.zig b/src/chips.zig index 50b2aad..2487aa0 100644 --- a/src/chips.zig +++ b/src/chips.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const micro = @import("../deps/microzig/src/main.zig"); +const micro = @import("../deps/microzig/build.zig"); const Chip = micro.Chip; const MemoryRegion = micro.MemoryRegion; From 2872b218e0c21d9f023b81360407cb173e8becd0 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 28 Feb 2023 01:47:56 -0800 Subject: [PATCH 05/20] Update microzig (#5) * update microzig * update to new api --------- Co-authored-by: mattnite --- build.zig | 18 ++++++++++-------- deps/microzig | 2 +- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/build.zig b/build.zig index d659002..edb8df8 100644 --- a/build.zig +++ b/build.zig @@ -1,6 +1,7 @@ const std = @import("std"); const microzig = @import("deps/microzig/build.zig"); -const chips = @import("src/chips.zig"); + +pub const chips = @import("src/chips.zig"); pub fn build(b: *std.build.Builder) void { const optimize = b.standardOptimizeOption(.{}); @@ -8,13 +9,14 @@ pub fn build(b: *std.build.Builder) void { if (!decl.is_pub) continue; - const exe = microzig.addEmbeddedExecutable( - b, - decl.name ++ ".minimal", - "test/programs/minimal.zig", - .{ .chip = @field(chips, decl.name) }, - .{ .optimize = optimize }, - ); + const exe = microzig.addEmbeddedExecutable(b, .{ + .name = decl.name ++ ".minimal", + .source_file = .{ + .path = "test/programs/minimal.zig", + }, + .backing = .{ .chip = @field(chips, decl.name) }, + .optimize = optimize, + }); exe.install(); } } diff --git a/deps/microzig b/deps/microzig index 11214ed..08e7d5b 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732 +Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725 From bdc5606a387df2c7ee694b1adba3ef6a58df1355 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 19 Mar 2023 16:32:29 -0700 Subject: [PATCH 06/20] update microzig (#7) --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 08e7d5b..6f5b726 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725 +Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde From 04fad531d9b8d45ca73c835fbbd322fc07028617 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 22 Mar 2023 00:54:56 -0700 Subject: [PATCH 07/20] update microzig (#8) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 6f5b726..dabc932 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde +Subproject commit dabc9325cdee394ff66e28c91803cb814954b157 From 14239a66fa3eda789eadb24e8ea7390fe07bd383 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 23 Mar 2023 08:28:11 -0700 Subject: [PATCH 08/20] Update microzig (#9) * update microzig * add zig version --------- Co-authored-by: mattnite --- README.adoc | 4 ++++ deps/microzig | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/README.adoc b/README.adoc index 0a66afd..9bef093 100644 --- a/README.adoc +++ b/README.adoc @@ -2,6 +2,10 @@ HALs and register definitions for nrf5x devices +== What version of Zig to use + +Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig. + == Renode supports: - nrf52840 development kit diff --git a/deps/microzig b/deps/microzig index dabc932..5b0176e 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit dabc9325cdee394ff66e28c91803cb814954b157 +Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5 From ea7bdcb3fbf64b44e3a7bc7dfb7ca0985f43634a Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 23 Mar 2023 08:43:04 -0700 Subject: [PATCH 09/20] Update microzig (#10) * update microzig * fix link --------- Co-authored-by: mattnite --- README.adoc | 2 +- deps/microzig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/README.adoc b/README.adoc index 9bef093..7c2fa2f 100644 --- a/README.adoc +++ b/README.adoc @@ -4,7 +4,7 @@ HALs and register definitions for nrf5x devices == What version of Zig to use -Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig. +Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig. == Renode supports: diff --git a/deps/microzig b/deps/microzig index 5b0176e..ceaa9dd 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5 +Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e From 68ebc9a0adb0ab584a9852d93bb7d4cd45bae1c7 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 5 Apr 2023 17:19:06 -0700 Subject: [PATCH 10/20] update microzig (#11) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index ceaa9dd..23482a6 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e +Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7 From f1d338b3e22e0e484071559da696cbda5b46d253 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 13 Apr 2023 22:24:36 -0700 Subject: [PATCH 11/20] Update microzig (#12) * update microzig * fixed build.zig --------- Co-authored-by: mattnite --- build.zig | 2 +- deps/microzig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/build.zig b/build.zig index edb8df8..ff60e94 100644 --- a/build.zig +++ b/build.zig @@ -17,6 +17,6 @@ pub fn build(b: *std.build.Builder) void { .backing = .{ .chip = @field(chips, decl.name) }, .optimize = optimize, }); - exe.install(); + exe.installArtifact(b); } } diff --git a/deps/microzig b/deps/microzig index 23482a6..ae6e619 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7 +Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763 From 8b7cbf09d3a261a7d7b83cb9520d237126006c77 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 23 Apr 2023 11:56:04 -0700 Subject: [PATCH 12/20] update microzig (#14) --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index ae6e619..dd491cc 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763 +Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab From 78da6fd10c59c72fd3bc70afa49d8e21abd38067 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 25 Apr 2023 23:41:51 -0700 Subject: [PATCH 13/20] update microzig (#15) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index dd491cc..658648b 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab +Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1 From c9943f54ef889e9be97781f8a379474743d33452 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 26 Apr 2023 00:29:22 -0700 Subject: [PATCH 14/20] update microzig (#17) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 658648b..b5edf6d 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1 +Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d From aeadb4155451910e93b40b7d07bf9be7029c908a Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 3 May 2023 21:40:56 -0700 Subject: [PATCH 15/20] update microzig (#18) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index b5edf6d..4e62e99 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d +Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be From 72f7689700141e99a1af77202e1aa22cd46f5418 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 15 May 2023 21:47:29 -0700 Subject: [PATCH 16/20] update microzig (#19) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 4e62e99..9588941 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be +Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5 From 6e68f32b4bfab2c3756fc2250ab2e314d1837d7f Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 27 Jun 2023 20:31:39 -0700 Subject: [PATCH 17/20] update microzig (#20) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 9588941..9392fe0 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5 +Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791 From 80e5e694203ca379fc0bab888614c850b7b0bb16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Sat, 26 Aug 2023 14:25:07 +0200 Subject: [PATCH 18/20] Updates to Zig 0.11.0 (#22) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Felix "xq" Queißner --- .buildkite/pipeline.yml | 6 -- .github/FUNDING.yml | 1 + .github/workflows/build.yml | 19 +++++ build.zig | 5 +- build.zig.zon | 10 +++ deps/microzig | 1 - src/chips.zig | 21 ++--- src/chips/nrf52.zig | 132 ++++++++++++++++---------------- src/chips/nrf52840.zig | 148 ++++++++++++++++++------------------ 9 files changed, 179 insertions(+), 164 deletions(-) delete mode 100644 .buildkite/pipeline.yml create mode 100644 .github/FUNDING.yml create mode 100644 .github/workflows/build.yml create mode 100644 build.zig.zon delete mode 160000 deps/microzig diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml deleted file mode 100644 index 5fd8795..0000000 --- a/.buildkite/pipeline.yml +++ /dev/null @@ -1,6 +0,0 @@ -steps: - - group: Build and Test - steps: - - command: zig build - - label: 🔨 Test - command: renode-test test/nrf52840.robot diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml new file mode 100644 index 0000000..85b5393 --- /dev/null +++ b/.github/FUNDING.yml @@ -0,0 +1 @@ +github: MasterQ32 diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 0000000..63ea533 --- /dev/null +++ b/.github/workflows/build.yml @@ -0,0 +1,19 @@ +name: Build +on: + push: + +jobs: + build: + runs-on: ${{ matrix.os }} + strategy: + matrix: + os: [ubuntu-latest, windows-latest, macos-latest] + optimize: [Debug, ReleaseSmall, ReleaseFast, ReleaseSafe] + steps: + - uses: actions/checkout@v2 + - uses: goto-bus-stop/setup-zig@v2.1.1 + with: + version: 0.11.0 + + - name: Build + run: zig build install "-Doptimize=${{matrix.optimize}}" diff --git a/build.zig b/build.zig index ff60e94..1e421fd 100644 --- a/build.zig +++ b/build.zig @@ -1,14 +1,11 @@ const std = @import("std"); -const microzig = @import("deps/microzig/build.zig"); +const microzig = @import("microzig"); pub const chips = @import("src/chips.zig"); pub fn build(b: *std.build.Builder) void { const optimize = b.standardOptimizeOption(.{}); inline for (@typeInfo(chips).Struct.decls) |decl| { - if (!decl.is_pub) - continue; - const exe = microzig.addEmbeddedExecutable(b, .{ .name = decl.name ++ ".minimal", .source_file = .{ diff --git a/build.zig.zon b/build.zig.zon new file mode 100644 index 0000000..f69b76d --- /dev/null +++ b/build.zig.zon @@ -0,0 +1,10 @@ +.{ + .name = "microzig-nordic-nrf5x", + .version = "0.1.0", + .dependencies = .{ + .microzig = .{ + .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz", + .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152", + }, + }, +} diff --git a/deps/microzig b/deps/microzig deleted file mode 160000 index 9392fe0..0000000 --- a/deps/microzig +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791 diff --git a/src/chips.zig b/src/chips.zig index 2487aa0..f53d85b 100644 --- a/src/chips.zig +++ b/src/chips.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const micro = @import("../deps/microzig/build.zig"); +const micro = @import("microzig"); const Chip = micro.Chip; const MemoryRegion = micro.MemoryRegion; @@ -9,19 +9,17 @@ fn root_dir() []const u8 { pub const nrf52840 = Chip{ .name = "nrf52840", - .source = .{ - .path = root_dir() ++ "/chips/nrf52840.zig", - }, - .json_register_schema = .{ - .path = root_dir() ++ "/chips.nrf52840.json", - }, + .source = .{ .path = root_dir() ++ "/chips/nrf52840.zig" }, + .json_register_schema = .{ .path = root_dir() ++ "/chips.nrf52840.json" }, .cpu = micro.cpus.cortex_m4, + .memory_regions = &.{ MemoryRegion{ .offset = 0x00000000, .length = 0x100000, .kind = .flash }, MemoryRegion{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, // EXTFLASH MemoryRegion{ .offset = 0x12000000, .length = 0x8000000, .kind = .flash }, + // CODE_RAM MemoryRegion{ .offset = 0x800000, .length = 0x40000, .kind = .ram }, }, @@ -29,13 +27,10 @@ pub const nrf52840 = Chip{ pub const nrf52832 = Chip{ .name = "nrf52", - .source = .{ - .path = root_dir() ++ "/chips/nrf52.zig", - }, - .json_register_schema = .{ - .path = root_dir() ++ "/chips.nrf52.json", - }, + .source = .{ .path = root_dir() ++ "/chips/nrf52.zig" }, + .json_register_schema = .{ .path = root_dir() ++ "/chips.nrf52.json" }, .cpu = micro.cpus.cortex_m4, + .memory_regions = &.{ MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, diff --git a/src/chips/nrf52.zig b/src/chips/nrf52.zig index 1e3de3b..0f6b368 100644 --- a/src/chips/nrf52.zig +++ b/src/chips/nrf52.zig @@ -104,137 +104,137 @@ pub const devices = struct { pub const peripherals = struct { /// Factory Information Configuration Registers - pub const FICR = @intToPtr(*volatile types.peripherals.FICR, 0x10000000); + pub const FICR = @as(*volatile types.peripherals.FICR, @ptrFromInt(0x10000000)); /// User Information Configuration Registers - pub const UICR = @intToPtr(*volatile types.peripherals.UICR, 0x10001000); + pub const UICR = @as(*volatile types.peripherals.UICR, @ptrFromInt(0x10001000)); /// Block Protect - pub const BPROT = @intToPtr(*volatile types.peripherals.BPROT, 0x40000000); + pub const BPROT = @as(*volatile types.peripherals.BPROT, @ptrFromInt(0x40000000)); /// Power control - pub const POWER = @intToPtr(*volatile types.peripherals.POWER, 0x40000000); + pub const POWER = @as(*volatile types.peripherals.POWER, @ptrFromInt(0x40000000)); /// Clock control - pub const CLOCK = @intToPtr(*volatile types.peripherals.CLOCK, 0x40000000); + pub const CLOCK = @as(*volatile types.peripherals.CLOCK, @ptrFromInt(0x40000000)); /// 2.4 GHz Radio - pub const RADIO = @intToPtr(*volatile types.peripherals.RADIO, 0x40001000); + pub const RADIO = @as(*volatile types.peripherals.RADIO, @ptrFromInt(0x40001000)); /// UART with EasyDMA - pub const UARTE0 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40002000); + pub const UARTE0 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40002000)); /// Universal Asynchronous Receiver/Transmitter - pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x40002000); + pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40002000)); /// Serial Peripheral Interface Master with EasyDMA 0 - pub const SPIM0 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40003000); + pub const SPIM0 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40003000)); /// SPI Slave 0 - pub const SPIS0 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40003000); + pub const SPIS0 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40003000)); /// I2C compatible Two-Wire Master Interface with EasyDMA 0 - pub const TWIM0 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40003000); + pub const TWIM0 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40003000)); /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 - pub const TWIS0 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40003000); + pub const TWIS0 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40003000)); /// Serial Peripheral Interface 0 - pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003000); + pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40003000)); /// I2C compatible Two-Wire Interface 0 - pub const TWI0 = @intToPtr(*volatile types.peripherals.TWI0, 0x40003000); + pub const TWI0 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40003000)); /// Serial Peripheral Interface Master with EasyDMA 1 - pub const SPIM1 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40004000); + pub const SPIM1 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40004000)); /// SPI Slave 1 - pub const SPIS1 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40004000); + pub const SPIS1 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40004000)); /// I2C compatible Two-Wire Master Interface with EasyDMA 1 - pub const TWIM1 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40004000); + pub const TWIM1 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40004000)); /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 - pub const TWIS1 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40004000); + pub const TWIS1 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40004000)); /// Serial Peripheral Interface 1 - pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40004000); + pub const SPI1 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40004000)); /// I2C compatible Two-Wire Interface 1 - pub const TWI1 = @intToPtr(*volatile types.peripherals.TWI0, 0x40004000); + pub const TWI1 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40004000)); /// NFC-A compatible radio - pub const NFCT = @intToPtr(*volatile types.peripherals.NFCT, 0x40005000); + pub const NFCT = @as(*volatile types.peripherals.NFCT, @ptrFromInt(0x40005000)); /// GPIO Tasks and Events - pub const GPIOTE = @intToPtr(*volatile types.peripherals.GPIOTE, 0x40006000); + pub const GPIOTE = @as(*volatile types.peripherals.GPIOTE, @ptrFromInt(0x40006000)); /// Analog to Digital Converter - pub const SAADC = @intToPtr(*volatile types.peripherals.SAADC, 0x40007000); + pub const SAADC = @as(*volatile types.peripherals.SAADC, @ptrFromInt(0x40007000)); /// Timer/Counter 0 - pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40008000); + pub const TIMER0 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40008000)); /// Timer/Counter 1 - pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40009000); + pub const TIMER1 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40009000)); /// Timer/Counter 2 - pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4000a000); + pub const TIMER2 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4000a000)); /// Real time counter 0 - pub const RTC0 = @intToPtr(*volatile types.peripherals.RTC0, 0x4000b000); + pub const RTC0 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x4000b000)); /// Temperature Sensor - pub const TEMP = @intToPtr(*volatile types.peripherals.TEMP, 0x4000c000); + pub const TEMP = @as(*volatile types.peripherals.TEMP, @ptrFromInt(0x4000c000)); /// Random Number Generator - pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x4000d000); + pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x4000d000)); /// AES ECB Mode Encryption - pub const ECB = @intToPtr(*volatile types.peripherals.ECB, 0x4000e000); + pub const ECB = @as(*volatile types.peripherals.ECB, @ptrFromInt(0x4000e000)); /// AES CCM Mode Encryption - pub const CCM = @intToPtr(*volatile types.peripherals.CCM, 0x4000f000); + pub const CCM = @as(*volatile types.peripherals.CCM, @ptrFromInt(0x4000f000)); /// Accelerated Address Resolver - pub const AAR = @intToPtr(*volatile types.peripherals.AAR, 0x4000f000); + pub const AAR = @as(*volatile types.peripherals.AAR, @ptrFromInt(0x4000f000)); /// Watchdog Timer - pub const WDT = @intToPtr(*volatile types.peripherals.WDT, 0x40010000); + pub const WDT = @as(*volatile types.peripherals.WDT, @ptrFromInt(0x40010000)); /// Real time counter 1 - pub const RTC1 = @intToPtr(*volatile types.peripherals.RTC0, 0x40011000); + pub const RTC1 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40011000)); /// Quadrature Decoder - pub const QDEC = @intToPtr(*volatile types.peripherals.QDEC, 0x40012000); + pub const QDEC = @as(*volatile types.peripherals.QDEC, @ptrFromInt(0x40012000)); /// Comparator - pub const COMP = @intToPtr(*volatile types.peripherals.COMP, 0x40013000); + pub const COMP = @as(*volatile types.peripherals.COMP, @ptrFromInt(0x40013000)); /// Low Power Comparator - pub const LPCOMP = @intToPtr(*volatile types.peripherals.LPCOMP, 0x40013000); + pub const LPCOMP = @as(*volatile types.peripherals.LPCOMP, @ptrFromInt(0x40013000)); /// Software interrupt 0 - pub const SWI0 = @intToPtr(*volatile types.peripherals.SWI0, 0x40014000); + pub const SWI0 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40014000)); /// Event Generator Unit 0 - pub const EGU0 = @intToPtr(*volatile types.peripherals.EGU0, 0x40014000); + pub const EGU0 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40014000)); /// Software interrupt 1 - pub const SWI1 = @intToPtr(*volatile types.peripherals.SWI0, 0x40015000); + pub const SWI1 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40015000)); /// Event Generator Unit 1 - pub const EGU1 = @intToPtr(*volatile types.peripherals.EGU0, 0x40015000); + pub const EGU1 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40015000)); /// Software interrupt 2 - pub const SWI2 = @intToPtr(*volatile types.peripherals.SWI0, 0x40016000); + pub const SWI2 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40016000)); /// Event Generator Unit 2 - pub const EGU2 = @intToPtr(*volatile types.peripherals.EGU0, 0x40016000); + pub const EGU2 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40016000)); /// Software interrupt 3 - pub const SWI3 = @intToPtr(*volatile types.peripherals.SWI0, 0x40017000); + pub const SWI3 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40017000)); /// Event Generator Unit 3 - pub const EGU3 = @intToPtr(*volatile types.peripherals.EGU0, 0x40017000); + pub const EGU3 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40017000)); /// Software interrupt 4 - pub const SWI4 = @intToPtr(*volatile types.peripherals.SWI0, 0x40018000); + pub const SWI4 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40018000)); /// Event Generator Unit 4 - pub const EGU4 = @intToPtr(*volatile types.peripherals.EGU0, 0x40018000); + pub const EGU4 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40018000)); /// Software interrupt 5 - pub const SWI5 = @intToPtr(*volatile types.peripherals.SWI0, 0x40019000); + pub const SWI5 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40019000)); /// Event Generator Unit 5 - pub const EGU5 = @intToPtr(*volatile types.peripherals.EGU0, 0x40019000); + pub const EGU5 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40019000)); /// Timer/Counter 3 - pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001a000); + pub const TIMER3 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001a000)); /// Timer/Counter 4 - pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001b000); + pub const TIMER4 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001b000)); /// Pulse Width Modulation Unit 0 - pub const PWM0 = @intToPtr(*volatile types.peripherals.PWM0, 0x4001c000); + pub const PWM0 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4001c000)); /// Pulse Density Modulation (Digital Microphone) Interface - pub const PDM = @intToPtr(*volatile types.peripherals.PDM, 0x4001d000); + pub const PDM = @as(*volatile types.peripherals.PDM, @ptrFromInt(0x4001d000)); /// Non Volatile Memory Controller - pub const NVMC = @intToPtr(*volatile types.peripherals.NVMC, 0x4001e000); + pub const NVMC = @as(*volatile types.peripherals.NVMC, @ptrFromInt(0x4001e000)); /// Programmable Peripheral Interconnect - pub const PPI = @intToPtr(*volatile types.peripherals.PPI, 0x4001f000); + pub const PPI = @as(*volatile types.peripherals.PPI, @ptrFromInt(0x4001f000)); /// Memory Watch Unit - pub const MWU = @intToPtr(*volatile types.peripherals.MWU, 0x40020000); + pub const MWU = @as(*volatile types.peripherals.MWU, @ptrFromInt(0x40020000)); /// Pulse Width Modulation Unit 1 - pub const PWM1 = @intToPtr(*volatile types.peripherals.PWM0, 0x40021000); + pub const PWM1 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40021000)); /// Pulse Width Modulation Unit 2 - pub const PWM2 = @intToPtr(*volatile types.peripherals.PWM0, 0x40022000); + pub const PWM2 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40022000)); /// Serial Peripheral Interface Master with EasyDMA 2 - pub const SPIM2 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40023000); + pub const SPIM2 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40023000)); /// SPI Slave 2 - pub const SPIS2 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40023000); + pub const SPIS2 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40023000)); /// Serial Peripheral Interface 2 - pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40023000); + pub const SPI2 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40023000)); /// Real time counter 2 - pub const RTC2 = @intToPtr(*volatile types.peripherals.RTC0, 0x40024000); + pub const RTC2 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40024000)); /// Inter-IC Sound - pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x40025000); + pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x40025000)); /// FPU - pub const FPU = @intToPtr(*volatile types.peripherals.FPU, 0x40026000); + pub const FPU = @as(*volatile types.peripherals.FPU, @ptrFromInt(0x40026000)); /// GPIO Port 1 - pub const P0 = @intToPtr(*volatile types.peripherals.P0, 0x50000000); + pub const P0 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000000)); /// System Tick Timer - pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010); + pub const SysTick = @as(*volatile types.peripherals.SCS.SysTick, @ptrFromInt(0xe000e010)); }; }; }; diff --git a/src/chips/nrf52840.zig b/src/chips/nrf52840.zig index 8c1ffa2..955d043 100644 --- a/src/chips/nrf52840.zig +++ b/src/chips/nrf52840.zig @@ -112,153 +112,153 @@ pub const devices = struct { pub const peripherals = struct { /// Factory information configuration registers - pub const FICR = @intToPtr(*volatile types.peripherals.FICR, 0x10000000); + pub const FICR = @as(*volatile types.peripherals.FICR, @ptrFromInt(0x10000000)); /// User information configuration registers - pub const UICR = @intToPtr(*volatile types.peripherals.UICR, 0x10001000); + pub const UICR = @as(*volatile types.peripherals.UICR, @ptrFromInt(0x10001000)); /// Clock control - pub const CLOCK = @intToPtr(*volatile types.peripherals.CLOCK, 0x40000000); + pub const CLOCK = @as(*volatile types.peripherals.CLOCK, @ptrFromInt(0x40000000)); /// Power control - pub const POWER = @intToPtr(*volatile types.peripherals.POWER, 0x40000000); + pub const POWER = @as(*volatile types.peripherals.POWER, @ptrFromInt(0x40000000)); /// 2.4 GHz radio - pub const RADIO = @intToPtr(*volatile types.peripherals.RADIO, 0x40001000); + pub const RADIO = @as(*volatile types.peripherals.RADIO, @ptrFromInt(0x40001000)); /// Universal Asynchronous Receiver/Transmitter - pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x40002000); + pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40002000)); /// UART with EasyDMA 0 - pub const UARTE0 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40002000); + pub const UARTE0 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40002000)); /// Serial Peripheral Interface 0 - pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003000); + pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40003000)); /// Serial Peripheral Interface Master with EasyDMA 0 - pub const SPIM0 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40003000); + pub const SPIM0 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40003000)); /// SPI Slave 0 - pub const SPIS0 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40003000); + pub const SPIS0 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40003000)); /// I2C compatible Two-Wire Interface 0 - pub const TWI0 = @intToPtr(*volatile types.peripherals.TWI0, 0x40003000); + pub const TWI0 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40003000)); /// I2C compatible Two-Wire Master Interface with EasyDMA 0 - pub const TWIM0 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40003000); + pub const TWIM0 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40003000)); /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 - pub const TWIS0 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40003000); + pub const TWIS0 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40003000)); /// Serial Peripheral Interface 1 - pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40004000); + pub const SPI1 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40004000)); /// Serial Peripheral Interface Master with EasyDMA 1 - pub const SPIM1 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40004000); + pub const SPIM1 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40004000)); /// SPI Slave 1 - pub const SPIS1 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40004000); + pub const SPIS1 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40004000)); /// I2C compatible Two-Wire Interface 1 - pub const TWI1 = @intToPtr(*volatile types.peripherals.TWI0, 0x40004000); + pub const TWI1 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40004000)); /// I2C compatible Two-Wire Master Interface with EasyDMA 1 - pub const TWIM1 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40004000); + pub const TWIM1 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40004000)); /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 - pub const TWIS1 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40004000); + pub const TWIS1 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40004000)); /// NFC-A compatible radio - pub const NFCT = @intToPtr(*volatile types.peripherals.NFCT, 0x40005000); + pub const NFCT = @as(*volatile types.peripherals.NFCT, @ptrFromInt(0x40005000)); /// GPIO Tasks and Events - pub const GPIOTE = @intToPtr(*volatile types.peripherals.GPIOTE, 0x40006000); + pub const GPIOTE = @as(*volatile types.peripherals.GPIOTE, @ptrFromInt(0x40006000)); /// Successive approximation register (SAR) analog-to-digital converter - pub const SAADC = @intToPtr(*volatile types.peripherals.SAADC, 0x40007000); + pub const SAADC = @as(*volatile types.peripherals.SAADC, @ptrFromInt(0x40007000)); /// Timer/Counter 0 - pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40008000); + pub const TIMER0 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40008000)); /// Timer/Counter 1 - pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40009000); + pub const TIMER1 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40009000)); /// Timer/Counter 2 - pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4000a000); + pub const TIMER2 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4000a000)); /// Real time counter 0 - pub const RTC0 = @intToPtr(*volatile types.peripherals.RTC0, 0x4000b000); + pub const RTC0 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x4000b000)); /// Temperature Sensor - pub const TEMP = @intToPtr(*volatile types.peripherals.TEMP, 0x4000c000); + pub const TEMP = @as(*volatile types.peripherals.TEMP, @ptrFromInt(0x4000c000)); /// Random Number Generator - pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x4000d000); + pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x4000d000)); /// AES ECB Mode Encryption - pub const ECB = @intToPtr(*volatile types.peripherals.ECB, 0x4000e000); + pub const ECB = @as(*volatile types.peripherals.ECB, @ptrFromInt(0x4000e000)); /// Accelerated Address Resolver - pub const AAR = @intToPtr(*volatile types.peripherals.AAR, 0x4000f000); + pub const AAR = @as(*volatile types.peripherals.AAR, @ptrFromInt(0x4000f000)); /// AES CCM Mode Encryption - pub const CCM = @intToPtr(*volatile types.peripherals.CCM, 0x4000f000); + pub const CCM = @as(*volatile types.peripherals.CCM, @ptrFromInt(0x4000f000)); /// Watchdog Timer - pub const WDT = @intToPtr(*volatile types.peripherals.WDT, 0x40010000); + pub const WDT = @as(*volatile types.peripherals.WDT, @ptrFromInt(0x40010000)); /// Real time counter 1 - pub const RTC1 = @intToPtr(*volatile types.peripherals.RTC0, 0x40011000); + pub const RTC1 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40011000)); /// Quadrature Decoder - pub const QDEC = @intToPtr(*volatile types.peripherals.QDEC, 0x40012000); + pub const QDEC = @as(*volatile types.peripherals.QDEC, @ptrFromInt(0x40012000)); /// Comparator - pub const COMP = @intToPtr(*volatile types.peripherals.COMP, 0x40013000); + pub const COMP = @as(*volatile types.peripherals.COMP, @ptrFromInt(0x40013000)); /// Low Power Comparator - pub const LPCOMP = @intToPtr(*volatile types.peripherals.LPCOMP, 0x40013000); + pub const LPCOMP = @as(*volatile types.peripherals.LPCOMP, @ptrFromInt(0x40013000)); /// Event Generator Unit 0 - pub const EGU0 = @intToPtr(*volatile types.peripherals.EGU0, 0x40014000); + pub const EGU0 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40014000)); /// Software interrupt 0 - pub const SWI0 = @intToPtr(*volatile types.peripherals.SWI0, 0x40014000); + pub const SWI0 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40014000)); /// Event Generator Unit 1 - pub const EGU1 = @intToPtr(*volatile types.peripherals.EGU0, 0x40015000); + pub const EGU1 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40015000)); /// Software interrupt 1 - pub const SWI1 = @intToPtr(*volatile types.peripherals.SWI0, 0x40015000); + pub const SWI1 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40015000)); /// Event Generator Unit 2 - pub const EGU2 = @intToPtr(*volatile types.peripherals.EGU0, 0x40016000); + pub const EGU2 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40016000)); /// Software interrupt 2 - pub const SWI2 = @intToPtr(*volatile types.peripherals.SWI0, 0x40016000); + pub const SWI2 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40016000)); /// Event Generator Unit 3 - pub const EGU3 = @intToPtr(*volatile types.peripherals.EGU0, 0x40017000); + pub const EGU3 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40017000)); /// Software interrupt 3 - pub const SWI3 = @intToPtr(*volatile types.peripherals.SWI0, 0x40017000); + pub const SWI3 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40017000)); /// Event Generator Unit 4 - pub const EGU4 = @intToPtr(*volatile types.peripherals.EGU0, 0x40018000); + pub const EGU4 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40018000)); /// Software interrupt 4 - pub const SWI4 = @intToPtr(*volatile types.peripherals.SWI0, 0x40018000); + pub const SWI4 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40018000)); /// Event Generator Unit 5 - pub const EGU5 = @intToPtr(*volatile types.peripherals.EGU0, 0x40019000); + pub const EGU5 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40019000)); /// Software interrupt 5 - pub const SWI5 = @intToPtr(*volatile types.peripherals.SWI0, 0x40019000); + pub const SWI5 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40019000)); /// Timer/Counter 3 - pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001a000); + pub const TIMER3 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001a000)); /// Timer/Counter 4 - pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001b000); + pub const TIMER4 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001b000)); /// Pulse width modulation unit 0 - pub const PWM0 = @intToPtr(*volatile types.peripherals.PWM0, 0x4001c000); + pub const PWM0 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4001c000)); /// Pulse Density Modulation (Digital Microphone) Interface - pub const PDM = @intToPtr(*volatile types.peripherals.PDM, 0x4001d000); + pub const PDM = @as(*volatile types.peripherals.PDM, @ptrFromInt(0x4001d000)); /// Access control lists - pub const ACL = @intToPtr(*volatile types.peripherals.ACL, 0x4001e000); + pub const ACL = @as(*volatile types.peripherals.ACL, @ptrFromInt(0x4001e000)); /// Non Volatile Memory Controller - pub const NVMC = @intToPtr(*volatile types.peripherals.NVMC, 0x4001e000); + pub const NVMC = @as(*volatile types.peripherals.NVMC, @ptrFromInt(0x4001e000)); /// Programmable Peripheral Interconnect - pub const PPI = @intToPtr(*volatile types.peripherals.PPI, 0x4001f000); + pub const PPI = @as(*volatile types.peripherals.PPI, @ptrFromInt(0x4001f000)); /// Memory Watch Unit - pub const MWU = @intToPtr(*volatile types.peripherals.MWU, 0x40020000); + pub const MWU = @as(*volatile types.peripherals.MWU, @ptrFromInt(0x40020000)); /// Pulse width modulation unit 1 - pub const PWM1 = @intToPtr(*volatile types.peripherals.PWM0, 0x40021000); + pub const PWM1 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40021000)); /// Pulse width modulation unit 2 - pub const PWM2 = @intToPtr(*volatile types.peripherals.PWM0, 0x40022000); + pub const PWM2 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40022000)); /// Serial Peripheral Interface 2 - pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40023000); + pub const SPI2 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40023000)); /// Serial Peripheral Interface Master with EasyDMA 2 - pub const SPIM2 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40023000); + pub const SPIM2 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40023000)); /// SPI Slave 2 - pub const SPIS2 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40023000); + pub const SPIS2 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40023000)); /// Real time counter 2 - pub const RTC2 = @intToPtr(*volatile types.peripherals.RTC0, 0x40024000); + pub const RTC2 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40024000)); /// Inter-IC Sound - pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x40025000); + pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x40025000)); /// FPU - pub const FPU = @intToPtr(*volatile types.peripherals.FPU, 0x40026000); + pub const FPU = @as(*volatile types.peripherals.FPU, @ptrFromInt(0x40026000)); /// Universal serial bus device - pub const USBD = @intToPtr(*volatile types.peripherals.USBD, 0x40027000); + pub const USBD = @as(*volatile types.peripherals.USBD, @ptrFromInt(0x40027000)); /// UART with EasyDMA 1 - pub const UARTE1 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40028000); + pub const UARTE1 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40028000)); /// External flash interface - pub const QSPI = @intToPtr(*volatile types.peripherals.QSPI, 0x40029000); + pub const QSPI = @as(*volatile types.peripherals.QSPI, @ptrFromInt(0x40029000)); /// Pulse width modulation unit 3 - pub const PWM3 = @intToPtr(*volatile types.peripherals.PWM0, 0x4002d000); + pub const PWM3 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4002d000)); /// Serial Peripheral Interface Master with EasyDMA 3 - pub const SPIM3 = @intToPtr(*volatile types.peripherals.SPIM0, 0x4002f000); + pub const SPIM3 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x4002f000)); /// GPIO Port 1 - pub const P0 = @intToPtr(*volatile types.peripherals.P0, 0x50000000); + pub const P0 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000000)); /// GPIO Port 2 - pub const P1 = @intToPtr(*volatile types.peripherals.P0, 0x50000300); + pub const P1 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000300)); /// CRYPTOCELL HOST_RGF interface - pub const CC_HOST_RGF = @intToPtr(*volatile types.peripherals.CC_HOST_RGF, 0x5002a000); + pub const CC_HOST_RGF = @as(*volatile types.peripherals.CC_HOST_RGF, @ptrFromInt(0x5002a000)); /// ARM TrustZone CryptoCell register interface - pub const CRYPTOCELL = @intToPtr(*volatile types.peripherals.CRYPTOCELL, 0x5002a000); + pub const CRYPTOCELL = @as(*volatile types.peripherals.CRYPTOCELL, @ptrFromInt(0x5002a000)); /// System Tick Timer - pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010); + pub const SysTick = @as(*volatile types.peripherals.SCS.SysTick, @ptrFromInt(0xe000e010)); }; }; }; From dbbbb1392f43eea0047aa1a6d91ae2c87d75ec9b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Fri, 22 Sep 2023 09:02:23 +0200 Subject: [PATCH 19/20] Microzig Generation 2 Build Interface (#23) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Rework for MicroZig Gen 2 Build * Drops CI --------- Co-authored-by: Felix "xq" Queißner --- .github/FUNDING.yml | 1 - .github/workflows/build.yml | 19 - .gitmodules | 3 - build.zig | 74 +- build.zig.zon | 7 +- src/boards/nrf52840-dongle.zig | 1 + src/chips.zig | 38 - src/chips/nrf52.zig | 16821 ------------------------ src/chips/nrf52840.zig | 21782 ------------------------------- 9 files changed, 62 insertions(+), 38684 deletions(-) delete mode 100644 .github/FUNDING.yml delete mode 100644 .github/workflows/build.yml create mode 100644 src/boards/nrf52840-dongle.zig delete mode 100644 src/chips.zig delete mode 100644 src/chips/nrf52.zig delete mode 100644 src/chips/nrf52840.zig diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml deleted file mode 100644 index 85b5393..0000000 --- a/.github/FUNDING.yml +++ /dev/null @@ -1 +0,0 @@ -github: MasterQ32 diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml deleted file mode 100644 index 63ea533..0000000 --- a/.github/workflows/build.yml +++ /dev/null @@ -1,19 +0,0 @@ -name: Build -on: - push: - -jobs: - build: - runs-on: ${{ matrix.os }} - strategy: - matrix: - os: [ubuntu-latest, windows-latest, macos-latest] - optimize: [Debug, ReleaseSmall, ReleaseFast, ReleaseSafe] - steps: - - uses: actions/checkout@v2 - - uses: goto-bus-stop/setup-zig@v2.1.1 - with: - version: 0.11.0 - - - name: Build - run: zig build install "-Doptimize=${{matrix.optimize}}" diff --git a/.gitmodules b/.gitmodules index 32e895c..e69de29 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +0,0 @@ -[submodule "deps/microzig"] - path = deps/microzig - url = https://github.com/ZigEmbeddedGroup/microzig.git diff --git a/build.zig b/build.zig index 1e421fd..1690e0c 100644 --- a/build.zig +++ b/build.zig @@ -1,19 +1,65 @@ const std = @import("std"); -const microzig = @import("microzig"); -pub const chips = @import("src/chips.zig"); +fn path(comptime suffix: []const u8) std.Build.LazyPath { + return .{ + .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix), + }; +} -pub fn build(b: *std.build.Builder) void { - const optimize = b.standardOptimizeOption(.{}); - inline for (@typeInfo(chips).Struct.decls) |decl| { - const exe = microzig.addEmbeddedExecutable(b, .{ - .name = decl.name ++ ".minimal", - .source_file = .{ - .path = "test/programs/minimal.zig", +pub const chips = struct { + pub const nrf52840 = .{ + .preferred_format = .elf, + .chip = .{ + .name = "nrf52840", + .url = "https://www.nordicsemi.com/products/nrf52840", + .cpu = .cortex_m4, + .register_definition = .{ + .json = path("/src/chips/nrf52840.json"), + }, + .memory_regions = &.{ + .{ .offset = 0x00000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + + // EXTFLASH + .{ .offset = 0x12000000, .length = 0x8000000, .kind = .flash }, + + // CODE_RAM + .{ .offset = 0x800000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + pub const nrf52832 = .{ + .preferred_format = .elf, + .chip = .{ + .name = "nrf52", + .url = "https://www.nordicsemi.com/products/nrf52832", + .cpu = .cortex_m4, + .register_definition = .{ + .json = path("/src/chips/nrf52.json"), + }, + .memory_regions = &.{ + .{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; +}; + +pub const boards = struct { + pub const nordic = struct { + pub const nRF52840_Dongle = .{ + .preferred_format = .elf, + .chip = chips.nrf52840.chip, + .board = .{ + .name = "nRF52840 Dongle", + .url = "https://www.nordicsemi.com/Products/Development-hardware/nrf52840-dongle", + .source_file = path("/src/boards/nrf52840-dongle.zig"), }, - .backing = .{ .chip = @field(chips, decl.name) }, - .optimize = optimize, - }); - exe.installArtifact(b); - } + }; + }; +}; + +pub fn build(b: *std.build.Builder) void { + _ = b; } diff --git a/build.zig.zon b/build.zig.zon index f69b76d..64c0de6 100644 --- a/build.zig.zon +++ b/build.zig.zon @@ -1,10 +1,5 @@ .{ .name = "microzig-nordic-nrf5x", .version = "0.1.0", - .dependencies = .{ - .microzig = .{ - .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz", - .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152", - }, - }, + .dependencies = .{}, } diff --git a/src/boards/nrf52840-dongle.zig b/src/boards/nrf52840-dongle.zig new file mode 100644 index 0000000..8bbed2f --- /dev/null +++ b/src/boards/nrf52840-dongle.zig @@ -0,0 +1 @@ +// TODO: Implement board support diff --git a/src/chips.zig b/src/chips.zig deleted file mode 100644 index f53d85b..0000000 --- a/src/chips.zig +++ /dev/null @@ -1,38 +0,0 @@ -const std = @import("std"); -const micro = @import("microzig"); -const Chip = micro.Chip; -const MemoryRegion = micro.MemoryRegion; - -fn root_dir() []const u8 { - return std.fs.path.dirname(@src().file) orelse unreachable; -} - -pub const nrf52840 = Chip{ - .name = "nrf52840", - .source = .{ .path = root_dir() ++ "/chips/nrf52840.zig" }, - .json_register_schema = .{ .path = root_dir() ++ "/chips.nrf52840.json" }, - .cpu = micro.cpus.cortex_m4, - - .memory_regions = &.{ - MemoryRegion{ .offset = 0x00000000, .length = 0x100000, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - - // EXTFLASH - MemoryRegion{ .offset = 0x12000000, .length = 0x8000000, .kind = .flash }, - - // CODE_RAM - MemoryRegion{ .offset = 0x800000, .length = 0x40000, .kind = .ram }, - }, -}; - -pub const nrf52832 = Chip{ - .name = "nrf52", - .source = .{ .path = root_dir() ++ "/chips/nrf52.zig" }, - .json_register_schema = .{ .path = root_dir() ++ "/chips.nrf52.json" }, - .cpu = micro.cpus.cortex_m4, - - .memory_regions = &.{ - MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, -}; diff --git a/src/chips/nrf52.zig b/src/chips/nrf52.zig deleted file mode 100644 index 0f6b368..0000000 --- a/src/chips/nrf52.zig +++ /dev/null @@ -1,16821 +0,0 @@ -const micro = @import("microzig"); -const mmio = micro.mmio; - -pub const devices = struct { - /// nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller - pub const nrf52 = struct { - pub const properties = struct { - pub const @"cpu.nvic_prio_bits" = "3"; - pub const @"cpu.mpu" = "1"; - pub const @"cpu.fpu" = "1"; - pub const @"cpu.revision" = "r0p1"; - pub const @"cpu.vendor_systick_config" = "0"; - pub const license = - \\ - \\Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n - \\\n - \\Redistribution and use in source and binary forms, with or without\n - \\modification, are permitted provided that the following conditions are met:\n - \\\n - \\1. Redistributions of source code must retain the above copyright notice, this\n - \\ list of conditions and the following disclaimer.\n - \\\n - \\2. Redistributions in binary form must reproduce the above copyright\n - \\ notice, this list of conditions and the following disclaimer in the\n - \\ documentation and/or other materials provided with the distribution.\n - \\\n - \\3. Neither the name of Nordic Semiconductor ASA nor the names of its\n - \\ contributors may be used to endorse or promote products derived from this\n - \\ software without specific prior written permission.\n - \\\n - \\THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n - \\AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n - \\IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n - \\ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n - \\LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n - \\CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n - \\SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n - \\INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n - \\CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n - \\ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n - \\POSSIBILITY OF SUCH DAMAGE.\n - \\ - ; - pub const @"cpu.name" = "CM4"; - pub const @"cpu.endian" = "little"; - }; - - pub const VectorTable = extern struct { - const Handler = micro.interrupt.Handler; - const unhandled = micro.interrupt.unhandled; - - initial_stack_pointer: u32, - Reset: Handler = unhandled, - NMI: Handler = unhandled, - HardFault: Handler = unhandled, - MemManageFault: Handler = unhandled, - BusFault: Handler = unhandled, - UsageFault: Handler = unhandled, - reserved5: [4]u32 = undefined, - SVCall: Handler = unhandled, - DebugMonitor: Handler = unhandled, - reserved11: [1]u32 = undefined, - PendSV: Handler = unhandled, - SysTick: Handler = unhandled, - POWER_CLOCK: Handler = unhandled, - RADIO: Handler = unhandled, - UARTE0_UART0: Handler = unhandled, - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: Handler = unhandled, - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: Handler = unhandled, - NFCT: Handler = unhandled, - GPIOTE: Handler = unhandled, - SAADC: Handler = unhandled, - TIMER0: Handler = unhandled, - TIMER1: Handler = unhandled, - TIMER2: Handler = unhandled, - RTC0: Handler = unhandled, - TEMP: Handler = unhandled, - RNG: Handler = unhandled, - ECB: Handler = unhandled, - CCM_AAR: Handler = unhandled, - WDT: Handler = unhandled, - RTC1: Handler = unhandled, - QDEC: Handler = unhandled, - COMP_LPCOMP: Handler = unhandled, - SWI0_EGU0: Handler = unhandled, - SWI1_EGU1: Handler = unhandled, - SWI2_EGU2: Handler = unhandled, - SWI3_EGU3: Handler = unhandled, - SWI4_EGU4: Handler = unhandled, - SWI5_EGU5: Handler = unhandled, - TIMER3: Handler = unhandled, - TIMER4: Handler = unhandled, - PWM0: Handler = unhandled, - PDM: Handler = unhandled, - reserved44: [2]u32 = undefined, - MWU: Handler = unhandled, - PWM1: Handler = unhandled, - PWM2: Handler = unhandled, - SPIM2_SPIS2_SPI2: Handler = unhandled, - RTC2: Handler = unhandled, - I2S: Handler = unhandled, - FPU: Handler = unhandled, - }; - - pub const peripherals = struct { - /// Factory Information Configuration Registers - pub const FICR = @as(*volatile types.peripherals.FICR, @ptrFromInt(0x10000000)); - /// User Information Configuration Registers - pub const UICR = @as(*volatile types.peripherals.UICR, @ptrFromInt(0x10001000)); - /// Block Protect - pub const BPROT = @as(*volatile types.peripherals.BPROT, @ptrFromInt(0x40000000)); - /// Power control - pub const POWER = @as(*volatile types.peripherals.POWER, @ptrFromInt(0x40000000)); - /// Clock control - pub const CLOCK = @as(*volatile types.peripherals.CLOCK, @ptrFromInt(0x40000000)); - /// 2.4 GHz Radio - pub const RADIO = @as(*volatile types.peripherals.RADIO, @ptrFromInt(0x40001000)); - /// UART with EasyDMA - pub const UARTE0 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40002000)); - /// Universal Asynchronous Receiver/Transmitter - pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40002000)); - /// Serial Peripheral Interface Master with EasyDMA 0 - pub const SPIM0 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40003000)); - /// SPI Slave 0 - pub const SPIS0 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40003000)); - /// I2C compatible Two-Wire Master Interface with EasyDMA 0 - pub const TWIM0 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40003000)); - /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 - pub const TWIS0 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40003000)); - /// Serial Peripheral Interface 0 - pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40003000)); - /// I2C compatible Two-Wire Interface 0 - pub const TWI0 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40003000)); - /// Serial Peripheral Interface Master with EasyDMA 1 - pub const SPIM1 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40004000)); - /// SPI Slave 1 - pub const SPIS1 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40004000)); - /// I2C compatible Two-Wire Master Interface with EasyDMA 1 - pub const TWIM1 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40004000)); - /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 - pub const TWIS1 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40004000)); - /// Serial Peripheral Interface 1 - pub const SPI1 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40004000)); - /// I2C compatible Two-Wire Interface 1 - pub const TWI1 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40004000)); - /// NFC-A compatible radio - pub const NFCT = @as(*volatile types.peripherals.NFCT, @ptrFromInt(0x40005000)); - /// GPIO Tasks and Events - pub const GPIOTE = @as(*volatile types.peripherals.GPIOTE, @ptrFromInt(0x40006000)); - /// Analog to Digital Converter - pub const SAADC = @as(*volatile types.peripherals.SAADC, @ptrFromInt(0x40007000)); - /// Timer/Counter 0 - pub const TIMER0 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40008000)); - /// Timer/Counter 1 - pub const TIMER1 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40009000)); - /// Timer/Counter 2 - pub const TIMER2 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4000a000)); - /// Real time counter 0 - pub const RTC0 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x4000b000)); - /// Temperature Sensor - pub const TEMP = @as(*volatile types.peripherals.TEMP, @ptrFromInt(0x4000c000)); - /// Random Number Generator - pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x4000d000)); - /// AES ECB Mode Encryption - pub const ECB = @as(*volatile types.peripherals.ECB, @ptrFromInt(0x4000e000)); - /// AES CCM Mode Encryption - pub const CCM = @as(*volatile types.peripherals.CCM, @ptrFromInt(0x4000f000)); - /// Accelerated Address Resolver - pub const AAR = @as(*volatile types.peripherals.AAR, @ptrFromInt(0x4000f000)); - /// Watchdog Timer - pub const WDT = @as(*volatile types.peripherals.WDT, @ptrFromInt(0x40010000)); - /// Real time counter 1 - pub const RTC1 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40011000)); - /// Quadrature Decoder - pub const QDEC = @as(*volatile types.peripherals.QDEC, @ptrFromInt(0x40012000)); - /// Comparator - pub const COMP = @as(*volatile types.peripherals.COMP, @ptrFromInt(0x40013000)); - /// Low Power Comparator - pub const LPCOMP = @as(*volatile types.peripherals.LPCOMP, @ptrFromInt(0x40013000)); - /// Software interrupt 0 - pub const SWI0 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40014000)); - /// Event Generator Unit 0 - pub const EGU0 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40014000)); - /// Software interrupt 1 - pub const SWI1 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40015000)); - /// Event Generator Unit 1 - pub const EGU1 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40015000)); - /// Software interrupt 2 - pub const SWI2 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40016000)); - /// Event Generator Unit 2 - pub const EGU2 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40016000)); - /// Software interrupt 3 - pub const SWI3 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40017000)); - /// Event Generator Unit 3 - pub const EGU3 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40017000)); - /// Software interrupt 4 - pub const SWI4 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40018000)); - /// Event Generator Unit 4 - pub const EGU4 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40018000)); - /// Software interrupt 5 - pub const SWI5 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40019000)); - /// Event Generator Unit 5 - pub const EGU5 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40019000)); - /// Timer/Counter 3 - pub const TIMER3 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001a000)); - /// Timer/Counter 4 - pub const TIMER4 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001b000)); - /// Pulse Width Modulation Unit 0 - pub const PWM0 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4001c000)); - /// Pulse Density Modulation (Digital Microphone) Interface - pub const PDM = @as(*volatile types.peripherals.PDM, @ptrFromInt(0x4001d000)); - /// Non Volatile Memory Controller - pub const NVMC = @as(*volatile types.peripherals.NVMC, @ptrFromInt(0x4001e000)); - /// Programmable Peripheral Interconnect - pub const PPI = @as(*volatile types.peripherals.PPI, @ptrFromInt(0x4001f000)); - /// Memory Watch Unit - pub const MWU = @as(*volatile types.peripherals.MWU, @ptrFromInt(0x40020000)); - /// Pulse Width Modulation Unit 1 - pub const PWM1 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40021000)); - /// Pulse Width Modulation Unit 2 - pub const PWM2 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40022000)); - /// Serial Peripheral Interface Master with EasyDMA 2 - pub const SPIM2 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40023000)); - /// SPI Slave 2 - pub const SPIS2 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40023000)); - /// Serial Peripheral Interface 2 - pub const SPI2 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40023000)); - /// Real time counter 2 - pub const RTC2 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40024000)); - /// Inter-IC Sound - pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x40025000)); - /// FPU - pub const FPU = @as(*volatile types.peripherals.FPU, @ptrFromInt(0x40026000)); - /// GPIO Port 1 - pub const P0 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000000)); - /// System Tick Timer - pub const SysTick = @as(*volatile types.peripherals.SCS.SysTick, @ptrFromInt(0xe000e010)); - }; - }; -}; - -pub const types = struct { - pub const peripherals = struct { - /// System Control Space - pub const SCS = struct { - /// System Tick Timer - pub const SysTick = extern struct { - /// SysTick Control and Status Register - CTRL: mmio.Mmio(packed struct(u32) { - ENABLE: u1, - TICKINT: u1, - CLKSOURCE: u1, - reserved16: u13, - COUNTFLAG: u1, - padding: u15, - }), - /// SysTick Reload Value Register - LOAD: mmio.Mmio(packed struct(u32) { - RELOAD: u24, - padding: u8, - }), - /// SysTick Current Value Register - VAL: mmio.Mmio(packed struct(u32) { - CURRENT: u24, - padding: u8, - }), - /// SysTick Calibration Register - CALIB: mmio.Mmio(packed struct(u32) { - TENMS: u24, - reserved30: u6, - SKEW: u1, - NOREF: u1, - }), - }; - }; - - /// Factory Information Configuration Registers - pub const FICR = extern struct { - reserved16: [16]u8, - /// Code memory page size - CODEPAGESIZE: mmio.Mmio(packed struct(u32) { - /// Code memory page size - CODEPAGESIZE: u32, - }), - /// Code memory size - CODESIZE: mmio.Mmio(packed struct(u32) { - /// Code memory size in number of pages - CODESIZE: u32, - }), - reserved96: [72]u8, - /// Description collection[0]: Device identifier - DEVICEID: [2]mmio.Mmio(packed struct(u32) { - /// 64 bit unique device identifier - DEVICEID: u32, - }), - reserved128: [24]u8, - /// Description collection[0]: Encryption Root, word 0 - ER: [4]mmio.Mmio(packed struct(u32) { - /// Encryption Root, word n - ER: u32, - }), - /// Description collection[0]: Identity Root, word 0 - IR: [4]mmio.Mmio(packed struct(u32) { - /// Identity Root, word n - IR: u32, - }), - /// Device address type - DEVICEADDRTYPE: mmio.Mmio(packed struct(u32) { - /// Device address type - DEVICEADDRTYPE: packed union { - raw: u1, - value: enum(u1) { - /// Public address - Public = 0x0, - /// Random address - Random = 0x1, - }, - }, - padding: u31, - }), - /// Description collection[0]: Device address 0 - DEVICEADDR: [2]mmio.Mmio(packed struct(u32) { - /// 48 bit device address - DEVICEADDR: u32, - }), - }; - - /// User Information Configuration Registers - pub const UICR = extern struct { - /// Unspecified - UNUSED0: u32, - /// Unspecified - UNUSED1: u32, - /// Unspecified - UNUSED2: u32, - reserved16: [4]u8, - /// Unspecified - UNUSED3: u32, - /// Description collection[0]: Reserved for Nordic firmware design - NRFFW: [15]mmio.Mmio(packed struct(u32) { - /// Reserved for Nordic firmware design - NRFFW: u32, - }), - /// Description collection[0]: Reserved for Nordic hardware design - NRFHW: [12]mmio.Mmio(packed struct(u32) { - /// Reserved for Nordic hardware design - NRFHW: u32, - }), - /// Description collection[0]: Reserved for customer - CUSTOMER: [32]mmio.Mmio(packed struct(u32) { - /// Reserved for customer - CUSTOMER: u32, - }), - reserved512: [256]u8, - /// Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) - PSELRESET: [2]mmio.Mmio(packed struct(u32) { - /// GPIO number P0.n onto which Reset is exposed - PIN: u6, - reserved31: u25, - /// Connection - CONNECT: packed union { - raw: u1, - value: enum(u1) { - /// Disconnect - Disconnected = 0x1, - /// Connect - Connected = 0x0, - }, - }, - }), - /// Access Port protection - APPROTECT: mmio.Mmio(packed struct(u32) { - /// Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. - PALL: packed union { - raw: u8, - value: enum(u8) { - /// Disable - Disabled = 0xff, - /// Enable - Enabled = 0x0, - _, - }, - }, - padding: u24, - }), - /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO - NFCPINS: mmio.Mmio(packed struct(u32) { - /// Setting of pins dedicated to NFC functionality - PROTECT: packed union { - raw: u1, - value: enum(u1) { - /// Operation as GPIO pins. Same protection as normal GPIO pins - Disabled = 0x0, - /// Operation as NFC antenna pins. Configures the protection for NFC operation - NFC = 0x1, - }, - }, - padding: u31, - }), - }; - - /// Block Protect - pub const BPROT = extern struct { - reserved1536: [1536]u8, - /// Block protect configuration register 0 - CONFIG0: mmio.Mmio(packed struct(u32) { - /// Enable protection for region 0. Write '0' has no effect. - REGION0: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 1. Write '0' has no effect. - REGION1: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 2. Write '0' has no effect. - REGION2: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 3. Write '0' has no effect. - REGION3: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 4. Write '0' has no effect. - REGION4: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 5. Write '0' has no effect. - REGION5: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 6. Write '0' has no effect. - REGION6: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 7. Write '0' has no effect. - REGION7: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 8. Write '0' has no effect. - REGION8: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 9. Write '0' has no effect. - REGION9: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 10. Write '0' has no effect. - REGION10: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 11. Write '0' has no effect. - REGION11: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 12. Write '0' has no effect. - REGION12: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 13. Write '0' has no effect. - REGION13: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 14. Write '0' has no effect. - REGION14: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 15. Write '0' has no effect. - REGION15: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 16. Write '0' has no effect. - REGION16: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 17. Write '0' has no effect. - REGION17: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 18. Write '0' has no effect. - REGION18: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 19. Write '0' has no effect. - REGION19: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 20. Write '0' has no effect. - REGION20: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 21. Write '0' has no effect. - REGION21: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 22. Write '0' has no effect. - REGION22: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 23. Write '0' has no effect. - REGION23: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 24. Write '0' has no effect. - REGION24: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 25. Write '0' has no effect. - REGION25: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 26. Write '0' has no effect. - REGION26: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 27. Write '0' has no effect. - REGION27: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 28. Write '0' has no effect. - REGION28: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 29. Write '0' has no effect. - REGION29: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 30. Write '0' has no effect. - REGION30: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - /// Enable protection for region 31. Write '0' has no effect. - REGION31: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enable - Enabled = 0x1, - }, - }, - }), - /// Block protect configuration register 1 - CONFIG1: mmio.Mmio(packed struct(u32) { - /// Enable protection for region 32. Write '0' has no effect. - REGION32: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 33. Write '0' has no effect. - REGION33: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 34. Write '0' has no effect. - REGION34: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 35. Write '0' has no effect. - REGION35: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 36. Write '0' has no effect. - REGION36: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 37. Write '0' has no effect. - REGION37: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 38. Write '0' has no effect. - REGION38: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 39. Write '0' has no effect. - REGION39: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 40. Write '0' has no effect. - REGION40: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 41. Write '0' has no effect. - REGION41: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 42. Write '0' has no effect. - REGION42: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 43. Write '0' has no effect. - REGION43: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 44. Write '0' has no effect. - REGION44: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 45. Write '0' has no effect. - REGION45: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 46. Write '0' has no effect. - REGION46: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 47. Write '0' has no effect. - REGION47: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 48. Write '0' has no effect. - REGION48: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 49. Write '0' has no effect. - REGION49: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 50. Write '0' has no effect. - REGION50: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 51. Write '0' has no effect. - REGION51: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 52. Write '0' has no effect. - REGION52: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 53. Write '0' has no effect. - REGION53: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 54. Write '0' has no effect. - REGION54: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 55. Write '0' has no effect. - REGION55: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 56. Write '0' has no effect. - REGION56: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 57. Write '0' has no effect. - REGION57: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 58. Write '0' has no effect. - REGION58: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 59. Write '0' has no effect. - REGION59: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 60. Write '0' has no effect. - REGION60: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 61. Write '0' has no effect. - REGION61: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 62. Write '0' has no effect. - REGION62: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 63. Write '0' has no effect. - REGION63: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - }), - /// Disable protection mechanism in debug interface mode - DISABLEINDEBUG: mmio.Mmio(packed struct(u32) { - /// Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. - DISABLEINDEBUG: packed union { - raw: u1, - value: enum(u1) { - /// Disable in debug - Disabled = 0x1, - /// Enable in debug - Enabled = 0x0, - }, - }, - padding: u31, - }), - /// Unspecified - UNUSED0: u32, - /// Block protect configuration register 2 - CONFIG2: mmio.Mmio(packed struct(u32) { - /// Enable protection for region 64. Write '0' has no effect. - REGION64: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 65. Write '0' has no effect. - REGION65: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 66. Write '0' has no effect. - REGION66: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 67. Write '0' has no effect. - REGION67: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 68. Write '0' has no effect. - REGION68: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 69. Write '0' has no effect. - REGION69: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 70. Write '0' has no effect. - REGION70: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 71. Write '0' has no effect. - REGION71: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 72. Write '0' has no effect. - REGION72: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 73. Write '0' has no effect. - REGION73: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 74. Write '0' has no effect. - REGION74: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 75. Write '0' has no effect. - REGION75: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 76. Write '0' has no effect. - REGION76: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 77. Write '0' has no effect. - REGION77: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 78. Write '0' has no effect. - REGION78: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 79. Write '0' has no effect. - REGION79: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 80. Write '0' has no effect. - REGION80: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 81. Write '0' has no effect. - REGION81: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 82. Write '0' has no effect. - REGION82: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 83. Write '0' has no effect. - REGION83: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 84. Write '0' has no effect. - REGION84: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 85. Write '0' has no effect. - REGION85: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 86. Write '0' has no effect. - REGION86: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 87. Write '0' has no effect. - REGION87: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 88. Write '0' has no effect. - REGION88: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 89. Write '0' has no effect. - REGION89: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 90. Write '0' has no effect. - REGION90: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 91. Write '0' has no effect. - REGION91: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 92. Write '0' has no effect. - REGION92: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 93. Write '0' has no effect. - REGION93: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 94. Write '0' has no effect. - REGION94: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 95. Write '0' has no effect. - REGION95: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - }), - /// Block protect configuration register 3 - CONFIG3: mmio.Mmio(packed struct(u32) { - /// Enable protection for region 96. Write '0' has no effect. - REGION96: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 97. Write '0' has no effect. - REGION97: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 98. Write '0' has no effect. - REGION98: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 99. Write '0' has no effect. - REGION99: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 100. Write '0' has no effect. - REGION100: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 101. Write '0' has no effect. - REGION101: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 102. Write '0' has no effect. - REGION102: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 103. Write '0' has no effect. - REGION103: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 104. Write '0' has no effect. - REGION104: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 105. Write '0' has no effect. - REGION105: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 106. Write '0' has no effect. - REGION106: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 107. Write '0' has no effect. - REGION107: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 108. Write '0' has no effect. - REGION108: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 109. Write '0' has no effect. - REGION109: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 110. Write '0' has no effect. - REGION110: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 111. Write '0' has no effect. - REGION111: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 112. Write '0' has no effect. - REGION112: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 113. Write '0' has no effect. - REGION113: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 114. Write '0' has no effect. - REGION114: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 115. Write '0' has no effect. - REGION115: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 116. Write '0' has no effect. - REGION116: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 117. Write '0' has no effect. - REGION117: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 118. Write '0' has no effect. - REGION118: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 119. Write '0' has no effect. - REGION119: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 120. Write '0' has no effect. - REGION120: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 121. Write '0' has no effect. - REGION121: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 122. Write '0' has no effect. - REGION122: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 123. Write '0' has no effect. - REGION123: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 124. Write '0' has no effect. - REGION124: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 125. Write '0' has no effect. - REGION125: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 126. Write '0' has no effect. - REGION126: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - /// Enable protection for region 127. Write '0' has no effect. - REGION127: packed union { - raw: u1, - value: enum(u1) { - /// Protection disabled - Disabled = 0x0, - /// Protection enabled - Enabled = 0x1, - }, - }, - }), - }; - - /// Power control - pub const POWER = extern struct { - reserved120: [120]u8, - /// Enable constant latency mode - TASKS_CONSTLAT: u32, - /// Enable low power mode (variable latency) - TASKS_LOWPWR: u32, - reserved264: [136]u8, - /// Power failure warning - EVENTS_POFWARN: u32, - reserved276: [8]u8, - /// CPU entered WFI/WFE sleep - EVENTS_SLEEPENTER: u32, - /// CPU exited WFI/WFE sleep - EVENTS_SLEEPEXIT: u32, - reserved772: [488]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Write '1' to Enable interrupt for POFWARN event - POFWARN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved5: u2, - /// Write '1' to Enable interrupt for SLEEPENTER event - SLEEPENTER: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for SLEEPEXIT event - SLEEPEXIT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u25, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Write '1' to Disable interrupt for POFWARN event - POFWARN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved5: u2, - /// Write '1' to Disable interrupt for SLEEPENTER event - SLEEPENTER: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for SLEEPEXIT event - SLEEPEXIT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u25, - }), - reserved1024: [244]u8, - /// Reset reason - RESETREAS: mmio.Mmio(packed struct(u32) { - /// Reset from pin-reset detected - RESETPIN: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset from watchdog detected - DOG: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset from soft reset detected - SREQ: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset from CPU lock-up detected - LOCKUP: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - reserved16: u12, - /// Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO - OFF: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP - LPCOMP: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode - DIF: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset due to wake up from System OFF mode by NFC field detect - NFC: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - padding: u12, - }), - reserved1064: [36]u8, - /// Deprecated register - RAM status register - RAMSTATUS: mmio.Mmio(packed struct(u32) { - /// RAM block 0 is on or off/powering up - RAMBLOCK0: packed union { - raw: u1, - value: enum(u1) { - /// Off - Off = 0x0, - /// On - On = 0x1, - }, - }, - /// RAM block 1 is on or off/powering up - RAMBLOCK1: packed union { - raw: u1, - value: enum(u1) { - /// Off - Off = 0x0, - /// On - On = 0x1, - }, - }, - /// RAM block 2 is on or off/powering up - RAMBLOCK2: packed union { - raw: u1, - value: enum(u1) { - /// Off - Off = 0x0, - /// On - On = 0x1, - }, - }, - /// RAM block 3 is on or off/powering up - RAMBLOCK3: packed union { - raw: u1, - value: enum(u1) { - /// Off - Off = 0x0, - /// On - On = 0x1, - }, - }, - padding: u28, - }), - reserved1280: [212]u8, - /// System OFF register - SYSTEMOFF: mmio.Mmio(packed struct(u32) { - /// Enable System OFF mode - SYSTEMOFF: packed union { - raw: u1, - value: enum(u1) { - /// Enable System OFF mode - Enter = 0x1, - _, - }, - }, - padding: u31, - }), - reserved1296: [12]u8, - /// Power failure comparator configuration - POFCON: mmio.Mmio(packed struct(u32) { - /// Enable or disable power failure comparator - POF: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Power failure comparator threshold setting - THRESHOLD: packed union { - raw: u4, - value: enum(u4) { - /// Set threshold to 1.7 V - V17 = 0x4, - /// Set threshold to 1.8 V - V18 = 0x5, - /// Set threshold to 1.9 V - V19 = 0x6, - /// Set threshold to 2.0 V - V20 = 0x7, - /// Set threshold to 2.1 V - V21 = 0x8, - /// Set threshold to 2.2 V - V22 = 0x9, - /// Set threshold to 2.3 V - V23 = 0xa, - /// Set threshold to 2.4 V - V24 = 0xb, - /// Set threshold to 2.5 V - V25 = 0xc, - /// Set threshold to 2.6 V - V26 = 0xd, - /// Set threshold to 2.7 V - V27 = 0xe, - /// Set threshold to 2.8 V - V28 = 0xf, - _, - }, - }, - padding: u27, - }), - reserved1308: [8]u8, - /// General purpose retention register - GPREGRET: mmio.Mmio(packed struct(u32) { - /// General purpose retention register - GPREGRET: u8, - padding: u24, - }), - /// General purpose retention register - GPREGRET2: mmio.Mmio(packed struct(u32) { - /// General purpose retention register - GPREGRET: u8, - padding: u24, - }), - /// Deprecated register - RAM on/off register (this register is retained) - RAMON: mmio.Mmio(packed struct(u32) { - /// Keep RAM block 0 on or off in system ON Mode - ONRAM0: packed union { - raw: u1, - value: enum(u1) { - /// Off - RAM0Off = 0x0, - /// On - RAM0On = 0x1, - }, - }, - /// Keep RAM block 1 on or off in system ON Mode - ONRAM1: packed union { - raw: u1, - value: enum(u1) { - /// Off - RAM1Off = 0x0, - /// On - RAM1On = 0x1, - }, - }, - reserved16: u14, - /// Keep retention on RAM block 0 when RAM block is switched off - OFFRAM0: packed union { - raw: u1, - value: enum(u1) { - /// Off - RAM0Off = 0x0, - /// On - RAM0On = 0x1, - }, - }, - /// Keep retention on RAM block 1 when RAM block is switched off - OFFRAM1: packed union { - raw: u1, - value: enum(u1) { - /// Off - RAM1Off = 0x0, - /// On - RAM1On = 0x1, - }, - }, - padding: u14, - }), - reserved1364: [44]u8, - /// Deprecated register - RAM on/off register (this register is retained) - RAMONB: mmio.Mmio(packed struct(u32) { - /// Keep RAM block 2 on or off in system ON Mode - ONRAM2: packed union { - raw: u1, - value: enum(u1) { - /// Off - RAM2Off = 0x0, - /// On - RAM2On = 0x1, - }, - }, - /// Keep RAM block 3 on or off in system ON Mode - ONRAM3: packed union { - raw: u1, - value: enum(u1) { - /// Off - RAM3Off = 0x0, - /// On - RAM3On = 0x1, - }, - }, - reserved16: u14, - /// Keep retention on RAM block 2 when RAM block is switched off - OFFRAM2: packed union { - raw: u1, - value: enum(u1) { - /// Off - RAM2Off = 0x0, - /// On - RAM2On = 0x1, - }, - }, - /// Keep retention on RAM block 3 when RAM block is switched off - OFFRAM3: packed union { - raw: u1, - value: enum(u1) { - /// Off - RAM3Off = 0x0, - /// On - RAM3On = 0x1, - }, - }, - padding: u14, - }), - reserved1400: [32]u8, - /// DC/DC enable register - DCDCEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable DC/DC converter - DCDCEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - }; - - /// Clock control - pub const CLOCK = extern struct { - /// Start HFCLK crystal oscillator - TASKS_HFCLKSTART: u32, - /// Stop HFCLK crystal oscillator - TASKS_HFCLKSTOP: u32, - /// Start LFCLK source - TASKS_LFCLKSTART: u32, - /// Stop LFCLK source - TASKS_LFCLKSTOP: u32, - /// Start calibration of LFRC oscillator - TASKS_CAL: u32, - /// Start calibration timer - TASKS_CTSTART: u32, - /// Stop calibration timer - TASKS_CTSTOP: u32, - reserved256: [228]u8, - /// HFCLK oscillator started - EVENTS_HFCLKSTARTED: u32, - /// LFCLK started - EVENTS_LFCLKSTARTED: u32, - reserved268: [4]u8, - /// Calibration of LFCLK RC oscillator complete event - EVENTS_DONE: u32, - /// Calibration timer timeout - EVENTS_CTTO: u32, - reserved772: [496]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for HFCLKSTARTED event - HFCLKSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for LFCLKSTARTED event - LFCLKSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved3: u1, - /// Write '1' to Enable interrupt for DONE event - DONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CTTO event - CTTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u27, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for HFCLKSTARTED event - HFCLKSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for LFCLKSTARTED event - LFCLKSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved3: u1, - /// Write '1' to Disable interrupt for DONE event - DONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CTTO event - CTTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved1032: [252]u8, - /// Status indicating that HFCLKSTART task has been triggered - HFCLKRUN: mmio.Mmio(packed struct(u32) { - /// HFCLKSTART task triggered or not - STATUS: packed union { - raw: u1, - value: enum(u1) { - /// Task not triggered - NotTriggered = 0x0, - /// Task triggered - Triggered = 0x1, - }, - }, - padding: u31, - }), - /// HFCLK status - HFCLKSTAT: mmio.Mmio(packed struct(u32) { - /// Source of HFCLK - SRC: packed union { - raw: u1, - value: enum(u1) { - /// 64 MHz internal oscillator (HFINT) - RC = 0x0, - /// 64 MHz crystal oscillator (HFXO) - Xtal = 0x1, - }, - }, - reserved16: u15, - /// HFCLK state - STATE: packed union { - raw: u1, - value: enum(u1) { - /// HFCLK not running - NotRunning = 0x0, - /// HFCLK running - Running = 0x1, - }, - }, - padding: u15, - }), - reserved1044: [4]u8, - /// Status indicating that LFCLKSTART task has been triggered - LFCLKRUN: mmio.Mmio(packed struct(u32) { - /// LFCLKSTART task triggered or not - STATUS: packed union { - raw: u1, - value: enum(u1) { - /// Task not triggered - NotTriggered = 0x0, - /// Task triggered - Triggered = 0x1, - }, - }, - padding: u31, - }), - /// LFCLK status - LFCLKSTAT: mmio.Mmio(packed struct(u32) { - /// Source of LFCLK - SRC: packed union { - raw: u2, - value: enum(u2) { - /// 32.768 kHz RC oscillator - RC = 0x0, - /// 32.768 kHz crystal oscillator - Xtal = 0x1, - /// 32.768 kHz synthesized from HFCLK - Synth = 0x2, - _, - }, - }, - reserved16: u14, - /// LFCLK state - STATE: packed union { - raw: u1, - value: enum(u1) { - /// LFCLK not running - NotRunning = 0x0, - /// LFCLK running - Running = 0x1, - }, - }, - padding: u15, - }), - /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered - LFCLKSRCCOPY: mmio.Mmio(packed struct(u32) { - /// Clock source - SRC: packed union { - raw: u2, - value: enum(u2) { - /// 32.768 kHz RC oscillator - RC = 0x0, - /// 32.768 kHz crystal oscillator - Xtal = 0x1, - /// 32.768 kHz synthesized from HFCLK - Synth = 0x2, - _, - }, - }, - padding: u30, - }), - reserved1304: [248]u8, - /// Clock source for the LFCLK - LFCLKSRC: mmio.Mmio(packed struct(u32) { - /// Clock source - SRC: packed union { - raw: u2, - value: enum(u2) { - /// 32.768 kHz RC oscillator - RC = 0x0, - /// 32.768 kHz crystal oscillator - Xtal = 0x1, - /// 32.768 kHz synthesized from HFCLK - Synth = 0x2, - _, - }, - }, - reserved16: u14, - /// Enable or disable bypass of LFCLK crystal oscillator with external clock source - BYPASS: packed union { - raw: u1, - value: enum(u1) { - /// Disable (use with Xtal or low-swing external source) - Disabled = 0x0, - /// Enable (use with rail-to-rail external source) - Enabled = 0x1, - }, - }, - /// Enable or disable external source for LFCLK - EXTERNAL: packed union { - raw: u1, - value: enum(u1) { - /// Disable external source (use with Xtal) - Disabled = 0x0, - /// Enable use of external source instead of Xtal (SRC needs to be set to Xtal) - Enabled = 0x1, - }, - }, - padding: u14, - }), - reserved1336: [28]u8, - /// Calibration timer interval - CTIV: mmio.Mmio(packed struct(u32) { - /// Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. - CTIV: u7, - padding: u25, - }), - reserved1372: [32]u8, - /// Clocking options for the Trace Port debug interface - TRACECONFIG: mmio.Mmio(packed struct(u32) { - /// Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. - TRACEPORTSPEED: packed union { - raw: u2, - value: enum(u2) { - /// 32 MHz Trace Port clock (TRACECLK = 16 MHz) - @"32MHz" = 0x0, - /// 16 MHz Trace Port clock (TRACECLK = 8 MHz) - @"16MHz" = 0x1, - /// 8 MHz Trace Port clock (TRACECLK = 4 MHz) - @"8MHz" = 0x2, - /// 4 MHz Trace Port clock (TRACECLK = 2 MHz) - @"4MHz" = 0x3, - }, - }, - reserved16: u14, - /// Pin multiplexing of trace signals. - TRACEMUX: packed union { - raw: u2, - value: enum(u2) { - /// GPIOs multiplexed onto all trace-pins - GPIO = 0x0, - /// SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins - Serial = 0x1, - /// TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. - Parallel = 0x2, - _, - }, - }, - padding: u14, - }), - }; - - /// 2.4 GHz Radio - pub const RADIO = extern struct { - /// Enable RADIO in TX mode - TASKS_TXEN: u32, - /// Enable RADIO in RX mode - TASKS_RXEN: u32, - /// Start RADIO - TASKS_START: u32, - /// Stop RADIO - TASKS_STOP: u32, - /// Disable RADIO - TASKS_DISABLE: u32, - /// Start the RSSI and take one single sample of the receive signal strength. - TASKS_RSSISTART: u32, - /// Stop the RSSI measurement - TASKS_RSSISTOP: u32, - /// Start the bit counter - TASKS_BCSTART: u32, - /// Stop the bit counter - TASKS_BCSTOP: u32, - reserved256: [220]u8, - /// RADIO has ramped up and is ready to be started - EVENTS_READY: u32, - /// Address sent or received - EVENTS_ADDRESS: u32, - /// Packet payload sent or received - EVENTS_PAYLOAD: u32, - /// Packet sent or received - EVENTS_END: u32, - /// RADIO has been disabled - EVENTS_DISABLED: u32, - /// A device address match occurred on the last received packet - EVENTS_DEVMATCH: u32, - /// No device address match occurred on the last received packet - EVENTS_DEVMISS: u32, - /// Sampling of receive signal strength complete. - EVENTS_RSSIEND: u32, - reserved296: [8]u8, - /// Bit counter reached bit count value. - EVENTS_BCMATCH: u32, - reserved304: [4]u8, - /// Packet received with CRC ok - EVENTS_CRCOK: u32, - /// Packet received with CRC error - EVENTS_CRCERROR: u32, - reserved512: [200]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between READY event and START task - READY_START: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between END event and DISABLE task - END_DISABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between DISABLED event and TXEN task - DISABLED_TXEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between DISABLED event and RXEN task - DISABLED_RXEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between ADDRESS event and RSSISTART task - ADDRESS_RSSISTART: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between END event and START task - END_START: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between ADDRESS event and BCSTART task - ADDRESS_BCSTART: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - reserved8: u1, - /// Shortcut between DISABLED event and RSSISTOP task - DISABLED_RSSISTOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u23, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for ADDRESS event - ADDRESS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for PAYLOAD event - PAYLOAD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for DISABLED event - DISABLED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for DEVMATCH event - DEVMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for DEVMISS event - DEVMISS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for RSSIEND event - RSSIEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u2, - /// Write '1' to Enable interrupt for BCMATCH event - BCMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved12: u1, - /// Write '1' to Enable interrupt for CRCOK event - CRCOK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CRCERROR event - CRCERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u18, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for ADDRESS event - ADDRESS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for PAYLOAD event - PAYLOAD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for DISABLED event - DISABLED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for DEVMATCH event - DEVMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for DEVMISS event - DEVMISS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for RSSIEND event - RSSIEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u2, - /// Write '1' to Disable interrupt for BCMATCH event - BCMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved12: u1, - /// Write '1' to Disable interrupt for CRCOK event - CRCOK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CRCERROR event - CRCERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u18, - }), - reserved1024: [244]u8, - /// CRC status - CRCSTATUS: mmio.Mmio(packed struct(u32) { - /// CRC status of packet received - CRCSTATUS: packed union { - raw: u1, - value: enum(u1) { - /// Packet received with CRC error - CRCError = 0x0, - /// Packet received with CRC ok - CRCOk = 0x1, - }, - }, - padding: u31, - }), - reserved1032: [4]u8, - /// Received address - RXMATCH: mmio.Mmio(packed struct(u32) { - /// Received address - RXMATCH: u3, - padding: u29, - }), - /// CRC field of previously received packet - RXCRC: mmio.Mmio(packed struct(u32) { - /// CRC field of previously received packet - RXCRC: u24, - padding: u8, - }), - /// Device address match index - DAI: mmio.Mmio(packed struct(u32) { - /// Device address match index - DAI: u3, - padding: u29, - }), - reserved1284: [240]u8, - /// Packet pointer - PACKETPTR: mmio.Mmio(packed struct(u32) { - /// Packet pointer - PACKETPTR: u32, - }), - /// Frequency - FREQUENCY: mmio.Mmio(packed struct(u32) { - /// Radio channel frequency - FREQUENCY: u7, - reserved8: u1, - /// Channel map selection. - MAP: packed union { - raw: u1, - value: enum(u1) { - /// Channel map between 2400 MHZ .. 2500 MHz - Default = 0x0, - /// Channel map between 2360 MHZ .. 2460 MHz - Low = 0x1, - }, - }, - padding: u23, - }), - /// Output power - TXPOWER: mmio.Mmio(packed struct(u32) { - /// RADIO output power. - TXPOWER: packed union { - raw: u8, - value: enum(u8) { - /// +4 dBm - Pos4dBm = 0x4, - /// +3 dBm - Pos3dBm = 0x3, - /// 0 dBm - @"0dBm" = 0x0, - /// -4 dBm - Neg4dBm = 0xfc, - /// -8 dBm - Neg8dBm = 0xf8, - /// -12 dBm - Neg12dBm = 0xf4, - /// -16 dBm - Neg16dBm = 0xf0, - /// -20 dBm - Neg20dBm = 0xec, - /// Deprecated enumerator - -40 dBm - Neg30dBm = 0xff, - /// -40 dBm - Neg40dBm = 0xd8, - _, - }, - }, - padding: u24, - }), - /// Data rate and modulation - MODE: mmio.Mmio(packed struct(u32) { - /// Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. - MODE: packed union { - raw: u4, - value: enum(u4) { - /// 1 Mbit/s Nordic proprietary radio mode - Nrf_1Mbit = 0x0, - /// 2 Mbit/s Nordic proprietary radio mode - Nrf_2Mbit = 0x1, - /// Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode - Nrf_250Kbit = 0x2, - /// 1 Mbit/s Bluetooth Low Energy - Ble_1Mbit = 0x3, - /// 2 Mbit/s Bluetooth Low Energy - Ble_2Mbit = 0x4, - _, - }, - }, - padding: u28, - }), - /// Packet configuration register 0 - PCNF0: mmio.Mmio(packed struct(u32) { - /// Length on air of LENGTH field in number of bits. - LFLEN: u4, - reserved8: u4, - /// Length on air of S0 field in number of bytes. - S0LEN: u1, - reserved16: u7, - /// Length on air of S1 field in number of bits. - S1LEN: u4, - /// Include or exclude S1 field in RAM - S1INCL: packed union { - raw: u1, - value: enum(u1) { - /// Include S1 field in RAM only if S1LEN > 0 - Automatic = 0x0, - /// Always include S1 field in RAM independent of S1LEN - Include = 0x1, - }, - }, - reserved24: u3, - /// Length of preamble on air. Decision point: TASKS_START task - PLEN: packed union { - raw: u1, - value: enum(u1) { - /// 8-bit preamble - @"8bit" = 0x0, - /// 16-bit preamble - @"16bit" = 0x1, - }, - }, - padding: u7, - }), - /// Packet configuration register 1 - PCNF1: mmio.Mmio(packed struct(u32) { - /// Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. - MAXLEN: u8, - /// Static length in number of bytes - STATLEN: u8, - /// Base address length in number of bytes - BALEN: u3, - reserved24: u5, - /// On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. - ENDIAN: packed union { - raw: u1, - value: enum(u1) { - /// Least Significant bit on air first - Little = 0x0, - /// Most significant bit on air first - Big = 0x1, - }, - }, - /// Enable or disable packet whitening - WHITEEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u6, - }), - /// Base address 0 - BASE0: mmio.Mmio(packed struct(u32) { - /// Base address 0 - BASE0: u32, - }), - /// Base address 1 - BASE1: mmio.Mmio(packed struct(u32) { - /// Base address 1 - BASE1: u32, - }), - /// Prefixes bytes for logical addresses 0-3 - PREFIX0: mmio.Mmio(packed struct(u32) { - /// Address prefix 0. - AP0: u8, - /// Address prefix 1. - AP1: u8, - /// Address prefix 2. - AP2: u8, - /// Address prefix 3. - AP3: u8, - }), - /// Prefixes bytes for logical addresses 4-7 - PREFIX1: mmio.Mmio(packed struct(u32) { - /// Address prefix 4. - AP4: u8, - /// Address prefix 5. - AP5: u8, - /// Address prefix 6. - AP6: u8, - /// Address prefix 7. - AP7: u8, - }), - /// Transmit address select - TXADDRESS: mmio.Mmio(packed struct(u32) { - /// Transmit address select - TXADDRESS: u3, - padding: u29, - }), - /// Receive address select - RXADDRESSES: mmio.Mmio(packed struct(u32) { - /// Enable or disable reception on logical address 0. - ADDR0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 1. - ADDR1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 2. - ADDR2: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 3. - ADDR3: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 4. - ADDR4: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 5. - ADDR5: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 6. - ADDR6: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 7. - ADDR7: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u24, - }), - /// CRC configuration - CRCCNF: mmio.Mmio(packed struct(u32) { - /// CRC length in number of bytes. - LEN: packed union { - raw: u2, - value: enum(u2) { - /// CRC length is zero and CRC calculation is disabled - Disabled = 0x0, - /// CRC length is one byte and CRC calculation is enabled - One = 0x1, - /// CRC length is two bytes and CRC calculation is enabled - Two = 0x2, - /// CRC length is three bytes and CRC calculation is enabled - Three = 0x3, - }, - }, - reserved8: u6, - /// Include or exclude packet address field out of CRC calculation. - SKIPADDR: packed union { - raw: u1, - value: enum(u1) { - /// CRC calculation includes address field - Include = 0x0, - /// CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. - Skip = 0x1, - }, - }, - padding: u23, - }), - /// CRC polynomial - CRCPOLY: mmio.Mmio(packed struct(u32) { - /// CRC polynomial - CRCPOLY: u24, - padding: u8, - }), - /// CRC initial value - CRCINIT: mmio.Mmio(packed struct(u32) { - /// CRC initial value - CRCINIT: u24, - padding: u8, - }), - /// Unspecified - UNUSED0: u32, - /// Inter Frame Spacing in us - TIFS: mmio.Mmio(packed struct(u32) { - /// Inter Frame Spacing in us - TIFS: u8, - padding: u24, - }), - /// RSSI sample - RSSISAMPLE: mmio.Mmio(packed struct(u32) { - /// RSSI sample - RSSISAMPLE: u7, - padding: u25, - }), - reserved1360: [4]u8, - /// Current radio state - STATE: mmio.Mmio(packed struct(u32) { - /// Current radio state - STATE: packed union { - raw: u4, - value: enum(u4) { - /// RADIO is in the Disabled state - Disabled = 0x0, - /// RADIO is in the RXRU state - RxRu = 0x1, - /// RADIO is in the RXIDLE state - RxIdle = 0x2, - /// RADIO is in the RX state - Rx = 0x3, - /// RADIO is in the RXDISABLED state - RxDisable = 0x4, - /// RADIO is in the TXRU state - TxRu = 0x9, - /// RADIO is in the TXIDLE state - TxIdle = 0xa, - /// RADIO is in the TX state - Tx = 0xb, - /// RADIO is in the TXDISABLED state - TxDisable = 0xc, - _, - }, - }, - padding: u28, - }), - /// Data whitening initial value - DATAWHITEIV: mmio.Mmio(packed struct(u32) { - /// Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. - DATAWHITEIV: u7, - padding: u25, - }), - reserved1376: [8]u8, - /// Bit counter compare - BCC: mmio.Mmio(packed struct(u32) { - /// Bit counter compare - BCC: u32, - }), - reserved1536: [156]u8, - /// Description collection[0]: Device address base segment 0 - DAB: [8]mmio.Mmio(packed struct(u32) { - /// Device address base segment 0 - DAB: u32, - }), - /// Description collection[0]: Device address prefix 0 - DAP: [8]mmio.Mmio(packed struct(u32) { - /// Device address prefix 0 - DAP: u16, - padding: u16, - }), - /// Device address match configuration - DACNF: mmio.Mmio(packed struct(u32) { - /// Enable or disable device address matching using device address 0 - ENA0: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 1 - ENA1: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 2 - ENA2: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 3 - ENA3: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 4 - ENA4: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 5 - ENA5: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 6 - ENA6: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 7 - ENA7: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// TxAdd for device address 0 - TXADD0: u1, - /// TxAdd for device address 1 - TXADD1: u1, - /// TxAdd for device address 2 - TXADD2: u1, - /// TxAdd for device address 3 - TXADD3: u1, - /// TxAdd for device address 4 - TXADD4: u1, - /// TxAdd for device address 5 - TXADD5: u1, - /// TxAdd for device address 6 - TXADD6: u1, - /// TxAdd for device address 7 - TXADD7: u1, - padding: u16, - }), - reserved1616: [12]u8, - /// Radio mode configuration register 0 - MODECNF0: mmio.Mmio(packed struct(u32) { - /// Radio ramp-up time - RU: packed union { - raw: u1, - value: enum(u1) { - /// Default ramp-up time (tRXEN), compatible with firmware written for nRF51 - Default = 0x0, - /// Fast ramp-up (tRXEN,FAST), see electrical specification for more information - Fast = 0x1, - }, - }, - reserved8: u7, - /// Default TX value - DTX: packed union { - raw: u2, - value: enum(u2) { - /// Transmit '1' - B1 = 0x0, - /// Transmit '0' - B0 = 0x1, - /// Transmit center frequency - Center = 0x2, - _, - }, - }, - padding: u22, - }), - reserved4092: [2472]u8, - /// Peripheral power control - POWER: mmio.Mmio(packed struct(u32) { - /// Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. - POWER: packed union { - raw: u1, - value: enum(u1) { - /// Peripheral is powered off - Disabled = 0x0, - /// Peripheral is powered on - Enabled = 0x1, - }, - }, - padding: u31, - }), - }; - - /// UART with EasyDMA - pub const UARTE0 = extern struct { - /// Start UART receiver - TASKS_STARTRX: u32, - /// Stop UART receiver - TASKS_STOPRX: u32, - /// Start UART transmitter - TASKS_STARTTX: u32, - /// Stop UART transmitter - TASKS_STOPTX: u32, - reserved44: [28]u8, - /// Flush RX FIFO into RX buffer - TASKS_FLUSHRX: u32, - reserved256: [208]u8, - /// CTS is activated (set low). Clear To Send. - EVENTS_CTS: u32, - /// CTS is deactivated (set high). Not Clear To Send. - EVENTS_NCTS: u32, - /// Data received in RXD (but potentially not yet transferred to Data RAM) - EVENTS_RXDRDY: u32, - reserved272: [4]u8, - /// Receive buffer is filled up - EVENTS_ENDRX: u32, - reserved284: [8]u8, - /// Data sent from TXD - EVENTS_TXDRDY: u32, - /// Last TX byte transmitted - EVENTS_ENDTX: u32, - /// Error detected - EVENTS_ERROR: u32, - reserved324: [28]u8, - /// Receiver timeout - EVENTS_RXTO: u32, - reserved332: [4]u8, - /// UART receiver has started - EVENTS_RXSTARTED: u32, - /// UART transmitter has started - EVENTS_TXSTARTED: u32, - reserved344: [4]u8, - /// Transmitter stopped - EVENTS_TXSTOPPED: u32, - reserved512: [164]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Shortcut between ENDRX event and STARTRX task - ENDRX_STARTRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between ENDRX event and STOPRX task - ENDRX_STOPRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u25, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for CTS event - CTS: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for NCTS event - NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for RXDRDY event - RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved4: u1, - /// Enable or disable interrupt for ENDRX event - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved7: u2, - /// Enable or disable interrupt for TXDRDY event - TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for ENDTX event - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved17: u7, - /// Enable or disable interrupt for RXTO event - RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved19: u1, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved22: u1, - /// Enable or disable interrupt for TXSTOPPED event - TXSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u9, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for CTS event - CTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for NCTS event - NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for RXDRDY event - RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u1, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u2, - /// Write '1' to Enable interrupt for TXDRDY event - TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved17: u7, - /// Write '1' to Enable interrupt for RXTO event - RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u1, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved22: u1, - /// Write '1' to Enable interrupt for TXSTOPPED event - TXSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u9, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for CTS event - CTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for NCTS event - NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for RXDRDY event - RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u1, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u2, - /// Write '1' to Disable interrupt for TXDRDY event - TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved17: u7, - /// Write '1' to Disable interrupt for RXTO event - RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u1, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved22: u1, - /// Write '1' to Disable interrupt for TXSTOPPED event - TXSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u9, - }), - reserved1152: [372]u8, - /// Error source - ERRORSRC: mmio.Mmio(packed struct(u32) { - /// Overrun error - OVERRUN: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Parity error - PARITY: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Framing error occurred - FRAMING: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Break condition - BREAK: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - padding: u28, - }), - reserved1280: [124]u8, - /// Enable UART - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable UARTE - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable UARTE - Disabled = 0x0, - /// Enable UARTE - Enabled = 0x8, - _, - }, - }, - padding: u28, - }), - reserved1316: [32]u8, - /// Baud rate. Accuracy depends on the HFCLK source selected. - BAUDRATE: mmio.Mmio(packed struct(u32) { - /// Baud rate - BAUDRATE: packed union { - raw: u32, - value: enum(u32) { - /// 1200 baud (actual rate: 1205) - Baud1200 = 0x4f000, - /// 2400 baud (actual rate: 2396) - Baud2400 = 0x9d000, - /// 4800 baud (actual rate: 4808) - Baud4800 = 0x13b000, - /// 9600 baud (actual rate: 9598) - Baud9600 = 0x275000, - /// 14400 baud (actual rate: 14401) - Baud14400 = 0x3af000, - /// 19200 baud (actual rate: 19208) - Baud19200 = 0x4ea000, - /// 28800 baud (actual rate: 28777) - Baud28800 = 0x75c000, - /// 31250 baud - Baud31250 = 0x800000, - /// 38400 baud (actual rate: 38369) - Baud38400 = 0x9d0000, - /// 56000 baud (actual rate: 55944) - Baud56000 = 0xe50000, - /// 57600 baud (actual rate: 57554) - Baud57600 = 0xeb0000, - /// 76800 baud (actual rate: 76923) - Baud76800 = 0x13a9000, - /// 115200 baud (actual rate: 115108) - Baud115200 = 0x1d60000, - /// 230400 baud (actual rate: 231884) - Baud230400 = 0x3b00000, - /// 250000 baud - Baud250000 = 0x4000000, - /// 460800 baud (actual rate: 457143) - Baud460800 = 0x7400000, - /// 921600 baud (actual rate: 941176) - Baud921600 = 0xf000000, - /// 1Mega baud - Baud1M = 0x10000000, - _, - }, - }, - }), - reserved1388: [68]u8, - /// Configuration of parity and hardware flow control - CONFIG: mmio.Mmio(packed struct(u32) { - /// Hardware flow control - HWFC: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Parity - PARITY: packed union { - raw: u3, - value: enum(u3) { - /// Exclude parity bit - Excluded = 0x0, - /// Include parity bit - Included = 0x7, - _, - }, - }, - padding: u28, - }), - }; - - /// Universal Asynchronous Receiver/Transmitter - pub const UART0 = extern struct { - /// Start UART receiver - TASKS_STARTRX: u32, - /// Stop UART receiver - TASKS_STOPRX: u32, - /// Start UART transmitter - TASKS_STARTTX: u32, - /// Stop UART transmitter - TASKS_STOPTX: u32, - reserved28: [12]u8, - /// Suspend UART - TASKS_SUSPEND: u32, - reserved256: [224]u8, - /// CTS is activated (set low). Clear To Send. - EVENTS_CTS: u32, - /// CTS is deactivated (set high). Not Clear To Send. - EVENTS_NCTS: u32, - /// Data received in RXD - EVENTS_RXDRDY: u32, - reserved284: [16]u8, - /// Data sent from TXD - EVENTS_TXDRDY: u32, - reserved292: [4]u8, - /// Error detected - EVENTS_ERROR: u32, - reserved324: [28]u8, - /// Receiver timeout - EVENTS_RXTO: u32, - reserved512: [184]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Shortcut between CTS event and STARTRX task - CTS_STARTRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between NCTS event and STOPRX task - NCTS_STOPRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for CTS event - CTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for NCTS event - NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for RXDRDY event - RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u4, - /// Write '1' to Enable interrupt for TXDRDY event - TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved17: u7, - /// Write '1' to Enable interrupt for RXTO event - RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u14, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for CTS event - CTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for NCTS event - NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for RXDRDY event - RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u4, - /// Write '1' to Disable interrupt for TXDRDY event - TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved17: u7, - /// Write '1' to Disable interrupt for RXTO event - RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u14, - }), - reserved1152: [372]u8, - /// Error source - ERRORSRC: mmio.Mmio(packed struct(u32) { - /// Overrun error - OVERRUN: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Parity error - PARITY: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Framing error occurred - FRAMING: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Break condition - BREAK: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - padding: u28, - }), - reserved1280: [124]u8, - /// Enable UART - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable UART - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable UART - Disabled = 0x0, - /// Enable UART - Enabled = 0x4, - _, - }, - }, - padding: u28, - }), - reserved1288: [4]u8, - /// Pin select for RTS - PSELRTS: mmio.Mmio(packed struct(u32) { - /// Pin number configuration for UART RTS signal - PSELRTS: packed union { - raw: u32, - value: enum(u32) { - /// Disconnect - Disconnected = 0xffffffff, - _, - }, - }, - }), - /// Pin select for TXD - PSELTXD: mmio.Mmio(packed struct(u32) { - /// Pin number configuration for UART TXD signal - PSELTXD: packed union { - raw: u32, - value: enum(u32) { - /// Disconnect - Disconnected = 0xffffffff, - _, - }, - }, - }), - /// Pin select for CTS - PSELCTS: mmio.Mmio(packed struct(u32) { - /// Pin number configuration for UART CTS signal - PSELCTS: packed union { - raw: u32, - value: enum(u32) { - /// Disconnect - Disconnected = 0xffffffff, - _, - }, - }, - }), - /// Pin select for RXD - PSELRXD: mmio.Mmio(packed struct(u32) { - /// Pin number configuration for UART RXD signal - PSELRXD: packed union { - raw: u32, - value: enum(u32) { - /// Disconnect - Disconnected = 0xffffffff, - _, - }, - }, - }), - /// RXD register - RXD: mmio.Mmio(packed struct(u32) { - /// RX data received in previous transfers, double buffered - RXD: u8, - padding: u24, - }), - /// TXD register - TXD: mmio.Mmio(packed struct(u32) { - /// TX data to be transferred - TXD: u8, - padding: u24, - }), - reserved1316: [4]u8, - /// Baud rate - BAUDRATE: mmio.Mmio(packed struct(u32) { - /// Baud rate - BAUDRATE: packed union { - raw: u32, - value: enum(u32) { - /// 1200 baud (actual rate: 1205) - Baud1200 = 0x4f000, - /// 2400 baud (actual rate: 2396) - Baud2400 = 0x9d000, - /// 4800 baud (actual rate: 4808) - Baud4800 = 0x13b000, - /// 9600 baud (actual rate: 9598) - Baud9600 = 0x275000, - /// 14400 baud (actual rate: 14414) - Baud14400 = 0x3b0000, - /// 19200 baud (actual rate: 19208) - Baud19200 = 0x4ea000, - /// 28800 baud (actual rate: 28829) - Baud28800 = 0x75f000, - /// 31250 baud - Baud31250 = 0x800000, - /// 38400 baud (actual rate: 38462) - Baud38400 = 0x9d5000, - /// 56000 baud (actual rate: 55944) - Baud56000 = 0xe50000, - /// 57600 baud (actual rate: 57762) - Baud57600 = 0xebf000, - /// 76800 baud (actual rate: 76923) - Baud76800 = 0x13a9000, - /// 115200 baud (actual rate: 115942) - Baud115200 = 0x1d7e000, - /// 230400 baud (actual rate: 231884) - Baud230400 = 0x3afb000, - /// 250000 baud - Baud250000 = 0x4000000, - /// 460800 baud (actual rate: 470588) - Baud460800 = 0x75f7000, - /// 921600 baud (actual rate: 941176) - Baud921600 = 0xebed000, - /// 1Mega baud - Baud1M = 0x10000000, - _, - }, - }, - }), - reserved1388: [68]u8, - /// Configuration of parity and hardware flow control - CONFIG: mmio.Mmio(packed struct(u32) { - /// Hardware flow control - HWFC: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Parity - PARITY: packed union { - raw: u3, - value: enum(u3) { - /// Exclude parity bit - Excluded = 0x0, - /// Include parity bit - Included = 0x7, - _, - }, - }, - padding: u28, - }), - }; - - /// Serial Peripheral Interface Master with EasyDMA 0 - pub const SPIM0 = extern struct { - reserved16: [16]u8, - /// Start SPI transaction - TASKS_START: u32, - /// Stop SPI transaction - TASKS_STOP: u32, - reserved28: [4]u8, - /// Suspend SPI transaction - TASKS_SUSPEND: u32, - /// Resume SPI transaction - TASKS_RESUME: u32, - reserved260: [224]u8, - /// SPI transaction has stopped - EVENTS_STOPPED: u32, - reserved272: [8]u8, - /// End of RXD buffer reached - EVENTS_ENDRX: u32, - reserved280: [4]u8, - /// End of RXD buffer and TXD buffer reached - EVENTS_END: u32, - reserved288: [4]u8, - /// End of TXD buffer reached - EVENTS_ENDTX: u32, - reserved332: [40]u8, - /// Transaction started - EVENTS_STARTED: u32, - reserved512: [176]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - reserved17: u17, - /// Shortcut between END event and START task - END_START: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u14, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u2, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved6: u1, - /// Write '1' to Enable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved8: u1, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u10, - /// Write '1' to Enable interrupt for STARTED event - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u2, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved6: u1, - /// Write '1' to Disable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved8: u1, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u10, - /// Write '1' to Disable interrupt for STARTED event - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - reserved1280: [500]u8, - /// Enable SPIM - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable SPIM - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable SPIM - Disabled = 0x0, - /// Enable SPIM - Enabled = 0x7, - _, - }, - }, - padding: u28, - }), - reserved1316: [32]u8, - /// SPI frequency. Accuracy depends on the HFCLK source selected. - FREQUENCY: mmio.Mmio(packed struct(u32) { - /// SPI master data rate - FREQUENCY: packed union { - raw: u32, - value: enum(u32) { - /// 125 kbps - K125 = 0x2000000, - /// 250 kbps - K250 = 0x4000000, - /// 500 kbps - K500 = 0x8000000, - /// 1 Mbps - M1 = 0x10000000, - /// 2 Mbps - M2 = 0x20000000, - /// 4 Mbps - M4 = 0x40000000, - /// 8 Mbps - M8 = 0x80000000, - _, - }, - }, - }), - reserved1364: [44]u8, - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Bit order - ORDER: packed union { - raw: u1, - value: enum(u1) { - /// Most significant bit shifted out first - MsbFirst = 0x0, - /// Least significant bit shifted out first - LsbFirst = 0x1, - }, - }, - /// Serial clock (SCK) phase - CPHA: packed union { - raw: u1, - value: enum(u1) { - /// Sample on leading edge of clock, shift serial data on trailing edge - Leading = 0x0, - /// Sample on trailing edge of clock, shift serial data on leading edge - Trailing = 0x1, - }, - }, - /// Serial clock (SCK) polarity - CPOL: packed union { - raw: u1, - value: enum(u1) { - /// Active high - ActiveHigh = 0x0, - /// Active low - ActiveLow = 0x1, - }, - }, - padding: u29, - }), - reserved1472: [104]u8, - /// Over-read character. Character clocked out in case and over-read of the TXD buffer. - ORC: mmio.Mmio(packed struct(u32) { - /// Over-read character. Character clocked out in case and over-read of the TXD buffer. - ORC: u8, - padding: u24, - }), - }; - - /// SPI Slave 0 - pub const SPIS0 = extern struct { - reserved36: [36]u8, - /// Acquire SPI semaphore - TASKS_ACQUIRE: u32, - /// Release SPI semaphore, enabling the SPI slave to acquire it - TASKS_RELEASE: u32, - reserved260: [216]u8, - /// Granted transaction completed - EVENTS_END: u32, - reserved272: [8]u8, - /// End of RXD buffer reached - EVENTS_ENDRX: u32, - reserved296: [20]u8, - /// Semaphore acquired - EVENTS_ACQUIRED: u32, - reserved512: [212]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Shortcut between END event and ACQUIRE task - END_ACQUIRE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u29, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Enable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u2, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u5, - /// Write '1' to Enable interrupt for ACQUIRED event - ACQUIRED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u21, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Disable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u2, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u5, - /// Write '1' to Disable interrupt for ACQUIRED event - ACQUIRED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u21, - }), - reserved1024: [244]u8, - /// Semaphore status register - SEMSTAT: mmio.Mmio(packed struct(u32) { - /// Semaphore status - SEMSTAT: packed union { - raw: u2, - value: enum(u2) { - /// Semaphore is free - Free = 0x0, - /// Semaphore is assigned to CPU - CPU = 0x1, - /// Semaphore is assigned to SPI slave - SPIS = 0x2, - /// Semaphore is assigned to SPI but a handover to the CPU is pending - CPUPending = 0x3, - }, - }, - padding: u30, - }), - reserved1088: [60]u8, - /// Status from last transaction - STATUS: mmio.Mmio(packed struct(u32) { - /// TX buffer over-read detected, and prevented - OVERREAD: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// RX buffer overflow detected, and prevented - OVERFLOW: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - padding: u30, - }), - reserved1280: [188]u8, - /// Enable SPI slave - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable SPI slave - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable SPI slave - Disabled = 0x0, - /// Enable SPI slave - Enabled = 0x2, - _, - }, - }, - padding: u28, - }), - reserved1364: [80]u8, - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Bit order - ORDER: packed union { - raw: u1, - value: enum(u1) { - /// Most significant bit shifted out first - MsbFirst = 0x0, - /// Least significant bit shifted out first - LsbFirst = 0x1, - }, - }, - /// Serial clock (SCK) phase - CPHA: packed union { - raw: u1, - value: enum(u1) { - /// Sample on leading edge of clock, shift serial data on trailing edge - Leading = 0x0, - /// Sample on trailing edge of clock, shift serial data on leading edge - Trailing = 0x1, - }, - }, - /// Serial clock (SCK) polarity - CPOL: packed union { - raw: u1, - value: enum(u1) { - /// Active high - ActiveHigh = 0x0, - /// Active low - ActiveLow = 0x1, - }, - }, - padding: u29, - }), - reserved1372: [4]u8, - /// Default character. Character clocked out in case of an ignored transaction. - DEF: mmio.Mmio(packed struct(u32) { - /// Default character. Character clocked out in case of an ignored transaction. - DEF: u8, - padding: u24, - }), - reserved1472: [96]u8, - /// Over-read character - ORC: mmio.Mmio(packed struct(u32) { - /// Over-read character. Character clocked out after an over-read of the transmit buffer. - ORC: u8, - padding: u24, - }), - }; - - /// I2C compatible Two-Wire Master Interface with EasyDMA 0 - pub const TWIM0 = extern struct { - /// Start TWI receive sequence - TASKS_STARTRX: u32, - reserved8: [4]u8, - /// Start TWI transmit sequence - TASKS_STARTTX: u32, - reserved20: [8]u8, - /// Stop TWI transaction. Must be issued while the TWI master is not suspended. - TASKS_STOP: u32, - reserved28: [4]u8, - /// Suspend TWI transaction - TASKS_SUSPEND: u32, - /// Resume TWI transaction - TASKS_RESUME: u32, - reserved260: [224]u8, - /// TWI stopped - EVENTS_STOPPED: u32, - reserved292: [28]u8, - /// TWI error - EVENTS_ERROR: u32, - reserved328: [32]u8, - /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. - EVENTS_SUSPENDED: u32, - /// Receive sequence started - EVENTS_RXSTARTED: u32, - /// Transmit sequence started - EVENTS_TXSTARTED: u32, - reserved348: [8]u8, - /// Byte boundary, starting to receive the last byte - EVENTS_LASTRX: u32, - /// Byte boundary, starting to transmit the last byte - EVENTS_LASTTX: u32, - reserved512: [156]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// Shortcut between LASTTX event and STARTRX task - LASTTX_STARTRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between LASTTX event and SUSPEND task - LASTTX_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between LASTTX event and STOP task - LASTTX_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between LASTRX event and STARTTX task - LASTRX_STARTTX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - reserved12: u1, - /// Shortcut between LASTRX event and STOP task - LASTRX_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u19, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Enable or disable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved18: u8, - /// Enable or disable interrupt for SUSPENDED event - SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved23: u2, - /// Enable or disable interrupt for LASTRX event - LASTRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for LASTTX event - LASTTX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u7, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Write '1' to Enable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u8, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved23: u2, - /// Write '1' to Enable interrupt for LASTRX event - LASTRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for LASTTX event - LASTTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u7, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Write '1' to Disable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u8, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved23: u2, - /// Write '1' to Disable interrupt for LASTRX event - LASTRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for LASTTX event - LASTTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u7, - }), - reserved1220: [440]u8, - /// Error source - ERRORSRC: mmio.Mmio(packed struct(u32) { - /// Overrun error - OVERRUN: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotReceived = 0x0, - /// Error occurred - Received = 0x1, - }, - }, - /// NACK received after sending the address (write '1' to clear) - ANACK: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotReceived = 0x0, - /// Error occurred - Received = 0x1, - }, - }, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotReceived = 0x0, - /// Error occurred - Received = 0x1, - }, - }, - padding: u29, - }), - reserved1280: [56]u8, - /// Enable TWIM - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable TWIM - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable TWIM - Disabled = 0x0, - /// Enable TWIM - Enabled = 0x6, - _, - }, - }, - padding: u28, - }), - reserved1316: [32]u8, - /// TWI frequency - FREQUENCY: mmio.Mmio(packed struct(u32) { - /// TWI master clock frequency - FREQUENCY: packed union { - raw: u32, - value: enum(u32) { - /// 100 kbps - K100 = 0x1980000, - /// 250 kbps - K250 = 0x4000000, - /// 400 kbps - K400 = 0x6400000, - _, - }, - }, - }), - reserved1416: [96]u8, - /// Address used in the TWI transfer - ADDRESS: mmio.Mmio(packed struct(u32) { - /// Address used in the TWI transfer - ADDRESS: u7, - padding: u25, - }), - }; - - /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 - pub const TWIS0 = extern struct { - reserved20: [20]u8, - /// Stop TWI transaction - TASKS_STOP: u32, - reserved28: [4]u8, - /// Suspend TWI transaction - TASKS_SUSPEND: u32, - /// Resume TWI transaction - TASKS_RESUME: u32, - reserved48: [12]u8, - /// Prepare the TWI slave to respond to a write command - TASKS_PREPARERX: u32, - /// Prepare the TWI slave to respond to a read command - TASKS_PREPARETX: u32, - reserved260: [204]u8, - /// TWI stopped - EVENTS_STOPPED: u32, - reserved292: [28]u8, - /// TWI error - EVENTS_ERROR: u32, - reserved332: [36]u8, - /// Receive sequence started - EVENTS_RXSTARTED: u32, - /// Transmit sequence started - EVENTS_TXSTARTED: u32, - reserved356: [16]u8, - /// Write command received - EVENTS_WRITE: u32, - /// Read command received - EVENTS_READ: u32, - reserved512: [148]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// Shortcut between WRITE event and SUSPEND task - WRITE_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between READ event and SUSPEND task - READ_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u17, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Enable or disable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved19: u9, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved25: u4, - /// Enable or disable interrupt for WRITE event - WRITE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for READ event - READ: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u5, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Write '1' to Enable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u9, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved25: u4, - /// Write '1' to Enable interrupt for WRITE event - WRITE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for READ event - READ: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u5, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Write '1' to Disable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u9, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved25: u4, - /// Write '1' to Disable interrupt for WRITE event - WRITE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for READ event - READ: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u5, - }), - reserved1232: [452]u8, - /// Error source - ERRORSRC: mmio.Mmio(packed struct(u32) { - /// RX buffer overflow detected, and prevented - OVERFLOW: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotDetected = 0x0, - /// Error occurred - Detected = 0x1, - }, - }, - reserved2: u1, - /// NACK sent after receiving a data byte - DNACK: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotReceived = 0x0, - /// Error occurred - Received = 0x1, - }, - }, - /// TX buffer over-read detected, and prevented - OVERREAD: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotDetected = 0x0, - /// Error occurred - Detected = 0x1, - }, - }, - padding: u28, - }), - /// Status register indicating which address had a match - MATCH: mmio.Mmio(packed struct(u32) { - /// Which of the addresses in {ADDRESS} matched the incoming address - MATCH: u1, - padding: u31, - }), - reserved1280: [40]u8, - /// Enable TWIS - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable TWIS - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable TWIS - Disabled = 0x0, - /// Enable TWIS - Enabled = 0x9, - _, - }, - }, - padding: u28, - }), - reserved1416: [132]u8, - /// Description collection[0]: TWI slave address 0 - ADDRESS: [2]mmio.Mmio(packed struct(u32) { - /// TWI slave address - ADDRESS: u7, - padding: u25, - }), - reserved1428: [4]u8, - /// Configuration register for the address match mechanism - CONFIG: mmio.Mmio(packed struct(u32) { - /// Enable or disable address matching on ADDRESS[0] - ADDRESS0: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable address matching on ADDRESS[1] - ADDRESS1: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - padding: u30, - }), - reserved1472: [40]u8, - /// Over-read character. Character sent out in case of an over-read of the transmit buffer. - ORC: mmio.Mmio(packed struct(u32) { - /// Over-read character. Character sent out in case of an over-read of the transmit buffer. - ORC: u8, - padding: u24, - }), - }; - - /// Serial Peripheral Interface 0 - pub const SPI0 = extern struct { - reserved264: [264]u8, - /// TXD byte sent and RXD byte received - EVENTS_READY: u32, - reserved772: [504]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Write '1' to Enable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Write '1' to Disable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - reserved1280: [500]u8, - /// Enable SPI - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable SPI - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable SPI - Disabled = 0x0, - /// Enable SPI - Enabled = 0x1, - _, - }, - }, - padding: u28, - }), - reserved1304: [20]u8, - /// RXD register - RXD: mmio.Mmio(packed struct(u32) { - /// RX data received. Double buffered - RXD: u8, - padding: u24, - }), - /// TXD register - TXD: mmio.Mmio(packed struct(u32) { - /// TX data to send. Double buffered - TXD: u8, - padding: u24, - }), - reserved1316: [4]u8, - /// SPI frequency - FREQUENCY: mmio.Mmio(packed struct(u32) { - /// SPI master data rate - FREQUENCY: packed union { - raw: u32, - value: enum(u32) { - /// 125 kbps - K125 = 0x2000000, - /// 250 kbps - K250 = 0x4000000, - /// 500 kbps - K500 = 0x8000000, - /// 1 Mbps - M1 = 0x10000000, - /// 2 Mbps - M2 = 0x20000000, - /// 4 Mbps - M4 = 0x40000000, - /// 8 Mbps - M8 = 0x80000000, - _, - }, - }, - }), - reserved1364: [44]u8, - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Bit order - ORDER: packed union { - raw: u1, - value: enum(u1) { - /// Most significant bit shifted out first - MsbFirst = 0x0, - /// Least significant bit shifted out first - LsbFirst = 0x1, - }, - }, - /// Serial clock (SCK) phase - CPHA: packed union { - raw: u1, - value: enum(u1) { - /// Sample on leading edge of clock, shift serial data on trailing edge - Leading = 0x0, - /// Sample on trailing edge of clock, shift serial data on leading edge - Trailing = 0x1, - }, - }, - /// Serial clock (SCK) polarity - CPOL: packed union { - raw: u1, - value: enum(u1) { - /// Active high - ActiveHigh = 0x0, - /// Active low - ActiveLow = 0x1, - }, - }, - padding: u29, - }), - }; - - /// I2C compatible Two-Wire Interface 0 - pub const TWI0 = extern struct { - /// Start TWI receive sequence - TASKS_STARTRX: u32, - reserved8: [4]u8, - /// Start TWI transmit sequence - TASKS_STARTTX: u32, - reserved20: [8]u8, - /// Stop TWI transaction - TASKS_STOP: u32, - reserved28: [4]u8, - /// Suspend TWI transaction - TASKS_SUSPEND: u32, - /// Resume TWI transaction - TASKS_RESUME: u32, - reserved260: [224]u8, - /// TWI stopped - EVENTS_STOPPED: u32, - /// TWI RXD byte received - EVENTS_RXDREADY: u32, - reserved284: [16]u8, - /// TWI TXD byte sent - EVENTS_TXDSENT: u32, - reserved292: [4]u8, - /// TWI error - EVENTS_ERROR: u32, - reserved312: [16]u8, - /// TWI byte boundary, generated before each byte that is sent or received - EVENTS_BB: u32, - reserved328: [12]u8, - /// TWI entered the suspended state - EVENTS_SUSPENDED: u32, - reserved512: [180]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between BB event and SUSPEND task - BB_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between BB event and STOP task - BB_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u30, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for RXDREADY event - RXDREADY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u4, - /// Write '1' to Enable interrupt for TXDSENT event - TXDSENT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved14: u4, - /// Write '1' to Enable interrupt for BB event - BB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u3, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u13, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for RXDREADY event - RXDREADY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u4, - /// Write '1' to Disable interrupt for TXDSENT event - TXDSENT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved14: u4, - /// Write '1' to Disable interrupt for BB event - BB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u3, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u13, - }), - reserved1220: [440]u8, - /// Error source - ERRORSRC: mmio.Mmio(packed struct(u32) { - /// Overrun error - OVERRUN: packed union { - raw: u1, - value: enum(u1) { - /// Read: no overrun occured - NotPresent = 0x0, - /// Read: overrun occured - Present = 0x1, - }, - }, - /// NACK received after sending the address (write '1' to clear) - ANACK: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - padding: u29, - }), - reserved1280: [56]u8, - /// Enable TWI - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable TWI - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable TWI - Disabled = 0x0, - /// Enable TWI - Enabled = 0x5, - _, - }, - }, - padding: u28, - }), - reserved1288: [4]u8, - /// Pin select for SCL - PSELSCL: mmio.Mmio(packed struct(u32) { - /// Pin number configuration for TWI SCL signal - PSELSCL: packed union { - raw: u32, - value: enum(u32) { - /// Disconnect - Disconnected = 0xffffffff, - _, - }, - }, - }), - /// Pin select for SDA - PSELSDA: mmio.Mmio(packed struct(u32) { - /// Pin number configuration for TWI SDA signal - PSELSDA: packed union { - raw: u32, - value: enum(u32) { - /// Disconnect - Disconnected = 0xffffffff, - _, - }, - }, - }), - reserved1304: [8]u8, - /// RXD register - RXD: mmio.Mmio(packed struct(u32) { - /// RXD register - RXD: u8, - padding: u24, - }), - /// TXD register - TXD: mmio.Mmio(packed struct(u32) { - /// TXD register - TXD: u8, - padding: u24, - }), - reserved1316: [4]u8, - /// TWI frequency - FREQUENCY: mmio.Mmio(packed struct(u32) { - /// TWI master clock frequency - FREQUENCY: packed union { - raw: u32, - value: enum(u32) { - /// 100 kbps - K100 = 0x1980000, - /// 250 kbps - K250 = 0x4000000, - /// 400 kbps (actual rate 410.256 kbps) - K400 = 0x6680000, - _, - }, - }, - }), - reserved1416: [96]u8, - /// Address used in the TWI transfer - ADDRESS: mmio.Mmio(packed struct(u32) { - /// Address used in the TWI transfer - ADDRESS: u7, - padding: u25, - }), - }; - - /// GPIO Port 1 - pub const P0 = extern struct { - reserved1284: [1284]u8, - /// Write GPIO port - OUT: mmio.Mmio(packed struct(u32) { - /// Pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - }), - /// Set individual bits in GPIO port - OUTSET: mmio.Mmio(packed struct(u32) { - /// Pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - }), - /// Clear individual bits in GPIO port - OUTCLR: mmio.Mmio(packed struct(u32) { - /// Pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - }), - /// Read GPIO port - IN: mmio.Mmio(packed struct(u32) { - /// Pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - }), - /// Direction of GPIO pins - DIR: mmio.Mmio(packed struct(u32) { - /// Pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - }), - /// DIR set register - DIRSET: mmio.Mmio(packed struct(u32) { - /// Set as output pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - }), - /// DIR clear register - DIRCLR: mmio.Mmio(packed struct(u32) { - /// Set as input pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - }), - /// Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers - LATCH: mmio.Mmio(packed struct(u32) { - /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - }), - /// Select between default DETECT signal behaviour and LDETECT mode - DETECTMODE: mmio.Mmio(packed struct(u32) { - /// Select between default DETECT signal behaviour and LDETECT mode - DETECTMODE: packed union { - raw: u1, - value: enum(u1) { - /// DETECT directly connected to PIN DETECT signals - Default = 0x0, - /// Use the latched LDETECT behaviour - LDETECT = 0x1, - }, - }, - padding: u31, - }), - reserved1792: [472]u8, - /// Description collection[0]: Configuration of GPIO pins - PIN_CNF: [32]mmio.Mmio(packed struct(u32) { - /// Pin direction. Same physical register as DIR register - DIR: packed union { - raw: u1, - value: enum(u1) { - /// Configure pin as an input pin - Input = 0x0, - /// Configure pin as an output pin - Output = 0x1, - }, - }, - /// Connect or disconnect input buffer - INPUT: packed union { - raw: u1, - value: enum(u1) { - /// Connect input buffer - Connect = 0x0, - /// Disconnect input buffer - Disconnect = 0x1, - }, - }, - /// Pull configuration - PULL: packed union { - raw: u2, - value: enum(u2) { - /// No pull - Disabled = 0x0, - /// Pull down on pin - Pulldown = 0x1, - /// Pull up on pin - Pullup = 0x3, - _, - }, - }, - reserved8: u4, - /// Drive configuration - DRIVE: packed union { - raw: u3, - value: enum(u3) { - /// Standard '0', standard '1' - S0S1 = 0x0, - /// High drive '0', standard '1' - H0S1 = 0x1, - /// Standard '0', high drive '1' - S0H1 = 0x2, - /// High drive '0', high 'drive '1'' - H0H1 = 0x3, - /// Disconnect '0' standard '1' (normally used for wired-or connections) - D0S1 = 0x4, - /// Disconnect '0', high drive '1' (normally used for wired-or connections) - D0H1 = 0x5, - /// Standard '0'. disconnect '1' (normally used for wired-and connections) - S0D1 = 0x6, - /// High drive '0', disconnect '1' (normally used for wired-and connections) - H0D1 = 0x7, - }, - }, - reserved16: u5, - /// Pin sensing mechanism - SENSE: packed union { - raw: u2, - value: enum(u2) { - /// Disabled - Disabled = 0x0, - /// Sense for high level - High = 0x2, - /// Sense for low level - Low = 0x3, - _, - }, - }, - padding: u14, - }), - }; - - /// FPU - pub const FPU = extern struct { - /// Unused. - UNUSED: u32, - }; - - /// Inter-IC Sound - pub const I2S = extern struct { - /// Starts continuous I2S transfer. Also starts MCK generator when this is enabled. - TASKS_START: u32, - /// Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. - TASKS_STOP: u32, - reserved260: [252]u8, - /// The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. - EVENTS_RXPTRUPD: u32, - /// I2S transfer stopped. - EVENTS_STOPPED: u32, - reserved276: [8]u8, - /// The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. - EVENTS_TXPTRUPD: u32, - reserved768: [488]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Enable or disable interrupt for RXPTRUPD event - RXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved5: u2, - /// Enable or disable interrupt for TXPTRUPD event - TXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u26, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Enable interrupt for RXPTRUPD event - RXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved5: u2, - /// Write '1' to Enable interrupt for TXPTRUPD event - TXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u26, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Disable interrupt for RXPTRUPD event - RXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved5: u2, - /// Write '1' to Disable interrupt for TXPTRUPD event - TXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u26, - }), - reserved1280: [500]u8, - /// Enable I2S module. - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable I2S module. - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - }; - - /// Event Generator Unit 0 - pub const EGU0 = extern struct { - /// Description collection[0]: Trigger 0 for triggering the corresponding TRIGGERED[0] event - TASKS_TRIGGER: [16]u32, - reserved256: [192]u8, - /// Description collection[0]: Event number 0 generated by triggering the corresponding TRIGGER[0] task - EVENTS_TRIGGERED: [16]u32, - reserved768: [448]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u16, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u16, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u16, - }), - }; - - /// Memory Watch Unit - pub const MWU = extern struct { - reserved768: [768]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for REGION[0].WA event - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for REGION[0].RA event - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for REGION[1].WA event - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for REGION[1].RA event - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for REGION[2].WA event - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for REGION[2].RA event - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for REGION[3].WA event - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for REGION[3].RA event - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Enable or disable interrupt for PREGION[0].WA event - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for PREGION[0].RA event - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for PREGION[1].WA event - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for PREGION[1].RA event - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u4, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for REGION[0].WA event - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for REGION[0].RA event - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for REGION[1].WA event - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for REGION[1].RA event - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for REGION[2].WA event - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for REGION[2].RA event - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for REGION[3].WA event - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for REGION[3].RA event - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Write '1' to Enable interrupt for PREGION[0].WA event - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for PREGION[0].RA event - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for PREGION[1].WA event - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for PREGION[1].RA event - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for REGION[0].WA event - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for REGION[0].RA event - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for REGION[1].WA event - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for REGION[1].RA event - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for REGION[2].WA event - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for REGION[2].RA event - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for REGION[3].WA event - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for REGION[3].RA event - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Write '1' to Disable interrupt for PREGION[0].WA event - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for PREGION[0].RA event - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for PREGION[1].WA event - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for PREGION[1].RA event - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - reserved800: [20]u8, - /// Enable or disable non-maskable interrupt - NMIEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable non-maskable interrupt for REGION[0].WA event - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable non-maskable interrupt for REGION[0].RA event - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable non-maskable interrupt for REGION[1].WA event - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable non-maskable interrupt for REGION[1].RA event - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable non-maskable interrupt for REGION[2].WA event - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable non-maskable interrupt for REGION[2].RA event - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable non-maskable interrupt for REGION[3].WA event - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable non-maskable interrupt for REGION[3].RA event - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Enable or disable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u4, - }), - /// Enable non-maskable interrupt - NMIENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable non-maskable interrupt for REGION[0].WA event - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable non-maskable interrupt for REGION[0].RA event - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable non-maskable interrupt for REGION[1].WA event - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable non-maskable interrupt for REGION[1].RA event - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable non-maskable interrupt for REGION[2].WA event - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable non-maskable interrupt for REGION[2].RA event - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable non-maskable interrupt for REGION[3].WA event - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable non-maskable interrupt for REGION[3].RA event - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Write '1' to Enable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - /// Disable non-maskable interrupt - NMIENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable non-maskable interrupt for REGION[0].WA event - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable non-maskable interrupt for REGION[0].RA event - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable non-maskable interrupt for REGION[1].WA event - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable non-maskable interrupt for REGION[1].RA event - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable non-maskable interrupt for REGION[2].WA event - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable non-maskable interrupt for REGION[2].RA event - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable non-maskable interrupt for REGION[3].WA event - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable non-maskable interrupt for REGION[3].RA event - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Write '1' to Disable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - reserved1296: [484]u8, - /// Enable/disable regions watch - REGIONEN: mmio.Mmio(packed struct(u32) { - /// Enable/disable write access watch in region[0] - RGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this region - Disable = 0x0, - /// Enable write access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in region[0] - RGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this region - Disable = 0x0, - /// Enable read access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable write access watch in region[1] - RGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this region - Disable = 0x0, - /// Enable write access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in region[1] - RGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this region - Disable = 0x0, - /// Enable read access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable write access watch in region[2] - RGN2WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this region - Disable = 0x0, - /// Enable write access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in region[2] - RGN2RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this region - Disable = 0x0, - /// Enable read access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable write access watch in region[3] - RGN3WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this region - Disable = 0x0, - /// Enable write access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in region[3] - RGN3RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this region - Disable = 0x0, - /// Enable read access watch in this region - Enable = 0x1, - }, - }, - reserved24: u16, - /// Enable/disable write access watch in PREGION[0] - PRGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this PREGION - Disable = 0x0, - /// Enable write access watch in this PREGION - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in PREGION[0] - PRGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this PREGION - Disable = 0x0, - /// Enable read access watch in this PREGION - Enable = 0x1, - }, - }, - /// Enable/disable write access watch in PREGION[1] - PRGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this PREGION - Disable = 0x0, - /// Enable write access watch in this PREGION - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in PREGION[1] - PRGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this PREGION - Disable = 0x0, - /// Enable read access watch in this PREGION - Enable = 0x1, - }, - }, - padding: u4, - }), - /// Enable regions watch - REGIONENSET: mmio.Mmio(packed struct(u32) { - /// Enable write access watch in region[0] - RGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in region[0] - RGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable write access watch in region[1] - RGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in region[1] - RGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable write access watch in region[2] - RGN2WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in region[2] - RGN2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable write access watch in region[3] - RGN3WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in region[3] - RGN3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Enable write access watch in PREGION[0] - PRGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this PREGION is disabled - Disabled = 0x0, - /// Write access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in PREGION[0] - PRGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this PREGION is disabled - Disabled = 0x0, - /// Read access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Enable write access watch in PREGION[1] - PRGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this PREGION is disabled - Disabled = 0x0, - /// Write access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in PREGION[1] - PRGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this PREGION is disabled - Disabled = 0x0, - /// Read access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - /// Disable regions watch - REGIONENCLR: mmio.Mmio(packed struct(u32) { - /// Disable write access watch in region[0] - RGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in region[0] - RGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable write access watch in region[1] - RGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in region[1] - RGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable write access watch in region[2] - RGN2WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in region[2] - RGN2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable write access watch in region[3] - RGN3WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in region[3] - RGN3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Disable write access watch in PREGION[0] - PRGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this PREGION is disabled - Disabled = 0x0, - /// Write access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in PREGION[0] - PRGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this PREGION is disabled - Disabled = 0x0, - /// Read access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Disable write access watch in PREGION[1] - PRGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this PREGION is disabled - Disabled = 0x0, - /// Write access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in PREGION[1] - PRGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this PREGION is disabled - Disabled = 0x0, - /// Read access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - }; - - /// Programmable Peripheral Interconnect - pub const PPI = extern struct { - reserved1280: [1280]u8, - /// Channel enable register - CHEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable channel 0 - CH0: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 1 - CH1: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 2 - CH2: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 3 - CH3: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 4 - CH4: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 5 - CH5: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 6 - CH6: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 7 - CH7: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 8 - CH8: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 9 - CH9: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 10 - CH10: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 11 - CH11: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 12 - CH12: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 13 - CH13: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 14 - CH14: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 15 - CH15: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 16 - CH16: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 17 - CH17: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 18 - CH18: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 19 - CH19: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 20 - CH20: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 21 - CH21: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 22 - CH22: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 23 - CH23: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 24 - CH24: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 25 - CH25: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 26 - CH26: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 27 - CH27: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 28 - CH28: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 29 - CH29: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 30 - CH30: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 31 - CH31: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - }), - /// Channel enable set register - CHENSET: mmio.Mmio(packed struct(u32) { - /// Channel 0 enable set register. Writing '0' has no effect - CH0: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 1 enable set register. Writing '0' has no effect - CH1: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 2 enable set register. Writing '0' has no effect - CH2: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 3 enable set register. Writing '0' has no effect - CH3: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 4 enable set register. Writing '0' has no effect - CH4: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 5 enable set register. Writing '0' has no effect - CH5: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 6 enable set register. Writing '0' has no effect - CH6: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 7 enable set register. Writing '0' has no effect - CH7: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 8 enable set register. Writing '0' has no effect - CH8: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 9 enable set register. Writing '0' has no effect - CH9: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 10 enable set register. Writing '0' has no effect - CH10: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 11 enable set register. Writing '0' has no effect - CH11: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 12 enable set register. Writing '0' has no effect - CH12: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 13 enable set register. Writing '0' has no effect - CH13: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 14 enable set register. Writing '0' has no effect - CH14: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 15 enable set register. Writing '0' has no effect - CH15: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 16 enable set register. Writing '0' has no effect - CH16: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 17 enable set register. Writing '0' has no effect - CH17: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 18 enable set register. Writing '0' has no effect - CH18: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 19 enable set register. Writing '0' has no effect - CH19: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 20 enable set register. Writing '0' has no effect - CH20: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 21 enable set register. Writing '0' has no effect - CH21: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 22 enable set register. Writing '0' has no effect - CH22: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 23 enable set register. Writing '0' has no effect - CH23: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 24 enable set register. Writing '0' has no effect - CH24: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 25 enable set register. Writing '0' has no effect - CH25: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 26 enable set register. Writing '0' has no effect - CH26: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 27 enable set register. Writing '0' has no effect - CH27: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 28 enable set register. Writing '0' has no effect - CH28: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 29 enable set register. Writing '0' has no effect - CH29: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 30 enable set register. Writing '0' has no effect - CH30: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 31 enable set register. Writing '0' has no effect - CH31: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - }), - /// Channel enable clear register - CHENCLR: mmio.Mmio(packed struct(u32) { - /// Channel 0 enable clear register. Writing '0' has no effect - CH0: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 1 enable clear register. Writing '0' has no effect - CH1: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 2 enable clear register. Writing '0' has no effect - CH2: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 3 enable clear register. Writing '0' has no effect - CH3: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 4 enable clear register. Writing '0' has no effect - CH4: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 5 enable clear register. Writing '0' has no effect - CH5: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 6 enable clear register. Writing '0' has no effect - CH6: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 7 enable clear register. Writing '0' has no effect - CH7: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 8 enable clear register. Writing '0' has no effect - CH8: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 9 enable clear register. Writing '0' has no effect - CH9: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 10 enable clear register. Writing '0' has no effect - CH10: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 11 enable clear register. Writing '0' has no effect - CH11: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 12 enable clear register. Writing '0' has no effect - CH12: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 13 enable clear register. Writing '0' has no effect - CH13: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 14 enable clear register. Writing '0' has no effect - CH14: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 15 enable clear register. Writing '0' has no effect - CH15: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 16 enable clear register. Writing '0' has no effect - CH16: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 17 enable clear register. Writing '0' has no effect - CH17: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 18 enable clear register. Writing '0' has no effect - CH18: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 19 enable clear register. Writing '0' has no effect - CH19: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 20 enable clear register. Writing '0' has no effect - CH20: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 21 enable clear register. Writing '0' has no effect - CH21: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 22 enable clear register. Writing '0' has no effect - CH22: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 23 enable clear register. Writing '0' has no effect - CH23: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 24 enable clear register. Writing '0' has no effect - CH24: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 25 enable clear register. Writing '0' has no effect - CH25: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 26 enable clear register. Writing '0' has no effect - CH26: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 27 enable clear register. Writing '0' has no effect - CH27: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 28 enable clear register. Writing '0' has no effect - CH28: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 29 enable clear register. Writing '0' has no effect - CH29: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 30 enable clear register. Writing '0' has no effect - CH30: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 31 enable clear register. Writing '0' has no effect - CH31: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - }), - reserved2048: [756]u8, - /// Description collection[0]: Channel group 0 - CHG: [6]mmio.Mmio(packed struct(u32) { - /// Include or exclude channel 0 - CH0: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 1 - CH1: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 2 - CH2: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 3 - CH3: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 4 - CH4: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 5 - CH5: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 6 - CH6: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 7 - CH7: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 8 - CH8: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 9 - CH9: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 10 - CH10: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 11 - CH11: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 12 - CH12: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 13 - CH13: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 14 - CH14: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 15 - CH15: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 16 - CH16: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 17 - CH17: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 18 - CH18: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 19 - CH19: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 20 - CH20: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 21 - CH21: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 22 - CH22: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 23 - CH23: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 24 - CH24: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 25 - CH25: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 26 - CH26: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 27 - CH27: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 28 - CH28: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 29 - CH29: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 30 - CH30: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 31 - CH31: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - }), - }; - - /// NFC-A compatible radio - pub const NFCT = extern struct { - /// Activate NFC peripheral for incoming and outgoing frames, change state to activated - TASKS_ACTIVATE: u32, - /// Disable NFC peripheral - TASKS_DISABLE: u32, - /// Enable NFC sense field mode, change state to sense mode - TASKS_SENSE: u32, - /// Start transmission of a outgoing frame, change state to transmit - TASKS_STARTTX: u32, - reserved28: [12]u8, - /// Initializes the EasyDMA for receive. - TASKS_ENABLERXDATA: u32, - reserved36: [4]u8, - /// Force state machine to IDLE state - TASKS_GOIDLE: u32, - /// Force state machine to SLEEP_A state - TASKS_GOSLEEP: u32, - reserved256: [212]u8, - /// The NFC peripheral is ready to receive and send frames - EVENTS_READY: u32, - /// Remote NFC field detected - EVENTS_FIELDDETECTED: u32, - /// Remote NFC field lost - EVENTS_FIELDLOST: u32, - /// Marks the start of the first symbol of a transmitted frame - EVENTS_TXFRAMESTART: u32, - /// Marks the end of the last transmitted on-air symbol of a frame - EVENTS_TXFRAMEEND: u32, - /// Marks the end of the first symbol of a received frame - EVENTS_RXFRAMESTART: u32, - /// Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer - EVENTS_RXFRAMEEND: u32, - /// NFC error reported. The ERRORSTATUS register contains details on the source of the error. - EVENTS_ERROR: u32, - reserved296: [8]u8, - /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. - EVENTS_RXERROR: u32, - /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. - EVENTS_ENDRX: u32, - /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer - EVENTS_ENDTX: u32, - reserved312: [4]u8, - /// Auto collision resolution process has started - EVENTS_AUTOCOLRESSTARTED: u32, - reserved328: [12]u8, - /// NFC Auto collision resolution error reported. - EVENTS_COLLISION: u32, - /// NFC Auto collision resolution successfully completed - EVENTS_SELECTED: u32, - /// EasyDMA is ready to receive or send frames. - EVENTS_STARTED: u32, - reserved512: [172]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between FIELDDETECTED event and ACTIVATE task - FIELDDETECTED_ACTIVATE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between FIELDLOST event and SENSE task - FIELDLOST_SENSE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u30, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for FIELDDETECTED event - FIELDDETECTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for FIELDLOST event - FIELDLOST: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TXFRAMESTART event - TXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for TXFRAMEEND event - TXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for RXFRAMESTART event - RXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for RXFRAMEEND event - RXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved10: u2, - /// Enable or disable interrupt for RXERROR event - RXERROR: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for ENDRX event - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for ENDTX event - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved14: u1, - /// Enable or disable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved18: u3, - /// Enable or disable interrupt for COLLISION event - COLLISION: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for SELECTED event - SELECTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for STARTED event - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u11, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for FIELDDETECTED event - FIELDDETECTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for FIELDLOST event - FIELDLOST: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TXFRAMESTART event - TXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for TXFRAMEEND event - TXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for RXFRAMESTART event - RXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for RXFRAMEEND event - RXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u2, - /// Write '1' to Enable interrupt for RXERROR event - RXERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved14: u1, - /// Write '1' to Enable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u3, - /// Write '1' to Enable interrupt for COLLISION event - COLLISION: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for SELECTED event - SELECTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for STARTED event - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u11, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for FIELDDETECTED event - FIELDDETECTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for FIELDLOST event - FIELDLOST: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TXFRAMESTART event - TXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for TXFRAMEEND event - TXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for RXFRAMESTART event - RXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for RXFRAMEEND event - RXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u2, - /// Write '1' to Disable interrupt for RXERROR event - RXERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved14: u1, - /// Write '1' to Disable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u3, - /// Write '1' to Disable interrupt for COLLISION event - COLLISION: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for SELECTED event - SELECTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for STARTED event - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u11, - }), - reserved1028: [248]u8, - /// NFC Error Status register - ERRORSTATUS: mmio.Mmio(packed struct(u32) { - /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX - FRAMEDELAYTIMEOUT: u1, - reserved2: u1, - /// Field level is too high at max load resistance - NFCFIELDTOOSTRONG: u1, - /// Field level is too low at min load resistance - NFCFIELDTOOWEAK: u1, - padding: u28, - }), - reserved1072: [40]u8, - /// Current value driven to the NFC Load Control - CURRENTLOADCTRL: mmio.Mmio(packed struct(u32) { - /// Current value driven to the NFC Load Control - CURRENTLOADCTRL: u6, - padding: u26, - }), - reserved1084: [8]u8, - /// Indicates the presence or not of a valid field - FIELDPRESENT: mmio.Mmio(packed struct(u32) { - /// Indicates the presence or not of a valid field. Available only in the activated state. - FIELDPRESENT: packed union { - raw: u1, - value: enum(u1) { - /// No valid field detected - NoField = 0x0, - /// Valid field detected - FieldPresent = 0x1, - }, - }, - /// Indicates if the low level has locked to the field - LOCKDETECT: packed union { - raw: u1, - value: enum(u1) { - /// Not locked to field - NotLocked = 0x0, - /// Locked to field - Locked = 0x1, - }, - }, - padding: u30, - }), - reserved1284: [196]u8, - /// Minimum frame delay - FRAMEDELAYMIN: mmio.Mmio(packed struct(u32) { - /// Minimum frame delay in number of 13.56 MHz clocks - FRAMEDELAYMIN: u16, - padding: u16, - }), - /// Maximum frame delay - FRAMEDELAYMAX: mmio.Mmio(packed struct(u32) { - /// Maximum frame delay in number of 13.56 MHz clocks - FRAMEDELAYMAX: u16, - padding: u16, - }), - /// Configuration register for the Frame Delay Timer - FRAMEDELAYMODE: mmio.Mmio(packed struct(u32) { - /// Configuration register for the Frame Delay Timer - FRAMEDELAYMODE: packed union { - raw: u2, - value: enum(u2) { - /// Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. - FreeRun = 0x0, - /// Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX - Window = 0x1, - /// Frame is transmitted exactly at FRAMEDELAYMAX - ExactVal = 0x2, - /// Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX - WindowGrid = 0x3, - }, - }, - padding: u30, - }), - /// Packet pointer for TXD and RXD data storage in Data RAM - PACKETPTR: mmio.Mmio(packed struct(u32) { - /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. - PTR: u32, - }), - /// Size of allocated for TXD and RXD data storage buffer in Data RAM - MAXLEN: mmio.Mmio(packed struct(u32) { - /// Size of allocated for TXD and RXD data storage buffer in Data RAM - MAXLEN: u9, - padding: u23, - }), - reserved1424: [120]u8, - /// Last NFCID1 part (4, 7 or 10 bytes ID) - NFCID1_LAST: mmio.Mmio(packed struct(u32) { - /// NFCID1 byte Z (very last byte sent) - NFCID1_Z: u8, - /// NFCID1 byte Y - NFCID1_Y: u8, - /// NFCID1 byte X - NFCID1_X: u8, - /// NFCID1 byte W - NFCID1_W: u8, - }), - /// Second last NFCID1 part (7 or 10 bytes ID) - NFCID1_2ND_LAST: mmio.Mmio(packed struct(u32) { - /// NFCID1 byte V - NFCID1_V: u8, - /// NFCID1 byte U - NFCID1_U: u8, - /// NFCID1 byte T - NFCID1_T: u8, - padding: u8, - }), - /// Third last NFCID1 part (10 bytes ID) - NFCID1_3RD_LAST: mmio.Mmio(packed struct(u32) { - /// NFCID1 byte S - NFCID1_S: u8, - /// NFCID1 byte R - NFCID1_R: u8, - /// NFCID1 byte Q - NFCID1_Q: u8, - padding: u8, - }), - reserved1440: [4]u8, - /// NFC-A SENS_RES auto-response settings - SENSRES: mmio.Mmio(packed struct(u32) { - /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - BITFRAMESDD: packed union { - raw: u5, - value: enum(u5) { - /// SDD pattern 00000 - SDD00000 = 0x0, - /// SDD pattern 00001 - SDD00001 = 0x1, - /// SDD pattern 00010 - SDD00010 = 0x2, - /// SDD pattern 00100 - SDD00100 = 0x4, - /// SDD pattern 01000 - SDD01000 = 0x8, - /// SDD pattern 10000 - SDD10000 = 0x10, - _, - }, - }, - /// Reserved for future use. Shall be 0. - RFU5: u1, - /// NFCID1 size. This value is used by the Auto collision resolution engine. - NFCIDSIZE: packed union { - raw: u2, - value: enum(u2) { - /// NFCID1 size: single (4 bytes) - NFCID1Single = 0x0, - /// NFCID1 size: double (7 bytes) - NFCID1Double = 0x1, - /// NFCID1 size: triple (10 bytes) - NFCID1Triple = 0x2, - _, - }, - }, - /// Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - PLATFCONFIG: u4, - /// Reserved for future use. Shall be 0. - RFU74: u4, - padding: u16, - }), - /// NFC-A SEL_RES auto-response settings - SELRES: mmio.Mmio(packed struct(u32) { - /// Reserved for future use. Shall be 0. - RFU10: u2, - /// Cascade bit (controlled by hardware, write has no effect) - CASCADE: packed union { - raw: u1, - value: enum(u1) { - /// NFCID1 complete - Complete = 0x0, - /// NFCID1 not complete - NotComplete = 0x1, - }, - }, - /// Reserved for future use. Shall be 0. - RFU43: u2, - /// Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - PROTOCOL: u2, - /// Reserved for future use. Shall be 0. - RFU7: u1, - padding: u24, - }), - }; - - /// GPIO Tasks and Events - pub const GPIOTE = extern struct { - /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. - TASKS_OUT: [8]u32, - reserved48: [16]u8, - /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high. - TASKS_SET: [8]u32, - reserved96: [16]u8, - /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low. - TASKS_CLR: [8]u32, - reserved256: [128]u8, - /// Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL - EVENTS_IN: [8]u32, - reserved380: [92]u8, - /// Event generated from multiple input GPIO pins with SENSE mechanism enabled - EVENTS_PORT: u32, - reserved772: [388]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for IN[0] event - IN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for IN[1] event - IN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for IN[2] event - IN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for IN[3] event - IN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for IN[4] event - IN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for IN[5] event - IN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for IN[6] event - IN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for IN[7] event - IN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved31: u23, - /// Write '1' to Enable interrupt for PORT event - PORT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for IN[0] event - IN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for IN[1] event - IN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for IN[2] event - IN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for IN[3] event - IN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for IN[4] event - IN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for IN[5] event - IN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for IN[6] event - IN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for IN[7] event - IN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved31: u23, - /// Write '1' to Disable interrupt for PORT event - PORT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - }), - reserved1296: [516]u8, - /// Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event - CONFIG: [8]mmio.Mmio(packed struct(u32) { - /// Mode - MODE: packed union { - raw: u2, - value: enum(u2) { - /// Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. - Disabled = 0x0, - /// Event mode - Event = 0x1, - /// Task mode - Task = 0x3, - _, - }, - }, - reserved8: u6, - /// GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event - PSEL: u5, - reserved16: u3, - /// When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. - POLARITY: packed union { - raw: u2, - value: enum(u2) { - /// Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. - None = 0x0, - /// Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. - LoToHi = 0x1, - /// Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. - HiToLo = 0x2, - /// Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. - Toggle = 0x3, - }, - }, - reserved20: u2, - /// When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. - OUTINIT: packed union { - raw: u1, - value: enum(u1) { - /// Task mode: Initial value of pin before task triggering is low - Low = 0x0, - /// Task mode: Initial value of pin before task triggering is high - High = 0x1, - }, - }, - padding: u11, - }), - }; - - /// Analog to Digital Converter - pub const SAADC = extern struct { - /// Start the ADC and prepare the result buffer in RAM - TASKS_START: u32, - /// Take one ADC sample, if scan is enabled all channels are sampled - TASKS_SAMPLE: u32, - /// Stop the ADC and terminate any on-going conversion - TASKS_STOP: u32, - /// Starts offset auto-calibration - TASKS_CALIBRATEOFFSET: u32, - reserved256: [240]u8, - /// The ADC has started - EVENTS_STARTED: u32, - /// The ADC has filled up the Result buffer - EVENTS_END: u32, - /// A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. - EVENTS_DONE: u32, - /// A result is ready to get transferred to RAM. - EVENTS_RESULTDONE: u32, - /// Calibration is complete - EVENTS_CALIBRATEDONE: u32, - /// The ADC has stopped - EVENTS_STOPPED: u32, - reserved768: [488]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for STARTED event - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for DONE event - DONE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for RESULTDONE event - RESULTDONE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CALIBRATEDONE event - CALIBRATEDONE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[0].LIMITH event - CH0LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[0].LIMITL event - CH0LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[1].LIMITH event - CH1LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[1].LIMITL event - CH1LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[2].LIMITH event - CH2LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[2].LIMITL event - CH2LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[3].LIMITH event - CH3LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[3].LIMITL event - CH3LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[4].LIMITH event - CH4LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[4].LIMITL event - CH4LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[5].LIMITH event - CH5LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[5].LIMITL event - CH5LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[6].LIMITH event - CH6LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[6].LIMITL event - CH6LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[7].LIMITH event - CH7LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CH[7].LIMITL event - CH7LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u10, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for STARTED event - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for DONE event - DONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for RESULTDONE event - RESULTDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CALIBRATEDONE event - CALIBRATEDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[0].LIMITH event - CH0LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[0].LIMITL event - CH0LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[1].LIMITH event - CH1LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[1].LIMITL event - CH1LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[2].LIMITH event - CH2LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[2].LIMITL event - CH2LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[3].LIMITH event - CH3LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[3].LIMITL event - CH3LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[4].LIMITH event - CH4LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[4].LIMITL event - CH4LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[5].LIMITH event - CH5LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[5].LIMITL event - CH5LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[6].LIMITH event - CH6LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[6].LIMITL event - CH6LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[7].LIMITH event - CH7LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CH[7].LIMITL event - CH7LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u10, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for STARTED event - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for DONE event - DONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for RESULTDONE event - RESULTDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CALIBRATEDONE event - CALIBRATEDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[0].LIMITH event - CH0LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[0].LIMITL event - CH0LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[1].LIMITH event - CH1LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[1].LIMITL event - CH1LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[2].LIMITH event - CH2LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[2].LIMITL event - CH2LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[3].LIMITH event - CH3LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[3].LIMITL event - CH3LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[4].LIMITH event - CH4LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[4].LIMITL event - CH4LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[5].LIMITH event - CH5LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[5].LIMITL event - CH5LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[6].LIMITH event - CH6LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[6].LIMITL event - CH6LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[7].LIMITH event - CH7LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CH[7].LIMITL event - CH7LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u10, - }), - reserved1024: [244]u8, - /// Status - STATUS: mmio.Mmio(packed struct(u32) { - /// Status - STATUS: packed union { - raw: u1, - value: enum(u1) { - /// ADC is ready. No on-going conversion. - Ready = 0x0, - /// ADC is busy. Conversion in progress. - Busy = 0x1, - }, - }, - padding: u31, - }), - reserved1280: [252]u8, - /// Enable or disable ADC - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable ADC - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable ADC - Disabled = 0x0, - /// Enable ADC - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1520: [236]u8, - /// Resolution configuration - RESOLUTION: mmio.Mmio(packed struct(u32) { - /// Set the resolution - VAL: packed union { - raw: u3, - value: enum(u3) { - /// 8 bit - @"8bit" = 0x0, - /// 10 bit - @"10bit" = 0x1, - /// 12 bit - @"12bit" = 0x2, - /// 14 bit - @"14bit" = 0x3, - _, - }, - }, - padding: u29, - }), - /// Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. - OVERSAMPLE: mmio.Mmio(packed struct(u32) { - /// Oversample control - OVERSAMPLE: packed union { - raw: u4, - value: enum(u4) { - /// Bypass oversampling - Bypass = 0x0, - /// Oversample 2x - Over2x = 0x1, - /// Oversample 4x - Over4x = 0x2, - /// Oversample 8x - Over8x = 0x3, - /// Oversample 16x - Over16x = 0x4, - /// Oversample 32x - Over32x = 0x5, - /// Oversample 64x - Over64x = 0x6, - /// Oversample 128x - Over128x = 0x7, - /// Oversample 256x - Over256x = 0x8, - _, - }, - }, - padding: u28, - }), - /// Controls normal or continuous sample rate - SAMPLERATE: mmio.Mmio(packed struct(u32) { - /// Capture and compare value. Sample rate is 16 MHz/CC - CC: u11, - reserved12: u1, - /// Select mode for sample rate control - MODE: packed union { - raw: u1, - value: enum(u1) { - /// Rate is controlled from SAMPLE task - Task = 0x0, - /// Rate is controlled from local timer (use CC to control the rate) - Timers = 0x1, - }, - }, - padding: u19, - }), - }; - - /// Timer/Counter 0 - pub const TIMER0 = extern struct { - /// Start Timer - TASKS_START: u32, - /// Stop Timer - TASKS_STOP: u32, - /// Increment Timer (Counter mode only) - TASKS_COUNT: u32, - /// Clear time - TASKS_CLEAR: u32, - /// Deprecated register - Shut down timer - TASKS_SHUTDOWN: u32, - reserved64: [44]u8, - /// Description collection[0]: Capture Timer value to CC[0] register - TASKS_CAPTURE: [6]u32, - reserved320: [232]u8, - /// Description collection[0]: Compare event on CC[0] match - EVENTS_COMPARE: [6]u32, - reserved512: [168]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - reserved8: u2, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u18, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u10, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u10, - }), - reserved1284: [504]u8, - /// Timer mode selection - MODE: mmio.Mmio(packed struct(u32) { - /// Timer mode - MODE: packed union { - raw: u2, - value: enum(u2) { - /// Select Timer mode - Timer = 0x0, - /// Deprecated enumerator - Select Counter mode - Counter = 0x1, - /// Select Low Power Counter mode - LowPowerCounter = 0x2, - _, - }, - }, - padding: u30, - }), - /// Configure the number of bits used by the TIMER - BITMODE: mmio.Mmio(packed struct(u32) { - /// Timer bit width - BITMODE: packed union { - raw: u2, - value: enum(u2) { - /// 16 bit timer bit width - @"16Bit" = 0x0, - /// 8 bit timer bit width - @"08Bit" = 0x1, - /// 24 bit timer bit width - @"24Bit" = 0x2, - /// 32 bit timer bit width - @"32Bit" = 0x3, - }, - }, - padding: u30, - }), - reserved1296: [4]u8, - /// Timer prescaler register - PRESCALER: mmio.Mmio(packed struct(u32) { - /// Prescaler value - PRESCALER: u4, - padding: u28, - }), - reserved1344: [44]u8, - /// Description collection[0]: Capture/Compare register 0 - CC: [6]mmio.Mmio(packed struct(u32) { - /// Capture/Compare value - CC: u32, - }), - }; - - /// Non Volatile Memory Controller - pub const NVMC = extern struct { - reserved1024: [1024]u8, - /// Ready flag - READY: mmio.Mmio(packed struct(u32) { - /// NVMC is ready or busy - READY: packed union { - raw: u1, - value: enum(u1) { - /// NVMC is busy (on-going write or erase operation) - Busy = 0x0, - /// NVMC is ready - Ready = 0x1, - }, - }, - padding: u31, - }), - reserved1284: [256]u8, - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. - WEN: packed union { - raw: u2, - value: enum(u2) { - /// Read only access - Ren = 0x0, - /// Write Enabled - Wen = 0x1, - /// Erase enabled - Een = 0x2, - _, - }, - }, - padding: u30, - }), - /// Register for erasing a page in Code area - ERASEPAGE: mmio.Mmio(packed struct(u32) { - /// Register for starting erase of a page in Code area - ERASEPAGE: u32, - }), - /// Register for erasing all non-volatile user memory - ERASEALL: mmio.Mmio(packed struct(u32) { - /// Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. - ERASEALL: packed union { - raw: u1, - value: enum(u1) { - /// No operation - NoOperation = 0x0, - /// Start chip erase - Erase = 0x1, - }, - }, - padding: u31, - }), - /// Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. - ERASEPCR0: mmio.Mmio(packed struct(u32) { - /// Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. - ERASEPCR0: u32, - }), - /// Register for erasing User Information Configuration Registers - ERASEUICR: mmio.Mmio(packed struct(u32) { - /// Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. - ERASEUICR: packed union { - raw: u1, - value: enum(u1) { - /// No operation - NoOperation = 0x0, - /// Start erase of UICR - Erase = 0x1, - }, - }, - padding: u31, - }), - reserved1344: [40]u8, - /// I-Code cache configuration register. - ICACHECNF: mmio.Mmio(packed struct(u32) { - /// Cache enable - CACHEEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable cache. Invalidates all cache entries. - Disabled = 0x0, - /// Enable cache - Enabled = 0x1, - }, - }, - reserved8: u7, - /// Cache profiling enable - CACHEPROFEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable cache profiling - Disabled = 0x0, - /// Enable cache profiling - Enabled = 0x1, - }, - }, - padding: u23, - }), - reserved1352: [4]u8, - /// I-Code cache hit counter. - IHIT: mmio.Mmio(packed struct(u32) { - /// Number of cache hits - HITS: u32, - }), - /// I-Code cache miss counter. - IMISS: mmio.Mmio(packed struct(u32) { - /// Number of cache misses - MISSES: u32, - }), - }; - - /// Pulse Density Modulation (Digital Microphone) Interface - pub const PDM = extern struct { - /// Starts continuous PDM transfer - TASKS_START: u32, - /// Stops PDM transfer - TASKS_STOP: u32, - reserved256: [248]u8, - /// PDM transfer has started - EVENTS_STARTED: u32, - /// PDM transfer has finished - EVENTS_STOPPED: u32, - /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM - EVENTS_END: u32, - reserved768: [500]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for STARTED event - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u29, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for STARTED event - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for STARTED event - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - reserved1280: [500]u8, - /// PDM module enable register - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable PDM module - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// PDM clock generator control - PDMCLKCTRL: mmio.Mmio(packed struct(u32) { - /// PDM_CLK frequency - FREQ: packed union { - raw: u32, - value: enum(u32) { - /// PDM_CLK = 32 MHz / 32 = 1.000 MHz - @"1000K" = 0x8000000, - /// PDM_CLK = 32 MHz / 31 = 1.032 MHz - Default = 0x8400000, - /// PDM_CLK = 32 MHz / 30 = 1.067 MHz - @"1067K" = 0x8800000, - _, - }, - }, - }), - /// Defines the routing of the connected PDM microphones' signals - MODE: mmio.Mmio(packed struct(u32) { - /// Mono or stereo operation - OPERATION: packed union { - raw: u1, - value: enum(u1) { - /// Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] - Stereo = 0x0, - /// Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] - Mono = 0x1, - }, - }, - /// Defines on which PDM_CLK edge Left (or mono) is sampled - EDGE: packed union { - raw: u1, - value: enum(u1) { - /// Left (or mono) is sampled on falling edge of PDM_CLK - LeftFalling = 0x0, - /// Left (or mono) is sampled on rising edge of PDM_CLK - LeftRising = 0x1, - }, - }, - padding: u30, - }), - reserved1304: [12]u8, - /// Left output gain adjustment - GAINL: mmio.Mmio(packed struct(u32) { - /// Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust - GAINL: packed union { - raw: u7, - value: enum(u7) { - /// -20dB gain adjustment (minimum) - MinGain = 0x0, - /// 0dB gain adjustment ('2500 RMS' requirement) - DefaultGain = 0x28, - /// +20dB gain adjustment (maximum) - MaxGain = 0x50, - _, - }, - }, - padding: u25, - }), - /// Right output gain adjustment - GAINR: mmio.Mmio(packed struct(u32) { - /// Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) - GAINR: packed union { - raw: u8, - value: enum(u8) { - /// -20dB gain adjustment (minimum) - MinGain = 0x0, - /// 0dB gain adjustment ('2500 RMS' requirement) - DefaultGain = 0x28, - /// +20dB gain adjustment (maximum) - MaxGain = 0x50, - _, - }, - }, - padding: u24, - }), - }; - - /// Real time counter 0 - pub const RTC0 = extern struct { - /// Start RTC COUNTER - TASKS_START: u32, - /// Stop RTC COUNTER - TASKS_STOP: u32, - /// Clear RTC COUNTER - TASKS_CLEAR: u32, - /// Set COUNTER to 0xFFFFF0 - TASKS_TRIGOVRFLW: u32, - reserved256: [240]u8, - /// Event on COUNTER increment - EVENTS_TICK: u32, - /// Event on COUNTER overflow - EVENTS_OVRFLW: u32, - reserved320: [56]u8, - /// Description collection[0]: Compare event on CC[0] match - EVENTS_COMPARE: [4]u32, - reserved772: [436]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for TICK event - TICK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for OVRFLW event - OVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved16: u14, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for TICK event - TICK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for OVRFLW event - OVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved16: u14, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - reserved832: [52]u8, - /// Enable or disable event routing - EVTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable event routing for TICK event - TICK: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable event routing for OVRFLW event - OVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved16: u14, - /// Enable or disable event routing for COMPARE[0] event - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable event routing for COMPARE[1] event - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable event routing for COMPARE[2] event - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable event routing for COMPARE[3] event - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u12, - }), - /// Enable event routing - EVTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable event routing for TICK event - TICK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable event routing for OVRFLW event - OVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved16: u14, - /// Write '1' to Enable event routing for COMPARE[0] event - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable event routing for COMPARE[1] event - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable event routing for COMPARE[2] event - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable event routing for COMPARE[3] event - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - /// Disable event routing - EVTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable event routing for TICK event - TICK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable event routing for OVRFLW event - OVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved16: u14, - /// Write '1' to Disable event routing for COMPARE[0] event - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable event routing for COMPARE[1] event - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable event routing for COMPARE[2] event - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable event routing for COMPARE[3] event - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - reserved1284: [440]u8, - /// Current COUNTER value - COUNTER: mmio.Mmio(packed struct(u32) { - /// Counter value - COUNTER: u24, - padding: u8, - }), - /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped - PRESCALER: mmio.Mmio(packed struct(u32) { - /// Prescaler value - PRESCALER: u12, - padding: u20, - }), - reserved1344: [52]u8, - /// Description collection[0]: Compare register 0 - CC: [4]mmio.Mmio(packed struct(u32) { - /// Compare value - COMPARE: u24, - padding: u8, - }), - }; - - /// Temperature Sensor - pub const TEMP = extern struct { - /// Start temperature measurement - TASKS_START: u32, - /// Stop temperature measurement - TASKS_STOP: u32, - reserved256: [248]u8, - /// Temperature measurement complete, data ready - EVENTS_DATARDY: u32, - reserved772: [512]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for DATARDY event - DATARDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for DATARDY event - DATARDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1288: [508]u8, - /// Temperature in degC (0.25deg steps) - TEMP: mmio.Mmio(packed struct(u32) { - /// Temperature in degC (0.25deg steps) - TEMP: u32, - }), - reserved1312: [20]u8, - /// Slope of 1st piece wise linear function - A0: mmio.Mmio(packed struct(u32) { - /// Slope of 1st piece wise linear function - A0: u12, - padding: u20, - }), - /// Slope of 2nd piece wise linear function - A1: mmio.Mmio(packed struct(u32) { - /// Slope of 2nd piece wise linear function - A1: u12, - padding: u20, - }), - /// Slope of 3rd piece wise linear function - A2: mmio.Mmio(packed struct(u32) { - /// Slope of 3rd piece wise linear function - A2: u12, - padding: u20, - }), - /// Slope of 4th piece wise linear function - A3: mmio.Mmio(packed struct(u32) { - /// Slope of 4th piece wise linear function - A3: u12, - padding: u20, - }), - /// Slope of 5th piece wise linear function - A4: mmio.Mmio(packed struct(u32) { - /// Slope of 5th piece wise linear function - A4: u12, - padding: u20, - }), - /// Slope of 6th piece wise linear function - A5: mmio.Mmio(packed struct(u32) { - /// Slope of 6th piece wise linear function - A5: u12, - padding: u20, - }), - reserved1344: [8]u8, - /// y-intercept of 1st piece wise linear function - B0: mmio.Mmio(packed struct(u32) { - /// y-intercept of 1st piece wise linear function - B0: u14, - padding: u18, - }), - /// y-intercept of 2nd piece wise linear function - B1: mmio.Mmio(packed struct(u32) { - /// y-intercept of 2nd piece wise linear function - B1: u14, - padding: u18, - }), - /// y-intercept of 3rd piece wise linear function - B2: mmio.Mmio(packed struct(u32) { - /// y-intercept of 3rd piece wise linear function - B2: u14, - padding: u18, - }), - /// y-intercept of 4th piece wise linear function - B3: mmio.Mmio(packed struct(u32) { - /// y-intercept of 4th piece wise linear function - B3: u14, - padding: u18, - }), - /// y-intercept of 5th piece wise linear function - B4: mmio.Mmio(packed struct(u32) { - /// y-intercept of 5th piece wise linear function - B4: u14, - padding: u18, - }), - /// y-intercept of 6th piece wise linear function - B5: mmio.Mmio(packed struct(u32) { - /// y-intercept of 6th piece wise linear function - B5: u14, - padding: u18, - }), - reserved1376: [8]u8, - /// End point of 1st piece wise linear function - T0: mmio.Mmio(packed struct(u32) { - /// End point of 1st piece wise linear function - T0: u8, - padding: u24, - }), - /// End point of 2nd piece wise linear function - T1: mmio.Mmio(packed struct(u32) { - /// End point of 2nd piece wise linear function - T1: u8, - padding: u24, - }), - /// End point of 3rd piece wise linear function - T2: mmio.Mmio(packed struct(u32) { - /// End point of 3rd piece wise linear function - T2: u8, - padding: u24, - }), - /// End point of 4th piece wise linear function - T3: mmio.Mmio(packed struct(u32) { - /// End point of 4th piece wise linear function - T3: u8, - padding: u24, - }), - /// End point of 5th piece wise linear function - T4: mmio.Mmio(packed struct(u32) { - /// End point of 5th piece wise linear function - T4: u8, - padding: u24, - }), - }; - - /// Random Number Generator - pub const RNG = extern struct { - /// Task starting the random number generator - TASKS_START: u32, - /// Task stopping the random number generator - TASKS_STOP: u32, - reserved256: [248]u8, - /// Event being generated for every new random number written to the VALUE register - EVENTS_VALRDY: u32, - reserved512: [252]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between VALRDY event and STOP task - VALRDY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for VALRDY event - VALRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for VALRDY event - VALRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1284: [504]u8, - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Bias correction - DERCEN: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Output random number - VALUE: mmio.Mmio(packed struct(u32) { - /// Generated random number - VALUE: u8, - padding: u24, - }), - }; - - /// AES ECB Mode Encryption - pub const ECB = extern struct { - /// Start ECB block encrypt - TASKS_STARTECB: u32, - /// Abort a possible executing ECB operation - TASKS_STOPECB: u32, - reserved256: [248]u8, - /// ECB block encrypt complete - EVENTS_ENDECB: u32, - /// ECB block encrypt aborted because of a STOPECB task or due to an error - EVENTS_ERRORECB: u32, - reserved772: [508]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for ENDECB event - ENDECB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for ERRORECB event - ERRORECB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u30, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for ENDECB event - ENDECB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for ERRORECB event - ERRORECB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u30, - }), - reserved1284: [504]u8, - /// ECB block encrypt memory pointers - ECBDATAPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to the ECB data structure (see Table 1 ECB data structure overview) - ECBDATAPTR: u32, - }), - }; - - /// AES CCM Mode Encryption - pub const CCM = extern struct { - /// Start generation of key-stream. This operation will stop by itself when completed. - TASKS_KSGEN: u32, - /// Start encryption/decryption. This operation will stop by itself when completed. - TASKS_CRYPT: u32, - /// Stop encryption/decryption - TASKS_STOP: u32, - reserved256: [244]u8, - /// Key-stream generation complete - EVENTS_ENDKSGEN: u32, - /// Encrypt/decrypt complete - EVENTS_ENDCRYPT: u32, - /// CCM error event - EVENTS_ERROR: u32, - reserved512: [244]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between ENDKSGEN event and CRYPT task - ENDKSGEN_CRYPT: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for ENDKSGEN event - ENDKSGEN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for ENDCRYPT event - ENDCRYPT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for ENDKSGEN event - ENDKSGEN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for ENDCRYPT event - ENDCRYPT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for ERROR event - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - reserved1024: [244]u8, - /// MIC check result - MICSTATUS: mmio.Mmio(packed struct(u32) { - /// The result of the MIC check performed during the previous decryption operation - MICSTATUS: packed union { - raw: u1, - value: enum(u1) { - /// MIC check failed - CheckFailed = 0x0, - /// MIC check passed - CheckPassed = 0x1, - }, - }, - padding: u31, - }), - reserved1280: [252]u8, - /// Enable - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable CCM - ENABLE: packed union { - raw: u2, - value: enum(u2) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x2, - _, - }, - }, - padding: u30, - }), - /// Operation mode - MODE: mmio.Mmio(packed struct(u32) { - /// The mode of operation to be used - MODE: packed union { - raw: u1, - value: enum(u1) { - /// AES CCM packet encryption mode - Encryption = 0x0, - /// AES CCM packet decryption mode - Decryption = 0x1, - }, - }, - reserved16: u15, - /// Data rate that the CCM shall run in synch with - DATARATE: packed union { - raw: u1, - value: enum(u1) { - /// In synch with 1 Mbit data rate - @"1Mbit" = 0x0, - /// In synch with 2 Mbit data rate - @"2Mbit" = 0x1, - }, - }, - reserved24: u7, - /// Packet length configuration - LENGTH: packed union { - raw: u1, - value: enum(u1) { - /// Default length. Effective length of LENGTH field is 5-bit - Default = 0x0, - /// Extended length. Effective length of LENGTH field is 8-bit - Extended = 0x1, - }, - }, - padding: u7, - }), - /// Pointer to data structure holding AES key and NONCE vector - CNFPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) - CNFPTR: u32, - }), - /// Input pointer - INPTR: mmio.Mmio(packed struct(u32) { - /// Input pointer - INPTR: u32, - }), - /// Output pointer - OUTPTR: mmio.Mmio(packed struct(u32) { - /// Output pointer - OUTPTR: u32, - }), - /// Pointer to data area used for temporary storage - SCRATCHPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. - SCRATCHPTR: u32, - }), - }; - - /// Accelerated Address Resolver - pub const AAR = extern struct { - /// Start resolving addresses based on IRKs specified in the IRK data structure - TASKS_START: u32, - reserved8: [4]u8, - /// Stop resolving addresses - TASKS_STOP: u32, - reserved256: [244]u8, - /// Address resolution procedure complete - EVENTS_END: u32, - /// Address resolved - EVENTS_RESOLVED: u32, - /// Address not resolved - EVENTS_NOTRESOLVED: u32, - reserved772: [504]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for RESOLVED event - RESOLVED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for NOTRESOLVED event - NOTRESOLVED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for END event - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for RESOLVED event - RESOLVED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for NOTRESOLVED event - NOTRESOLVED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - reserved1024: [244]u8, - /// Resolution status - STATUS: mmio.Mmio(packed struct(u32) { - /// The IRK that was used last time an address was resolved - STATUS: u4, - padding: u28, - }), - reserved1280: [252]u8, - /// Enable AAR - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable AAR - ENABLE: packed union { - raw: u2, - value: enum(u2) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x3, - _, - }, - }, - padding: u30, - }), - /// Number of IRKs - NIRK: mmio.Mmio(packed struct(u32) { - /// Number of Identity root keys available in the IRK data structure - NIRK: u5, - padding: u27, - }), - /// Pointer to IRK data structure - IRKPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to the IRK data structure - IRKPTR: u32, - }), - reserved1296: [4]u8, - /// Pointer to the resolvable address - ADDRPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to the resolvable address (6-bytes) - ADDRPTR: u32, - }), - /// Pointer to data area used for temporary storage - SCRATCHPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. - SCRATCHPTR: u32, - }), - }; - - /// Watchdog Timer - pub const WDT = extern struct { - /// Start the watchdog - TASKS_START: u32, - reserved256: [252]u8, - /// Watchdog timeout - EVENTS_TIMEOUT: u32, - reserved772: [512]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for TIMEOUT event - TIMEOUT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for TIMEOUT event - TIMEOUT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1024: [244]u8, - /// Run status - RUNSTATUS: mmio.Mmio(packed struct(u32) { - /// Indicates whether or not the watchdog is running - RUNSTATUS: packed union { - raw: u1, - value: enum(u1) { - /// Watchdog not running - NotRunning = 0x0, - /// Watchdog is running - Running = 0x1, - }, - }, - padding: u31, - }), - /// Request status - REQSTATUS: mmio.Mmio(packed struct(u32) { - /// Request status for RR[0] register - RR0: packed union { - raw: u1, - value: enum(u1) { - /// RR[0] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[0] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[1] register - RR1: packed union { - raw: u1, - value: enum(u1) { - /// RR[1] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[1] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[2] register - RR2: packed union { - raw: u1, - value: enum(u1) { - /// RR[2] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[2] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[3] register - RR3: packed union { - raw: u1, - value: enum(u1) { - /// RR[3] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[3] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[4] register - RR4: packed union { - raw: u1, - value: enum(u1) { - /// RR[4] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[4] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[5] register - RR5: packed union { - raw: u1, - value: enum(u1) { - /// RR[5] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[5] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[6] register - RR6: packed union { - raw: u1, - value: enum(u1) { - /// RR[6] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[6] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[7] register - RR7: packed union { - raw: u1, - value: enum(u1) { - /// RR[7] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[7] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - padding: u24, - }), - reserved1284: [252]u8, - /// Counter reload value - CRV: mmio.Mmio(packed struct(u32) { - /// Counter reload value in number of cycles of the 32.768 kHz clock - CRV: u32, - }), - /// Enable register for reload request registers - RREN: mmio.Mmio(packed struct(u32) { - /// Enable or disable RR[0] register - RR0: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[0] register - Disabled = 0x0, - /// Enable RR[0] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[1] register - RR1: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[1] register - Disabled = 0x0, - /// Enable RR[1] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[2] register - RR2: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[2] register - Disabled = 0x0, - /// Enable RR[2] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[3] register - RR3: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[3] register - Disabled = 0x0, - /// Enable RR[3] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[4] register - RR4: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[4] register - Disabled = 0x0, - /// Enable RR[4] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[5] register - RR5: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[5] register - Disabled = 0x0, - /// Enable RR[5] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[6] register - RR6: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[6] register - Disabled = 0x0, - /// Enable RR[6] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[7] register - RR7: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[7] register - Disabled = 0x0, - /// Enable RR[7] register - Enabled = 0x1, - }, - }, - padding: u24, - }), - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Configure the watchdog to either be paused, or kept running, while the CPU is sleeping - SLEEP: packed union { - raw: u1, - value: enum(u1) { - /// Pause watchdog while the CPU is sleeping - Pause = 0x0, - /// Keep the watchdog running while the CPU is sleeping - Run = 0x1, - }, - }, - reserved3: u2, - /// Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger - HALT: packed union { - raw: u1, - value: enum(u1) { - /// Pause watchdog while the CPU is halted by the debugger - Pause = 0x0, - /// Keep the watchdog running while the CPU is halted by the debugger - Run = 0x1, - }, - }, - padding: u28, - }), - reserved1536: [240]u8, - /// Description collection[0]: Reload request 0 - RR: [8]mmio.Mmio(packed struct(u32) { - /// Reload request register - RR: packed union { - raw: u32, - value: enum(u32) { - /// Value to request a reload of the watchdog timer - Reload = 0x6e524635, - _, - }, - }, - }), - }; - - /// Pulse Width Modulation Unit 0 - pub const PWM0 = extern struct { - reserved4: [4]u8, - /// Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback - TASKS_STOP: u32, - /// Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running. - TASKS_SEQSTART: [2]u32, - /// Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running. - TASKS_NEXTSTEP: u32, - reserved260: [240]u8, - /// Response to STOP task, emitted when PWM pulses are no longer generated - EVENTS_STOPPED: u32, - /// Description collection[0]: First PWM period started on sequence 0 - EVENTS_SEQSTARTED: [2]u32, - /// Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter - EVENTS_SEQEND: [2]u32, - /// Emitted at the end of each PWM period - EVENTS_PWMPERIODEND: u32, - /// Concatenated sequences have been played the amount of times defined in LOOP.CNT - EVENTS_LOOPSDONE: u32, - reserved512: [224]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between SEQEND[0] event and STOP task - SEQEND0_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between SEQEND[1] event and STOP task - SEQEND1_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between LOOPSDONE event and SEQSTART[0] task - LOOPSDONE_SEQSTART0: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between LOOPSDONE event and SEQSTART[1] task - LOOPSDONE_SEQSTART1: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between LOOPSDONE event and STOP task - LOOPSDONE_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for SEQEND[0] event - SEQEND0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for SEQEND[1] event - SEQEND1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for PWMPERIODEND event - PWMPERIODEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for LOOPSDONE event - LOOPSDONE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u24, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for SEQSTARTED[0] event - SEQSTARTED0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for SEQSTARTED[1] event - SEQSTARTED1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for SEQEND[0] event - SEQEND0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for SEQEND[1] event - SEQEND1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for PWMPERIODEND event - PWMPERIODEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for LOOPSDONE event - LOOPSDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u24, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for SEQEND[0] event - SEQEND0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for SEQEND[1] event - SEQEND1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for PWMPERIODEND event - PWMPERIODEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for LOOPSDONE event - LOOPSDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u24, - }), - reserved1280: [500]u8, - /// PWM module enable register - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable PWM module - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Selects operating mode of the wave counter - MODE: mmio.Mmio(packed struct(u32) { - /// Selects up or up and down as wave counter mode - UPDOWN: packed union { - raw: u1, - value: enum(u1) { - /// Up counter - edge aligned PWM duty-cycle - Up = 0x0, - /// Up and down counter - center aligned PWM duty cycle - UpAndDown = 0x1, - }, - }, - padding: u31, - }), - /// Value up to which the pulse generator counter counts - COUNTERTOP: mmio.Mmio(packed struct(u32) { - /// Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. - COUNTERTOP: u15, - padding: u17, - }), - /// Configuration for PWM_CLK - PRESCALER: mmio.Mmio(packed struct(u32) { - /// Pre-scaler of PWM_CLK - PRESCALER: packed union { - raw: u3, - value: enum(u3) { - /// Divide by 1 (16MHz) - DIV_1 = 0x0, - /// Divide by 2 ( 8MHz) - DIV_2 = 0x1, - /// Divide by 4 ( 4MHz) - DIV_4 = 0x2, - /// Divide by 8 ( 2MHz) - DIV_8 = 0x3, - /// Divide by 16 ( 1MHz) - DIV_16 = 0x4, - /// Divide by 32 ( 500kHz) - DIV_32 = 0x5, - /// Divide by 64 ( 250kHz) - DIV_64 = 0x6, - /// Divide by 128 ( 125kHz) - DIV_128 = 0x7, - }, - }, - padding: u29, - }), - /// Configuration of the decoder - DECODER: mmio.Mmio(packed struct(u32) { - /// How a sequence is read from RAM and spread to the compare register - LOAD: packed union { - raw: u2, - value: enum(u2) { - /// 1st half word (16-bit) used in all PWM channels 0..3 - Common = 0x0, - /// 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 - Grouped = 0x1, - /// 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 - Individual = 0x2, - /// 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP - WaveForm = 0x3, - }, - }, - reserved8: u6, - /// Selects source for advancing the active sequence - MODE: packed union { - raw: u1, - value: enum(u1) { - /// SEQ[n].REFRESH is used to determine loading internal compare registers - RefreshCount = 0x0, - /// NEXTSTEP task causes a new value to be loaded to internal compare registers - NextStep = 0x1, - }, - }, - padding: u23, - }), - /// Amount of playback of a loop - LOOP: mmio.Mmio(packed struct(u32) { - /// Amount of playback of pattern cycles - CNT: packed union { - raw: u16, - value: enum(u16) { - /// Looping disabled (stop at the end of the sequence) - Disabled = 0x0, - _, - }, - }, - padding: u16, - }), - }; - - /// Quadrature Decoder - pub const QDEC = extern struct { - /// Task starting the quadrature decoder - TASKS_START: u32, - /// Task stopping the quadrature decoder - TASKS_STOP: u32, - /// Read and clear ACC and ACCDBL - TASKS_READCLRACC: u32, - /// Read and clear ACC - TASKS_RDCLRACC: u32, - /// Read and clear ACCDBL - TASKS_RDCLRDBL: u32, - reserved256: [236]u8, - /// Event being generated for every new sample value written to the SAMPLE register - EVENTS_SAMPLERDY: u32, - /// Non-null report ready - EVENTS_REPORTRDY: u32, - /// ACC or ACCDBL register overflow - EVENTS_ACCOF: u32, - /// Double displacement(s) detected - EVENTS_DBLRDY: u32, - /// QDEC has been stopped - EVENTS_STOPPED: u32, - reserved512: [236]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between REPORTRDY event and READCLRACC task - REPORTRDY_READCLRACC: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between SAMPLERDY event and STOP task - SAMPLERDY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between REPORTRDY event and RDCLRACC task - REPORTRDY_RDCLRACC: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between REPORTRDY event and STOP task - REPORTRDY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between DBLRDY event and RDCLRDBL task - DBLRDY_RDCLRDBL: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between DBLRDY event and STOP task - DBLRDY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between SAMPLERDY event and READCLRACC task - SAMPLERDY_READCLRACC: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u25, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for SAMPLERDY event - SAMPLERDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for REPORTRDY event - REPORTRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for ACCOF event - ACCOF: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for DBLRDY event - DBLRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u27, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for SAMPLERDY event - SAMPLERDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for REPORTRDY event - REPORTRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for ACCOF event - ACCOF: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for DBLRDY event - DBLRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved1280: [500]u8, - /// Enable the quadrature decoder - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable the quadrature decoder - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// LED output pin polarity - LEDPOL: mmio.Mmio(packed struct(u32) { - /// LED output pin polarity - LEDPOL: packed union { - raw: u1, - value: enum(u1) { - /// Led active on output pin low - ActiveLow = 0x0, - /// Led active on output pin high - ActiveHigh = 0x1, - }, - }, - padding: u31, - }), - /// Sample period - SAMPLEPER: mmio.Mmio(packed struct(u32) { - /// Sample period. The SAMPLE register will be updated for every new sample - SAMPLEPER: packed union { - raw: u4, - value: enum(u4) { - /// 128 us - @"128us" = 0x0, - /// 256 us - @"256us" = 0x1, - /// 512 us - @"512us" = 0x2, - /// 1024 us - @"1024us" = 0x3, - /// 2048 us - @"2048us" = 0x4, - /// 4096 us - @"4096us" = 0x5, - /// 8192 us - @"8192us" = 0x6, - /// 16384 us - @"16384us" = 0x7, - /// 32768 us - @"32ms" = 0x8, - /// 65536 us - @"65ms" = 0x9, - /// 131072 us - @"131ms" = 0xa, - _, - }, - }, - padding: u28, - }), - /// Motion sample value - SAMPLE: mmio.Mmio(packed struct(u32) { - /// Last motion sample - SAMPLE: u32, - }), - /// Number of samples to be taken before REPORTRDY and DBLRDY events can be generated - REPORTPER: mmio.Mmio(packed struct(u32) { - /// Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated - REPORTPER: packed union { - raw: u4, - value: enum(u4) { - /// 10 samples / report - @"10Smpl" = 0x0, - /// 40 samples / report - @"40Smpl" = 0x1, - /// 80 samples / report - @"80Smpl" = 0x2, - /// 120 samples / report - @"120Smpl" = 0x3, - /// 160 samples / report - @"160Smpl" = 0x4, - /// 200 samples / report - @"200Smpl" = 0x5, - /// 240 samples / report - @"240Smpl" = 0x6, - /// 280 samples / report - @"280Smpl" = 0x7, - /// 1 sample / report - @"1Smpl" = 0x8, - _, - }, - }, - padding: u28, - }), - /// Register accumulating the valid transitions - ACC: mmio.Mmio(packed struct(u32) { - /// Register accumulating all valid samples (not double transition) read from the SAMPLE register - ACC: u32, - }), - /// Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task - ACCREAD: mmio.Mmio(packed struct(u32) { - /// Snapshot of the ACC register. - ACCREAD: u32, - }), - reserved1320: [12]u8, - /// Enable input debounce filters - DBFEN: mmio.Mmio(packed struct(u32) { - /// Enable input debounce filters - DBFEN: packed union { - raw: u1, - value: enum(u1) { - /// Debounce input filters disabled - Disabled = 0x0, - /// Debounce input filters enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1344: [20]u8, - /// Time period the LED is switched ON prior to sampling - LEDPRE: mmio.Mmio(packed struct(u32) { - /// Period in us the LED is switched on prior to sampling - LEDPRE: u9, - padding: u23, - }), - /// Register accumulating the number of detected double transitions - ACCDBL: mmio.Mmio(packed struct(u32) { - /// Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). - ACCDBL: u4, - padding: u28, - }), - /// Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task - ACCDBLREAD: mmio.Mmio(packed struct(u32) { - /// Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. - ACCDBLREAD: u4, - padding: u28, - }), - }; - - /// Comparator - pub const COMP = extern struct { - /// Start comparator - TASKS_START: u32, - /// Stop comparator - TASKS_STOP: u32, - /// Sample comparator value - TASKS_SAMPLE: u32, - reserved256: [244]u8, - /// COMP is ready and output is valid - EVENTS_READY: u32, - /// Downward crossing - EVENTS_DOWN: u32, - /// Upward crossing - EVENTS_UP: u32, - /// Downward or upward crossing - EVENTS_CROSS: u32, - reserved512: [240]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between READY event and SAMPLE task - READY_SAMPLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between READY event and STOP task - READY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between DOWN event and STOP task - DOWN_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between UP event and STOP task - UP_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between CROSS event and STOP task - CROSS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for DOWN event - DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for UP event - UP: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for CROSS event - CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u28, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for DOWN event - DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for UP event - UP: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CROSS event - CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u28, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for DOWN event - DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for UP event - UP: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CROSS event - CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u28, - }), - reserved1024: [244]u8, - /// Compare result - RESULT: mmio.Mmio(packed struct(u32) { - /// Result of last compare. Decision point SAMPLE task. - RESULT: packed union { - raw: u1, - value: enum(u1) { - /// Input voltage is below the threshold (VIN+ < VIN-) - Below = 0x0, - /// Input voltage is above the threshold (VIN+ > VIN-) - Above = 0x1, - }, - }, - padding: u31, - }), - reserved1280: [252]u8, - /// COMP enable - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable COMP - ENABLE: packed union { - raw: u2, - value: enum(u2) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x2, - _, - }, - }, - padding: u30, - }), - /// Pin select - PSEL: mmio.Mmio(packed struct(u32) { - /// Analog pin select - PSEL: packed union { - raw: u3, - value: enum(u3) { - /// AIN0 selected as analog input - AnalogInput0 = 0x0, - /// AIN1 selected as analog input - AnalogInput1 = 0x1, - /// AIN2 selected as analog input - AnalogInput2 = 0x2, - /// AIN3 selected as analog input - AnalogInput3 = 0x3, - /// AIN4 selected as analog input - AnalogInput4 = 0x4, - /// AIN5 selected as analog input - AnalogInput5 = 0x5, - /// AIN6 selected as analog input - AnalogInput6 = 0x6, - /// AIN7 selected as analog input - AnalogInput7 = 0x7, - }, - }, - padding: u29, - }), - /// Reference source select for single-ended mode - REFSEL: mmio.Mmio(packed struct(u32) { - /// Reference select - REFSEL: packed union { - raw: u3, - value: enum(u3) { - /// VREF = internal 1.2 V reference (VDD >= 1.7 V) - Int1V2 = 0x0, - /// VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) - Int1V8 = 0x1, - /// VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) - Int2V4 = 0x2, - /// VREF = VDD - VDD = 0x4, - /// VREF = AREF (VDD >= VREF >= AREFMIN) - ARef = 0x7, - _, - }, - }, - padding: u29, - }), - /// External reference select - EXTREFSEL: mmio.Mmio(packed struct(u32) { - /// External analog reference select - EXTREFSEL: packed union { - raw: u3, - value: enum(u3) { - /// Use AIN0 as external analog reference - AnalogReference0 = 0x0, - /// Use AIN1 as external analog reference - AnalogReference1 = 0x1, - /// Use AIN2 as external analog reference - AnalogReference2 = 0x2, - /// Use AIN3 as external analog reference - AnalogReference3 = 0x3, - /// Use AIN4 as external analog reference - AnalogReference4 = 0x4, - /// Use AIN5 as external analog reference - AnalogReference5 = 0x5, - /// Use AIN6 as external analog reference - AnalogReference6 = 0x6, - /// Use AIN7 as external analog reference - AnalogReference7 = 0x7, - }, - }, - padding: u29, - }), - reserved1328: [32]u8, - /// Threshold configuration for hysteresis unit - TH: mmio.Mmio(packed struct(u32) { - /// VDOWN = (THDOWN+1)/64*VREF - THDOWN: u6, - reserved8: u2, - /// VUP = (THUP+1)/64*VREF - THUP: u6, - padding: u18, - }), - /// Mode configuration - MODE: mmio.Mmio(packed struct(u32) { - /// Speed and power modes - SP: packed union { - raw: u2, - value: enum(u2) { - /// Low-power mode - Low = 0x0, - /// Normal mode - Normal = 0x1, - /// High-speed mode - High = 0x2, - _, - }, - }, - reserved8: u6, - /// Main operation modes - MAIN: packed union { - raw: u1, - value: enum(u1) { - /// Single-ended mode - SE = 0x0, - /// Differential mode - Diff = 0x1, - }, - }, - padding: u23, - }), - /// Comparator hysteresis enable - HYST: mmio.Mmio(packed struct(u32) { - /// Comparator hysteresis - HYST: packed union { - raw: u1, - value: enum(u1) { - /// Comparator hysteresis disabled - NoHyst = 0x0, - /// Comparator hysteresis enabled - Hyst50mV = 0x1, - }, - }, - padding: u31, - }), - /// Current source select on analog input - ISOURCE: mmio.Mmio(packed struct(u32) { - /// Comparator hysteresis - ISOURCE: packed union { - raw: u2, - value: enum(u2) { - /// Current source disabled - Off = 0x0, - /// Current source enabled (+/- 2.5 uA) - Ien2mA5 = 0x1, - /// Current source enabled (+/- 5 uA) - Ien5mA = 0x2, - /// Current source enabled (+/- 10 uA) - Ien10mA = 0x3, - }, - }, - padding: u30, - }), - }; - - /// Low Power Comparator - pub const LPCOMP = extern struct { - /// Start comparator - TASKS_START: u32, - /// Stop comparator - TASKS_STOP: u32, - /// Sample comparator value - TASKS_SAMPLE: u32, - reserved256: [244]u8, - /// LPCOMP is ready and output is valid - EVENTS_READY: u32, - /// Downward crossing - EVENTS_DOWN: u32, - /// Upward crossing - EVENTS_UP: u32, - /// Downward or upward crossing - EVENTS_CROSS: u32, - reserved512: [240]u8, - /// Shortcut register - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between READY event and SAMPLE task - READY_SAMPLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between READY event and STOP task - READY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between DOWN event and STOP task - DOWN_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between UP event and STOP task - UP_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between CROSS event and STOP task - CROSS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to Enable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for DOWN event - DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for UP event - UP: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Enable interrupt for CROSS event - CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u28, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to Disable interrupt for READY event - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for DOWN event - DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for UP event - UP: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to Disable interrupt for CROSS event - CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u28, - }), - reserved1024: [244]u8, - /// Compare result - RESULT: mmio.Mmio(packed struct(u32) { - /// Result of last compare. Decision point SAMPLE task. - RESULT: packed union { - raw: u1, - value: enum(u1) { - /// Input voltage is below the reference threshold (VIN+ < VIN-). - Below = 0x0, - /// Input voltage is above the reference threshold (VIN+ > VIN-). - Above = 0x1, - }, - }, - padding: u31, - }), - reserved1280: [252]u8, - /// Enable LPCOMP - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable LPCOMP - ENABLE: packed union { - raw: u2, - value: enum(u2) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - _, - }, - }, - padding: u30, - }), - /// Input pin select - PSEL: mmio.Mmio(packed struct(u32) { - /// Analog pin select - PSEL: packed union { - raw: u3, - value: enum(u3) { - /// AIN0 selected as analog input - AnalogInput0 = 0x0, - /// AIN1 selected as analog input - AnalogInput1 = 0x1, - /// AIN2 selected as analog input - AnalogInput2 = 0x2, - /// AIN3 selected as analog input - AnalogInput3 = 0x3, - /// AIN4 selected as analog input - AnalogInput4 = 0x4, - /// AIN5 selected as analog input - AnalogInput5 = 0x5, - /// AIN6 selected as analog input - AnalogInput6 = 0x6, - /// AIN7 selected as analog input - AnalogInput7 = 0x7, - }, - }, - padding: u29, - }), - /// Reference select - REFSEL: mmio.Mmio(packed struct(u32) { - /// Reference select - REFSEL: packed union { - raw: u4, - value: enum(u4) { - /// VDD * 1/8 selected as reference - Ref1_8Vdd = 0x0, - /// VDD * 2/8 selected as reference - Ref2_8Vdd = 0x1, - /// VDD * 3/8 selected as reference - Ref3_8Vdd = 0x2, - /// VDD * 4/8 selected as reference - Ref4_8Vdd = 0x3, - /// VDD * 5/8 selected as reference - Ref5_8Vdd = 0x4, - /// VDD * 6/8 selected as reference - Ref6_8Vdd = 0x5, - /// VDD * 7/8 selected as reference - Ref7_8Vdd = 0x6, - /// External analog reference selected - ARef = 0x7, - /// VDD * 1/16 selected as reference - Ref1_16Vdd = 0x8, - /// VDD * 3/16 selected as reference - Ref3_16Vdd = 0x9, - /// VDD * 5/16 selected as reference - Ref5_16Vdd = 0xa, - /// VDD * 7/16 selected as reference - Ref7_16Vdd = 0xb, - /// VDD * 9/16 selected as reference - Ref9_16Vdd = 0xc, - /// VDD * 11/16 selected as reference - Ref11_16Vdd = 0xd, - /// VDD * 13/16 selected as reference - Ref13_16Vdd = 0xe, - /// VDD * 15/16 selected as reference - Ref15_16Vdd = 0xf, - }, - }, - padding: u28, - }), - /// External reference select - EXTREFSEL: mmio.Mmio(packed struct(u32) { - /// External analog reference select - EXTREFSEL: packed union { - raw: u1, - value: enum(u1) { - /// Use AIN0 as external analog reference - AnalogReference0 = 0x0, - /// Use AIN1 as external analog reference - AnalogReference1 = 0x1, - }, - }, - padding: u31, - }), - reserved1312: [16]u8, - /// Analog detect configuration - ANADETECT: mmio.Mmio(packed struct(u32) { - /// Analog detect configuration - ANADETECT: packed union { - raw: u2, - value: enum(u2) { - /// Generate ANADETECT on crossing, both upward crossing and downward crossing - Cross = 0x0, - /// Generate ANADETECT on upward crossing only - Up = 0x1, - /// Generate ANADETECT on downward crossing only - Down = 0x2, - _, - }, - }, - padding: u30, - }), - reserved1336: [20]u8, - /// Comparator hysteresis enable - HYST: mmio.Mmio(packed struct(u32) { - /// Comparator hysteresis enable - HYST: packed union { - raw: u1, - value: enum(u1) { - /// Comparator hysteresis disabled - NoHyst = 0x0, - /// Comparator hysteresis disabled (typ. 50 mV) - Hyst50mV = 0x1, - }, - }, - padding: u31, - }), - }; - - /// Software interrupt 0 - pub const SWI0 = extern struct { - /// Unused. - UNUSED: u32, - }; - }; -}; diff --git a/src/chips/nrf52840.zig b/src/chips/nrf52840.zig deleted file mode 100644 index 955d043..0000000 --- a/src/chips/nrf52840.zig +++ /dev/null @@ -1,21782 +0,0 @@ -const micro = @import("microzig"); -const mmio = micro.mmio; - -pub const devices = struct { - /// nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller - pub const nrf52840 = struct { - pub const properties = struct { - pub const @"cpu.nvic_prio_bits" = "3"; - pub const @"cpu.mpu" = "1"; - pub const @"cpu.fpu" = "1"; - pub const @"cpu.revision" = "r0p1"; - pub const @"cpu.vendor_systick_config" = "0"; - pub const license = - \\ - \\Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n - \\\n - \\Redistribution and use in source and binary forms, with or without\n - \\modification, are permitted provided that the following conditions are met:\n - \\\n - \\1. Redistributions of source code must retain the above copyright notice, this\n - \\ list of conditions and the following disclaimer.\n - \\\n - \\2. Redistributions in binary form must reproduce the above copyright\n - \\ notice, this list of conditions and the following disclaimer in the\n - \\ documentation and/or other materials provided with the distribution.\n - \\\n - \\3. Neither the name of Nordic Semiconductor ASA nor the names of its\n - \\ contributors may be used to endorse or promote products derived from this\n - \\ software without specific prior written permission.\n - \\\n - \\THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n - \\AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n - \\IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n - \\ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n - \\LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n - \\CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n - \\SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n - \\INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n - \\CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n - \\ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n - \\POSSIBILITY OF SUCH DAMAGE.\n - \\ - ; - pub const @"cpu.name" = "CM4"; - pub const @"cpu.endian" = "little"; - }; - - pub const VectorTable = extern struct { - const Handler = micro.interrupt.Handler; - const unhandled = micro.interrupt.unhandled; - - initial_stack_pointer: u32, - Reset: Handler = unhandled, - NMI: Handler = unhandled, - HardFault: Handler = unhandled, - MemManageFault: Handler = unhandled, - BusFault: Handler = unhandled, - UsageFault: Handler = unhandled, - reserved5: [4]u32 = undefined, - SVCall: Handler = unhandled, - DebugMonitor: Handler = unhandled, - reserved11: [1]u32 = undefined, - PendSV: Handler = unhandled, - SysTick: Handler = unhandled, - POWER_CLOCK: Handler = unhandled, - RADIO: Handler = unhandled, - UARTE0_UART0: Handler = unhandled, - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: Handler = unhandled, - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: Handler = unhandled, - NFCT: Handler = unhandled, - GPIOTE: Handler = unhandled, - SAADC: Handler = unhandled, - TIMER0: Handler = unhandled, - TIMER1: Handler = unhandled, - TIMER2: Handler = unhandled, - RTC0: Handler = unhandled, - TEMP: Handler = unhandled, - RNG: Handler = unhandled, - ECB: Handler = unhandled, - CCM_AAR: Handler = unhandled, - WDT: Handler = unhandled, - RTC1: Handler = unhandled, - QDEC: Handler = unhandled, - COMP_LPCOMP: Handler = unhandled, - SWI0_EGU0: Handler = unhandled, - SWI1_EGU1: Handler = unhandled, - SWI2_EGU2: Handler = unhandled, - SWI3_EGU3: Handler = unhandled, - SWI4_EGU4: Handler = unhandled, - SWI5_EGU5: Handler = unhandled, - TIMER3: Handler = unhandled, - TIMER4: Handler = unhandled, - PWM0: Handler = unhandled, - PDM: Handler = unhandled, - reserved44: [2]u32 = undefined, - MWU: Handler = unhandled, - PWM1: Handler = unhandled, - PWM2: Handler = unhandled, - SPIM2_SPIS2_SPI2: Handler = unhandled, - RTC2: Handler = unhandled, - I2S: Handler = unhandled, - FPU: Handler = unhandled, - USBD: Handler = unhandled, - UARTE1: Handler = unhandled, - QSPI: Handler = unhandled, - CRYPTOCELL: Handler = unhandled, - reserved57: [2]u32 = undefined, - PWM3: Handler = unhandled, - reserved60: [1]u32 = undefined, - SPIM3: Handler = unhandled, - }; - - pub const peripherals = struct { - /// Factory information configuration registers - pub const FICR = @as(*volatile types.peripherals.FICR, @ptrFromInt(0x10000000)); - /// User information configuration registers - pub const UICR = @as(*volatile types.peripherals.UICR, @ptrFromInt(0x10001000)); - /// Clock control - pub const CLOCK = @as(*volatile types.peripherals.CLOCK, @ptrFromInt(0x40000000)); - /// Power control - pub const POWER = @as(*volatile types.peripherals.POWER, @ptrFromInt(0x40000000)); - /// 2.4 GHz radio - pub const RADIO = @as(*volatile types.peripherals.RADIO, @ptrFromInt(0x40001000)); - /// Universal Asynchronous Receiver/Transmitter - pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40002000)); - /// UART with EasyDMA 0 - pub const UARTE0 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40002000)); - /// Serial Peripheral Interface 0 - pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40003000)); - /// Serial Peripheral Interface Master with EasyDMA 0 - pub const SPIM0 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40003000)); - /// SPI Slave 0 - pub const SPIS0 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40003000)); - /// I2C compatible Two-Wire Interface 0 - pub const TWI0 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40003000)); - /// I2C compatible Two-Wire Master Interface with EasyDMA 0 - pub const TWIM0 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40003000)); - /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 - pub const TWIS0 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40003000)); - /// Serial Peripheral Interface 1 - pub const SPI1 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40004000)); - /// Serial Peripheral Interface Master with EasyDMA 1 - pub const SPIM1 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40004000)); - /// SPI Slave 1 - pub const SPIS1 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40004000)); - /// I2C compatible Two-Wire Interface 1 - pub const TWI1 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40004000)); - /// I2C compatible Two-Wire Master Interface with EasyDMA 1 - pub const TWIM1 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40004000)); - /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 - pub const TWIS1 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40004000)); - /// NFC-A compatible radio - pub const NFCT = @as(*volatile types.peripherals.NFCT, @ptrFromInt(0x40005000)); - /// GPIO Tasks and Events - pub const GPIOTE = @as(*volatile types.peripherals.GPIOTE, @ptrFromInt(0x40006000)); - /// Successive approximation register (SAR) analog-to-digital converter - pub const SAADC = @as(*volatile types.peripherals.SAADC, @ptrFromInt(0x40007000)); - /// Timer/Counter 0 - pub const TIMER0 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40008000)); - /// Timer/Counter 1 - pub const TIMER1 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40009000)); - /// Timer/Counter 2 - pub const TIMER2 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4000a000)); - /// Real time counter 0 - pub const RTC0 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x4000b000)); - /// Temperature Sensor - pub const TEMP = @as(*volatile types.peripherals.TEMP, @ptrFromInt(0x4000c000)); - /// Random Number Generator - pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x4000d000)); - /// AES ECB Mode Encryption - pub const ECB = @as(*volatile types.peripherals.ECB, @ptrFromInt(0x4000e000)); - /// Accelerated Address Resolver - pub const AAR = @as(*volatile types.peripherals.AAR, @ptrFromInt(0x4000f000)); - /// AES CCM Mode Encryption - pub const CCM = @as(*volatile types.peripherals.CCM, @ptrFromInt(0x4000f000)); - /// Watchdog Timer - pub const WDT = @as(*volatile types.peripherals.WDT, @ptrFromInt(0x40010000)); - /// Real time counter 1 - pub const RTC1 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40011000)); - /// Quadrature Decoder - pub const QDEC = @as(*volatile types.peripherals.QDEC, @ptrFromInt(0x40012000)); - /// Comparator - pub const COMP = @as(*volatile types.peripherals.COMP, @ptrFromInt(0x40013000)); - /// Low Power Comparator - pub const LPCOMP = @as(*volatile types.peripherals.LPCOMP, @ptrFromInt(0x40013000)); - /// Event Generator Unit 0 - pub const EGU0 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40014000)); - /// Software interrupt 0 - pub const SWI0 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40014000)); - /// Event Generator Unit 1 - pub const EGU1 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40015000)); - /// Software interrupt 1 - pub const SWI1 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40015000)); - /// Event Generator Unit 2 - pub const EGU2 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40016000)); - /// Software interrupt 2 - pub const SWI2 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40016000)); - /// Event Generator Unit 3 - pub const EGU3 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40017000)); - /// Software interrupt 3 - pub const SWI3 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40017000)); - /// Event Generator Unit 4 - pub const EGU4 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40018000)); - /// Software interrupt 4 - pub const SWI4 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40018000)); - /// Event Generator Unit 5 - pub const EGU5 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40019000)); - /// Software interrupt 5 - pub const SWI5 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40019000)); - /// Timer/Counter 3 - pub const TIMER3 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001a000)); - /// Timer/Counter 4 - pub const TIMER4 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001b000)); - /// Pulse width modulation unit 0 - pub const PWM0 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4001c000)); - /// Pulse Density Modulation (Digital Microphone) Interface - pub const PDM = @as(*volatile types.peripherals.PDM, @ptrFromInt(0x4001d000)); - /// Access control lists - pub const ACL = @as(*volatile types.peripherals.ACL, @ptrFromInt(0x4001e000)); - /// Non Volatile Memory Controller - pub const NVMC = @as(*volatile types.peripherals.NVMC, @ptrFromInt(0x4001e000)); - /// Programmable Peripheral Interconnect - pub const PPI = @as(*volatile types.peripherals.PPI, @ptrFromInt(0x4001f000)); - /// Memory Watch Unit - pub const MWU = @as(*volatile types.peripherals.MWU, @ptrFromInt(0x40020000)); - /// Pulse width modulation unit 1 - pub const PWM1 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40021000)); - /// Pulse width modulation unit 2 - pub const PWM2 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40022000)); - /// Serial Peripheral Interface 2 - pub const SPI2 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40023000)); - /// Serial Peripheral Interface Master with EasyDMA 2 - pub const SPIM2 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40023000)); - /// SPI Slave 2 - pub const SPIS2 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40023000)); - /// Real time counter 2 - pub const RTC2 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40024000)); - /// Inter-IC Sound - pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x40025000)); - /// FPU - pub const FPU = @as(*volatile types.peripherals.FPU, @ptrFromInt(0x40026000)); - /// Universal serial bus device - pub const USBD = @as(*volatile types.peripherals.USBD, @ptrFromInt(0x40027000)); - /// UART with EasyDMA 1 - pub const UARTE1 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40028000)); - /// External flash interface - pub const QSPI = @as(*volatile types.peripherals.QSPI, @ptrFromInt(0x40029000)); - /// Pulse width modulation unit 3 - pub const PWM3 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4002d000)); - /// Serial Peripheral Interface Master with EasyDMA 3 - pub const SPIM3 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x4002f000)); - /// GPIO Port 1 - pub const P0 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000000)); - /// GPIO Port 2 - pub const P1 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000300)); - /// CRYPTOCELL HOST_RGF interface - pub const CC_HOST_RGF = @as(*volatile types.peripherals.CC_HOST_RGF, @ptrFromInt(0x5002a000)); - /// ARM TrustZone CryptoCell register interface - pub const CRYPTOCELL = @as(*volatile types.peripherals.CRYPTOCELL, @ptrFromInt(0x5002a000)); - /// System Tick Timer - pub const SysTick = @as(*volatile types.peripherals.SCS.SysTick, @ptrFromInt(0xe000e010)); - }; - }; -}; - -pub const types = struct { - pub const peripherals = struct { - /// System Control Space - pub const SCS = struct { - /// System Tick Timer - pub const SysTick = extern struct { - /// SysTick Control and Status Register - CTRL: mmio.Mmio(packed struct(u32) { - ENABLE: u1, - TICKINT: u1, - CLKSOURCE: u1, - reserved16: u13, - COUNTFLAG: u1, - padding: u15, - }), - /// SysTick Reload Value Register - LOAD: mmio.Mmio(packed struct(u32) { - RELOAD: u24, - padding: u8, - }), - /// SysTick Current Value Register - VAL: mmio.Mmio(packed struct(u32) { - CURRENT: u24, - padding: u8, - }), - /// SysTick Calibration Register - CALIB: mmio.Mmio(packed struct(u32) { - TENMS: u24, - reserved30: u6, - SKEW: u1, - NOREF: u1, - }), - }; - }; - - /// Factory information configuration registers - pub const FICR = extern struct { - reserved16: [16]u8, - /// Code memory page size - CODEPAGESIZE: mmio.Mmio(packed struct(u32) { - /// Code memory page size - CODEPAGESIZE: u32, - }), - /// Code memory size - CODESIZE: mmio.Mmio(packed struct(u32) { - /// Code memory size in number of pages - CODESIZE: u32, - }), - reserved96: [72]u8, - /// Description collection: Device identifier - DEVICEID: [2]mmio.Mmio(packed struct(u32) { - /// 64 bit unique device identifier - DEVICEID: u32, - }), - reserved128: [24]u8, - /// Description collection: Encryption root, word n - ER: [4]mmio.Mmio(packed struct(u32) { - /// Encryption root, word n - ER: u32, - }), - /// Description collection: Identity Root, word n - IR: [4]mmio.Mmio(packed struct(u32) { - /// Identity Root, word n - IR: u32, - }), - /// Device address type - DEVICEADDRTYPE: mmio.Mmio(packed struct(u32) { - /// Device address type - DEVICEADDRTYPE: packed union { - raw: u1, - value: enum(u1) { - /// Public address - Public = 0x0, - /// Random address - Random = 0x1, - }, - }, - padding: u31, - }), - /// Description collection: Device address n - DEVICEADDR: [2]mmio.Mmio(packed struct(u32) { - /// 48 bit device address - DEVICEADDR: u32, - }), - reserved848: [676]u8, - /// Description collection: Production test signature n - PRODTEST: [3]mmio.Mmio(packed struct(u32) { - /// Production test signature n - PRODTEST: packed union { - raw: u32, - value: enum(u32) { - /// Production tests done - Done = 0xbb42319f, - /// Production tests not done - NotDone = 0xffffffff, - _, - }, - }, - }), - }; - - /// User information configuration registers - pub const UICR = extern struct { - reserved20: [20]u8, - /// Description collection: Reserved for Nordic firmware design - NRFFW: [13]mmio.Mmio(packed struct(u32) { - /// Reserved for Nordic firmware design - NRFFW: u32, - }), - reserved80: [8]u8, - /// Description collection: Reserved for Nordic hardware design - NRFHW: [12]mmio.Mmio(packed struct(u32) { - /// Reserved for Nordic hardware design - NRFHW: u32, - }), - /// Description collection: Reserved for customer - CUSTOMER: [32]mmio.Mmio(packed struct(u32) { - /// Reserved for customer - CUSTOMER: u32, - }), - reserved512: [256]u8, - /// Description collection: Mapping of the nRESET function (see POWER chapter for details) - PSELRESET: [2]mmio.Mmio(packed struct(u32) { - /// GPIO pin number onto which nRESET is exposed - PIN: u5, - /// Port number onto which nRESET is exposed - PORT: u1, - reserved31: u25, - /// Connection - CONNECT: packed union { - raw: u1, - value: enum(u1) { - /// Disconnect - Disconnected = 0x1, - /// Connect - Connected = 0x0, - }, - }, - }), - /// Access port protection - APPROTECT: mmio.Mmio(packed struct(u32) { - /// Enable or disable access port protection. - PALL: packed union { - raw: u8, - value: enum(u8) { - /// Disable - Disabled = 0xff, - /// Enable - Enabled = 0x0, - _, - }, - }, - padding: u24, - }), - /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO - NFCPINS: mmio.Mmio(packed struct(u32) { - /// Setting of pins dedicated to NFC functionality - PROTECT: packed union { - raw: u1, - value: enum(u1) { - /// Operation as GPIO pins. Same protection as normal GPIO pins - Disabled = 0x0, - /// Operation as NFC antenna pins. Configures the protection for NFC operation - NFC = 0x1, - }, - }, - padding: u31, - }), - /// Processor debug control - DEBUGCTRL: mmio.Mmio(packed struct(u32) { - /// Configure CPU non-intrusive debug features - CPUNIDEN: packed union { - raw: u8, - value: enum(u8) { - /// Enable CPU ITM and ETM functionality (default behavior) - Enabled = 0xff, - /// Disable CPU ITM and ETM functionality - Disabled = 0x0, - _, - }, - }, - /// Configure CPU flash patch and breakpoint (FPB) unit behavior - CPUFPBEN: packed union { - raw: u8, - value: enum(u8) { - /// Enable CPU FPB unit (default behavior) - Enabled = 0xff, - /// Disable CPU FPB unit. Writes into the FPB registers will be ignored. - Disabled = 0x0, - _, - }, - }, - padding: u16, - }), - reserved772: [240]u8, - /// GPIO reference voltage / external output supply voltage in high voltage mode - REGOUT0: mmio.Mmio(packed struct(u32) { - /// Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. - VOUT: packed union { - raw: u3, - value: enum(u3) { - /// 1.8 V - @"1V8" = 0x0, - /// 2.1 V - @"2V1" = 0x1, - /// 2.4 V - @"2V4" = 0x2, - /// 2.7 V - @"2V7" = 0x3, - /// 3.0 V - @"3V0" = 0x4, - /// 3.3 V - @"3V3" = 0x5, - /// Default voltage: 1.8 V - DEFAULT = 0x7, - _, - }, - }, - padding: u29, - }), - }; - - /// Clock control - pub const CLOCK = extern struct { - /// Start HFXO crystal oscillator - TASKS_HFCLKSTART: mmio.Mmio(packed struct(u32) { - /// Start HFXO crystal oscillator - TASKS_HFCLKSTART: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop HFXO crystal oscillator - TASKS_HFCLKSTOP: mmio.Mmio(packed struct(u32) { - /// Stop HFXO crystal oscillator - TASKS_HFCLKSTOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start LFCLK - TASKS_LFCLKSTART: mmio.Mmio(packed struct(u32) { - /// Start LFCLK - TASKS_LFCLKSTART: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop LFCLK - TASKS_LFCLKSTOP: mmio.Mmio(packed struct(u32) { - /// Stop LFCLK - TASKS_LFCLKSTOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start calibration of LFRC - TASKS_CAL: mmio.Mmio(packed struct(u32) { - /// Start calibration of LFRC - TASKS_CAL: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start calibration timer - TASKS_CTSTART: mmio.Mmio(packed struct(u32) { - /// Start calibration timer - TASKS_CTSTART: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop calibration timer - TASKS_CTSTOP: mmio.Mmio(packed struct(u32) { - /// Stop calibration timer - TASKS_CTSTOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [228]u8, - /// HFXO crystal oscillator started - EVENTS_HFCLKSTARTED: mmio.Mmio(packed struct(u32) { - /// HFXO crystal oscillator started - EVENTS_HFCLKSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// LFCLK started - EVENTS_LFCLKSTARTED: mmio.Mmio(packed struct(u32) { - /// LFCLK started - EVENTS_LFCLKSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved268: [4]u8, - /// Calibration of LFRC completed - EVENTS_DONE: mmio.Mmio(packed struct(u32) { - /// Calibration of LFRC completed - EVENTS_DONE: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Calibration timer timeout - EVENTS_CTTO: mmio.Mmio(packed struct(u32) { - /// Calibration timer timeout - EVENTS_CTTO: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved296: [20]u8, - /// Calibration timer has been started and is ready to process new tasks - EVENTS_CTSTARTED: mmio.Mmio(packed struct(u32) { - /// Calibration timer has been started and is ready to process new tasks - EVENTS_CTSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Calibration timer has been stopped and is ready to process new tasks - EVENTS_CTSTOPPED: mmio.Mmio(packed struct(u32) { - /// Calibration timer has been stopped and is ready to process new tasks - EVENTS_CTSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved772: [468]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event HFCLKSTARTED - HFCLKSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event LFCLKSTARTED - LFCLKSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved3: u1, - /// Write '1' to enable interrupt for event DONE - DONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CTTO - CTTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u5, - /// Write '1' to enable interrupt for event CTSTARTED - CTSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CTSTOPPED - CTSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u20, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event HFCLKSTARTED - HFCLKSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event LFCLKSTARTED - LFCLKSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved3: u1, - /// Write '1' to disable interrupt for event DONE - DONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CTTO - CTTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u5, - /// Write '1' to disable interrupt for event CTSTARTED - CTSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CTSTOPPED - CTSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u20, - }), - reserved1032: [252]u8, - /// Status indicating that HFCLKSTART task has been triggered - HFCLKRUN: mmio.Mmio(packed struct(u32) { - /// HFCLKSTART task triggered or not - STATUS: packed union { - raw: u1, - value: enum(u1) { - /// Task not triggered - NotTriggered = 0x0, - /// Task triggered - Triggered = 0x1, - }, - }, - padding: u31, - }), - /// HFCLK status - HFCLKSTAT: mmio.Mmio(packed struct(u32) { - /// Source of HFCLK - SRC: packed union { - raw: u1, - value: enum(u1) { - /// 64 MHz internal oscillator (HFINT) - RC = 0x0, - /// 64 MHz crystal oscillator (HFXO) - Xtal = 0x1, - }, - }, - reserved16: u15, - /// HFCLK state - STATE: packed union { - raw: u1, - value: enum(u1) { - /// HFCLK not running - NotRunning = 0x0, - /// HFCLK running - Running = 0x1, - }, - }, - padding: u15, - }), - reserved1044: [4]u8, - /// Status indicating that LFCLKSTART task has been triggered - LFCLKRUN: mmio.Mmio(packed struct(u32) { - /// LFCLKSTART task triggered or not - STATUS: packed union { - raw: u1, - value: enum(u1) { - /// Task not triggered - NotTriggered = 0x0, - /// Task triggered - Triggered = 0x1, - }, - }, - padding: u31, - }), - /// LFCLK status - LFCLKSTAT: mmio.Mmio(packed struct(u32) { - /// Source of LFCLK - SRC: packed union { - raw: u2, - value: enum(u2) { - /// 32.768 kHz RC oscillator (LFRC) - RC = 0x0, - /// 32.768 kHz crystal oscillator (LFXO) - Xtal = 0x1, - /// 32.768 kHz synthesized from HFCLK (LFSYNT) - Synth = 0x2, - _, - }, - }, - reserved16: u14, - /// LFCLK state - STATE: packed union { - raw: u1, - value: enum(u1) { - /// LFCLK not running - NotRunning = 0x0, - /// LFCLK running - Running = 0x1, - }, - }, - padding: u15, - }), - /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered - LFCLKSRCCOPY: mmio.Mmio(packed struct(u32) { - /// Clock source - SRC: packed union { - raw: u2, - value: enum(u2) { - /// 32.768 kHz RC oscillator (LFRC) - RC = 0x0, - /// 32.768 kHz crystal oscillator (LFXO) - Xtal = 0x1, - /// 32.768 kHz synthesized from HFCLK (LFSYNT) - Synth = 0x2, - _, - }, - }, - padding: u30, - }), - reserved1304: [248]u8, - /// Clock source for the LFCLK - LFCLKSRC: mmio.Mmio(packed struct(u32) { - /// Clock source - SRC: packed union { - raw: u2, - value: enum(u2) { - /// 32.768 kHz RC oscillator (LFRC) - RC = 0x0, - /// 32.768 kHz crystal oscillator (LFXO) - Xtal = 0x1, - /// 32.768 kHz synthesized from HFCLK (LFSYNT) - Synth = 0x2, - _, - }, - }, - reserved16: u14, - /// Enable or disable bypass of LFCLK crystal oscillator with external clock source - BYPASS: packed union { - raw: u1, - value: enum(u1) { - /// Disable (use with Xtal or low-swing external source) - Disabled = 0x0, - /// Enable (use with rail-to-rail external source) - Enabled = 0x1, - }, - }, - /// Enable or disable external source for LFCLK - EXTERNAL: packed union { - raw: u1, - value: enum(u1) { - /// Disable external source (use with Xtal) - Disabled = 0x0, - /// Enable use of external source instead of Xtal (SRC needs to be set to Xtal) - Enabled = 0x1, - }, - }, - padding: u14, - }), - reserved1320: [12]u8, - /// HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. - HFXODEBOUNCE: mmio.Mmio(packed struct(u32) { - /// HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. - HFXODEBOUNCE: packed union { - raw: u8, - value: enum(u8) { - /// 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. - Db256us = 0x10, - /// 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. - Db1024us = 0x40, - _, - }, - }, - padding: u24, - }), - reserved1336: [12]u8, - /// Calibration timer interval - CTIV: mmio.Mmio(packed struct(u32) { - /// Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. - CTIV: u7, - padding: u25, - }), - reserved1372: [32]u8, - /// Clocking options for the trace port debug interface - TRACECONFIG: mmio.Mmio(packed struct(u32) { - /// Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. - TRACEPORTSPEED: packed union { - raw: u2, - value: enum(u2) { - /// 32 MHz trace port clock (TRACECLK = 16 MHz) - @"32MHz" = 0x0, - /// 16 MHz trace port clock (TRACECLK = 8 MHz) - @"16MHz" = 0x1, - /// 8 MHz trace port clock (TRACECLK = 4 MHz) - @"8MHz" = 0x2, - /// 4 MHz trace port clock (TRACECLK = 2 MHz) - @"4MHz" = 0x3, - }, - }, - reserved16: u14, - /// Pin multiplexing of trace signals. See pin assignment chapter for more details. - TRACEMUX: packed union { - raw: u2, - value: enum(u2) { - /// No trace signals routed to pins. All pins can be used as regular GPIOs. - GPIO = 0x0, - /// SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. - Serial = 0x1, - /// All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. - Parallel = 0x2, - _, - }, - }, - padding: u14, - }), - reserved1460: [84]u8, - /// LFRC mode configuration - LFRCMODE: mmio.Mmio(packed struct(u32) { - /// Set LFRC mode - MODE: packed union { - raw: u1, - value: enum(u1) { - /// Normal mode - Normal = 0x0, - /// Ultra-low power mode (ULP) - ULP = 0x1, - }, - }, - reserved16: u15, - /// Active LFRC mode. This field is read only. - STATUS: packed union { - raw: u1, - value: enum(u1) { - /// Normal mode - Normal = 0x0, - /// Ultra-low power mode (ULP) - ULP = 0x1, - }, - }, - padding: u15, - }), - }; - - /// Power control - pub const POWER = extern struct { - reserved120: [120]u8, - /// Enable Constant Latency mode - TASKS_CONSTLAT: mmio.Mmio(packed struct(u32) { - /// Enable Constant Latency mode - TASKS_CONSTLAT: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Enable Low-power mode (variable latency) - TASKS_LOWPWR: mmio.Mmio(packed struct(u32) { - /// Enable Low-power mode (variable latency) - TASKS_LOWPWR: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved264: [136]u8, - /// Power failure warning - EVENTS_POFWARN: mmio.Mmio(packed struct(u32) { - /// Power failure warning - EVENTS_POFWARN: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved276: [8]u8, - /// CPU entered WFI/WFE sleep - EVENTS_SLEEPENTER: mmio.Mmio(packed struct(u32) { - /// CPU entered WFI/WFE sleep - EVENTS_SLEEPENTER: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// CPU exited WFI/WFE sleep - EVENTS_SLEEPEXIT: mmio.Mmio(packed struct(u32) { - /// CPU exited WFI/WFE sleep - EVENTS_SLEEPEXIT: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Voltage supply detected on VBUS - EVENTS_USBDETECTED: mmio.Mmio(packed struct(u32) { - /// Voltage supply detected on VBUS - EVENTS_USBDETECTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Voltage supply removed from VBUS - EVENTS_USBREMOVED: mmio.Mmio(packed struct(u32) { - /// Voltage supply removed from VBUS - EVENTS_USBREMOVED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// USB 3.3 V supply ready - EVENTS_USBPWRRDY: mmio.Mmio(packed struct(u32) { - /// USB 3.3 V supply ready - EVENTS_USBPWRRDY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved772: [476]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Write '1' to enable interrupt for event POFWARN - POFWARN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved5: u2, - /// Write '1' to enable interrupt for event SLEEPENTER - SLEEPENTER: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event SLEEPEXIT - SLEEPEXIT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event USBDETECTED - USBDETECTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event USBREMOVED - USBREMOVED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event USBPWRRDY - USBPWRRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u22, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Write '1' to disable interrupt for event POFWARN - POFWARN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved5: u2, - /// Write '1' to disable interrupt for event SLEEPENTER - SLEEPENTER: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event SLEEPEXIT - SLEEPEXIT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event USBDETECTED - USBDETECTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event USBREMOVED - USBREMOVED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event USBPWRRDY - USBPWRRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u22, - }), - reserved1024: [244]u8, - /// Reset reason - RESETREAS: mmio.Mmio(packed struct(u32) { - /// Reset from pin-reset detected - RESETPIN: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset from watchdog detected - DOG: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset from soft reset detected - SREQ: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset from CPU lock-up detected - LOCKUP: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - reserved16: u12, - /// Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO - OFF: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP - LPCOMP: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode - DIF: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset due to wake up from System OFF mode by NFC field detect - NFC: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - /// Reset due to wake up from System OFF mode by VBUS rising into valid range - VBUS: packed union { - raw: u1, - value: enum(u1) { - /// Not detected - NotDetected = 0x0, - /// Detected - Detected = 0x1, - }, - }, - padding: u11, - }), - reserved1064: [36]u8, - /// Deprecated register - RAM status register - RAMSTATUS: mmio.Mmio(packed struct(u32) { - /// RAM block 0 is on or off/powering up - RAMBLOCK0: packed union { - raw: u1, - value: enum(u1) { - /// Off - Off = 0x0, - /// On - On = 0x1, - }, - }, - /// RAM block 1 is on or off/powering up - RAMBLOCK1: packed union { - raw: u1, - value: enum(u1) { - /// Off - Off = 0x0, - /// On - On = 0x1, - }, - }, - /// RAM block 2 is on or off/powering up - RAMBLOCK2: packed union { - raw: u1, - value: enum(u1) { - /// Off - Off = 0x0, - /// On - On = 0x1, - }, - }, - /// RAM block 3 is on or off/powering up - RAMBLOCK3: packed union { - raw: u1, - value: enum(u1) { - /// Off - Off = 0x0, - /// On - On = 0x1, - }, - }, - padding: u28, - }), - reserved1080: [12]u8, - /// USB supply status - USBREGSTATUS: mmio.Mmio(packed struct(u32) { - /// VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) - VBUSDETECT: packed union { - raw: u1, - value: enum(u1) { - /// VBUS voltage below valid threshold - NoVbus = 0x0, - /// VBUS voltage above valid threshold - VbusPresent = 0x1, - }, - }, - /// USB supply output settling time elapsed - OUTPUTRDY: packed union { - raw: u1, - value: enum(u1) { - /// USBREG output settling time not elapsed - NotReady = 0x0, - /// USBREG output settling time elapsed (same information as USBPWRRDY event) - Ready = 0x1, - }, - }, - padding: u30, - }), - reserved1280: [196]u8, - /// System OFF register - SYSTEMOFF: mmio.Mmio(packed struct(u32) { - /// Enable System OFF mode - SYSTEMOFF: packed union { - raw: u1, - value: enum(u1) { - /// Enable System OFF mode - Enter = 0x1, - _, - }, - }, - padding: u31, - }), - reserved1296: [12]u8, - /// Power-fail comparator configuration - POFCON: mmio.Mmio(packed struct(u32) { - /// Enable or disable power failure warning - POF: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. - THRESHOLD: packed union { - raw: u4, - value: enum(u4) { - /// Set threshold to 1.7 V - V17 = 0x4, - /// Set threshold to 1.8 V - V18 = 0x5, - /// Set threshold to 1.9 V - V19 = 0x6, - /// Set threshold to 2.0 V - V20 = 0x7, - /// Set threshold to 2.1 V - V21 = 0x8, - /// Set threshold to 2.2 V - V22 = 0x9, - /// Set threshold to 2.3 V - V23 = 0xa, - /// Set threshold to 2.4 V - V24 = 0xb, - /// Set threshold to 2.5 V - V25 = 0xc, - /// Set threshold to 2.6 V - V26 = 0xd, - /// Set threshold to 2.7 V - V27 = 0xe, - /// Set threshold to 2.8 V - V28 = 0xf, - _, - }, - }, - reserved8: u3, - /// Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). - THRESHOLDVDDH: packed union { - raw: u4, - value: enum(u4) { - /// Set threshold to 2.7 V - V27 = 0x0, - /// Set threshold to 2.8 V - V28 = 0x1, - /// Set threshold to 2.9 V - V29 = 0x2, - /// Set threshold to 3.0 V - V30 = 0x3, - /// Set threshold to 3.1 V - V31 = 0x4, - /// Set threshold to 3.2 V - V32 = 0x5, - /// Set threshold to 3.3 V - V33 = 0x6, - /// Set threshold to 3.4 V - V34 = 0x7, - /// Set threshold to 3.5 V - V35 = 0x8, - /// Set threshold to 3.6 V - V36 = 0x9, - /// Set threshold to 3.7 V - V37 = 0xa, - /// Set threshold to 3.8 V - V38 = 0xb, - /// Set threshold to 3.9 V - V39 = 0xc, - /// Set threshold to 4.0 V - V40 = 0xd, - /// Set threshold to 4.1 V - V41 = 0xe, - /// Set threshold to 4.2 V - V42 = 0xf, - }, - }, - padding: u20, - }), - reserved1308: [8]u8, - /// General purpose retention register - GPREGRET: mmio.Mmio(packed struct(u32) { - /// General purpose retention register - GPREGRET: u8, - padding: u24, - }), - /// General purpose retention register - GPREGRET2: mmio.Mmio(packed struct(u32) { - /// General purpose retention register - GPREGRET: u8, - padding: u24, - }), - reserved1400: [84]u8, - /// Enable DC/DC converter for REG1 stage - DCDCEN: mmio.Mmio(packed struct(u32) { - /// Enable DC/DC converter for REG1 stage. - DCDCEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1408: [4]u8, - /// Enable DC/DC converter for REG0 stage - DCDCEN0: mmio.Mmio(packed struct(u32) { - /// Enable DC/DC converter for REG0 stage. - DCDCEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1600: [188]u8, - /// Main supply status - MAINREGSTATUS: mmio.Mmio(packed struct(u32) { - /// Main supply status - MAINREGSTATUS: packed union { - raw: u1, - value: enum(u1) { - /// Normal voltage mode. Voltage supplied on VDD. - Normal = 0x0, - /// High voltage mode. Voltage supplied on VDDH. - High = 0x1, - }, - }, - padding: u31, - }), - }; - - /// GPIO Port 1 - pub const P0 = extern struct { - reserved1284: [1284]u8, - /// Write GPIO port - OUT: mmio.Mmio(packed struct(u32) { - /// Pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - /// Pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Pin driver is low - Low = 0x0, - /// Pin driver is high - High = 0x1, - }, - }, - }), - /// Set individual bits in GPIO port - OUTSET: mmio.Mmio(packed struct(u32) { - /// Pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - }), - /// Clear individual bits in GPIO port - OUTCLR: mmio.Mmio(packed struct(u32) { - /// Pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - /// Pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin driver is low - Low = 0x0, - /// Read: pin driver is high - High = 0x1, - }, - }, - }), - /// Read GPIO port - IN: mmio.Mmio(packed struct(u32) { - /// Pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - /// Pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Pin input is low - Low = 0x0, - /// Pin input is high - High = 0x1, - }, - }, - }), - /// Direction of GPIO pins - DIR: mmio.Mmio(packed struct(u32) { - /// Pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - /// Pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Pin set as input - Input = 0x0, - /// Pin set as output - Output = 0x1, - }, - }, - }), - /// DIR set register - DIRSET: mmio.Mmio(packed struct(u32) { - /// Set as output pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as output pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - }), - /// DIR clear register - DIRCLR: mmio.Mmio(packed struct(u32) { - /// Set as input pin 0 - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 1 - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 2 - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 3 - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 4 - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 5 - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 6 - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 7 - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 8 - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 9 - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 10 - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 11 - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 12 - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 13 - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 14 - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 15 - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 16 - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 17 - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 18 - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 19 - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 20 - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 21 - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 22 - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 23 - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 24 - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 25 - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 26 - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 27 - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 28 - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 29 - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 30 - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - /// Set as input pin 31 - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Read: pin set as input - Input = 0x0, - /// Read: pin set as output - Output = 0x1, - }, - }, - }), - /// Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers - LATCH: mmio.Mmio(packed struct(u32) { - /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. - PIN0: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. - PIN1: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. - PIN2: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. - PIN3: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. - PIN4: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. - PIN5: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. - PIN6: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. - PIN7: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. - PIN8: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. - PIN9: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. - PIN10: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. - PIN11: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. - PIN12: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. - PIN13: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. - PIN14: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. - PIN15: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. - PIN16: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. - PIN17: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. - PIN18: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. - PIN19: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. - PIN20: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. - PIN21: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. - PIN22: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. - PIN23: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. - PIN24: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. - PIN25: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. - PIN26: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. - PIN27: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. - PIN28: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. - PIN29: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. - PIN30: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - /// Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. - PIN31: packed union { - raw: u1, - value: enum(u1) { - /// Criteria has not been met - NotLatched = 0x0, - /// Criteria has been met - Latched = 0x1, - }, - }, - }), - /// Select between default DETECT signal behaviour and LDETECT mode - DETECTMODE: mmio.Mmio(packed struct(u32) { - /// Select between default DETECT signal behaviour and LDETECT mode - DETECTMODE: packed union { - raw: u1, - value: enum(u1) { - /// DETECT directly connected to PIN DETECT signals - Default = 0x0, - /// Use the latched LDETECT behaviour - LDETECT = 0x1, - }, - }, - padding: u31, - }), - reserved1792: [472]u8, - /// Description collection: Configuration of GPIO pins - PIN_CNF: [32]mmio.Mmio(packed struct(u32) { - /// Pin direction. Same physical register as DIR register - DIR: packed union { - raw: u1, - value: enum(u1) { - /// Configure pin as an input pin - Input = 0x0, - /// Configure pin as an output pin - Output = 0x1, - }, - }, - /// Connect or disconnect input buffer - INPUT: packed union { - raw: u1, - value: enum(u1) { - /// Connect input buffer - Connect = 0x0, - /// Disconnect input buffer - Disconnect = 0x1, - }, - }, - /// Pull configuration - PULL: packed union { - raw: u2, - value: enum(u2) { - /// No pull - Disabled = 0x0, - /// Pull down on pin - Pulldown = 0x1, - /// Pull up on pin - Pullup = 0x3, - _, - }, - }, - reserved8: u4, - /// Drive configuration - DRIVE: packed union { - raw: u3, - value: enum(u3) { - /// Standard '0', standard '1' - S0S1 = 0x0, - /// High drive '0', standard '1' - H0S1 = 0x1, - /// Standard '0', high drive '1' - S0H1 = 0x2, - /// High drive '0', high 'drive '1'' - H0H1 = 0x3, - /// Disconnect '0' standard '1' (normally used for wired-or connections) - D0S1 = 0x4, - /// Disconnect '0', high drive '1' (normally used for wired-or connections) - D0H1 = 0x5, - /// Standard '0'. disconnect '1' (normally used for wired-and connections) - S0D1 = 0x6, - /// High drive '0', disconnect '1' (normally used for wired-and connections) - H0D1 = 0x7, - }, - }, - reserved16: u5, - /// Pin sensing mechanism - SENSE: packed union { - raw: u2, - value: enum(u2) { - /// Disabled - Disabled = 0x0, - /// Sense for high level - High = 0x2, - /// Sense for low level - Low = 0x3, - _, - }, - }, - padding: u14, - }), - }; - - /// Access control lists - pub const ACL = struct {}; - - /// 2.4 GHz radio - pub const RADIO = extern struct { - /// Enable RADIO in TX mode - TASKS_TXEN: mmio.Mmio(packed struct(u32) { - /// Enable RADIO in TX mode - TASKS_TXEN: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Enable RADIO in RX mode - TASKS_RXEN: mmio.Mmio(packed struct(u32) { - /// Enable RADIO in RX mode - TASKS_RXEN: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start RADIO - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Start RADIO - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop RADIO - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop RADIO - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Disable RADIO - TASKS_DISABLE: mmio.Mmio(packed struct(u32) { - /// Disable RADIO - TASKS_DISABLE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start the RSSI and take one single sample of the receive signal strength - TASKS_RSSISTART: mmio.Mmio(packed struct(u32) { - /// Start the RSSI and take one single sample of the receive signal strength - TASKS_RSSISTART: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop the RSSI measurement - TASKS_RSSISTOP: mmio.Mmio(packed struct(u32) { - /// Stop the RSSI measurement - TASKS_RSSISTOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start the bit counter - TASKS_BCSTART: mmio.Mmio(packed struct(u32) { - /// Start the bit counter - TASKS_BCSTART: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop the bit counter - TASKS_BCSTOP: mmio.Mmio(packed struct(u32) { - /// Stop the bit counter - TASKS_BCSTOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start the energy detect measurement used in IEEE 802.15.4 mode - TASKS_EDSTART: mmio.Mmio(packed struct(u32) { - /// Start the energy detect measurement used in IEEE 802.15.4 mode - TASKS_EDSTART: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop the energy detect measurement - TASKS_EDSTOP: mmio.Mmio(packed struct(u32) { - /// Stop the energy detect measurement - TASKS_EDSTOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start the clear channel assessment used in IEEE 802.15.4 mode - TASKS_CCASTART: mmio.Mmio(packed struct(u32) { - /// Start the clear channel assessment used in IEEE 802.15.4 mode - TASKS_CCASTART: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop the clear channel assessment - TASKS_CCASTOP: mmio.Mmio(packed struct(u32) { - /// Stop the clear channel assessment - TASKS_CCASTOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [204]u8, - /// RADIO has ramped up and is ready to be started - EVENTS_READY: mmio.Mmio(packed struct(u32) { - /// RADIO has ramped up and is ready to be started - EVENTS_READY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Address sent or received - EVENTS_ADDRESS: mmio.Mmio(packed struct(u32) { - /// Address sent or received - EVENTS_ADDRESS: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Packet payload sent or received - EVENTS_PAYLOAD: mmio.Mmio(packed struct(u32) { - /// Packet payload sent or received - EVENTS_PAYLOAD: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Packet sent or received - EVENTS_END: mmio.Mmio(packed struct(u32) { - /// Packet sent or received - EVENTS_END: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// RADIO has been disabled - EVENTS_DISABLED: mmio.Mmio(packed struct(u32) { - /// RADIO has been disabled - EVENTS_DISABLED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// A device address match occurred on the last received packet - EVENTS_DEVMATCH: mmio.Mmio(packed struct(u32) { - /// A device address match occurred on the last received packet - EVENTS_DEVMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// No device address match occurred on the last received packet - EVENTS_DEVMISS: mmio.Mmio(packed struct(u32) { - /// No device address match occurred on the last received packet - EVENTS_DEVMISS: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Sampling of receive signal strength complete - EVENTS_RSSIEND: mmio.Mmio(packed struct(u32) { - /// Sampling of receive signal strength complete - EVENTS_RSSIEND: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved296: [8]u8, - /// Bit counter reached bit count value - EVENTS_BCMATCH: mmio.Mmio(packed struct(u32) { - /// Bit counter reached bit count value - EVENTS_BCMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved304: [4]u8, - /// Packet received with CRC ok - EVENTS_CRCOK: mmio.Mmio(packed struct(u32) { - /// Packet received with CRC ok - EVENTS_CRCOK: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Packet received with CRC error - EVENTS_CRCERROR: mmio.Mmio(packed struct(u32) { - /// Packet received with CRC error - EVENTS_CRCERROR: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// IEEE 802.15.4 length field received - EVENTS_FRAMESTART: mmio.Mmio(packed struct(u32) { - /// IEEE 802.15.4 length field received - EVENTS_FRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. - EVENTS_EDEND: mmio.Mmio(packed struct(u32) { - /// Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. - EVENTS_EDEND: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// The sampling of energy detection has stopped - EVENTS_EDSTOPPED: mmio.Mmio(packed struct(u32) { - /// The sampling of energy detection has stopped - EVENTS_EDSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Wireless medium in idle - clear to send - EVENTS_CCAIDLE: mmio.Mmio(packed struct(u32) { - /// Wireless medium in idle - clear to send - EVENTS_CCAIDLE: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Wireless medium busy - do not send - EVENTS_CCABUSY: mmio.Mmio(packed struct(u32) { - /// Wireless medium busy - do not send - EVENTS_CCABUSY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// The CCA has stopped - EVENTS_CCASTOPPED: mmio.Mmio(packed struct(u32) { - /// The CCA has stopped - EVENTS_CCASTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. - EVENTS_RATEBOOST: mmio.Mmio(packed struct(u32) { - /// Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. - EVENTS_RATEBOOST: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// RADIO has ramped up and is ready to be started TX path - EVENTS_TXREADY: mmio.Mmio(packed struct(u32) { - /// RADIO has ramped up and is ready to be started TX path - EVENTS_TXREADY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// RADIO has ramped up and is ready to be started RX path - EVENTS_RXREADY: mmio.Mmio(packed struct(u32) { - /// RADIO has ramped up and is ready to be started RX path - EVENTS_RXREADY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// MAC header match found - EVENTS_MHRMATCH: mmio.Mmio(packed struct(u32) { - /// MAC header match found - EVENTS_MHRMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved360: [8]u8, - /// Preamble indicator. - EVENTS_SYNC: mmio.Mmio(packed struct(u32) { - /// Preamble indicator. - EVENTS_SYNC: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. - EVENTS_PHYEND: mmio.Mmio(packed struct(u32) { - /// Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. - EVENTS_PHYEND: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [144]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between event READY and task START - READY_START: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event END and task DISABLE - END_DISABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event DISABLED and task TXEN - DISABLED_TXEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event DISABLED and task RXEN - DISABLED_RXEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event ADDRESS and task RSSISTART - ADDRESS_RSSISTART: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event END and task START - END_START: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event ADDRESS and task BCSTART - ADDRESS_BCSTART: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - reserved8: u1, - /// Shortcut between event DISABLED and task RSSISTOP - DISABLED_RSSISTOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - reserved11: u2, - /// Shortcut between event RXREADY and task CCASTART - RXREADY_CCASTART: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event CCAIDLE and task TXEN - CCAIDLE_TXEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event CCABUSY and task DISABLE - CCABUSY_DISABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event FRAMESTART and task BCSTART - FRAMESTART_BCSTART: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event READY and task EDSTART - READY_EDSTART: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event EDEND and task DISABLE - EDEND_DISABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event CCAIDLE and task STOP - CCAIDLE_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event TXREADY and task START - TXREADY_START: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event RXREADY and task START - RXREADY_START: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event PHYEND and task DISABLE - PHYEND_DISABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event PHYEND and task START - PHYEND_START: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u10, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ADDRESS - ADDRESS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event PAYLOAD - PAYLOAD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event DISABLED - DISABLED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event DEVMATCH - DEVMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event DEVMISS - DEVMISS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event RSSIEND - RSSIEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u2, - /// Write '1' to enable interrupt for event BCMATCH - BCMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved12: u1, - /// Write '1' to enable interrupt for event CRCOK - CRCOK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CRCERROR - CRCERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event FRAMESTART - FRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event EDEND - EDEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event EDSTOPPED - EDSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CCAIDLE - CCAIDLE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CCABUSY - CCABUSY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CCASTOPPED - CCASTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event RATEBOOST - RATEBOOST: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TXREADY - TXREADY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event RXREADY - RXREADY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event MHRMATCH - MHRMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved26: u2, - /// Write '1' to enable interrupt for event SYNC - SYNC: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event PHYEND - PHYEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ADDRESS - ADDRESS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event PAYLOAD - PAYLOAD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event DISABLED - DISABLED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event DEVMATCH - DEVMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event DEVMISS - DEVMISS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event RSSIEND - RSSIEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u2, - /// Write '1' to disable interrupt for event BCMATCH - BCMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved12: u1, - /// Write '1' to disable interrupt for event CRCOK - CRCOK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CRCERROR - CRCERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event FRAMESTART - FRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event EDEND - EDEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event EDSTOPPED - EDSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CCAIDLE - CCAIDLE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CCABUSY - CCABUSY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CCASTOPPED - CCASTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event RATEBOOST - RATEBOOST: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TXREADY - TXREADY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event RXREADY - RXREADY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event MHRMATCH - MHRMATCH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved26: u2, - /// Write '1' to disable interrupt for event SYNC - SYNC: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event PHYEND - PHYEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - reserved1024: [244]u8, - /// CRC status - CRCSTATUS: mmio.Mmio(packed struct(u32) { - /// CRC status of packet received - CRCSTATUS: packed union { - raw: u1, - value: enum(u1) { - /// Packet received with CRC error - CRCError = 0x0, - /// Packet received with CRC ok - CRCOk = 0x1, - }, - }, - padding: u31, - }), - reserved1032: [4]u8, - /// Received address - RXMATCH: mmio.Mmio(packed struct(u32) { - /// Received address - RXMATCH: u3, - padding: u29, - }), - /// CRC field of previously received packet - RXCRC: mmio.Mmio(packed struct(u32) { - /// CRC field of previously received packet - RXCRC: u24, - padding: u8, - }), - /// Device address match index - DAI: mmio.Mmio(packed struct(u32) { - /// Device address match index - DAI: u3, - padding: u29, - }), - /// Payload status - PDUSTAT: mmio.Mmio(packed struct(u32) { - /// Status on payload length vs. PCNF1.MAXLEN - PDUSTAT: packed union { - raw: u1, - value: enum(u1) { - /// Payload less than PCNF1.MAXLEN - LessThan = 0x0, - /// Payload greater than PCNF1.MAXLEN - GreaterThan = 0x1, - }, - }, - /// Status on what rate packet is received with in Long Range - CISTAT: packed union { - raw: u2, - value: enum(u2) { - /// Frame is received at 125kbps - LR125kbit = 0x0, - /// Frame is received at 500kbps - LR500kbit = 0x1, - _, - }, - }, - padding: u29, - }), - reserved1284: [236]u8, - /// Packet pointer - PACKETPTR: mmio.Mmio(packed struct(u32) { - /// Packet pointer - PACKETPTR: u32, - }), - /// Frequency - FREQUENCY: mmio.Mmio(packed struct(u32) { - /// Radio channel frequency - FREQUENCY: u7, - reserved8: u1, - /// Channel map selection. - MAP: packed union { - raw: u1, - value: enum(u1) { - /// Channel map between 2400 MHZ .. 2500 MHz - Default = 0x0, - /// Channel map between 2360 MHZ .. 2460 MHz - Low = 0x1, - }, - }, - padding: u23, - }), - /// Output power - TXPOWER: mmio.Mmio(packed struct(u32) { - /// RADIO output power - TXPOWER: packed union { - raw: u8, - value: enum(u8) { - /// +8 dBm - Pos8dBm = 0x8, - /// +7 dBm - Pos7dBm = 0x7, - /// +6 dBm - Pos6dBm = 0x6, - /// +5 dBm - Pos5dBm = 0x5, - /// +4 dBm - Pos4dBm = 0x4, - /// +3 dBm - Pos3dBm = 0x3, - /// +2 dBm - Pos2dBm = 0x2, - /// 0 dBm - @"0dBm" = 0x0, - /// -4 dBm - Neg4dBm = 0xfc, - /// -8 dBm - Neg8dBm = 0xf8, - /// -12 dBm - Neg12dBm = 0xf4, - /// -16 dBm - Neg16dBm = 0xf0, - /// -20 dBm - Neg20dBm = 0xec, - /// Deprecated enumerator - -40 dBm - Neg30dBm = 0xe2, - /// -40 dBm - Neg40dBm = 0xd8, - _, - }, - }, - padding: u24, - }), - /// Data rate and modulation - MODE: mmio.Mmio(packed struct(u32) { - /// Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. - MODE: packed union { - raw: u4, - value: enum(u4) { - /// 1 Mbit/s Nordic proprietary radio mode - Nrf_1Mbit = 0x0, - /// 2 Mbit/s Nordic proprietary radio mode - Nrf_2Mbit = 0x1, - /// 1 Mbit/s BLE - Ble_1Mbit = 0x3, - /// 2 Mbit/s BLE - Ble_2Mbit = 0x4, - /// Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX - Ble_LR125Kbit = 0x5, - /// Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX - Ble_LR500Kbit = 0x6, - /// IEEE 802.15.4-2006 250 kbit/s - Ieee802154_250Kbit = 0xf, - _, - }, - }, - padding: u28, - }), - /// Packet configuration register 0 - PCNF0: mmio.Mmio(packed struct(u32) { - /// Length on air of LENGTH field in number of bits. - LFLEN: u4, - reserved8: u4, - /// Length on air of S0 field in number of bytes. - S0LEN: u1, - reserved16: u7, - /// Length on air of S1 field in number of bits. - S1LEN: u4, - /// Include or exclude S1 field in RAM - S1INCL: packed union { - raw: u1, - value: enum(u1) { - /// Include S1 field in RAM only if S1LEN > 0 - Automatic = 0x0, - /// Always include S1 field in RAM independent of S1LEN - Include = 0x1, - }, - }, - reserved22: u1, - /// Length of code indicator - long range - CILEN: u2, - /// Length of preamble on air. Decision point: TASKS_START task - PLEN: packed union { - raw: u2, - value: enum(u2) { - /// 8-bit preamble - @"8bit" = 0x0, - /// 16-bit preamble - @"16bit" = 0x1, - /// 32-bit zero preamble - used for IEEE 802.15.4 - @"32bitZero" = 0x2, - /// Preamble - used for BLE long range - LongRange = 0x3, - }, - }, - /// Indicates if LENGTH field contains CRC or not - CRCINC: packed union { - raw: u1, - value: enum(u1) { - /// LENGTH does not contain CRC - Exclude = 0x0, - /// LENGTH includes CRC - Include = 0x1, - }, - }, - reserved29: u2, - /// Length of TERM field in Long Range operation - TERMLEN: u2, - padding: u1, - }), - /// Packet configuration register 1 - PCNF1: mmio.Mmio(packed struct(u32) { - /// Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. - MAXLEN: u8, - /// Static length in number of bytes - STATLEN: u8, - /// Base address length in number of bytes - BALEN: u3, - reserved24: u5, - /// On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. - ENDIAN: packed union { - raw: u1, - value: enum(u1) { - /// Least significant bit on air first - Little = 0x0, - /// Most significant bit on air first - Big = 0x1, - }, - }, - /// Enable or disable packet whitening - WHITEEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u6, - }), - /// Base address 0 - BASE0: mmio.Mmio(packed struct(u32) { - /// Base address 0 - BASE0: u32, - }), - /// Base address 1 - BASE1: mmio.Mmio(packed struct(u32) { - /// Base address 1 - BASE1: u32, - }), - /// Prefixes bytes for logical addresses 0-3 - PREFIX0: mmio.Mmio(packed struct(u32) { - /// Address prefix 0. - AP0: u8, - /// Address prefix 1. - AP1: u8, - /// Address prefix 2. - AP2: u8, - /// Address prefix 3. - AP3: u8, - }), - /// Prefixes bytes for logical addresses 4-7 - PREFIX1: mmio.Mmio(packed struct(u32) { - /// Address prefix 4. - AP4: u8, - /// Address prefix 5. - AP5: u8, - /// Address prefix 6. - AP6: u8, - /// Address prefix 7. - AP7: u8, - }), - /// Transmit address select - TXADDRESS: mmio.Mmio(packed struct(u32) { - /// Transmit address select - TXADDRESS: u3, - padding: u29, - }), - /// Receive address select - RXADDRESSES: mmio.Mmio(packed struct(u32) { - /// Enable or disable reception on logical address 0. - ADDR0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 1. - ADDR1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 2. - ADDR2: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 3. - ADDR3: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 4. - ADDR4: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 5. - ADDR5: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 6. - ADDR6: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable reception on logical address 7. - ADDR7: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u24, - }), - /// CRC configuration - CRCCNF: mmio.Mmio(packed struct(u32) { - /// CRC length in number of bytes. - LEN: packed union { - raw: u2, - value: enum(u2) { - /// CRC length is zero and CRC calculation is disabled - Disabled = 0x0, - /// CRC length is one byte and CRC calculation is enabled - One = 0x1, - /// CRC length is two bytes and CRC calculation is enabled - Two = 0x2, - /// CRC length is three bytes and CRC calculation is enabled - Three = 0x3, - }, - }, - reserved8: u6, - /// Include or exclude packet address field out of CRC calculation. - SKIPADDR: packed union { - raw: u2, - value: enum(u2) { - /// CRC calculation includes address field - Include = 0x0, - /// CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. - Skip = 0x1, - /// CRC calculation as per 802.15.4 standard. Starting at first byte after length field. - Ieee802154 = 0x2, - _, - }, - }, - padding: u22, - }), - /// CRC polynomial - CRCPOLY: mmio.Mmio(packed struct(u32) { - /// CRC polynomial - CRCPOLY: u24, - padding: u8, - }), - /// CRC initial value - CRCINIT: mmio.Mmio(packed struct(u32) { - /// CRC initial value - CRCINIT: u24, - padding: u8, - }), - reserved1348: [4]u8, - /// Interframe spacing in us - TIFS: mmio.Mmio(packed struct(u32) { - /// Interframe spacing in us - TIFS: u10, - padding: u22, - }), - /// RSSI sample - RSSISAMPLE: mmio.Mmio(packed struct(u32) { - /// RSSI sample - RSSISAMPLE: u7, - padding: u25, - }), - reserved1360: [4]u8, - /// Current radio state - STATE: mmio.Mmio(packed struct(u32) { - /// Current radio state - STATE: packed union { - raw: u4, - value: enum(u4) { - /// RADIO is in the Disabled state - Disabled = 0x0, - /// RADIO is in the RXRU state - RxRu = 0x1, - /// RADIO is in the RXIDLE state - RxIdle = 0x2, - /// RADIO is in the RX state - Rx = 0x3, - /// RADIO is in the RXDISABLED state - RxDisable = 0x4, - /// RADIO is in the TXRU state - TxRu = 0x9, - /// RADIO is in the TXIDLE state - TxIdle = 0xa, - /// RADIO is in the TX state - Tx = 0xb, - /// RADIO is in the TXDISABLED state - TxDisable = 0xc, - _, - }, - }, - padding: u28, - }), - /// Data whitening initial value - DATAWHITEIV: mmio.Mmio(packed struct(u32) { - /// Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. - DATAWHITEIV: u7, - padding: u25, - }), - reserved1376: [8]u8, - /// Bit counter compare - BCC: mmio.Mmio(packed struct(u32) { - /// Bit counter compare - BCC: u32, - }), - reserved1536: [156]u8, - /// Description collection: Device address base segment n - DAB: [8]mmio.Mmio(packed struct(u32) { - /// Device address base segment n - DAB: u32, - }), - /// Description collection: Device address prefix n - DAP: [8]mmio.Mmio(packed struct(u32) { - /// Device address prefix n - DAP: u16, - padding: u16, - }), - /// Device address match configuration - DACNF: mmio.Mmio(packed struct(u32) { - /// Enable or disable device address matching using device address 0 - ENA0: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 1 - ENA1: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 2 - ENA2: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 3 - ENA3: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 4 - ENA4: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 5 - ENA5: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 6 - ENA6: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable device address matching using device address 7 - ENA7: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// TxAdd for device address 0 - TXADD0: u1, - /// TxAdd for device address 1 - TXADD1: u1, - /// TxAdd for device address 2 - TXADD2: u1, - /// TxAdd for device address 3 - TXADD3: u1, - /// TxAdd for device address 4 - TXADD4: u1, - /// TxAdd for device address 5 - TXADD5: u1, - /// TxAdd for device address 6 - TXADD6: u1, - /// TxAdd for device address 7 - TXADD7: u1, - padding: u16, - }), - /// Search pattern configuration - MHRMATCHCONF: mmio.Mmio(packed struct(u32) { - /// Search pattern configuration - MHRMATCHCONF: u32, - }), - /// Pattern mask - MHRMATCHMAS: mmio.Mmio(packed struct(u32) { - /// Pattern mask - MHRMATCHMAS: u32, - }), - reserved1616: [4]u8, - /// Radio mode configuration register 0 - MODECNF0: mmio.Mmio(packed struct(u32) { - /// Radio ramp-up time - RU: packed union { - raw: u1, - value: enum(u1) { - /// Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 - Default = 0x0, - /// Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information - Fast = 0x1, - }, - }, - reserved8: u7, - /// Default TX value - DTX: packed union { - raw: u2, - value: enum(u2) { - /// Transmit '1' - B1 = 0x0, - /// Transmit '0' - B0 = 0x1, - /// Transmit center frequency - Center = 0x2, - _, - }, - }, - padding: u22, - }), - reserved1632: [12]u8, - /// IEEE 802.15.4 start of frame delimiter - SFD: mmio.Mmio(packed struct(u32) { - /// IEEE 802.15.4 start of frame delimiter - SFD: u8, - padding: u24, - }), - /// IEEE 802.15.4 energy detect loop count - EDCNT: mmio.Mmio(packed struct(u32) { - /// IEEE 802.15.4 energy detect loop count - EDCNT: u21, - padding: u11, - }), - /// IEEE 802.15.4 energy detect level - EDSAMPLE: mmio.Mmio(packed struct(u32) { - /// IEEE 802.15.4 energy detect level - EDLVL: u8, - padding: u24, - }), - /// IEEE 802.15.4 clear channel assessment control - CCACTRL: mmio.Mmio(packed struct(u32) { - /// CCA mode of operation - CCAMODE: packed union { - raw: u3, - value: enum(u3) { - /// Energy above threshold - EdMode = 0x0, - /// Carrier seen - CarrierMode = 0x1, - /// Energy above threshold AND carrier seen - CarrierAndEdMode = 0x2, - /// Energy above threshold OR carrier seen - CarrierOrEdMode = 0x3, - /// Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. - EdModeTest1 = 0x4, - _, - }, - }, - reserved8: u5, - /// CCA energy busy threshold. Used in all the CCA modes except CarrierMode. - CCAEDTHRES: u8, - /// CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. - CCACORRTHRES: u8, - /// Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. - CCACORRCNT: u8, - }), - reserved4092: [2444]u8, - /// Peripheral power control - POWER: mmio.Mmio(packed struct(u32) { - /// Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. - POWER: packed union { - raw: u1, - value: enum(u1) { - /// Peripheral is powered off - Disabled = 0x0, - /// Peripheral is powered on - Enabled = 0x1, - }, - }, - padding: u31, - }), - }; - - /// Universal Asynchronous Receiver/Transmitter - pub const UART0 = extern struct { - /// Start UART receiver - TASKS_STARTRX: mmio.Mmio(packed struct(u32) { - /// Start UART receiver - TASKS_STARTRX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop UART receiver - TASKS_STOPRX: mmio.Mmio(packed struct(u32) { - /// Stop UART receiver - TASKS_STOPRX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start UART transmitter - TASKS_STARTTX: mmio.Mmio(packed struct(u32) { - /// Start UART transmitter - TASKS_STARTTX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop UART transmitter - TASKS_STOPTX: mmio.Mmio(packed struct(u32) { - /// Stop UART transmitter - TASKS_STOPTX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved28: [12]u8, - /// Suspend UART - TASKS_SUSPEND: mmio.Mmio(packed struct(u32) { - /// Suspend UART - TASKS_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [224]u8, - /// CTS is activated (set low). Clear To Send. - EVENTS_CTS: mmio.Mmio(packed struct(u32) { - /// CTS is activated (set low). Clear To Send. - EVENTS_CTS: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// CTS is deactivated (set high). Not Clear To Send. - EVENTS_NCTS: mmio.Mmio(packed struct(u32) { - /// CTS is deactivated (set high). Not Clear To Send. - EVENTS_NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Data received in RXD - EVENTS_RXDRDY: mmio.Mmio(packed struct(u32) { - /// Data received in RXD - EVENTS_RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved284: [16]u8, - /// Data sent from TXD - EVENTS_TXDRDY: mmio.Mmio(packed struct(u32) { - /// Data sent from TXD - EVENTS_TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved292: [4]u8, - /// Error detected - EVENTS_ERROR: mmio.Mmio(packed struct(u32) { - /// Error detected - EVENTS_ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved324: [28]u8, - /// Receiver timeout - EVENTS_RXTO: mmio.Mmio(packed struct(u32) { - /// Receiver timeout - EVENTS_RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [184]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Shortcut between event CTS and task STARTRX - CTS_STARTRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event NCTS and task STOPRX - NCTS_STOPRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event CTS - CTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event NCTS - NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event RXDRDY - RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u4, - /// Write '1' to enable interrupt for event TXDRDY - TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u1, - /// Write '1' to enable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved17: u7, - /// Write '1' to enable interrupt for event RXTO - RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u14, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event CTS - CTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event NCTS - NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event RXDRDY - RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u4, - /// Write '1' to disable interrupt for event TXDRDY - TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u1, - /// Write '1' to disable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved17: u7, - /// Write '1' to disable interrupt for event RXTO - RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u14, - }), - reserved1152: [372]u8, - /// Error source - ERRORSRC: mmio.Mmio(packed struct(u32) { - /// Overrun error - OVERRUN: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Parity error - PARITY: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Framing error occurred - FRAMING: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Break condition - BREAK: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - padding: u28, - }), - reserved1280: [124]u8, - /// Enable UART - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable UART - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable UART - Disabled = 0x0, - /// Enable UART - Enabled = 0x4, - _, - }, - }, - padding: u28, - }), - reserved1304: [20]u8, - /// RXD register - RXD: mmio.Mmio(packed struct(u32) { - /// RX data received in previous transfers, double buffered - RXD: u8, - padding: u24, - }), - /// TXD register - TXD: mmio.Mmio(packed struct(u32) { - /// TX data to be transferred - TXD: u8, - padding: u24, - }), - reserved1316: [4]u8, - /// Baud rate. Accuracy depends on the HFCLK source selected. - BAUDRATE: mmio.Mmio(packed struct(u32) { - /// Baud rate - BAUDRATE: packed union { - raw: u32, - value: enum(u32) { - /// 1200 baud (actual rate: 1205) - Baud1200 = 0x4f000, - /// 2400 baud (actual rate: 2396) - Baud2400 = 0x9d000, - /// 4800 baud (actual rate: 4808) - Baud4800 = 0x13b000, - /// 9600 baud (actual rate: 9598) - Baud9600 = 0x275000, - /// 14400 baud (actual rate: 14414) - Baud14400 = 0x3b0000, - /// 19200 baud (actual rate: 19208) - Baud19200 = 0x4ea000, - /// 28800 baud (actual rate: 28829) - Baud28800 = 0x75f000, - /// 31250 baud - Baud31250 = 0x800000, - /// 38400 baud (actual rate: 38462) - Baud38400 = 0x9d5000, - /// 56000 baud (actual rate: 55944) - Baud56000 = 0xe50000, - /// 57600 baud (actual rate: 57762) - Baud57600 = 0xebf000, - /// 76800 baud (actual rate: 76923) - Baud76800 = 0x13a9000, - /// 115200 baud (actual rate: 115942) - Baud115200 = 0x1d7e000, - /// 230400 baud (actual rate: 231884) - Baud230400 = 0x3afb000, - /// 250000 baud - Baud250000 = 0x4000000, - /// 460800 baud (actual rate: 470588) - Baud460800 = 0x75f7000, - /// 921600 baud (actual rate: 941176) - Baud921600 = 0xebed000, - /// 1Mega baud - Baud1M = 0x10000000, - _, - }, - }, - }), - reserved1388: [68]u8, - /// Configuration of parity and hardware flow control - CONFIG: mmio.Mmio(packed struct(u32) { - /// Hardware flow control - HWFC: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Parity - PARITY: packed union { - raw: u3, - value: enum(u3) { - /// Exclude parity bit - Excluded = 0x0, - /// Include parity bit - Included = 0x7, - _, - }, - }, - /// Stop bits - STOP: packed union { - raw: u1, - value: enum(u1) { - /// One stop bit - One = 0x0, - /// Two stop bits - Two = 0x1, - }, - }, - padding: u27, - }), - }; - - /// UART with EasyDMA 0 - pub const UARTE0 = extern struct { - /// Start UART receiver - TASKS_STARTRX: mmio.Mmio(packed struct(u32) { - /// Start UART receiver - TASKS_STARTRX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop UART receiver - TASKS_STOPRX: mmio.Mmio(packed struct(u32) { - /// Stop UART receiver - TASKS_STOPRX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start UART transmitter - TASKS_STARTTX: mmio.Mmio(packed struct(u32) { - /// Start UART transmitter - TASKS_STARTTX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop UART transmitter - TASKS_STOPTX: mmio.Mmio(packed struct(u32) { - /// Stop UART transmitter - TASKS_STOPTX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved44: [28]u8, - /// Flush RX FIFO into RX buffer - TASKS_FLUSHRX: mmio.Mmio(packed struct(u32) { - /// Flush RX FIFO into RX buffer - TASKS_FLUSHRX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [208]u8, - /// CTS is activated (set low). Clear To Send. - EVENTS_CTS: mmio.Mmio(packed struct(u32) { - /// CTS is activated (set low). Clear To Send. - EVENTS_CTS: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// CTS is deactivated (set high). Not Clear To Send. - EVENTS_NCTS: mmio.Mmio(packed struct(u32) { - /// CTS is deactivated (set high). Not Clear To Send. - EVENTS_NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Data received in RXD (but potentially not yet transferred to Data RAM) - EVENTS_RXDRDY: mmio.Mmio(packed struct(u32) { - /// Data received in RXD (but potentially not yet transferred to Data RAM) - EVENTS_RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved272: [4]u8, - /// Receive buffer is filled up - EVENTS_ENDRX: mmio.Mmio(packed struct(u32) { - /// Receive buffer is filled up - EVENTS_ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved284: [8]u8, - /// Data sent from TXD - EVENTS_TXDRDY: mmio.Mmio(packed struct(u32) { - /// Data sent from TXD - EVENTS_TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Last TX byte transmitted - EVENTS_ENDTX: mmio.Mmio(packed struct(u32) { - /// Last TX byte transmitted - EVENTS_ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Error detected - EVENTS_ERROR: mmio.Mmio(packed struct(u32) { - /// Error detected - EVENTS_ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved324: [28]u8, - /// Receiver timeout - EVENTS_RXTO: mmio.Mmio(packed struct(u32) { - /// Receiver timeout - EVENTS_RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved332: [4]u8, - /// UART receiver has started - EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) { - /// UART receiver has started - EVENTS_RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// UART transmitter has started - EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) { - /// UART transmitter has started - EVENTS_TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved344: [4]u8, - /// Transmitter stopped - EVENTS_TXSTOPPED: mmio.Mmio(packed struct(u32) { - /// Transmitter stopped - EVENTS_TXSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [164]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Shortcut between event ENDRX and task STARTRX - ENDRX_STARTRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event ENDRX and task STOPRX - ENDRX_STOPRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u25, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for event CTS - CTS: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event NCTS - NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event RXDRDY - RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved4: u1, - /// Enable or disable interrupt for event ENDRX - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved7: u2, - /// Enable or disable interrupt for event TXDRDY - TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDTX - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved17: u7, - /// Enable or disable interrupt for event RXTO - RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved19: u1, - /// Enable or disable interrupt for event RXSTARTED - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TXSTARTED - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved22: u1, - /// Enable or disable interrupt for event TXSTOPPED - TXSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u9, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event CTS - CTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event NCTS - NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event RXDRDY - RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u1, - /// Write '1' to enable interrupt for event ENDRX - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u2, - /// Write '1' to enable interrupt for event TXDRDY - TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDTX - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved17: u7, - /// Write '1' to enable interrupt for event RXTO - RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u1, - /// Write '1' to enable interrupt for event RXSTARTED - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TXSTARTED - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved22: u1, - /// Write '1' to enable interrupt for event TXSTOPPED - TXSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u9, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event CTS - CTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event NCTS - NCTS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event RXDRDY - RXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u1, - /// Write '1' to disable interrupt for event ENDRX - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u2, - /// Write '1' to disable interrupt for event TXDRDY - TXDRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDTX - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved17: u7, - /// Write '1' to disable interrupt for event RXTO - RXTO: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u1, - /// Write '1' to disable interrupt for event RXSTARTED - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TXSTARTED - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved22: u1, - /// Write '1' to disable interrupt for event TXSTOPPED - TXSTOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u9, - }), - reserved1152: [372]u8, - /// Error source Note : this register is read / write one to clear. - ERRORSRC: mmio.Mmio(packed struct(u32) { - /// Overrun error - OVERRUN: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Parity error - PARITY: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Framing error occurred - FRAMING: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// Break condition - BREAK: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - padding: u28, - }), - reserved1280: [124]u8, - /// Enable UART - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable UARTE - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable UARTE - Disabled = 0x0, - /// Enable UARTE - Enabled = 0x8, - _, - }, - }, - padding: u28, - }), - reserved1316: [32]u8, - /// Baud rate. Accuracy depends on the HFCLK source selected. - BAUDRATE: mmio.Mmio(packed struct(u32) { - /// Baud rate - BAUDRATE: packed union { - raw: u32, - value: enum(u32) { - /// 1200 baud (actual rate: 1205) - Baud1200 = 0x4f000, - /// 2400 baud (actual rate: 2396) - Baud2400 = 0x9d000, - /// 4800 baud (actual rate: 4808) - Baud4800 = 0x13b000, - /// 9600 baud (actual rate: 9598) - Baud9600 = 0x275000, - /// 14400 baud (actual rate: 14401) - Baud14400 = 0x3af000, - /// 19200 baud (actual rate: 19208) - Baud19200 = 0x4ea000, - /// 28800 baud (actual rate: 28777) - Baud28800 = 0x75c000, - /// 31250 baud - Baud31250 = 0x800000, - /// 38400 baud (actual rate: 38369) - Baud38400 = 0x9d0000, - /// 56000 baud (actual rate: 55944) - Baud56000 = 0xe50000, - /// 57600 baud (actual rate: 57554) - Baud57600 = 0xeb0000, - /// 76800 baud (actual rate: 76923) - Baud76800 = 0x13a9000, - /// 115200 baud (actual rate: 115108) - Baud115200 = 0x1d60000, - /// 230400 baud (actual rate: 231884) - Baud230400 = 0x3b00000, - /// 250000 baud - Baud250000 = 0x4000000, - /// 460800 baud (actual rate: 457143) - Baud460800 = 0x7400000, - /// 921600 baud (actual rate: 941176) - Baud921600 = 0xf000000, - /// 1Mega baud - Baud1M = 0x10000000, - _, - }, - }, - }), - reserved1388: [68]u8, - /// Configuration of parity and hardware flow control - CONFIG: mmio.Mmio(packed struct(u32) { - /// Hardware flow control - HWFC: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Parity - PARITY: packed union { - raw: u3, - value: enum(u3) { - /// Exclude parity bit - Excluded = 0x0, - /// Include even parity bit - Included = 0x7, - _, - }, - }, - /// Stop bits - STOP: packed union { - raw: u1, - value: enum(u1) { - /// One stop bit - One = 0x0, - /// Two stop bits - Two = 0x1, - }, - }, - padding: u27, - }), - }; - - /// Serial Peripheral Interface 0 - pub const SPI0 = extern struct { - reserved264: [264]u8, - /// TXD byte sent and RXD byte received - EVENTS_READY: mmio.Mmio(packed struct(u32) { - /// TXD byte sent and RXD byte received - EVENTS_READY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved772: [504]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Write '1' to enable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Write '1' to disable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - reserved1280: [500]u8, - /// Enable SPI - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable SPI - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable SPI - Disabled = 0x0, - /// Enable SPI - Enabled = 0x1, - _, - }, - }, - padding: u28, - }), - reserved1304: [20]u8, - /// RXD register - RXD: mmio.Mmio(packed struct(u32) { - /// RX data received. Double buffered - RXD: u8, - padding: u24, - }), - /// TXD register - TXD: mmio.Mmio(packed struct(u32) { - /// TX data to send. Double buffered - TXD: u8, - padding: u24, - }), - reserved1316: [4]u8, - /// SPI frequency. Accuracy depends on the HFCLK source selected. - FREQUENCY: mmio.Mmio(packed struct(u32) { - /// SPI master data rate - FREQUENCY: packed union { - raw: u32, - value: enum(u32) { - /// 125 kbps - K125 = 0x2000000, - /// 250 kbps - K250 = 0x4000000, - /// 500 kbps - K500 = 0x8000000, - /// 1 Mbps - M1 = 0x10000000, - /// 2 Mbps - M2 = 0x20000000, - /// 4 Mbps - M4 = 0x40000000, - /// 8 Mbps - M8 = 0x80000000, - _, - }, - }, - }), - reserved1364: [44]u8, - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Bit order - ORDER: packed union { - raw: u1, - value: enum(u1) { - /// Most significant bit shifted out first - MsbFirst = 0x0, - /// Least significant bit shifted out first - LsbFirst = 0x1, - }, - }, - /// Serial clock (SCK) phase - CPHA: packed union { - raw: u1, - value: enum(u1) { - /// Sample on leading edge of clock, shift serial data on trailing edge - Leading = 0x0, - /// Sample on trailing edge of clock, shift serial data on leading edge - Trailing = 0x1, - }, - }, - /// Serial clock (SCK) polarity - CPOL: packed union { - raw: u1, - value: enum(u1) { - /// Active high - ActiveHigh = 0x0, - /// Active low - ActiveLow = 0x1, - }, - }, - padding: u29, - }), - }; - - /// Serial Peripheral Interface Master with EasyDMA 0 - pub const SPIM0 = extern struct { - reserved16: [16]u8, - /// Start SPI transaction - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Start SPI transaction - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop SPI transaction - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop SPI transaction - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved28: [4]u8, - /// Suspend SPI transaction - TASKS_SUSPEND: mmio.Mmio(packed struct(u32) { - /// Suspend SPI transaction - TASKS_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Resume SPI transaction - TASKS_RESUME: mmio.Mmio(packed struct(u32) { - /// Resume SPI transaction - TASKS_RESUME: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved260: [224]u8, - /// SPI transaction has stopped - EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { - /// SPI transaction has stopped - EVENTS_STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved272: [8]u8, - /// End of RXD buffer reached - EVENTS_ENDRX: mmio.Mmio(packed struct(u32) { - /// End of RXD buffer reached - EVENTS_ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved280: [4]u8, - /// End of RXD buffer and TXD buffer reached - EVENTS_END: mmio.Mmio(packed struct(u32) { - /// End of RXD buffer and TXD buffer reached - EVENTS_END: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved288: [4]u8, - /// End of TXD buffer reached - EVENTS_ENDTX: mmio.Mmio(packed struct(u32) { - /// End of TXD buffer reached - EVENTS_ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved332: [40]u8, - /// Transaction started - EVENTS_STARTED: mmio.Mmio(packed struct(u32) { - /// Transaction started - EVENTS_STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [176]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - reserved17: u17, - /// Shortcut between event END and task START - END_START: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u14, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to enable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u2, - /// Write '1' to enable interrupt for event ENDRX - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved6: u1, - /// Write '1' to enable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved8: u1, - /// Write '1' to enable interrupt for event ENDTX - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u10, - /// Write '1' to enable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u2, - /// Write '1' to disable interrupt for event ENDRX - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved6: u1, - /// Write '1' to disable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved8: u1, - /// Write '1' to disable interrupt for event ENDTX - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u10, - /// Write '1' to disable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - reserved1024: [244]u8, - /// Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. - STALLSTAT: mmio.Mmio(packed struct(u32) { - /// Stall status for EasyDMA RAM reads - TX: packed union { - raw: u1, - value: enum(u1) { - /// No stall - NOSTALL = 0x0, - /// A stall has occurred - STALL = 0x1, - }, - }, - /// Stall status for EasyDMA RAM writes - RX: packed union { - raw: u1, - value: enum(u1) { - /// No stall - NOSTALL = 0x0, - /// A stall has occurred - STALL = 0x1, - }, - }, - padding: u30, - }), - reserved1280: [252]u8, - /// Enable SPIM - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable SPIM - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable SPIM - Disabled = 0x0, - /// Enable SPIM - Enabled = 0x7, - _, - }, - }, - padding: u28, - }), - reserved1316: [32]u8, - /// SPI frequency. Accuracy depends on the HFCLK source selected. - FREQUENCY: mmio.Mmio(packed struct(u32) { - /// SPI master data rate - FREQUENCY: packed union { - raw: u32, - value: enum(u32) { - /// 125 kbps - K125 = 0x2000000, - /// 250 kbps - K250 = 0x4000000, - /// 500 kbps - K500 = 0x8000000, - /// 1 Mbps - M1 = 0x10000000, - /// 2 Mbps - M2 = 0x20000000, - /// 4 Mbps - M4 = 0x40000000, - /// 8 Mbps - M8 = 0x80000000, - /// 16 Mbps - M16 = 0xa000000, - /// 32 Mbps - M32 = 0x14000000, - _, - }, - }, - }), - reserved1364: [44]u8, - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Bit order - ORDER: packed union { - raw: u1, - value: enum(u1) { - /// Most significant bit shifted out first - MsbFirst = 0x0, - /// Least significant bit shifted out first - LsbFirst = 0x1, - }, - }, - /// Serial clock (SCK) phase - CPHA: packed union { - raw: u1, - value: enum(u1) { - /// Sample on leading edge of clock, shift serial data on trailing edge - Leading = 0x0, - /// Sample on trailing edge of clock, shift serial data on leading edge - Trailing = 0x1, - }, - }, - /// Serial clock (SCK) polarity - CPOL: packed union { - raw: u1, - value: enum(u1) { - /// Active high - ActiveHigh = 0x0, - /// Active low - ActiveLow = 0x1, - }, - }, - padding: u29, - }), - reserved1384: [16]u8, - /// Polarity of CSN output - CSNPOL: mmio.Mmio(packed struct(u32) { - /// Polarity of CSN output - CSNPOL: packed union { - raw: u1, - value: enum(u1) { - /// Active low (idle state high) - LOW = 0x0, - /// Active high (idle state low) - HIGH = 0x1, - }, - }, - padding: u31, - }), - /// Pin select for DCX signal - PSELDCX: mmio.Mmio(packed struct(u32) { - /// Pin number - PIN: u5, - /// Port number - PORT: u1, - reserved31: u25, - /// Connection - CONNECT: packed union { - raw: u1, - value: enum(u1) { - /// Disconnect - Disconnected = 0x1, - /// Connect - Connected = 0x0, - }, - }, - }), - /// DCX configuration - DCXCNT: mmio.Mmio(packed struct(u32) { - /// This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. - DCXCNT: u4, - padding: u28, - }), - reserved1472: [76]u8, - /// Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT - ORC: mmio.Mmio(packed struct(u32) { - /// Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. - ORC: u8, - padding: u24, - }), - }; - - /// SPI Slave 0 - pub const SPIS0 = extern struct { - reserved36: [36]u8, - /// Acquire SPI semaphore - TASKS_ACQUIRE: mmio.Mmio(packed struct(u32) { - /// Acquire SPI semaphore - TASKS_ACQUIRE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Release SPI semaphore, enabling the SPI slave to acquire it - TASKS_RELEASE: mmio.Mmio(packed struct(u32) { - /// Release SPI semaphore, enabling the SPI slave to acquire it - TASKS_RELEASE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved260: [216]u8, - /// Granted transaction completed - EVENTS_END: mmio.Mmio(packed struct(u32) { - /// Granted transaction completed - EVENTS_END: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved272: [8]u8, - /// End of RXD buffer reached - EVENTS_ENDRX: mmio.Mmio(packed struct(u32) { - /// End of RXD buffer reached - EVENTS_ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved296: [20]u8, - /// Semaphore acquired - EVENTS_ACQUIRED: mmio.Mmio(packed struct(u32) { - /// Semaphore acquired - EVENTS_ACQUIRED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [212]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Shortcut between event END and task ACQUIRE - END_ACQUIRE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u29, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to enable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u2, - /// Write '1' to enable interrupt for event ENDRX - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u5, - /// Write '1' to enable interrupt for event ACQUIRED - ACQUIRED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u21, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to disable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved4: u2, - /// Write '1' to disable interrupt for event ENDRX - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u5, - /// Write '1' to disable interrupt for event ACQUIRED - ACQUIRED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u21, - }), - reserved1024: [244]u8, - /// Semaphore status register - SEMSTAT: mmio.Mmio(packed struct(u32) { - /// Semaphore status - SEMSTAT: packed union { - raw: u2, - value: enum(u2) { - /// Semaphore is free - Free = 0x0, - /// Semaphore is assigned to CPU - CPU = 0x1, - /// Semaphore is assigned to SPI slave - SPIS = 0x2, - /// Semaphore is assigned to SPI but a handover to the CPU is pending - CPUPending = 0x3, - }, - }, - padding: u30, - }), - reserved1088: [60]u8, - /// Status from last transaction - STATUS: mmio.Mmio(packed struct(u32) { - /// TX buffer over-read detected, and prevented - OVERREAD: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// RX buffer overflow detected, and prevented - OVERFLOW: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - padding: u30, - }), - reserved1280: [188]u8, - /// Enable SPI slave - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable SPI slave - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable SPI slave - Disabled = 0x0, - /// Enable SPI slave - Enabled = 0x2, - _, - }, - }, - padding: u28, - }), - reserved1364: [80]u8, - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Bit order - ORDER: packed union { - raw: u1, - value: enum(u1) { - /// Most significant bit shifted out first - MsbFirst = 0x0, - /// Least significant bit shifted out first - LsbFirst = 0x1, - }, - }, - /// Serial clock (SCK) phase - CPHA: packed union { - raw: u1, - value: enum(u1) { - /// Sample on leading edge of clock, shift serial data on trailing edge - Leading = 0x0, - /// Sample on trailing edge of clock, shift serial data on leading edge - Trailing = 0x1, - }, - }, - /// Serial clock (SCK) polarity - CPOL: packed union { - raw: u1, - value: enum(u1) { - /// Active high - ActiveHigh = 0x0, - /// Active low - ActiveLow = 0x1, - }, - }, - padding: u29, - }), - reserved1372: [4]u8, - /// Default character. Character clocked out in case of an ignored transaction. - DEF: mmio.Mmio(packed struct(u32) { - /// Default character. Character clocked out in case of an ignored transaction. - DEF: u8, - padding: u24, - }), - reserved1472: [96]u8, - /// Over-read character - ORC: mmio.Mmio(packed struct(u32) { - /// Over-read character. Character clocked out after an over-read of the transmit buffer. - ORC: u8, - padding: u24, - }), - }; - - /// I2C compatible Two-Wire Interface 0 - pub const TWI0 = extern struct { - /// Start TWI receive sequence - TASKS_STARTRX: mmio.Mmio(packed struct(u32) { - /// Start TWI receive sequence - TASKS_STARTRX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved8: [4]u8, - /// Start TWI transmit sequence - TASKS_STARTTX: mmio.Mmio(packed struct(u32) { - /// Start TWI transmit sequence - TASKS_STARTTX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved20: [8]u8, - /// Stop TWI transaction - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop TWI transaction - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved28: [4]u8, - /// Suspend TWI transaction - TASKS_SUSPEND: mmio.Mmio(packed struct(u32) { - /// Suspend TWI transaction - TASKS_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Resume TWI transaction - TASKS_RESUME: mmio.Mmio(packed struct(u32) { - /// Resume TWI transaction - TASKS_RESUME: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved260: [224]u8, - /// TWI stopped - EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { - /// TWI stopped - EVENTS_STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// TWI RXD byte received - EVENTS_RXDREADY: mmio.Mmio(packed struct(u32) { - /// TWI RXD byte received - EVENTS_RXDREADY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved284: [16]u8, - /// TWI TXD byte sent - EVENTS_TXDSENT: mmio.Mmio(packed struct(u32) { - /// TWI TXD byte sent - EVENTS_TXDSENT: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved292: [4]u8, - /// TWI error - EVENTS_ERROR: mmio.Mmio(packed struct(u32) { - /// TWI error - EVENTS_ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved312: [16]u8, - /// TWI byte boundary, generated before each byte that is sent or received - EVENTS_BB: mmio.Mmio(packed struct(u32) { - /// TWI byte boundary, generated before each byte that is sent or received - EVENTS_BB: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved328: [12]u8, - /// TWI entered the suspended state - EVENTS_SUSPENDED: mmio.Mmio(packed struct(u32) { - /// TWI entered the suspended state - EVENTS_SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [180]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between event BB and task SUSPEND - BB_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event BB and task STOP - BB_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u30, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to enable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event RXDREADY - RXDREADY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u4, - /// Write '1' to enable interrupt for event TXDSENT - TXDSENT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u1, - /// Write '1' to enable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved14: u4, - /// Write '1' to enable interrupt for event BB - BB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u3, - /// Write '1' to enable interrupt for event SUSPENDED - SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u13, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event RXDREADY - RXDREADY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved7: u4, - /// Write '1' to disable interrupt for event TXDSENT - TXDSENT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u1, - /// Write '1' to disable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved14: u4, - /// Write '1' to disable interrupt for event BB - BB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u3, - /// Write '1' to disable interrupt for event SUSPENDED - SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u13, - }), - reserved1220: [440]u8, - /// Error source - ERRORSRC: mmio.Mmio(packed struct(u32) { - /// Overrun error - OVERRUN: packed union { - raw: u1, - value: enum(u1) { - /// Read: no overrun occured - NotPresent = 0x0, - /// Read: overrun occured - Present = 0x1, - }, - }, - /// NACK received after sending the address (write '1' to clear) - ANACK: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: packed union { - raw: u1, - value: enum(u1) { - /// Read: error not present - NotPresent = 0x0, - /// Read: error present - Present = 0x1, - }, - }, - padding: u29, - }), - reserved1280: [56]u8, - /// Enable TWI - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable TWI - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable TWI - Disabled = 0x0, - /// Enable TWI - Enabled = 0x5, - _, - }, - }, - padding: u28, - }), - reserved1304: [20]u8, - /// RXD register - RXD: mmio.Mmio(packed struct(u32) { - /// RXD register - RXD: u8, - padding: u24, - }), - /// TXD register - TXD: mmio.Mmio(packed struct(u32) { - /// TXD register - TXD: u8, - padding: u24, - }), - reserved1316: [4]u8, - /// TWI frequency. Accuracy depends on the HFCLK source selected. - FREQUENCY: mmio.Mmio(packed struct(u32) { - /// TWI master clock frequency - FREQUENCY: packed union { - raw: u32, - value: enum(u32) { - /// 100 kbps - K100 = 0x1980000, - /// 250 kbps - K250 = 0x4000000, - /// 400 kbps (actual rate 410.256 kbps) - K400 = 0x6680000, - _, - }, - }, - }), - reserved1416: [96]u8, - /// Address used in the TWI transfer - ADDRESS: mmio.Mmio(packed struct(u32) { - /// Address used in the TWI transfer - ADDRESS: u7, - padding: u25, - }), - }; - - /// I2C compatible Two-Wire Master Interface with EasyDMA 0 - pub const TWIM0 = extern struct { - /// Start TWI receive sequence - TASKS_STARTRX: mmio.Mmio(packed struct(u32) { - /// Start TWI receive sequence - TASKS_STARTRX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved8: [4]u8, - /// Start TWI transmit sequence - TASKS_STARTTX: mmio.Mmio(packed struct(u32) { - /// Start TWI transmit sequence - TASKS_STARTTX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved20: [8]u8, - /// Stop TWI transaction. Must be issued while the TWI master is not suspended. - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop TWI transaction. Must be issued while the TWI master is not suspended. - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved28: [4]u8, - /// Suspend TWI transaction - TASKS_SUSPEND: mmio.Mmio(packed struct(u32) { - /// Suspend TWI transaction - TASKS_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Resume TWI transaction - TASKS_RESUME: mmio.Mmio(packed struct(u32) { - /// Resume TWI transaction - TASKS_RESUME: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved260: [224]u8, - /// TWI stopped - EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { - /// TWI stopped - EVENTS_STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved292: [28]u8, - /// TWI error - EVENTS_ERROR: mmio.Mmio(packed struct(u32) { - /// TWI error - EVENTS_ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved328: [32]u8, - /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. - EVENTS_SUSPENDED: mmio.Mmio(packed struct(u32) { - /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. - EVENTS_SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Receive sequence started - EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) { - /// Receive sequence started - EVENTS_RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Transmit sequence started - EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) { - /// Transmit sequence started - EVENTS_TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved348: [8]u8, - /// Byte boundary, starting to receive the last byte - EVENTS_LASTRX: mmio.Mmio(packed struct(u32) { - /// Byte boundary, starting to receive the last byte - EVENTS_LASTRX: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Byte boundary, starting to transmit the last byte - EVENTS_LASTTX: mmio.Mmio(packed struct(u32) { - /// Byte boundary, starting to transmit the last byte - EVENTS_LASTTX: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [156]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// Shortcut between event LASTTX and task STARTRX - LASTTX_STARTRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event LASTTX and task SUSPEND - LASTTX_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event LASTTX and task STOP - LASTTX_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event LASTRX and task STARTTX - LASTRX_STARTTX: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event LASTRX and task SUSPEND - LASTRX_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event LASTRX and task STOP - LASTRX_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u19, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Enable or disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Enable or disable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved18: u8, - /// Enable or disable interrupt for event SUSPENDED - SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event RXSTARTED - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TXSTARTED - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved23: u2, - /// Enable or disable interrupt for event LASTRX - LASTRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event LASTTX - LASTTX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u7, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to enable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Write '1' to enable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u8, - /// Write '1' to enable interrupt for event SUSPENDED - SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event RXSTARTED - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TXSTARTED - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved23: u2, - /// Write '1' to enable interrupt for event LASTRX - LASTRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event LASTTX - LASTTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u7, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Write '1' to disable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u8, - /// Write '1' to disable interrupt for event SUSPENDED - SUSPENDED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event RXSTARTED - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TXSTARTED - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved23: u2, - /// Write '1' to disable interrupt for event LASTRX - LASTRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event LASTTX - LASTTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u7, - }), - reserved1220: [440]u8, - /// Error source - ERRORSRC: mmio.Mmio(packed struct(u32) { - /// Overrun error - OVERRUN: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotReceived = 0x0, - /// Error occurred - Received = 0x1, - }, - }, - /// NACK received after sending the address (write '1' to clear) - ANACK: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotReceived = 0x0, - /// Error occurred - Received = 0x1, - }, - }, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotReceived = 0x0, - /// Error occurred - Received = 0x1, - }, - }, - padding: u29, - }), - reserved1280: [56]u8, - /// Enable TWIM - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable TWIM - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable TWIM - Disabled = 0x0, - /// Enable TWIM - Enabled = 0x6, - _, - }, - }, - padding: u28, - }), - reserved1316: [32]u8, - /// TWI frequency. Accuracy depends on the HFCLK source selected. - FREQUENCY: mmio.Mmio(packed struct(u32) { - /// TWI master clock frequency - FREQUENCY: packed union { - raw: u32, - value: enum(u32) { - /// 100 kbps - K100 = 0x1980000, - /// 250 kbps - K250 = 0x4000000, - /// 400 kbps - K400 = 0x6400000, - _, - }, - }, - }), - reserved1416: [96]u8, - /// Address used in the TWI transfer - ADDRESS: mmio.Mmio(packed struct(u32) { - /// Address used in the TWI transfer - ADDRESS: u7, - padding: u25, - }), - }; - - /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 - pub const TWIS0 = extern struct { - reserved20: [20]u8, - /// Stop TWI transaction - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop TWI transaction - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved28: [4]u8, - /// Suspend TWI transaction - TASKS_SUSPEND: mmio.Mmio(packed struct(u32) { - /// Suspend TWI transaction - TASKS_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Resume TWI transaction - TASKS_RESUME: mmio.Mmio(packed struct(u32) { - /// Resume TWI transaction - TASKS_RESUME: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved48: [12]u8, - /// Prepare the TWI slave to respond to a write command - TASKS_PREPARERX: mmio.Mmio(packed struct(u32) { - /// Prepare the TWI slave to respond to a write command - TASKS_PREPARERX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Prepare the TWI slave to respond to a read command - TASKS_PREPARETX: mmio.Mmio(packed struct(u32) { - /// Prepare the TWI slave to respond to a read command - TASKS_PREPARETX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved260: [204]u8, - /// TWI stopped - EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { - /// TWI stopped - EVENTS_STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved292: [28]u8, - /// TWI error - EVENTS_ERROR: mmio.Mmio(packed struct(u32) { - /// TWI error - EVENTS_ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved332: [36]u8, - /// Receive sequence started - EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) { - /// Receive sequence started - EVENTS_RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Transmit sequence started - EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) { - /// Transmit sequence started - EVENTS_TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved356: [16]u8, - /// Write command received - EVENTS_WRITE: mmio.Mmio(packed struct(u32) { - /// Write command received - EVENTS_WRITE: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Read command received - EVENTS_READ: mmio.Mmio(packed struct(u32) { - /// Read command received - EVENTS_READ: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [148]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// Shortcut between event WRITE and task SUSPEND - WRITE_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event READ and task SUSPEND - READ_SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u17, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Enable or disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Enable or disable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved19: u9, - /// Enable or disable interrupt for event RXSTARTED - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TXSTARTED - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved25: u4, - /// Enable or disable interrupt for event WRITE - WRITE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event READ - READ: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u5, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to enable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Write '1' to enable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u9, - /// Write '1' to enable interrupt for event RXSTARTED - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TXSTARTED - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved25: u4, - /// Write '1' to enable interrupt for event WRITE - WRITE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event READ - READ: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u5, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved9: u7, - /// Write '1' to disable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved19: u9, - /// Write '1' to disable interrupt for event RXSTARTED - RXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TXSTARTED - TXSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved25: u4, - /// Write '1' to disable interrupt for event WRITE - WRITE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event READ - READ: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u5, - }), - reserved1232: [452]u8, - /// Error source - ERRORSRC: mmio.Mmio(packed struct(u32) { - /// RX buffer overflow detected, and prevented - OVERFLOW: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotDetected = 0x0, - /// Error occurred - Detected = 0x1, - }, - }, - reserved2: u1, - /// NACK sent after receiving a data byte - DNACK: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotReceived = 0x0, - /// Error occurred - Received = 0x1, - }, - }, - /// TX buffer over-read detected, and prevented - OVERREAD: packed union { - raw: u1, - value: enum(u1) { - /// Error did not occur - NotDetected = 0x0, - /// Error occurred - Detected = 0x1, - }, - }, - padding: u28, - }), - /// Status register indicating which address had a match - MATCH: mmio.Mmio(packed struct(u32) { - /// Which of the addresses in {ADDRESS} matched the incoming address - MATCH: u1, - padding: u31, - }), - reserved1280: [40]u8, - /// Enable TWIS - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable TWIS - ENABLE: packed union { - raw: u4, - value: enum(u4) { - /// Disable TWIS - Disabled = 0x0, - /// Enable TWIS - Enabled = 0x9, - _, - }, - }, - padding: u28, - }), - reserved1416: [132]u8, - /// Description collection: TWI slave address n - ADDRESS: [2]mmio.Mmio(packed struct(u32) { - /// TWI slave address - ADDRESS: u7, - padding: u25, - }), - reserved1428: [4]u8, - /// Configuration register for the address match mechanism - CONFIG: mmio.Mmio(packed struct(u32) { - /// Enable or disable address matching on ADDRESS[0] - ADDRESS0: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - /// Enable or disable address matching on ADDRESS[1] - ADDRESS1: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - padding: u30, - }), - reserved1472: [40]u8, - /// Over-read character. Character sent out in case of an over-read of the transmit buffer. - ORC: mmio.Mmio(packed struct(u32) { - /// Over-read character. Character sent out in case of an over-read of the transmit buffer. - ORC: u8, - padding: u24, - }), - }; - - /// Pulse Density Modulation (Digital Microphone) Interface - pub const PDM = extern struct { - /// Starts continuous PDM transfer - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Starts continuous PDM transfer - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stops PDM transfer - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stops PDM transfer - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [248]u8, - /// PDM transfer has started - EVENTS_STARTED: mmio.Mmio(packed struct(u32) { - /// PDM transfer has started - EVENTS_STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// PDM transfer has finished - EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { - /// PDM transfer has finished - EVENTS_STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM - EVENTS_END: mmio.Mmio(packed struct(u32) { - /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM - EVENTS_END: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved768: [500]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u29, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - reserved1280: [500]u8, - /// PDM module enable register - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable PDM module - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// PDM clock generator control - PDMCLKCTRL: mmio.Mmio(packed struct(u32) { - /// PDM_CLK frequency - FREQ: packed union { - raw: u32, - value: enum(u32) { - /// PDM_CLK = 32 MHz / 32 = 1.000 MHz - @"1000K" = 0x8000000, - /// PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. - Default = 0x8400000, - /// PDM_CLK = 32 MHz / 30 = 1.067 MHz - @"1067K" = 0x8800000, - /// PDM_CLK = 32 MHz / 26 = 1.231 MHz - @"1231K" = 0x9800000, - /// PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. - @"1280K" = 0xa000000, - /// PDM_CLK = 32 MHz / 24 = 1.333 MHz - @"1333K" = 0xa800000, - _, - }, - }, - }), - /// Defines the routing of the connected PDM microphones' signals - MODE: mmio.Mmio(packed struct(u32) { - /// Mono or stereo operation - OPERATION: packed union { - raw: u1, - value: enum(u1) { - /// Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] - Stereo = 0x0, - /// Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] - Mono = 0x1, - }, - }, - /// Defines on which PDM_CLK edge Left (or mono) is sampled - EDGE: packed union { - raw: u1, - value: enum(u1) { - /// Left (or mono) is sampled on falling edge of PDM_CLK - LeftFalling = 0x0, - /// Left (or mono) is sampled on rising edge of PDM_CLK - LeftRising = 0x1, - }, - }, - padding: u30, - }), - reserved1304: [12]u8, - /// Left output gain adjustment - GAINL: mmio.Mmio(packed struct(u32) { - /// Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust - GAINL: packed union { - raw: u7, - value: enum(u7) { - /// -20dB gain adjustment (minimum) - MinGain = 0x0, - /// 0dB gain adjustment - DefaultGain = 0x28, - /// +20dB gain adjustment (maximum) - MaxGain = 0x50, - _, - }, - }, - padding: u25, - }), - /// Right output gain adjustment - GAINR: mmio.Mmio(packed struct(u32) { - /// Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) - GAINR: packed union { - raw: u7, - value: enum(u7) { - /// -20dB gain adjustment (minimum) - MinGain = 0x0, - /// 0dB gain adjustment - DefaultGain = 0x28, - /// +20dB gain adjustment (maximum) - MaxGain = 0x50, - _, - }, - }, - padding: u25, - }), - /// Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. - RATIO: mmio.Mmio(packed struct(u32) { - /// Selects the ratio between PDM_CLK and output sample rate - RATIO: packed union { - raw: u1, - value: enum(u1) { - /// Ratio of 64 - Ratio64 = 0x0, - /// Ratio of 80 - Ratio80 = 0x1, - }, - }, - padding: u31, - }), - }; - - /// ARM TrustZone CryptoCell register interface - pub const CRYPTOCELL = extern struct { - reserved1280: [1280]u8, - /// Enable CRYPTOCELL subsystem - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable the CRYPTOCELL subsystem - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// CRYPTOCELL subsystem disabled - Disabled = 0x0, - /// CRYPTOCELL subsystem enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - }; - - /// CRYPTOCELL HOST_RGF interface - pub const CC_HOST_RGF = extern struct { - reserved6712: [6712]u8, - /// AES hardware key select - HOST_CRYPTOKEY_SEL: mmio.Mmio(packed struct(u32) { - /// Select the source of the HW key that is used by the AES engine - HOST_CRYPTOKEY_SEL: packed union { - raw: u2, - value: enum(u2) { - /// Use device root key K_DR from CRYPTOCELL AO power domain - K_DR = 0x0, - /// Use hard-coded RTL key K_PRTL - K_PRTL = 0x1, - /// Use provided session key - Session = 0x2, - _, - }, - }, - padding: u30, - }), - reserved6732: [16]u8, - /// This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. - HOST_IOT_KPRTL_LOCK: mmio.Mmio(packed struct(u32) { - /// This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. - HOST_IOT_KPRTL_LOCK: packed union { - raw: u1, - value: enum(u1) { - /// K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL - Disabled = 0x0, - /// K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. - HOST_IOT_KDR0: mmio.Mmio(packed struct(u32) { - /// Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain - HOST_IOT_KDR0: u32, - }), - /// This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. - HOST_IOT_KDR1: mmio.Mmio(packed struct(u32) { - /// K_DR bits 63:32 - HOST_IOT_KDR1: u32, - }), - /// This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. - HOST_IOT_KDR2: mmio.Mmio(packed struct(u32) { - /// K_DR bits 95:64 - HOST_IOT_KDR2: u32, - }), - /// This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. - HOST_IOT_KDR3: mmio.Mmio(packed struct(u32) { - /// K_DR bits 127:96 - HOST_IOT_KDR3: u32, - }), - /// Controls lifecycle state (LCS) for CRYPTOCELL subsystem - HOST_IOT_LCS: mmio.Mmio(packed struct(u32) { - /// Lifecycle state value. This field is write-once per reset. - LCS: packed union { - raw: u3, - value: enum(u3) { - /// CC310 operates in debug mode - Debug = 0x0, - /// CC310 operates in secure mode - Secure = 0x2, - _, - }, - }, - reserved8: u5, - /// This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset - LCS_IS_VALID: packed union { - raw: u1, - value: enum(u1) { - /// A valid LCS is not yet retained in the CRYPTOCELL AO power domain - Invalid = 0x0, - /// A valid LCS is successfully retained in the CRYPTOCELL AO power domain - Valid = 0x1, - }, - }, - padding: u23, - }), - }; - - /// External flash interface - pub const QSPI = extern struct { - /// Activate QSPI interface - TASKS_ACTIVATE: mmio.Mmio(packed struct(u32) { - /// Activate QSPI interface - TASKS_ACTIVATE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start transfer from external flash memory to internal RAM - TASKS_READSTART: mmio.Mmio(packed struct(u32) { - /// Start transfer from external flash memory to internal RAM - TASKS_READSTART: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start transfer from internal RAM to external flash memory - TASKS_WRITESTART: mmio.Mmio(packed struct(u32) { - /// Start transfer from internal RAM to external flash memory - TASKS_WRITESTART: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start external flash memory erase operation - TASKS_ERASESTART: mmio.Mmio(packed struct(u32) { - /// Start external flash memory erase operation - TASKS_ERASESTART: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Deactivate QSPI interface - TASKS_DEACTIVATE: mmio.Mmio(packed struct(u32) { - /// Deactivate QSPI interface - TASKS_DEACTIVATE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [236]u8, - /// QSPI peripheral is ready. This event will be generated as a response to any QSPI task. - EVENTS_READY: mmio.Mmio(packed struct(u32) { - /// QSPI peripheral is ready. This event will be generated as a response to any QSPI task. - EVENTS_READY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved768: [508]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1280: [500]u8, - /// Enable QSPI peripheral and acquire the pins selected in PSELn registers - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable QSPI - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable QSPI - Disabled = 0x0, - /// Enable QSPI - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1344: [60]u8, - /// Address offset into the external memory for Execute in Place operation. - XIPOFFSET: mmio.Mmio(packed struct(u32) { - /// Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. - XIPOFFSET: u32, - }), - /// Interface configuration. - IFCONFIG0: mmio.Mmio(packed struct(u32) { - /// Configure number of data lines and opcode used for reading. - READOC: packed union { - raw: u3, - value: enum(u3) { - /// Single data line SPI. FAST_READ (opcode 0x0B). - FASTREAD = 0x0, - /// Dual data line SPI. READ2O (opcode 0x3B). - READ2O = 0x1, - /// Dual data line SPI. READ2IO (opcode 0xBB). - READ2IO = 0x2, - /// Quad data line SPI. READ4O (opcode 0x6B). - READ4O = 0x3, - /// Quad data line SPI. READ4IO (opcode 0xEB). - READ4IO = 0x4, - _, - }, - }, - /// Configure number of data lines and opcode used for writing. - WRITEOC: packed union { - raw: u3, - value: enum(u3) { - /// Single data line SPI. PP (opcode 0x02). - PP = 0x0, - /// Dual data line SPI. PP2O (opcode 0xA2). - PP2O = 0x1, - /// Quad data line SPI. PP4O (opcode 0x32). - PP4O = 0x2, - /// Quad data line SPI. PP4IO (opcode 0x38). - PP4IO = 0x3, - _, - }, - }, - /// Addressing mode. - ADDRMODE: packed union { - raw: u1, - value: enum(u1) { - /// 24-bit addressing. - @"24BIT" = 0x0, - /// 32-bit addressing. - @"32BIT" = 0x1, - }, - }, - /// Enable deep power-down mode (DPM) feature. - DPMENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable DPM feature. - Disable = 0x0, - /// Enable DPM feature. - Enable = 0x1, - }, - }, - reserved12: u4, - /// Page size for commands PP, PP2O, PP4O and PP4IO. - PPSIZE: packed union { - raw: u1, - value: enum(u1) { - /// 256 bytes. - @"256Bytes" = 0x0, - /// 512 bytes. - @"512Bytes" = 0x1, - }, - }, - padding: u19, - }), - reserved1536: [184]u8, - /// Interface configuration. - IFCONFIG1: mmio.Mmio(packed struct(u32) { - /// Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). - SCKDELAY: u8, - reserved24: u16, - /// Enter/exit deep power-down mode (DPM) for external flash memory. - DPMEN: packed union { - raw: u1, - value: enum(u1) { - /// Exit DPM. - Exit = 0x0, - /// Enter DPM. - Enter = 0x1, - }, - }, - /// Select SPI mode. - SPIMODE: packed union { - raw: u1, - value: enum(u1) { - /// Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). - MODE0 = 0x0, - /// Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). - MODE3 = 0x1, - }, - }, - reserved28: u2, - /// SCK frequency is given as 32 MHz / (SCKFREQ + 1). - SCKFREQ: u4, - }), - /// Status register. - STATUS: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Deep power-down mode (DPM) status of external flash. - DPM: packed union { - raw: u1, - value: enum(u1) { - /// External flash is not in DPM. - Disabled = 0x0, - /// External flash is in DPM. - Enabled = 0x1, - }, - }, - /// Ready status. - READY: packed union { - raw: u1, - value: enum(u1) { - /// QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. - READY = 0x1, - /// QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. - BUSY = 0x0, - }, - }, - reserved24: u20, - /// Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. - SREG: u8, - }), - reserved1556: [12]u8, - /// Set the duration required to enter/exit deep power-down mode (DPM). - DPMDUR: mmio.Mmio(packed struct(u32) { - /// Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. - ENTER: u16, - /// Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. - EXIT: u16, - }), - reserved1572: [12]u8, - /// Extended address configuration. - ADDRCONF: mmio.Mmio(packed struct(u32) { - /// Opcode that enters the 32-bit addressing mode. - OPCODE: u8, - /// Byte 0 following opcode. - BYTE0: u8, - /// Byte 1 following byte 0. - BYTE1: u8, - /// Extended addressing mode. - MODE: packed union { - raw: u2, - value: enum(u2) { - /// Do not send any instruction. - NoInstr = 0x0, - /// Send opcode. - Opcode = 0x1, - /// Send opcode, byte0. - OpByte0 = 0x2, - /// Send opcode, byte0, byte1. - All = 0x3, - }, - }, - /// Wait for write complete before sending command. - WIPWAIT: packed union { - raw: u1, - value: enum(u1) { - /// No wait. - Disable = 0x0, - /// Wait. - Enable = 0x1, - }, - }, - /// Send WREN (write enable opcode 0x06) before instruction. - WREN: packed union { - raw: u1, - value: enum(u1) { - /// Do not send WREN. - Disable = 0x0, - /// Send WREN. - Enable = 0x1, - }, - }, - padding: u4, - }), - reserved1588: [12]u8, - /// Custom instruction configuration register. - CINSTRCONF: mmio.Mmio(packed struct(u32) { - /// Opcode of Custom instruction. - OPCODE: u8, - /// Length of custom instruction in number of bytes. - LENGTH: packed union { - raw: u4, - value: enum(u4) { - /// Send opcode only. - @"1B" = 0x1, - /// Send opcode, CINSTRDAT0.BYTE0. - @"2B" = 0x2, - /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. - @"3B" = 0x3, - /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. - @"4B" = 0x4, - /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. - @"5B" = 0x5, - /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. - @"6B" = 0x6, - /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. - @"7B" = 0x7, - /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. - @"8B" = 0x8, - /// Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. - @"9B" = 0x9, - _, - }, - }, - /// Level of the IO2 pin (if connected) during transmission of custom instruction. - LIO2: u1, - /// Level of the IO3 pin (if connected) during transmission of custom instruction. - LIO3: u1, - /// Wait for write complete before sending command. - WIPWAIT: packed union { - raw: u1, - value: enum(u1) { - /// No wait. - Disable = 0x0, - /// Wait. - Enable = 0x1, - }, - }, - /// Send WREN (write enable opcode 0x06) before instruction. - WREN: packed union { - raw: u1, - value: enum(u1) { - /// Do not send WREN. - Disable = 0x0, - /// Send WREN. - Enable = 0x1, - }, - }, - /// Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. - LFEN: packed union { - raw: u1, - value: enum(u1) { - /// Long frame mode disabled - Disable = 0x0, - /// Long frame mode enabled - Enable = 0x1, - }, - }, - /// Stop (finalize) long frame transaction - LFSTOP: packed union { - raw: u1, - value: enum(u1) { - /// Stop - Stop = 0x1, - _, - }, - }, - padding: u14, - }), - /// Custom instruction data register 0. - CINSTRDAT0: mmio.Mmio(packed struct(u32) { - /// Data byte 0 - BYTE0: u8, - /// Data byte 1 - BYTE1: u8, - /// Data byte 2 - BYTE2: u8, - /// Data byte 3 - BYTE3: u8, - }), - /// Custom instruction data register 1. - CINSTRDAT1: mmio.Mmio(packed struct(u32) { - /// Data byte 4 - BYTE4: u8, - /// Data byte 5 - BYTE5: u8, - /// Data byte 6 - BYTE6: u8, - /// Data byte 7 - BYTE7: u8, - }), - /// SPI interface timing. - IFTIMING: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. - RXDELAY: u3, - padding: u21, - }), - }; - - /// Pulse width modulation unit 0 - pub const PWM0 = extern struct { - reserved4: [4]u8, - /// Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. - TASKS_SEQSTART: [2]mmio.Mmio(packed struct(u32) { - /// Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. - TASKS_SEQSTART: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. - TASKS_NEXTSTEP: mmio.Mmio(packed struct(u32) { - /// Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. - TASKS_NEXTSTEP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved260: [240]u8, - /// Response to STOP task, emitted when PWM pulses are no longer generated - EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { - /// Response to STOP task, emitted when PWM pulses are no longer generated - EVENTS_STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Description collection: First PWM period started on sequence n - EVENTS_SEQSTARTED: [2]mmio.Mmio(packed struct(u32) { - /// First PWM period started on sequence n - EVENTS_SEQSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter - EVENTS_SEQEND: [2]mmio.Mmio(packed struct(u32) { - /// Emitted at end of every sequence n, when last value from RAM has been applied to wave counter - EVENTS_SEQEND: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Emitted at the end of each PWM period - EVENTS_PWMPERIODEND: mmio.Mmio(packed struct(u32) { - /// Emitted at the end of each PWM period - EVENTS_PWMPERIODEND: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Concatenated sequences have been played the amount of times defined in LOOP.CNT - EVENTS_LOOPSDONE: mmio.Mmio(packed struct(u32) { - /// Concatenated sequences have been played the amount of times defined in LOOP.CNT - EVENTS_LOOPSDONE: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [224]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between event SEQEND[0] and task STOP - SEQEND0_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event SEQEND[1] and task STOP - SEQEND1_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event LOOPSDONE and task SEQSTART[0] - LOOPSDONE_SEQSTART0: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event LOOPSDONE and task SEQSTART[1] - LOOPSDONE_SEQSTART1: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event LOOPSDONE and task STOP - LOOPSDONE_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Enable or disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event SEQSTARTED[0] - SEQSTARTED0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event SEQSTARTED[1] - SEQSTARTED1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event SEQEND[0] - SEQEND0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event SEQEND[1] - SEQEND1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event PWMPERIODEND - PWMPERIODEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event LOOPSDONE - LOOPSDONE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u24, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to enable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event SEQSTARTED[0] - SEQSTARTED0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event SEQSTARTED[1] - SEQSTARTED1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event SEQEND[0] - SEQEND0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event SEQEND[1] - SEQEND1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event PWMPERIODEND - PWMPERIODEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event LOOPSDONE - LOOPSDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u24, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event SEQSTARTED[0] - SEQSTARTED0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event SEQSTARTED[1] - SEQSTARTED1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event SEQEND[0] - SEQEND0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event SEQEND[1] - SEQEND1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event PWMPERIODEND - PWMPERIODEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event LOOPSDONE - LOOPSDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u24, - }), - reserved1280: [500]u8, - /// PWM module enable register - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable PWM module - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Selects operating mode of the wave counter - MODE: mmio.Mmio(packed struct(u32) { - /// Selects up mode or up-and-down mode for the counter - UPDOWN: packed union { - raw: u1, - value: enum(u1) { - /// Up counter, edge-aligned PWM duty cycle - Up = 0x0, - /// Up and down counter, center-aligned PWM duty cycle - UpAndDown = 0x1, - }, - }, - padding: u31, - }), - /// Value up to which the pulse generator counter counts - COUNTERTOP: mmio.Mmio(packed struct(u32) { - /// Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. - COUNTERTOP: u15, - padding: u17, - }), - /// Configuration for PWM_CLK - PRESCALER: mmio.Mmio(packed struct(u32) { - /// Prescaler of PWM_CLK - PRESCALER: packed union { - raw: u3, - value: enum(u3) { - /// Divide by 1 (16 MHz) - DIV_1 = 0x0, - /// Divide by 2 (8 MHz) - DIV_2 = 0x1, - /// Divide by 4 (4 MHz) - DIV_4 = 0x2, - /// Divide by 8 (2 MHz) - DIV_8 = 0x3, - /// Divide by 16 (1 MHz) - DIV_16 = 0x4, - /// Divide by 32 (500 kHz) - DIV_32 = 0x5, - /// Divide by 64 (250 kHz) - DIV_64 = 0x6, - /// Divide by 128 (125 kHz) - DIV_128 = 0x7, - }, - }, - padding: u29, - }), - /// Configuration of the decoder - DECODER: mmio.Mmio(packed struct(u32) { - /// How a sequence is read from RAM and spread to the compare register - LOAD: packed union { - raw: u2, - value: enum(u2) { - /// 1st half word (16-bit) used in all PWM channels 0..3 - Common = 0x0, - /// 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 - Grouped = 0x1, - /// 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 - Individual = 0x2, - /// 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP - WaveForm = 0x3, - }, - }, - reserved8: u6, - /// Selects source for advancing the active sequence - MODE: packed union { - raw: u1, - value: enum(u1) { - /// SEQ[n].REFRESH is used to determine loading internal compare registers - RefreshCount = 0x0, - /// NEXTSTEP task causes a new value to be loaded to internal compare registers - NextStep = 0x1, - }, - }, - padding: u23, - }), - /// Number of playbacks of a loop - LOOP: mmio.Mmio(packed struct(u32) { - /// Number of playbacks of pattern cycles - CNT: packed union { - raw: u16, - value: enum(u16) { - /// Looping disabled (stop at the end of the sequence) - Disabled = 0x0, - _, - }, - }, - padding: u16, - }), - }; - - /// Universal serial bus device - pub const USBD = extern struct { - reserved4: [4]u8, - /// Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host - TASKS_STARTEPIN: [8]mmio.Mmio(packed struct(u32) { - /// Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host - TASKS_STARTEPIN: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint - TASKS_STARTISOIN: mmio.Mmio(packed struct(u32) { - /// Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint - TASKS_STARTISOIN: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host - TASKS_STARTEPOUT: [8]mmio.Mmio(packed struct(u32) { - /// Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host - TASKS_STARTEPOUT: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint - TASKS_STARTISOOUT: mmio.Mmio(packed struct(u32) { - /// Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint - TASKS_STARTISOOUT: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Allows OUT data stage on control endpoint 0 - TASKS_EP0RCVOUT: mmio.Mmio(packed struct(u32) { - /// Allows OUT data stage on control endpoint 0 - TASKS_EP0RCVOUT: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Allows status stage on control endpoint 0 - TASKS_EP0STATUS: mmio.Mmio(packed struct(u32) { - /// Allows status stage on control endpoint 0 - TASKS_EP0STATUS: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stalls data and status stage on control endpoint 0 - TASKS_EP0STALL: mmio.Mmio(packed struct(u32) { - /// Stalls data and status stage on control endpoint 0 - TASKS_EP0STALL: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Forces D+ and D- lines into the state defined in the DPDMVALUE register - TASKS_DPDMDRIVE: mmio.Mmio(packed struct(u32) { - /// Forces D+ and D- lines into the state defined in the DPDMVALUE register - TASKS_DPDMDRIVE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stops forcing D+ and D- lines into any state (USB engine takes control) - TASKS_DPDMNODRIVE: mmio.Mmio(packed struct(u32) { - /// Stops forcing D+ and D- lines into any state (USB engine takes control) - TASKS_DPDMNODRIVE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [160]u8, - /// Signals that a USB reset condition has been detected on USB lines - EVENTS_USBRESET: mmio.Mmio(packed struct(u32) { - /// Signals that a USB reset condition has been detected on USB lines - EVENTS_USBRESET: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register - EVENTS_STARTED: mmio.Mmio(packed struct(u32) { - /// Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register - EVENTS_STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. - EVENTS_ENDEPIN: [8]mmio.Mmio(packed struct(u32) { - /// The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. - EVENTS_ENDEPIN: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// An acknowledged data transfer has taken place on the control endpoint - EVENTS_EP0DATADONE: mmio.Mmio(packed struct(u32) { - /// An acknowledged data transfer has taken place on the control endpoint - EVENTS_EP0DATADONE: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. - EVENTS_ENDISOIN: mmio.Mmio(packed struct(u32) { - /// The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. - EVENTS_ENDISOIN: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. - EVENTS_ENDEPOUT: [8]mmio.Mmio(packed struct(u32) { - /// The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. - EVENTS_ENDEPOUT: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. - EVENTS_ENDISOOUT: mmio.Mmio(packed struct(u32) { - /// The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. - EVENTS_ENDISOOUT: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Signals that a SOF (start of frame) condition has been detected on USB lines - EVENTS_SOF: mmio.Mmio(packed struct(u32) { - /// Signals that a SOF (start of frame) condition has been detected on USB lines - EVENTS_SOF: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. - EVENTS_USBEVENT: mmio.Mmio(packed struct(u32) { - /// An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. - EVENTS_USBEVENT: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// A valid SETUP token has been received (and acknowledged) on the control endpoint - EVENTS_EP0SETUP: mmio.Mmio(packed struct(u32) { - /// A valid SETUP token has been received (and acknowledged) on the control endpoint - EVENTS_EP0SETUP: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register - EVENTS_EPDATA: mmio.Mmio(packed struct(u32) { - /// A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register - EVENTS_EPDATA: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [156]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between event EP0DATADONE and task STARTEPIN[0] - EP0DATADONE_STARTEPIN0: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event EP0DATADONE and task STARTEPOUT[0] - EP0DATADONE_STARTEPOUT0: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event EP0DATADONE and task EP0STATUS - EP0DATADONE_EP0STATUS: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event ENDEPOUT[0] and task EP0STATUS - ENDEPOUT0_EP0STATUS: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event ENDEPOUT[0] and task EP0RCVOUT - ENDEPOUT0_EP0RCVOUT: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for event USBRESET - USBRESET: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPIN[0] - ENDEPIN0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPIN[1] - ENDEPIN1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPIN[2] - ENDEPIN2: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPIN[3] - ENDEPIN3: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPIN[4] - ENDEPIN4: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPIN[5] - ENDEPIN5: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPIN[6] - ENDEPIN6: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPIN[7] - ENDEPIN7: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event EP0DATADONE - EP0DATADONE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDISOIN - ENDISOIN: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPOUT[0] - ENDEPOUT0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPOUT[1] - ENDEPOUT1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPOUT[2] - ENDEPOUT2: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPOUT[3] - ENDEPOUT3: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPOUT[4] - ENDEPOUT4: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPOUT[5] - ENDEPOUT5: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPOUT[6] - ENDEPOUT6: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDEPOUT[7] - ENDEPOUT7: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDISOOUT - ENDISOOUT: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event SOF - SOF: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event USBEVENT - USBEVENT: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event EP0SETUP - EP0SETUP: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event EPDATA - EPDATA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u7, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event USBRESET - USBRESET: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPIN[0] - ENDEPIN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPIN[1] - ENDEPIN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPIN[2] - ENDEPIN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPIN[3] - ENDEPIN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPIN[4] - ENDEPIN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPIN[5] - ENDEPIN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPIN[6] - ENDEPIN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPIN[7] - ENDEPIN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event EP0DATADONE - EP0DATADONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDISOIN - ENDISOIN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPOUT[0] - ENDEPOUT0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPOUT[1] - ENDEPOUT1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPOUT[2] - ENDEPOUT2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPOUT[3] - ENDEPOUT3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPOUT[4] - ENDEPOUT4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPOUT[5] - ENDEPOUT5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPOUT[6] - ENDEPOUT6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDEPOUT[7] - ENDEPOUT7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDISOOUT - ENDISOOUT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event SOF - SOF: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event USBEVENT - USBEVENT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event EP0SETUP - EP0SETUP: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event EPDATA - EPDATA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u7, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event USBRESET - USBRESET: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPIN[0] - ENDEPIN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPIN[1] - ENDEPIN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPIN[2] - ENDEPIN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPIN[3] - ENDEPIN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPIN[4] - ENDEPIN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPIN[5] - ENDEPIN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPIN[6] - ENDEPIN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPIN[7] - ENDEPIN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event EP0DATADONE - EP0DATADONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDISOIN - ENDISOIN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPOUT[0] - ENDEPOUT0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPOUT[1] - ENDEPOUT1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPOUT[2] - ENDEPOUT2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPOUT[3] - ENDEPOUT3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPOUT[4] - ENDEPOUT4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPOUT[5] - ENDEPOUT5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPOUT[6] - ENDEPOUT6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDEPOUT[7] - ENDEPOUT7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDISOOUT - ENDISOOUT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event SOF - SOF: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event USBEVENT - USBEVENT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event EP0SETUP - EP0SETUP: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event EPDATA - EPDATA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u7, - }), - reserved1024: [244]u8, - /// Details on what caused the USBEVENT event - EVENTCAUSE: mmio.Mmio(packed struct(u32) { - /// CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. - ISOOUTCRC: packed union { - raw: u1, - value: enum(u1) { - /// No error detected - NotDetected = 0x0, - /// Error detected - Detected = 0x1, - }, - }, - reserved8: u7, - /// Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. - SUSPEND: packed union { - raw: u1, - value: enum(u1) { - /// Suspend not detected - NotDetected = 0x0, - /// Suspend detected - Detected = 0x1, - }, - }, - /// Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. - RESUME: packed union { - raw: u1, - value: enum(u1) { - /// Resume not detected - NotDetected = 0x0, - /// Resume detected - Detected = 0x1, - }, - }, - /// USB MAC has been woken up and operational. Write '1' to clear. - USBWUALLOWED: packed union { - raw: u1, - value: enum(u1) { - /// Wake up not allowed - NotAllowed = 0x0, - /// Wake up allowed - Allowed = 0x1, - }, - }, - /// USB device is ready for normal operation. Write '1' to clear. - READY: packed union { - raw: u1, - value: enum(u1) { - /// USBEVENT was not issued due to USBD peripheral ready - NotDetected = 0x0, - /// USBD peripheral is ready - Ready = 0x1, - }, - }, - padding: u20, - }), - reserved1128: [100]u8, - /// Provides information on which endpoint's EasyDMA registers have been captured - EPSTATUS: mmio.Mmio(packed struct(u32) { - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPIN0: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPIN1: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPIN2: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPIN3: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPIN4: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPIN5: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPIN6: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPIN7: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPIN8: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - reserved16: u7, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPOUT0: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPOUT1: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPOUT2: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPOUT3: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPOUT4: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPOUT5: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPOUT6: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPOUT7: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - /// Captured state of endpoint's EasyDMA registers. Write '1' to clear. - EPOUT8: packed union { - raw: u1, - value: enum(u1) { - /// EasyDMA registers have not been captured for this endpoint - NoData = 0x0, - /// EasyDMA registers have been captured for this endpoint - DataDone = 0x1, - }, - }, - padding: u7, - }), - /// Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) - EPDATASTATUS: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. - EPIN1: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotDone = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - DataDone = 0x1, - }, - }, - /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. - EPIN2: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotDone = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - DataDone = 0x1, - }, - }, - /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. - EPIN3: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotDone = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - DataDone = 0x1, - }, - }, - /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. - EPIN4: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotDone = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - DataDone = 0x1, - }, - }, - /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. - EPIN5: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotDone = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - DataDone = 0x1, - }, - }, - /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. - EPIN6: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotDone = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - DataDone = 0x1, - }, - }, - /// Acknowledged data transfer on this IN endpoint. Write '1' to clear. - EPIN7: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotDone = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - DataDone = 0x1, - }, - }, - reserved17: u9, - /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - EPOUT1: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotStarted = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - Started = 0x1, - }, - }, - /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - EPOUT2: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotStarted = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - Started = 0x1, - }, - }, - /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - EPOUT3: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotStarted = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - Started = 0x1, - }, - }, - /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - EPOUT4: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotStarted = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - Started = 0x1, - }, - }, - /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - EPOUT5: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotStarted = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - Started = 0x1, - }, - }, - /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - EPOUT6: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotStarted = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - Started = 0x1, - }, - }, - /// Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - EPOUT7: packed union { - raw: u1, - value: enum(u1) { - /// No acknowledged data transfer on this endpoint - NotStarted = 0x0, - /// Acknowledged data transfer on this endpoint has occurred - Started = 0x1, - }, - }, - padding: u8, - }), - /// Device USB address - USBADDR: mmio.Mmio(packed struct(u32) { - /// Device USB address - ADDR: u7, - padding: u25, - }), - reserved1152: [12]u8, - /// SETUP data, byte 0, bmRequestType - BMREQUESTTYPE: mmio.Mmio(packed struct(u32) { - /// Data transfer type - RECIPIENT: packed union { - raw: u5, - value: enum(u5) { - /// Device - Device = 0x0, - /// Interface - Interface = 0x1, - /// Endpoint - Endpoint = 0x2, - /// Other - Other = 0x3, - _, - }, - }, - /// Data transfer type - TYPE: packed union { - raw: u2, - value: enum(u2) { - /// Standard - Standard = 0x0, - /// Class - Class = 0x1, - /// Vendor - Vendor = 0x2, - _, - }, - }, - /// Data transfer direction - DIRECTION: packed union { - raw: u1, - value: enum(u1) { - /// Host-to-device - HostToDevice = 0x0, - /// Device-to-host - DeviceToHost = 0x1, - }, - }, - padding: u24, - }), - /// SETUP data, byte 1, bRequest - BREQUEST: mmio.Mmio(packed struct(u32) { - /// SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. - BREQUEST: packed union { - raw: u8, - value: enum(u8) { - /// Standard request GET_STATUS - STD_GET_STATUS = 0x0, - /// Standard request CLEAR_FEATURE - STD_CLEAR_FEATURE = 0x1, - /// Standard request SET_FEATURE - STD_SET_FEATURE = 0x3, - /// Standard request SET_ADDRESS - STD_SET_ADDRESS = 0x5, - /// Standard request GET_DESCRIPTOR - STD_GET_DESCRIPTOR = 0x6, - /// Standard request SET_DESCRIPTOR - STD_SET_DESCRIPTOR = 0x7, - /// Standard request GET_CONFIGURATION - STD_GET_CONFIGURATION = 0x8, - /// Standard request SET_CONFIGURATION - STD_SET_CONFIGURATION = 0x9, - /// Standard request GET_INTERFACE - STD_GET_INTERFACE = 0xa, - /// Standard request SET_INTERFACE - STD_SET_INTERFACE = 0xb, - /// Standard request SYNCH_FRAME - STD_SYNCH_FRAME = 0xc, - _, - }, - }, - padding: u24, - }), - /// SETUP data, byte 2, LSB of wValue - WVALUEL: mmio.Mmio(packed struct(u32) { - /// SETUP data, byte 2, LSB of wValue - WVALUEL: u8, - padding: u24, - }), - /// SETUP data, byte 3, MSB of wValue - WVALUEH: mmio.Mmio(packed struct(u32) { - /// SETUP data, byte 3, MSB of wValue - WVALUEH: u8, - padding: u24, - }), - /// SETUP data, byte 4, LSB of wIndex - WINDEXL: mmio.Mmio(packed struct(u32) { - /// SETUP data, byte 4, LSB of wIndex - WINDEXL: u8, - padding: u24, - }), - /// SETUP data, byte 5, MSB of wIndex - WINDEXH: mmio.Mmio(packed struct(u32) { - /// SETUP data, byte 5, MSB of wIndex - WINDEXH: u8, - padding: u24, - }), - /// SETUP data, byte 6, LSB of wLength - WLENGTHL: mmio.Mmio(packed struct(u32) { - /// SETUP data, byte 6, LSB of wLength - WLENGTHL: u8, - padding: u24, - }), - /// SETUP data, byte 7, MSB of wLength - WLENGTHH: mmio.Mmio(packed struct(u32) { - /// SETUP data, byte 7, MSB of wLength - WLENGTHH: u8, - padding: u24, - }), - reserved1280: [96]u8, - /// Enable USB - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable USB - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// USB peripheral is disabled - Disabled = 0x0, - /// USB peripheral is enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Control of the USB pull-up - USBPULLUP: mmio.Mmio(packed struct(u32) { - /// Control of the USB pull-up on the D+ line - CONNECT: packed union { - raw: u1, - value: enum(u1) { - /// Pull-up is disconnected - Disabled = 0x0, - /// Pull-up is connected to D+ - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). - DPDMVALUE: mmio.Mmio(packed struct(u32) { - /// State D+ and D- lines will be forced into by the DPDMDRIVE task - STATE: packed union { - raw: u5, - value: enum(u5) { - /// D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) - Resume = 0x1, - /// D+ forced high, D- forced low (J state) - J = 0x2, - /// D+ forced low, D- forced high (K state) - K = 0x4, - _, - }, - }, - padding: u27, - }), - /// Data toggle control and status - DTOGGLE: mmio.Mmio(packed struct(u32) { - /// Select bulk endpoint number - EP: u3, - reserved7: u4, - /// Selects IN or OUT endpoint - IO: packed union { - raw: u1, - value: enum(u1) { - /// Selects OUT endpoint - Out = 0x0, - /// Selects IN endpoint - In = 0x1, - }, - }, - /// Data toggle value - VALUE: packed union { - raw: u2, - value: enum(u2) { - /// No action on data toggle when writing the register with this value - Nop = 0x0, - /// Data toggle is DATA0 on endpoint set by EP and IO - Data0 = 0x1, - /// Data toggle is DATA1 on endpoint set by EP and IO - Data1 = 0x2, - _, - }, - }, - padding: u22, - }), - /// Endpoint IN enable - EPINEN: mmio.Mmio(packed struct(u32) { - /// Enable IN endpoint 0 - IN0: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint IN 0 (no response to IN tokens) - Disable = 0x0, - /// Enable endpoint IN 0 (response to IN tokens) - Enable = 0x1, - }, - }, - /// Enable IN endpoint 1 - IN1: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint IN 1 (no response to IN tokens) - Disable = 0x0, - /// Enable endpoint IN 1 (response to IN tokens) - Enable = 0x1, - }, - }, - /// Enable IN endpoint 2 - IN2: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint IN 2 (no response to IN tokens) - Disable = 0x0, - /// Enable endpoint IN 2 (response to IN tokens) - Enable = 0x1, - }, - }, - /// Enable IN endpoint 3 - IN3: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint IN 3 (no response to IN tokens) - Disable = 0x0, - /// Enable endpoint IN 3 (response to IN tokens) - Enable = 0x1, - }, - }, - /// Enable IN endpoint 4 - IN4: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint IN 4 (no response to IN tokens) - Disable = 0x0, - /// Enable endpoint IN 4 (response to IN tokens) - Enable = 0x1, - }, - }, - /// Enable IN endpoint 5 - IN5: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint IN 5 (no response to IN tokens) - Disable = 0x0, - /// Enable endpoint IN 5 (response to IN tokens) - Enable = 0x1, - }, - }, - /// Enable IN endpoint 6 - IN6: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint IN 6 (no response to IN tokens) - Disable = 0x0, - /// Enable endpoint IN 6 (response to IN tokens) - Enable = 0x1, - }, - }, - /// Enable IN endpoint 7 - IN7: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint IN 7 (no response to IN tokens) - Disable = 0x0, - /// Enable endpoint IN 7 (response to IN tokens) - Enable = 0x1, - }, - }, - /// Enable ISO IN endpoint - ISOIN: packed union { - raw: u1, - value: enum(u1) { - /// Disable ISO IN endpoint 8 - Disable = 0x0, - /// Enable ISO IN endpoint 8 - Enable = 0x1, - }, - }, - padding: u23, - }), - /// Endpoint OUT enable - EPOUTEN: mmio.Mmio(packed struct(u32) { - /// Enable OUT endpoint 0 - OUT0: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint OUT 0 (no response to OUT tokens) - Disable = 0x0, - /// Enable endpoint OUT 0 (response to OUT tokens) - Enable = 0x1, - }, - }, - /// Enable OUT endpoint 1 - OUT1: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint OUT 1 (no response to OUT tokens) - Disable = 0x0, - /// Enable endpoint OUT 1 (response to OUT tokens) - Enable = 0x1, - }, - }, - /// Enable OUT endpoint 2 - OUT2: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint OUT 2 (no response to OUT tokens) - Disable = 0x0, - /// Enable endpoint OUT 2 (response to OUT tokens) - Enable = 0x1, - }, - }, - /// Enable OUT endpoint 3 - OUT3: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint OUT 3 (no response to OUT tokens) - Disable = 0x0, - /// Enable endpoint OUT 3 (response to OUT tokens) - Enable = 0x1, - }, - }, - /// Enable OUT endpoint 4 - OUT4: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint OUT 4 (no response to OUT tokens) - Disable = 0x0, - /// Enable endpoint OUT 4 (response to OUT tokens) - Enable = 0x1, - }, - }, - /// Enable OUT endpoint 5 - OUT5: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint OUT 5 (no response to OUT tokens) - Disable = 0x0, - /// Enable endpoint OUT 5 (response to OUT tokens) - Enable = 0x1, - }, - }, - /// Enable OUT endpoint 6 - OUT6: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint OUT 6 (no response to OUT tokens) - Disable = 0x0, - /// Enable endpoint OUT 6 (response to OUT tokens) - Enable = 0x1, - }, - }, - /// Enable OUT endpoint 7 - OUT7: packed union { - raw: u1, - value: enum(u1) { - /// Disable endpoint OUT 7 (no response to OUT tokens) - Disable = 0x0, - /// Enable endpoint OUT 7 (response to OUT tokens) - Enable = 0x1, - }, - }, - /// Enable ISO OUT endpoint 8 - ISOOUT: packed union { - raw: u1, - value: enum(u1) { - /// Disable ISO OUT endpoint 8 - Disable = 0x0, - /// Enable ISO OUT endpoint 8 - Enable = 0x1, - }, - }, - padding: u23, - }), - /// STALL endpoints - EPSTALL: mmio.Mmio(packed struct(u32) { - /// Select endpoint number - EP: u3, - reserved7: u4, - /// Selects IN or OUT endpoint - IO: packed union { - raw: u1, - value: enum(u1) { - /// Selects OUT endpoint - Out = 0x0, - /// Selects IN endpoint - In = 0x1, - }, - }, - /// Stall selected endpoint - STALL: packed union { - raw: u1, - value: enum(u1) { - /// Don't stall selected endpoint - UnStall = 0x0, - /// Stall selected endpoint - Stall = 0x1, - }, - }, - padding: u23, - }), - /// Controls the split of ISO buffers - ISOSPLIT: mmio.Mmio(packed struct(u32) { - /// Controls the split of ISO buffers - SPLIT: packed union { - raw: u16, - value: enum(u16) { - /// Full buffer dedicated to either iso IN or OUT - OneDir = 0x0, - /// Lower half for IN, upper half for OUT - HalfIN = 0x80, - _, - }, - }, - padding: u16, - }), - /// Returns the current value of the start of frame counter - FRAMECNTR: mmio.Mmio(packed struct(u32) { - /// Returns the current value of the start of frame counter - FRAMECNTR: u11, - padding: u21, - }), - reserved1324: [8]u8, - /// Controls USBD peripheral low power mode during USB suspend - LOWPOWER: mmio.Mmio(packed struct(u32) { - /// Controls USBD peripheral low-power mode during USB suspend - LOWPOWER: packed union { - raw: u1, - value: enum(u1) { - /// Software must write this value to exit low power mode and before performing a remote wake-up - ForceNormal = 0x0, - /// Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral - LowPower = 0x1, - }, - }, - padding: u31, - }), - /// Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent - ISOINCONFIG: mmio.Mmio(packed struct(u32) { - /// Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent - RESPONSE: packed union { - raw: u1, - value: enum(u1) { - /// Endpoint does not respond in that case - NoResp = 0x0, - /// Endpoint responds with a zero-length data packet in that case - ZeroData = 0x1, - }, - }, - padding: u31, - }), - }; - - /// NFC-A compatible radio - pub const NFCT = extern struct { - /// Activate NFCT peripheral for incoming and outgoing frames, change state to activated - TASKS_ACTIVATE: mmio.Mmio(packed struct(u32) { - /// Activate NFCT peripheral for incoming and outgoing frames, change state to activated - TASKS_ACTIVATE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Disable NFCT peripheral - TASKS_DISABLE: mmio.Mmio(packed struct(u32) { - /// Disable NFCT peripheral - TASKS_DISABLE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Enable NFC sense field mode, change state to sense mode - TASKS_SENSE: mmio.Mmio(packed struct(u32) { - /// Enable NFC sense field mode, change state to sense mode - TASKS_SENSE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start transmission of an outgoing frame, change state to transmit - TASKS_STARTTX: mmio.Mmio(packed struct(u32) { - /// Start transmission of an outgoing frame, change state to transmit - TASKS_STARTTX: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved28: [12]u8, - /// Initializes the EasyDMA for receive. - TASKS_ENABLERXDATA: mmio.Mmio(packed struct(u32) { - /// Initializes the EasyDMA for receive. - TASKS_ENABLERXDATA: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved36: [4]u8, - /// Force state machine to IDLE state - TASKS_GOIDLE: mmio.Mmio(packed struct(u32) { - /// Force state machine to IDLE state - TASKS_GOIDLE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Force state machine to SLEEP_A state - TASKS_GOSLEEP: mmio.Mmio(packed struct(u32) { - /// Force state machine to SLEEP_A state - TASKS_GOSLEEP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [212]u8, - /// The NFCT peripheral is ready to receive and send frames - EVENTS_READY: mmio.Mmio(packed struct(u32) { - /// The NFCT peripheral is ready to receive and send frames - EVENTS_READY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Remote NFC field detected - EVENTS_FIELDDETECTED: mmio.Mmio(packed struct(u32) { - /// Remote NFC field detected - EVENTS_FIELDDETECTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Remote NFC field lost - EVENTS_FIELDLOST: mmio.Mmio(packed struct(u32) { - /// Remote NFC field lost - EVENTS_FIELDLOST: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Marks the start of the first symbol of a transmitted frame - EVENTS_TXFRAMESTART: mmio.Mmio(packed struct(u32) { - /// Marks the start of the first symbol of a transmitted frame - EVENTS_TXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Marks the end of the last transmitted on-air symbol of a frame - EVENTS_TXFRAMEEND: mmio.Mmio(packed struct(u32) { - /// Marks the end of the last transmitted on-air symbol of a frame - EVENTS_TXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Marks the end of the first symbol of a received frame - EVENTS_RXFRAMESTART: mmio.Mmio(packed struct(u32) { - /// Marks the end of the first symbol of a received frame - EVENTS_RXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer - EVENTS_RXFRAMEEND: mmio.Mmio(packed struct(u32) { - /// Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer - EVENTS_RXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// NFC error reported. The ERRORSTATUS register contains details on the source of the error. - EVENTS_ERROR: mmio.Mmio(packed struct(u32) { - /// NFC error reported. The ERRORSTATUS register contains details on the source of the error. - EVENTS_ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved296: [8]u8, - /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. - EVENTS_RXERROR: mmio.Mmio(packed struct(u32) { - /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. - EVENTS_RXERROR: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. - EVENTS_ENDRX: mmio.Mmio(packed struct(u32) { - /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. - EVENTS_ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer - EVENTS_ENDTX: mmio.Mmio(packed struct(u32) { - /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer - EVENTS_ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved312: [4]u8, - /// Auto collision resolution process has started - EVENTS_AUTOCOLRESSTARTED: mmio.Mmio(packed struct(u32) { - /// Auto collision resolution process has started - EVENTS_AUTOCOLRESSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved328: [12]u8, - /// NFC auto collision resolution error reported. - EVENTS_COLLISION: mmio.Mmio(packed struct(u32) { - /// NFC auto collision resolution error reported. - EVENTS_COLLISION: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// NFC auto collision resolution successfully completed - EVENTS_SELECTED: mmio.Mmio(packed struct(u32) { - /// NFC auto collision resolution successfully completed - EVENTS_SELECTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// EasyDMA is ready to receive or send frames. - EVENTS_STARTED: mmio.Mmio(packed struct(u32) { - /// EasyDMA is ready to receive or send frames. - EVENTS_STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [172]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between event FIELDDETECTED and task ACTIVATE - FIELDDETECTED_ACTIVATE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event FIELDLOST and task SENSE - FIELDLOST_SENSE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - reserved5: u3, - /// Shortcut between event TXFRAMEEND and task ENABLERXDATA - TXFRAMEEND_ENABLERXDATA: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u26, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event FIELDDETECTED - FIELDDETECTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event FIELDLOST - FIELDLOST: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TXFRAMESTART - TXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TXFRAMEEND - TXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event RXFRAMESTART - RXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event RXFRAMEEND - RXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved10: u2, - /// Enable or disable interrupt for event RXERROR - RXERROR: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDRX - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event ENDTX - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved14: u1, - /// Enable or disable interrupt for event AUTOCOLRESSTARTED - AUTOCOLRESSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved18: u3, - /// Enable or disable interrupt for event COLLISION - COLLISION: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event SELECTED - SELECTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u11, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event FIELDDETECTED - FIELDDETECTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event FIELDLOST - FIELDLOST: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TXFRAMESTART - TXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TXFRAMEEND - TXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event RXFRAMESTART - RXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event RXFRAMEEND - RXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u2, - /// Write '1' to enable interrupt for event RXERROR - RXERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDRX - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDTX - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved14: u1, - /// Write '1' to enable interrupt for event AUTOCOLRESSTARTED - AUTOCOLRESSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u3, - /// Write '1' to enable interrupt for event COLLISION - COLLISION: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event SELECTED - SELECTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u11, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event FIELDDETECTED - FIELDDETECTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event FIELDLOST - FIELDLOST: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TXFRAMESTART - TXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TXFRAMEEND - TXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event RXFRAMESTART - RXFRAMESTART: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event RXFRAMEEND - RXFRAMEEND: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved10: u2, - /// Write '1' to disable interrupt for event RXERROR - RXERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDRX - ENDRX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDTX - ENDTX: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved14: u1, - /// Write '1' to disable interrupt for event AUTOCOLRESSTARTED - AUTOCOLRESSTARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved18: u3, - /// Write '1' to disable interrupt for event COLLISION - COLLISION: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event SELECTED - SELECTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u11, - }), - reserved1028: [248]u8, - /// NFC Error Status register - ERRORSTATUS: mmio.Mmio(packed struct(u32) { - /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX - FRAMEDELAYTIMEOUT: u1, - padding: u31, - }), - reserved1040: [8]u8, - /// NfcTag state register - NFCTAGSTATE: mmio.Mmio(packed struct(u32) { - /// NfcTag state - NFCTAGSTATE: packed union { - raw: u3, - value: enum(u3) { - /// Disabled or sense - Disabled = 0x0, - /// RampUp - RampUp = 0x2, - /// Idle - Idle = 0x3, - /// Receive - Receive = 0x4, - /// FrameDelay - FrameDelay = 0x5, - /// Transmit - Transmit = 0x6, - _, - }, - }, - padding: u29, - }), - reserved1056: [12]u8, - /// Sleep state during automatic collision resolution - SLEEPSTATE: mmio.Mmio(packed struct(u32) { - /// Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. - SLEEPSTATE: packed union { - raw: u1, - value: enum(u1) { - /// State is IDLE. - Idle = 0x0, - /// State is SLEEP_A. - SleepA = 0x1, - }, - }, - padding: u31, - }), - reserved1084: [24]u8, - /// Indicates the presence or not of a valid field - FIELDPRESENT: mmio.Mmio(packed struct(u32) { - /// Indicates if a valid field is present. Available only in the activated state. - FIELDPRESENT: packed union { - raw: u1, - value: enum(u1) { - /// No valid field detected - NoField = 0x0, - /// Valid field detected - FieldPresent = 0x1, - }, - }, - /// Indicates if the low level has locked to the field - LOCKDETECT: packed union { - raw: u1, - value: enum(u1) { - /// Not locked to field - NotLocked = 0x0, - /// Locked to field - Locked = 0x1, - }, - }, - padding: u30, - }), - reserved1284: [196]u8, - /// Minimum frame delay - FRAMEDELAYMIN: mmio.Mmio(packed struct(u32) { - /// Minimum frame delay in number of 13.56 MHz clocks - FRAMEDELAYMIN: u16, - padding: u16, - }), - /// Maximum frame delay - FRAMEDELAYMAX: mmio.Mmio(packed struct(u32) { - /// Maximum frame delay in number of 13.56 MHz clocks - FRAMEDELAYMAX: u20, - padding: u12, - }), - /// Configuration register for the Frame Delay Timer - FRAMEDELAYMODE: mmio.Mmio(packed struct(u32) { - /// Configuration register for the Frame Delay Timer - FRAMEDELAYMODE: packed union { - raw: u2, - value: enum(u2) { - /// Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. - FreeRun = 0x0, - /// Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX - Window = 0x1, - /// Frame is transmitted exactly at FRAMEDELAYMAX - ExactVal = 0x2, - /// Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX - WindowGrid = 0x3, - }, - }, - padding: u30, - }), - /// Packet pointer for TXD and RXD data storage in Data RAM - PACKETPTR: mmio.Mmio(packed struct(u32) { - /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. - PTR: u32, - }), - /// Size of the RAM buffer allocated to TXD and RXD data storage each - MAXLEN: mmio.Mmio(packed struct(u32) { - /// Size of the RAM buffer allocated to TXD and RXD data storage each - MAXLEN: u9, - padding: u23, - }), - reserved1424: [120]u8, - /// Last NFCID1 part (4, 7 or 10 bytes ID) - NFCID1_LAST: mmio.Mmio(packed struct(u32) { - /// NFCID1 byte Z (very last byte sent) - NFCID1_Z: u8, - /// NFCID1 byte Y - NFCID1_Y: u8, - /// NFCID1 byte X - NFCID1_X: u8, - /// NFCID1 byte W - NFCID1_W: u8, - }), - /// Second last NFCID1 part (7 or 10 bytes ID) - NFCID1_2ND_LAST: mmio.Mmio(packed struct(u32) { - /// NFCID1 byte V - NFCID1_V: u8, - /// NFCID1 byte U - NFCID1_U: u8, - /// NFCID1 byte T - NFCID1_T: u8, - padding: u8, - }), - /// Third last NFCID1 part (10 bytes ID) - NFCID1_3RD_LAST: mmio.Mmio(packed struct(u32) { - /// NFCID1 byte S - NFCID1_S: u8, - /// NFCID1 byte R - NFCID1_R: u8, - /// NFCID1 byte Q - NFCID1_Q: u8, - padding: u8, - }), - /// Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. - AUTOCOLRESCONFIG: mmio.Mmio(packed struct(u32) { - /// Enables/disables auto collision resolution - MODE: packed union { - raw: u1, - value: enum(u1) { - /// Auto collision resolution enabled - Enabled = 0x0, - /// Auto collision resolution disabled - Disabled = 0x1, - }, - }, - padding: u31, - }), - /// NFC-A SENS_RES auto-response settings - SENSRES: mmio.Mmio(packed struct(u32) { - /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - BITFRAMESDD: packed union { - raw: u5, - value: enum(u5) { - /// SDD pattern 00000 - SDD00000 = 0x0, - /// SDD pattern 00001 - SDD00001 = 0x1, - /// SDD pattern 00010 - SDD00010 = 0x2, - /// SDD pattern 00100 - SDD00100 = 0x4, - /// SDD pattern 01000 - SDD01000 = 0x8, - /// SDD pattern 10000 - SDD10000 = 0x10, - _, - }, - }, - /// Reserved for future use. Shall be 0. - RFU5: u1, - /// NFCID1 size. This value is used by the auto collision resolution engine. - NFCIDSIZE: packed union { - raw: u2, - value: enum(u2) { - /// NFCID1 size: single (4 bytes) - NFCID1Single = 0x0, - /// NFCID1 size: double (7 bytes) - NFCID1Double = 0x1, - /// NFCID1 size: triple (10 bytes) - NFCID1Triple = 0x2, - _, - }, - }, - /// Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - PLATFCONFIG: u4, - /// Reserved for future use. Shall be 0. - RFU74: u4, - padding: u16, - }), - /// NFC-A SEL_RES auto-response settings - SELRES: mmio.Mmio(packed struct(u32) { - /// Reserved for future use. Shall be 0. - RFU10: u2, - /// Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) - CASCADE: u1, - /// Reserved for future use. Shall be 0. - RFU43: u2, - /// Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - PROTOCOL: u2, - /// Reserved for future use. Shall be 0. - RFU7: u1, - padding: u24, - }), - }; - - /// GPIO Tasks and Events - pub const GPIOTE = extern struct { - /// Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. - TASKS_OUT: [8]mmio.Mmio(packed struct(u32) { - /// Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. - TASKS_OUT: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved48: [16]u8, - /// Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. - TASKS_SET: [8]mmio.Mmio(packed struct(u32) { - /// Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. - TASKS_SET: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved96: [16]u8, - /// Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. - TASKS_CLR: [8]mmio.Mmio(packed struct(u32) { - /// Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. - TASKS_CLR: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [128]u8, - /// Description collection: Event generated from pin specified in CONFIG[n].PSEL - EVENTS_IN: [8]mmio.Mmio(packed struct(u32) { - /// Event generated from pin specified in CONFIG[n].PSEL - EVENTS_IN: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved380: [92]u8, - /// Event generated from multiple input GPIO pins with SENSE mechanism enabled - EVENTS_PORT: mmio.Mmio(packed struct(u32) { - /// Event generated from multiple input GPIO pins with SENSE mechanism enabled - EVENTS_PORT: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved772: [388]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event IN[0] - IN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event IN[1] - IN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event IN[2] - IN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event IN[3] - IN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event IN[4] - IN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event IN[5] - IN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event IN[6] - IN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event IN[7] - IN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved31: u23, - /// Write '1' to enable interrupt for event PORT - PORT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event IN[0] - IN0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event IN[1] - IN1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event IN[2] - IN2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event IN[3] - IN3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event IN[4] - IN4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event IN[5] - IN5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event IN[6] - IN6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event IN[7] - IN7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved31: u23, - /// Write '1' to disable interrupt for event PORT - PORT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - }), - reserved1296: [516]u8, - /// Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event - CONFIG: [8]mmio.Mmio(packed struct(u32) { - /// Mode - MODE: packed union { - raw: u2, - value: enum(u2) { - /// Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. - Disabled = 0x0, - /// Event mode - Event = 0x1, - /// Task mode - Task = 0x3, - _, - }, - }, - reserved8: u6, - /// GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event - PSEL: u5, - /// Port number - PORT: u1, - reserved16: u2, - /// When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. - POLARITY: packed union { - raw: u2, - value: enum(u2) { - /// Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. - None = 0x0, - /// Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. - LoToHi = 0x1, - /// Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. - HiToLo = 0x2, - /// Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. - Toggle = 0x3, - }, - }, - reserved20: u2, - /// When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. - OUTINIT: packed union { - raw: u1, - value: enum(u1) { - /// Task mode: Initial value of pin before task triggering is low - Low = 0x0, - /// Task mode: Initial value of pin before task triggering is high - High = 0x1, - }, - }, - padding: u11, - }), - }; - - /// Successive approximation register (SAR) analog-to-digital converter - pub const SAADC = extern struct { - /// Starts the SAADC and prepares the result buffer in RAM - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Starts the SAADC and prepares the result buffer in RAM - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Takes one SAADC sample - TASKS_SAMPLE: mmio.Mmio(packed struct(u32) { - /// Takes one SAADC sample - TASKS_SAMPLE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stops the SAADC and terminates all on-going conversions - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stops the SAADC and terminates all on-going conversions - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Starts offset auto-calibration - TASKS_CALIBRATEOFFSET: mmio.Mmio(packed struct(u32) { - /// Starts offset auto-calibration - TASKS_CALIBRATEOFFSET: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [240]u8, - /// The SAADC has started - EVENTS_STARTED: mmio.Mmio(packed struct(u32) { - /// The SAADC has started - EVENTS_STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// The SAADC has filled up the result buffer - EVENTS_END: mmio.Mmio(packed struct(u32) { - /// The SAADC has filled up the result buffer - EVENTS_END: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. - EVENTS_DONE: mmio.Mmio(packed struct(u32) { - /// A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. - EVENTS_DONE: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Result ready for transfer to RAM - EVENTS_RESULTDONE: mmio.Mmio(packed struct(u32) { - /// Result ready for transfer to RAM - EVENTS_RESULTDONE: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Calibration is complete - EVENTS_CALIBRATEDONE: mmio.Mmio(packed struct(u32) { - /// Calibration is complete - EVENTS_CALIBRATEDONE: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// The SAADC has stopped - EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { - /// The SAADC has stopped - EVENTS_STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved768: [488]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event DONE - DONE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event RESULTDONE - RESULTDONE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CALIBRATEDONE - CALIBRATEDONE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH0LIMITH - CH0LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH0LIMITL - CH0LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH1LIMITH - CH1LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH1LIMITL - CH1LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH2LIMITH - CH2LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH2LIMITL - CH2LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH3LIMITH - CH3LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH3LIMITL - CH3LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH4LIMITH - CH4LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH4LIMITL - CH4LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH5LIMITH - CH5LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH5LIMITL - CH5LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH6LIMITH - CH6LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH6LIMITL - CH6LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH7LIMITH - CH7LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CH7LIMITL - CH7LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u10, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event DONE - DONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event RESULTDONE - RESULTDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CALIBRATEDONE - CALIBRATEDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH0LIMITH - CH0LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH0LIMITL - CH0LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH1LIMITH - CH1LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH1LIMITL - CH1LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH2LIMITH - CH2LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH2LIMITL - CH2LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH3LIMITH - CH3LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH3LIMITL - CH3LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH4LIMITH - CH4LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH4LIMITL - CH4LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH5LIMITH - CH5LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH5LIMITL - CH5LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH6LIMITH - CH6LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH6LIMITL - CH6LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH7LIMITH - CH7LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CH7LIMITL - CH7LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u10, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event STARTED - STARTED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event DONE - DONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event RESULTDONE - RESULTDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CALIBRATEDONE - CALIBRATEDONE: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH0LIMITH - CH0LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH0LIMITL - CH0LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH1LIMITH - CH1LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH1LIMITL - CH1LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH2LIMITH - CH2LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH2LIMITL - CH2LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH3LIMITH - CH3LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH3LIMITL - CH3LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH4LIMITH - CH4LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH4LIMITL - CH4LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH5LIMITH - CH5LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH5LIMITL - CH5LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH6LIMITH - CH6LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH6LIMITL - CH6LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH7LIMITH - CH7LIMITH: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CH7LIMITL - CH7LIMITL: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u10, - }), - reserved1024: [244]u8, - /// Status - STATUS: mmio.Mmio(packed struct(u32) { - /// Status - STATUS: packed union { - raw: u1, - value: enum(u1) { - /// SAADC is ready. No on-going conversions. - Ready = 0x0, - /// SAADC is busy. Conversion in progress. - Busy = 0x1, - }, - }, - padding: u31, - }), - reserved1280: [252]u8, - /// Enable or disable SAADC - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable SAADC - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable SAADC - Disabled = 0x0, - /// Enable SAADC - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1520: [236]u8, - /// Resolution configuration - RESOLUTION: mmio.Mmio(packed struct(u32) { - /// Set the resolution - VAL: packed union { - raw: u3, - value: enum(u3) { - /// 8 bits - @"8bit" = 0x0, - /// 10 bits - @"10bit" = 0x1, - /// 12 bits - @"12bit" = 0x2, - /// 14 bits - @"14bit" = 0x3, - _, - }, - }, - padding: u29, - }), - /// Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. - OVERSAMPLE: mmio.Mmio(packed struct(u32) { - /// Oversample control - OVERSAMPLE: packed union { - raw: u4, - value: enum(u4) { - /// Bypass oversampling - Bypass = 0x0, - /// Oversample 2x - Over2x = 0x1, - /// Oversample 4x - Over4x = 0x2, - /// Oversample 8x - Over8x = 0x3, - /// Oversample 16x - Over16x = 0x4, - /// Oversample 32x - Over32x = 0x5, - /// Oversample 64x - Over64x = 0x6, - /// Oversample 128x - Over128x = 0x7, - /// Oversample 256x - Over256x = 0x8, - _, - }, - }, - padding: u28, - }), - /// Controls normal or continuous sample rate - SAMPLERATE: mmio.Mmio(packed struct(u32) { - /// Capture and compare value. Sample rate is 16 MHz/CC - CC: u11, - reserved12: u1, - /// Select mode for sample rate control - MODE: packed union { - raw: u1, - value: enum(u1) { - /// Rate is controlled from SAMPLE task - Task = 0x0, - /// Rate is controlled from local timer (use CC to control the rate) - Timers = 0x1, - }, - }, - padding: u19, - }), - }; - - /// Timer/Counter 0 - pub const TIMER0 = extern struct { - /// Start Timer - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Start Timer - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop Timer - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop Timer - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Increment Timer (Counter mode only) - TASKS_COUNT: mmio.Mmio(packed struct(u32) { - /// Increment Timer (Counter mode only) - TASKS_COUNT: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Clear time - TASKS_CLEAR: mmio.Mmio(packed struct(u32) { - /// Clear time - TASKS_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Deprecated register - Shut down timer - TASKS_SHUTDOWN: mmio.Mmio(packed struct(u32) { - /// Deprecated field - Shut down timer - TASKS_SHUTDOWN: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved64: [44]u8, - /// Description collection: Capture Timer value to CC[n] register - TASKS_CAPTURE: [6]mmio.Mmio(packed struct(u32) { - /// Capture Timer value to CC[n] register - TASKS_CAPTURE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved320: [232]u8, - /// Description collection: Compare event on CC[n] match - EVENTS_COMPARE: [6]mmio.Mmio(packed struct(u32) { - /// Compare event on CC[n] match - EVENTS_COMPARE: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [168]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between event COMPARE[0] and task CLEAR - COMPARE0_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event COMPARE[1] and task CLEAR - COMPARE1_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event COMPARE[2] and task CLEAR - COMPARE2_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event COMPARE[3] and task CLEAR - COMPARE3_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event COMPARE[4] and task CLEAR - COMPARE4_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event COMPARE[5] and task CLEAR - COMPARE5_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - reserved8: u2, - /// Shortcut between event COMPARE[0] and task STOP - COMPARE0_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event COMPARE[1] and task STOP - COMPARE1_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event COMPARE[2] and task STOP - COMPARE2_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event COMPARE[3] and task STOP - COMPARE3_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event COMPARE[4] and task STOP - COMPARE4_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event COMPARE[5] and task STOP - COMPARE5_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u18, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Write '1' to enable interrupt for event COMPARE[0] - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event COMPARE[1] - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event COMPARE[2] - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event COMPARE[3] - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event COMPARE[4] - COMPARE4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event COMPARE[5] - COMPARE5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u10, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Write '1' to disable interrupt for event COMPARE[0] - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event COMPARE[1] - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event COMPARE[2] - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event COMPARE[3] - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event COMPARE[4] - COMPARE4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event COMPARE[5] - COMPARE5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u10, - }), - reserved1284: [504]u8, - /// Timer mode selection - MODE: mmio.Mmio(packed struct(u32) { - /// Timer mode - MODE: packed union { - raw: u2, - value: enum(u2) { - /// Select Timer mode - Timer = 0x0, - /// Deprecated enumerator - Select Counter mode - Counter = 0x1, - /// Select Low Power Counter mode - LowPowerCounter = 0x2, - _, - }, - }, - padding: u30, - }), - /// Configure the number of bits used by the TIMER - BITMODE: mmio.Mmio(packed struct(u32) { - /// Timer bit width - BITMODE: packed union { - raw: u2, - value: enum(u2) { - /// 16 bit timer bit width - @"16Bit" = 0x0, - /// 8 bit timer bit width - @"08Bit" = 0x1, - /// 24 bit timer bit width - @"24Bit" = 0x2, - /// 32 bit timer bit width - @"32Bit" = 0x3, - }, - }, - padding: u30, - }), - reserved1296: [4]u8, - /// Timer prescaler register - PRESCALER: mmio.Mmio(packed struct(u32) { - /// Prescaler value - PRESCALER: u4, - padding: u28, - }), - reserved1344: [44]u8, - /// Description collection: Capture/Compare register n - CC: [6]mmio.Mmio(packed struct(u32) { - /// Capture/Compare value - CC: u32, - }), - }; - - /// FPU - pub const FPU = extern struct { - /// Unused. - UNUSED: u32, - }; - - /// Inter-IC Sound - pub const I2S = extern struct { - /// Starts continuous I2S transfer. Also starts MCK generator when this is enabled. - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Starts continuous I2S transfer. Also starts MCK generator when this is enabled. - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved260: [252]u8, - /// The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. - EVENTS_RXPTRUPD: mmio.Mmio(packed struct(u32) { - /// The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. - EVENTS_RXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// I2S transfer stopped. - EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { - /// I2S transfer stopped. - EVENTS_STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved276: [8]u8, - /// The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. - EVENTS_TXPTRUPD: mmio.Mmio(packed struct(u32) { - /// The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. - EVENTS_TXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved768: [488]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Enable or disable interrupt for event RXPTRUPD - RXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved5: u2, - /// Enable or disable interrupt for event TXPTRUPD - TXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u26, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to enable interrupt for event RXPTRUPD - RXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved5: u2, - /// Write '1' to enable interrupt for event TXPTRUPD - TXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u26, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Write '1' to disable interrupt for event RXPTRUPD - RXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved5: u2, - /// Write '1' to disable interrupt for event TXPTRUPD - TXPTRUPD: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u26, - }), - reserved1280: [500]u8, - /// Enable I2S module. - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable I2S module. - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - }; - - /// Real time counter 0 - pub const RTC0 = extern struct { - /// Start RTC COUNTER - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Start RTC COUNTER - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop RTC COUNTER - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop RTC COUNTER - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Clear RTC COUNTER - TASKS_CLEAR: mmio.Mmio(packed struct(u32) { - /// Clear RTC COUNTER - TASKS_CLEAR: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Set COUNTER to 0xFFFFF0 - TASKS_TRIGOVRFLW: mmio.Mmio(packed struct(u32) { - /// Set COUNTER to 0xFFFFF0 - TASKS_TRIGOVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [240]u8, - /// Event on COUNTER increment - EVENTS_TICK: mmio.Mmio(packed struct(u32) { - /// Event on COUNTER increment - EVENTS_TICK: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Event on COUNTER overflow - EVENTS_OVRFLW: mmio.Mmio(packed struct(u32) { - /// Event on COUNTER overflow - EVENTS_OVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved320: [56]u8, - /// Description collection: Compare event on CC[n] match - EVENTS_COMPARE: [4]mmio.Mmio(packed struct(u32) { - /// Compare event on CC[n] match - EVENTS_COMPARE: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved772: [436]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event TICK - TICK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event OVRFLW - OVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved16: u14, - /// Write '1' to enable interrupt for event COMPARE[0] - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event COMPARE[1] - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event COMPARE[2] - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event COMPARE[3] - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event TICK - TICK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event OVRFLW - OVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved16: u14, - /// Write '1' to disable interrupt for event COMPARE[0] - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event COMPARE[1] - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event COMPARE[2] - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event COMPARE[3] - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - reserved832: [52]u8, - /// Enable or disable event routing - EVTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable event routing for event TICK - TICK: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Disable - Enabled = 0x1, - }, - }, - /// Enable or disable event routing for event OVRFLW - OVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Disable - Enabled = 0x1, - }, - }, - reserved16: u14, - /// Enable or disable event routing for event COMPARE[0] - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Disable - Enabled = 0x1, - }, - }, - /// Enable or disable event routing for event COMPARE[1] - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Disable - Enabled = 0x1, - }, - }, - /// Enable or disable event routing for event COMPARE[2] - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Disable - Enabled = 0x1, - }, - }, - /// Enable or disable event routing for event COMPARE[3] - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Disable - Enabled = 0x1, - }, - }, - padding: u12, - }), - /// Enable event routing - EVTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable event routing for event TICK - TICK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable event routing for event OVRFLW - OVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved16: u14, - /// Write '1' to enable event routing for event COMPARE[0] - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable event routing for event COMPARE[1] - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable event routing for event COMPARE[2] - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable event routing for event COMPARE[3] - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - /// Disable event routing - EVTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable event routing for event TICK - TICK: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable event routing for event OVRFLW - OVRFLW: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved16: u14, - /// Write '1' to disable event routing for event COMPARE[0] - COMPARE0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable event routing for event COMPARE[1] - COMPARE1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable event routing for event COMPARE[2] - COMPARE2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable event routing for event COMPARE[3] - COMPARE3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u12, - }), - reserved1284: [440]u8, - /// Current COUNTER value - COUNTER: mmio.Mmio(packed struct(u32) { - /// Counter value - COUNTER: u24, - padding: u8, - }), - /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped - PRESCALER: mmio.Mmio(packed struct(u32) { - /// Prescaler value - PRESCALER: u12, - padding: u20, - }), - reserved1344: [52]u8, - /// Description collection: Compare register n - CC: [4]mmio.Mmio(packed struct(u32) { - /// Compare value - COMPARE: u24, - padding: u8, - }), - }; - - /// Temperature Sensor - pub const TEMP = extern struct { - /// Start temperature measurement - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Start temperature measurement - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop temperature measurement - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop temperature measurement - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [248]u8, - /// Temperature measurement complete, data ready - EVENTS_DATARDY: mmio.Mmio(packed struct(u32) { - /// Temperature measurement complete, data ready - EVENTS_DATARDY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved772: [512]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event DATARDY - DATARDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event DATARDY - DATARDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1288: [508]u8, - /// Temperature in degC (0.25deg steps) - TEMP: mmio.Mmio(packed struct(u32) { - /// Temperature in degC (0.25deg steps) - TEMP: u32, - }), - reserved1312: [20]u8, - /// Slope of 1st piece wise linear function - A0: mmio.Mmio(packed struct(u32) { - /// Slope of 1st piece wise linear function - A0: u12, - padding: u20, - }), - /// Slope of 2nd piece wise linear function - A1: mmio.Mmio(packed struct(u32) { - /// Slope of 2nd piece wise linear function - A1: u12, - padding: u20, - }), - /// Slope of 3rd piece wise linear function - A2: mmio.Mmio(packed struct(u32) { - /// Slope of 3rd piece wise linear function - A2: u12, - padding: u20, - }), - /// Slope of 4th piece wise linear function - A3: mmio.Mmio(packed struct(u32) { - /// Slope of 4th piece wise linear function - A3: u12, - padding: u20, - }), - /// Slope of 5th piece wise linear function - A4: mmio.Mmio(packed struct(u32) { - /// Slope of 5th piece wise linear function - A4: u12, - padding: u20, - }), - /// Slope of 6th piece wise linear function - A5: mmio.Mmio(packed struct(u32) { - /// Slope of 6th piece wise linear function - A5: u12, - padding: u20, - }), - reserved1344: [8]u8, - /// y-intercept of 1st piece wise linear function - B0: mmio.Mmio(packed struct(u32) { - /// y-intercept of 1st piece wise linear function - B0: u14, - padding: u18, - }), - /// y-intercept of 2nd piece wise linear function - B1: mmio.Mmio(packed struct(u32) { - /// y-intercept of 2nd piece wise linear function - B1: u14, - padding: u18, - }), - /// y-intercept of 3rd piece wise linear function - B2: mmio.Mmio(packed struct(u32) { - /// y-intercept of 3rd piece wise linear function - B2: u14, - padding: u18, - }), - /// y-intercept of 4th piece wise linear function - B3: mmio.Mmio(packed struct(u32) { - /// y-intercept of 4th piece wise linear function - B3: u14, - padding: u18, - }), - /// y-intercept of 5th piece wise linear function - B4: mmio.Mmio(packed struct(u32) { - /// y-intercept of 5th piece wise linear function - B4: u14, - padding: u18, - }), - /// y-intercept of 6th piece wise linear function - B5: mmio.Mmio(packed struct(u32) { - /// y-intercept of 6th piece wise linear function - B5: u14, - padding: u18, - }), - reserved1376: [8]u8, - /// End point of 1st piece wise linear function - T0: mmio.Mmio(packed struct(u32) { - /// End point of 1st piece wise linear function - T0: u8, - padding: u24, - }), - /// End point of 2nd piece wise linear function - T1: mmio.Mmio(packed struct(u32) { - /// End point of 2nd piece wise linear function - T1: u8, - padding: u24, - }), - /// End point of 3rd piece wise linear function - T2: mmio.Mmio(packed struct(u32) { - /// End point of 3rd piece wise linear function - T2: u8, - padding: u24, - }), - /// End point of 4th piece wise linear function - T3: mmio.Mmio(packed struct(u32) { - /// End point of 4th piece wise linear function - T3: u8, - padding: u24, - }), - /// End point of 5th piece wise linear function - T4: mmio.Mmio(packed struct(u32) { - /// End point of 5th piece wise linear function - T4: u8, - padding: u24, - }), - }; - - /// Random Number Generator - pub const RNG = extern struct { - /// Task starting the random number generator - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Task starting the random number generator - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Task stopping the random number generator - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Task stopping the random number generator - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [248]u8, - /// Event being generated for every new random number written to the VALUE register - EVENTS_VALRDY: mmio.Mmio(packed struct(u32) { - /// Event being generated for every new random number written to the VALUE register - EVENTS_VALRDY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [252]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between event VALRDY and task STOP - VALRDY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event VALRDY - VALRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event VALRDY - VALRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1284: [504]u8, - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Bias correction - DERCEN: packed union { - raw: u1, - value: enum(u1) { - /// Disabled - Disabled = 0x0, - /// Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Output random number - VALUE: mmio.Mmio(packed struct(u32) { - /// Generated random number - VALUE: u8, - padding: u24, - }), - }; - - /// AES ECB Mode Encryption - pub const ECB = extern struct { - /// Start ECB block encrypt - TASKS_STARTECB: mmio.Mmio(packed struct(u32) { - /// Start ECB block encrypt - TASKS_STARTECB: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Abort a possible executing ECB operation - TASKS_STOPECB: mmio.Mmio(packed struct(u32) { - /// Abort a possible executing ECB operation - TASKS_STOPECB: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [248]u8, - /// ECB block encrypt complete - EVENTS_ENDECB: mmio.Mmio(packed struct(u32) { - /// ECB block encrypt complete - EVENTS_ENDECB: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// ECB block encrypt aborted because of a STOPECB task or due to an error - EVENTS_ERRORECB: mmio.Mmio(packed struct(u32) { - /// ECB block encrypt aborted because of a STOPECB task or due to an error - EVENTS_ERRORECB: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved772: [508]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event ENDECB - ENDECB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ERRORECB - ERRORECB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u30, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event ENDECB - ENDECB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ERRORECB - ERRORECB: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u30, - }), - reserved1284: [504]u8, - /// ECB block encrypt memory pointers - ECBDATAPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to the ECB data structure (see Table 1 ECB data structure overview) - ECBDATAPTR: u32, - }), - }; - - /// Accelerated Address Resolver - pub const AAR = extern struct { - /// Start resolving addresses based on IRKs specified in the IRK data structure - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Start resolving addresses based on IRKs specified in the IRK data structure - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved8: [4]u8, - /// Stop resolving addresses - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop resolving addresses - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [244]u8, - /// Address resolution procedure complete - EVENTS_END: mmio.Mmio(packed struct(u32) { - /// Address resolution procedure complete - EVENTS_END: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Address resolved - EVENTS_RESOLVED: mmio.Mmio(packed struct(u32) { - /// Address resolved - EVENTS_RESOLVED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Address not resolved - EVENTS_NOTRESOLVED: mmio.Mmio(packed struct(u32) { - /// Address not resolved - EVENTS_NOTRESOLVED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved772: [504]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event RESOLVED - RESOLVED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event NOTRESOLVED - NOTRESOLVED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event END - END: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event RESOLVED - RESOLVED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event NOTRESOLVED - NOTRESOLVED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - reserved1024: [244]u8, - /// Resolution status - STATUS: mmio.Mmio(packed struct(u32) { - /// The IRK that was used last time an address was resolved - STATUS: u4, - padding: u28, - }), - reserved1280: [252]u8, - /// Enable AAR - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable AAR - ENABLE: packed union { - raw: u2, - value: enum(u2) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x3, - _, - }, - }, - padding: u30, - }), - /// Number of IRKs - NIRK: mmio.Mmio(packed struct(u32) { - /// Number of Identity root keys available in the IRK data structure - NIRK: u5, - padding: u27, - }), - /// Pointer to IRK data structure - IRKPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to the IRK data structure - IRKPTR: u32, - }), - reserved1296: [4]u8, - /// Pointer to the resolvable address - ADDRPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to the resolvable address (6-bytes) - ADDRPTR: u32, - }), - /// Pointer to data area used for temporary storage - SCRATCHPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. - SCRATCHPTR: u32, - }), - }; - - /// AES CCM Mode Encryption - pub const CCM = extern struct { - /// Start generation of key-stream. This operation will stop by itself when completed. - TASKS_KSGEN: mmio.Mmio(packed struct(u32) { - /// Start generation of key-stream. This operation will stop by itself when completed. - TASKS_KSGEN: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Start encryption/decryption. This operation will stop by itself when completed. - TASKS_CRYPT: mmio.Mmio(packed struct(u32) { - /// Start encryption/decryption. This operation will stop by itself when completed. - TASKS_CRYPT: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop encryption/decryption - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop encryption/decryption - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption - TASKS_RATEOVERRIDE: mmio.Mmio(packed struct(u32) { - /// Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption - TASKS_RATEOVERRIDE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [240]u8, - /// Key-stream generation complete - EVENTS_ENDKSGEN: mmio.Mmio(packed struct(u32) { - /// Key-stream generation complete - EVENTS_ENDKSGEN: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Encrypt/decrypt complete - EVENTS_ENDCRYPT: mmio.Mmio(packed struct(u32) { - /// Encrypt/decrypt complete - EVENTS_ENDCRYPT: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Deprecated register - CCM error event - EVENTS_ERROR: mmio.Mmio(packed struct(u32) { - /// Deprecated field - CCM error event - EVENTS_ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [244]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between event ENDKSGEN and task CRYPT - ENDKSGEN_CRYPT: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event ENDKSGEN - ENDKSGEN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ENDCRYPT - ENDCRYPT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Deprecated intsetfield - Write '1' to enable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event ENDKSGEN - ENDKSGEN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ENDCRYPT - ENDCRYPT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Deprecated intclrfield - Write '1' to disable interrupt for event ERROR - ERROR: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u29, - }), - reserved1024: [244]u8, - /// MIC check result - MICSTATUS: mmio.Mmio(packed struct(u32) { - /// The result of the MIC check performed during the previous decryption operation - MICSTATUS: packed union { - raw: u1, - value: enum(u1) { - /// MIC check failed - CheckFailed = 0x0, - /// MIC check passed - CheckPassed = 0x1, - }, - }, - padding: u31, - }), - reserved1280: [252]u8, - /// Enable - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable CCM - ENABLE: packed union { - raw: u2, - value: enum(u2) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x2, - _, - }, - }, - padding: u30, - }), - /// Operation mode - MODE: mmio.Mmio(packed struct(u32) { - /// The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. - MODE: packed union { - raw: u1, - value: enum(u1) { - /// AES CCM packet encryption mode - Encryption = 0x0, - /// AES CCM packet decryption mode - Decryption = 0x1, - }, - }, - reserved16: u15, - /// Radio data rate that the CCM shall run synchronous with - DATARATE: packed union { - raw: u2, - value: enum(u2) { - /// 1 Mbps - @"1Mbit" = 0x0, - /// 2 Mbps - @"2Mbit" = 0x1, - /// 125 Kbps - @"125Kbps" = 0x2, - /// 500 Kbps - @"500Kbps" = 0x3, - }, - }, - reserved24: u6, - /// Packet length configuration - LENGTH: packed union { - raw: u1, - value: enum(u1) { - /// Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. - Default = 0x0, - /// Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. - Extended = 0x1, - }, - }, - padding: u7, - }), - /// Pointer to data structure holding AES key and NONCE vector - CNFPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) - CNFPTR: u32, - }), - /// Input pointer - INPTR: mmio.Mmio(packed struct(u32) { - /// Input pointer - INPTR: u32, - }), - /// Output pointer - OUTPTR: mmio.Mmio(packed struct(u32) { - /// Output pointer - OUTPTR: u32, - }), - /// Pointer to data area used for temporary storage - SCRATCHPTR: mmio.Mmio(packed struct(u32) { - /// Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. - SCRATCHPTR: u32, - }), - /// Length of key-stream generated when MODE.LENGTH = Extended. - MAXPACKETSIZE: mmio.Mmio(packed struct(u32) { - /// Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. - MAXPACKETSIZE: u8, - padding: u24, - }), - /// Data rate override setting. - RATEOVERRIDE: mmio.Mmio(packed struct(u32) { - /// Data rate override setting. - RATEOVERRIDE: packed union { - raw: u2, - value: enum(u2) { - /// 1 Mbps - @"1Mbit" = 0x0, - /// 2 Mbps - @"2Mbit" = 0x1, - /// 125 Kbps - @"125Kbps" = 0x2, - /// 500 Kbps - @"500Kbps" = 0x3, - }, - }, - padding: u30, - }), - }; - - /// Watchdog Timer - pub const WDT = extern struct { - /// Start the watchdog - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Start the watchdog - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [252]u8, - /// Watchdog timeout - EVENTS_TIMEOUT: mmio.Mmio(packed struct(u32) { - /// Watchdog timeout - EVENTS_TIMEOUT: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved772: [512]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event TIMEOUT - TIMEOUT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event TIMEOUT - TIMEOUT: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1024: [244]u8, - /// Run status - RUNSTATUS: mmio.Mmio(packed struct(u32) { - /// Indicates whether or not the watchdog is running - RUNSTATUS: packed union { - raw: u1, - value: enum(u1) { - /// Watchdog not running - NotRunning = 0x0, - /// Watchdog is running - Running = 0x1, - }, - }, - padding: u31, - }), - /// Request status - REQSTATUS: mmio.Mmio(packed struct(u32) { - /// Request status for RR[0] register - RR0: packed union { - raw: u1, - value: enum(u1) { - /// RR[0] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[0] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[1] register - RR1: packed union { - raw: u1, - value: enum(u1) { - /// RR[1] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[1] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[2] register - RR2: packed union { - raw: u1, - value: enum(u1) { - /// RR[2] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[2] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[3] register - RR3: packed union { - raw: u1, - value: enum(u1) { - /// RR[3] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[3] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[4] register - RR4: packed union { - raw: u1, - value: enum(u1) { - /// RR[4] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[4] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[5] register - RR5: packed union { - raw: u1, - value: enum(u1) { - /// RR[5] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[5] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[6] register - RR6: packed union { - raw: u1, - value: enum(u1) { - /// RR[6] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[6] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - /// Request status for RR[7] register - RR7: packed union { - raw: u1, - value: enum(u1) { - /// RR[7] register is not enabled, or are already requesting reload - DisabledOrRequested = 0x0, - /// RR[7] register is enabled, and are not yet requesting reload - EnabledAndUnrequested = 0x1, - }, - }, - padding: u24, - }), - reserved1284: [252]u8, - /// Counter reload value - CRV: mmio.Mmio(packed struct(u32) { - /// Counter reload value in number of cycles of the 32.768 kHz clock - CRV: u32, - }), - /// Enable register for reload request registers - RREN: mmio.Mmio(packed struct(u32) { - /// Enable or disable RR[0] register - RR0: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[0] register - Disabled = 0x0, - /// Enable RR[0] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[1] register - RR1: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[1] register - Disabled = 0x0, - /// Enable RR[1] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[2] register - RR2: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[2] register - Disabled = 0x0, - /// Enable RR[2] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[3] register - RR3: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[3] register - Disabled = 0x0, - /// Enable RR[3] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[4] register - RR4: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[4] register - Disabled = 0x0, - /// Enable RR[4] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[5] register - RR5: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[5] register - Disabled = 0x0, - /// Enable RR[5] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[6] register - RR6: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[6] register - Disabled = 0x0, - /// Enable RR[6] register - Enabled = 0x1, - }, - }, - /// Enable or disable RR[7] register - RR7: packed union { - raw: u1, - value: enum(u1) { - /// Disable RR[7] register - Disabled = 0x0, - /// Enable RR[7] register - Enabled = 0x1, - }, - }, - padding: u24, - }), - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Configure the watchdog to either be paused, or kept running, while the CPU is sleeping - SLEEP: packed union { - raw: u1, - value: enum(u1) { - /// Pause watchdog while the CPU is sleeping - Pause = 0x0, - /// Keep the watchdog running while the CPU is sleeping - Run = 0x1, - }, - }, - reserved3: u2, - /// Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger - HALT: packed union { - raw: u1, - value: enum(u1) { - /// Pause watchdog while the CPU is halted by the debugger - Pause = 0x0, - /// Keep the watchdog running while the CPU is halted by the debugger - Run = 0x1, - }, - }, - padding: u28, - }), - reserved1536: [240]u8, - /// Description collection: Reload request n - RR: [8]mmio.Mmio(packed struct(u32) { - /// Reload request register - RR: packed union { - raw: u32, - value: enum(u32) { - /// Value to request a reload of the watchdog timer - Reload = 0x6e524635, - _, - }, - }, - }), - }; - - /// Memory Watch Unit - pub const MWU = extern struct { - reserved768: [768]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for event REGION0WA - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION0RA - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION1WA - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION1RA - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION2WA - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION2RA - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION3WA - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION3RA - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Enable or disable interrupt for event PREGION0WA - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event PREGION0RA - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event PREGION1WA - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event PREGION1RA - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u4, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event REGION0WA - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION0RA - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION1WA - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION1RA - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION2WA - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION2RA - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION3WA - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION3RA - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Write '1' to enable interrupt for event PREGION0WA - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event PREGION0RA - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event PREGION1WA - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event PREGION1RA - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event REGION0WA - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION0RA - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION1WA - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION1RA - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION2WA - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION2RA - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION3WA - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION3RA - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Write '1' to disable interrupt for event PREGION0WA - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event PREGION0RA - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event PREGION1WA - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event PREGION1RA - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - reserved800: [20]u8, - /// Enable or disable interrupt - NMIEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for event REGION0WA - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION0RA - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION1WA - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION1RA - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION2WA - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION2RA - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION3WA - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event REGION3RA - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Enable or disable interrupt for event PREGION0WA - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event PREGION0RA - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event PREGION1WA - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event PREGION1RA - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u4, - }), - /// Enable interrupt - NMIENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event REGION0WA - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION0RA - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION1WA - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION1RA - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION2WA - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION2RA - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION3WA - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REGION3RA - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Write '1' to enable interrupt for event PREGION0WA - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event PREGION0RA - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event PREGION1WA - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event PREGION1RA - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - /// Disable interrupt - NMIENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event REGION0WA - REGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION0RA - REGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION1WA - REGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION1RA - REGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION2WA - REGION2WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION2RA - REGION2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION3WA - REGION3WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REGION3RA - REGION3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Write '1' to disable interrupt for event PREGION0WA - PREGION0WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event PREGION0RA - PREGION0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event PREGION1WA - PREGION1WA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event PREGION1RA - PREGION1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - reserved1296: [484]u8, - /// Enable/disable regions watch - REGIONEN: mmio.Mmio(packed struct(u32) { - /// Enable/disable write access watch in region[0] - RGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this region - Disable = 0x0, - /// Enable write access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in region[0] - RGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this region - Disable = 0x0, - /// Enable read access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable write access watch in region[1] - RGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this region - Disable = 0x0, - /// Enable write access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in region[1] - RGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this region - Disable = 0x0, - /// Enable read access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable write access watch in region[2] - RGN2WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this region - Disable = 0x0, - /// Enable write access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in region[2] - RGN2RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this region - Disable = 0x0, - /// Enable read access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable write access watch in region[3] - RGN3WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this region - Disable = 0x0, - /// Enable write access watch in this region - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in region[3] - RGN3RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this region - Disable = 0x0, - /// Enable read access watch in this region - Enable = 0x1, - }, - }, - reserved24: u16, - /// Enable/disable write access watch in PREGION[0] - PRGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this PREGION - Disable = 0x0, - /// Enable write access watch in this PREGION - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in PREGION[0] - PRGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this PREGION - Disable = 0x0, - /// Enable read access watch in this PREGION - Enable = 0x1, - }, - }, - /// Enable/disable write access watch in PREGION[1] - PRGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Disable write access watch in this PREGION - Disable = 0x0, - /// Enable write access watch in this PREGION - Enable = 0x1, - }, - }, - /// Enable/disable read access watch in PREGION[1] - PRGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Disable read access watch in this PREGION - Disable = 0x0, - /// Enable read access watch in this PREGION - Enable = 0x1, - }, - }, - padding: u4, - }), - /// Enable regions watch - REGIONENSET: mmio.Mmio(packed struct(u32) { - /// Enable write access watch in region[0] - RGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in region[0] - RGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable write access watch in region[1] - RGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in region[1] - RGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable write access watch in region[2] - RGN2WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in region[2] - RGN2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable write access watch in region[3] - RGN3WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in region[3] - RGN3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Enable write access watch in PREGION[0] - PRGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this PREGION is disabled - Disabled = 0x0, - /// Write access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in PREGION[0] - PRGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this PREGION is disabled - Disabled = 0x0, - /// Read access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Enable write access watch in PREGION[1] - PRGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this PREGION is disabled - Disabled = 0x0, - /// Write access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Enable read access watch in PREGION[1] - PRGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this PREGION is disabled - Disabled = 0x0, - /// Read access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - /// Disable regions watch - REGIONENCLR: mmio.Mmio(packed struct(u32) { - /// Disable write access watch in region[0] - RGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in region[0] - RGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable write access watch in region[1] - RGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in region[1] - RGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable write access watch in region[2] - RGN2WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in region[2] - RGN2RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable write access watch in region[3] - RGN3WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this region is disabled - Disabled = 0x0, - /// Write access watch in this region is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in region[3] - RGN3RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this region is disabled - Disabled = 0x0, - /// Read access watch in this region is enabled - Enabled = 0x1, - }, - }, - reserved24: u16, - /// Disable write access watch in PREGION[0] - PRGN0WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this PREGION is disabled - Disabled = 0x0, - /// Write access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in PREGION[0] - PRGN0RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this PREGION is disabled - Disabled = 0x0, - /// Read access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Disable write access watch in PREGION[1] - PRGN1WA: packed union { - raw: u1, - value: enum(u1) { - /// Write access watch in this PREGION is disabled - Disabled = 0x0, - /// Write access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - /// Disable read access watch in PREGION[1] - PRGN1RA: packed union { - raw: u1, - value: enum(u1) { - /// Read access watch in this PREGION is disabled - Disabled = 0x0, - /// Read access watch in this PREGION is enabled - Enabled = 0x1, - }, - }, - padding: u4, - }), - }; - - /// Quadrature Decoder - pub const QDEC = extern struct { - /// Task starting the quadrature decoder - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Task starting the quadrature decoder - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Task stopping the quadrature decoder - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Task stopping the quadrature decoder - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Read and clear ACC and ACCDBL - TASKS_READCLRACC: mmio.Mmio(packed struct(u32) { - /// Read and clear ACC and ACCDBL - TASKS_READCLRACC: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Read and clear ACC - TASKS_RDCLRACC: mmio.Mmio(packed struct(u32) { - /// Read and clear ACC - TASKS_RDCLRACC: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Read and clear ACCDBL - TASKS_RDCLRDBL: mmio.Mmio(packed struct(u32) { - /// Read and clear ACCDBL - TASKS_RDCLRDBL: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [236]u8, - /// Event being generated for every new sample value written to the SAMPLE register - EVENTS_SAMPLERDY: mmio.Mmio(packed struct(u32) { - /// Event being generated for every new sample value written to the SAMPLE register - EVENTS_SAMPLERDY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Non-null report ready - EVENTS_REPORTRDY: mmio.Mmio(packed struct(u32) { - /// Non-null report ready - EVENTS_REPORTRDY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// ACC or ACCDBL register overflow - EVENTS_ACCOF: mmio.Mmio(packed struct(u32) { - /// ACC or ACCDBL register overflow - EVENTS_ACCOF: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Double displacement(s) detected - EVENTS_DBLRDY: mmio.Mmio(packed struct(u32) { - /// Double displacement(s) detected - EVENTS_DBLRDY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// QDEC has been stopped - EVENTS_STOPPED: mmio.Mmio(packed struct(u32) { - /// QDEC has been stopped - EVENTS_STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [236]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between event REPORTRDY and task READCLRACC - REPORTRDY_READCLRACC: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event SAMPLERDY and task STOP - SAMPLERDY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event REPORTRDY and task RDCLRACC - REPORTRDY_RDCLRACC: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event REPORTRDY and task STOP - REPORTRDY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event DBLRDY and task RDCLRDBL - DBLRDY_RDCLRDBL: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event DBLRDY and task STOP - DBLRDY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event SAMPLERDY and task READCLRACC - SAMPLERDY_READCLRACC: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u25, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event SAMPLERDY - SAMPLERDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event REPORTRDY - REPORTRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event ACCOF - ACCOF: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event DBLRDY - DBLRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u27, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event SAMPLERDY - SAMPLERDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event REPORTRDY - REPORTRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event ACCOF - ACCOF: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event DBLRDY - DBLRDY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event STOPPED - STOPPED: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved1280: [500]u8, - /// Enable the quadrature decoder - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable the quadrature decoder - ENABLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u31, - }), - /// LED output pin polarity - LEDPOL: mmio.Mmio(packed struct(u32) { - /// LED output pin polarity - LEDPOL: packed union { - raw: u1, - value: enum(u1) { - /// Led active on output pin low - ActiveLow = 0x0, - /// Led active on output pin high - ActiveHigh = 0x1, - }, - }, - padding: u31, - }), - /// Sample period - SAMPLEPER: mmio.Mmio(packed struct(u32) { - /// Sample period. The SAMPLE register will be updated for every new sample - SAMPLEPER: packed union { - raw: u4, - value: enum(u4) { - /// 128 us - @"128us" = 0x0, - /// 256 us - @"256us" = 0x1, - /// 512 us - @"512us" = 0x2, - /// 1024 us - @"1024us" = 0x3, - /// 2048 us - @"2048us" = 0x4, - /// 4096 us - @"4096us" = 0x5, - /// 8192 us - @"8192us" = 0x6, - /// 16384 us - @"16384us" = 0x7, - /// 32768 us - @"32ms" = 0x8, - /// 65536 us - @"65ms" = 0x9, - /// 131072 us - @"131ms" = 0xa, - _, - }, - }, - padding: u28, - }), - /// Motion sample value - SAMPLE: mmio.Mmio(packed struct(u32) { - /// Last motion sample - SAMPLE: u32, - }), - /// Number of samples to be taken before REPORTRDY and DBLRDY events can be generated - REPORTPER: mmio.Mmio(packed struct(u32) { - /// Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated - REPORTPER: packed union { - raw: u4, - value: enum(u4) { - /// 10 samples / report - @"10Smpl" = 0x0, - /// 40 samples / report - @"40Smpl" = 0x1, - /// 80 samples / report - @"80Smpl" = 0x2, - /// 120 samples / report - @"120Smpl" = 0x3, - /// 160 samples / report - @"160Smpl" = 0x4, - /// 200 samples / report - @"200Smpl" = 0x5, - /// 240 samples / report - @"240Smpl" = 0x6, - /// 280 samples / report - @"280Smpl" = 0x7, - /// 1 sample / report - @"1Smpl" = 0x8, - _, - }, - }, - padding: u28, - }), - /// Register accumulating the valid transitions - ACC: mmio.Mmio(packed struct(u32) { - /// Register accumulating all valid samples (not double transition) read from the SAMPLE register - ACC: u32, - }), - /// Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task - ACCREAD: mmio.Mmio(packed struct(u32) { - /// Snapshot of the ACC register. - ACCREAD: u32, - }), - reserved1320: [12]u8, - /// Enable input debounce filters - DBFEN: mmio.Mmio(packed struct(u32) { - /// Enable input debounce filters - DBFEN: packed union { - raw: u1, - value: enum(u1) { - /// Debounce input filters disabled - Disabled = 0x0, - /// Debounce input filters enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - reserved1344: [20]u8, - /// Time period the LED is switched ON prior to sampling - LEDPRE: mmio.Mmio(packed struct(u32) { - /// Period in us the LED is switched on prior to sampling - LEDPRE: u9, - padding: u23, - }), - /// Register accumulating the number of detected double transitions - ACCDBL: mmio.Mmio(packed struct(u32) { - /// Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). - ACCDBL: u4, - padding: u28, - }), - /// Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task - ACCDBLREAD: mmio.Mmio(packed struct(u32) { - /// Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. - ACCDBLREAD: u4, - padding: u28, - }), - }; - - /// Comparator - pub const COMP = extern struct { - /// Start comparator - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Start comparator - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop comparator - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop comparator - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Sample comparator value - TASKS_SAMPLE: mmio.Mmio(packed struct(u32) { - /// Sample comparator value - TASKS_SAMPLE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [244]u8, - /// COMP is ready and output is valid - EVENTS_READY: mmio.Mmio(packed struct(u32) { - /// COMP is ready and output is valid - EVENTS_READY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Downward crossing - EVENTS_DOWN: mmio.Mmio(packed struct(u32) { - /// Downward crossing - EVENTS_DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Upward crossing - EVENTS_UP: mmio.Mmio(packed struct(u32) { - /// Upward crossing - EVENTS_UP: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Downward or upward crossing - EVENTS_CROSS: mmio.Mmio(packed struct(u32) { - /// Downward or upward crossing - EVENTS_CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [240]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between event READY and task SAMPLE - READY_SAMPLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event READY and task STOP - READY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event DOWN and task STOP - DOWN_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event UP and task STOP - UP_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event CROSS and task STOP - CROSS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved768: [252]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event DOWN - DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event UP - UP: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event CROSS - CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u28, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event DOWN - DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event UP - UP: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CROSS - CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u28, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event DOWN - DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event UP - UP: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CROSS - CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u28, - }), - reserved1024: [244]u8, - /// Compare result - RESULT: mmio.Mmio(packed struct(u32) { - /// Result of last compare. Decision point SAMPLE task. - RESULT: packed union { - raw: u1, - value: enum(u1) { - /// Input voltage is below the threshold (VIN+ < VIN-) - Below = 0x0, - /// Input voltage is above the threshold (VIN+ > VIN-) - Above = 0x1, - }, - }, - padding: u31, - }), - reserved1280: [252]u8, - /// COMP enable - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable COMP - ENABLE: packed union { - raw: u2, - value: enum(u2) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x2, - _, - }, - }, - padding: u30, - }), - /// Pin select - PSEL: mmio.Mmio(packed struct(u32) { - /// Analog pin select - PSEL: packed union { - raw: u3, - value: enum(u3) { - /// AIN0 selected as analog input - AnalogInput0 = 0x0, - /// AIN1 selected as analog input - AnalogInput1 = 0x1, - /// AIN2 selected as analog input - AnalogInput2 = 0x2, - /// AIN3 selected as analog input - AnalogInput3 = 0x3, - /// AIN4 selected as analog input - AnalogInput4 = 0x4, - /// AIN5 selected as analog input - AnalogInput5 = 0x5, - /// AIN6 selected as analog input - AnalogInput6 = 0x6, - /// AIN7 selected as analog input - AnalogInput7 = 0x7, - }, - }, - padding: u29, - }), - /// Reference source select for single-ended mode - REFSEL: mmio.Mmio(packed struct(u32) { - /// Reference select - REFSEL: packed union { - raw: u3, - value: enum(u3) { - /// VREF = internal 1.2 V reference (VDD >= 1.7 V) - Int1V2 = 0x0, - /// VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) - Int1V8 = 0x1, - /// VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) - Int2V4 = 0x2, - /// VREF = VDD - VDD = 0x4, - /// VREF = AREF (VDD >= VREF >= AREFMIN) - ARef = 0x5, - _, - }, - }, - padding: u29, - }), - /// External reference select - EXTREFSEL: mmio.Mmio(packed struct(u32) { - /// External analog reference select - EXTREFSEL: packed union { - raw: u3, - value: enum(u3) { - /// Use AIN0 as external analog reference - AnalogReference0 = 0x0, - /// Use AIN1 as external analog reference - AnalogReference1 = 0x1, - /// Use AIN2 as external analog reference - AnalogReference2 = 0x2, - /// Use AIN3 as external analog reference - AnalogReference3 = 0x3, - /// Use AIN4 as external analog reference - AnalogReference4 = 0x4, - /// Use AIN5 as external analog reference - AnalogReference5 = 0x5, - /// Use AIN6 as external analog reference - AnalogReference6 = 0x6, - /// Use AIN7 as external analog reference - AnalogReference7 = 0x7, - }, - }, - padding: u29, - }), - reserved1328: [32]u8, - /// Threshold configuration for hysteresis unit - TH: mmio.Mmio(packed struct(u32) { - /// VDOWN = (THDOWN+1)/64*VREF - THDOWN: u6, - reserved8: u2, - /// VUP = (THUP+1)/64*VREF - THUP: u6, - padding: u18, - }), - /// Mode configuration - MODE: mmio.Mmio(packed struct(u32) { - /// Speed and power modes - SP: packed union { - raw: u2, - value: enum(u2) { - /// Low-power mode - Low = 0x0, - /// Normal mode - Normal = 0x1, - /// High-speed mode - High = 0x2, - _, - }, - }, - reserved8: u6, - /// Main operation modes - MAIN: packed union { - raw: u1, - value: enum(u1) { - /// Single-ended mode - SE = 0x0, - /// Differential mode - Diff = 0x1, - }, - }, - padding: u23, - }), - /// Comparator hysteresis enable - HYST: mmio.Mmio(packed struct(u32) { - /// Comparator hysteresis - HYST: packed union { - raw: u1, - value: enum(u1) { - /// Comparator hysteresis disabled - NoHyst = 0x0, - /// Comparator hysteresis enabled - Hyst50mV = 0x1, - }, - }, - padding: u31, - }), - }; - - /// Low Power Comparator - pub const LPCOMP = extern struct { - /// Start comparator - TASKS_START: mmio.Mmio(packed struct(u32) { - /// Start comparator - TASKS_START: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Stop comparator - TASKS_STOP: mmio.Mmio(packed struct(u32) { - /// Stop comparator - TASKS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - /// Sample comparator value - TASKS_SAMPLE: mmio.Mmio(packed struct(u32) { - /// Sample comparator value - TASKS_SAMPLE: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [244]u8, - /// LPCOMP is ready and output is valid - EVENTS_READY: mmio.Mmio(packed struct(u32) { - /// LPCOMP is ready and output is valid - EVENTS_READY: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Downward crossing - EVENTS_DOWN: mmio.Mmio(packed struct(u32) { - /// Downward crossing - EVENTS_DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Upward crossing - EVENTS_UP: mmio.Mmio(packed struct(u32) { - /// Upward crossing - EVENTS_UP: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - /// Downward or upward crossing - EVENTS_CROSS: mmio.Mmio(packed struct(u32) { - /// Downward or upward crossing - EVENTS_CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved512: [240]u8, - /// Shortcuts between local events and tasks - SHORTS: mmio.Mmio(packed struct(u32) { - /// Shortcut between event READY and task SAMPLE - READY_SAMPLE: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event READY and task STOP - READY_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event DOWN and task STOP - DOWN_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event UP and task STOP - UP_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - /// Shortcut between event CROSS and task STOP - CROSS_STOP: packed union { - raw: u1, - value: enum(u1) { - /// Disable shortcut - Disabled = 0x0, - /// Enable shortcut - Enabled = 0x1, - }, - }, - padding: u27, - }), - reserved772: [256]u8, - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event DOWN - DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event UP - UP: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event CROSS - CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u28, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event READY - READY: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event DOWN - DOWN: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event UP - UP: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event CROSS - CROSS: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u28, - }), - reserved1024: [244]u8, - /// Compare result - RESULT: mmio.Mmio(packed struct(u32) { - /// Result of last compare. Decision point SAMPLE task. - RESULT: packed union { - raw: u1, - value: enum(u1) { - /// Input voltage is below the reference threshold (VIN+ < VIN-). - Below = 0x0, - /// Input voltage is above the reference threshold (VIN+ > VIN-). - Above = 0x1, - }, - }, - padding: u31, - }), - reserved1280: [252]u8, - /// Enable LPCOMP - ENABLE: mmio.Mmio(packed struct(u32) { - /// Enable or disable LPCOMP - ENABLE: packed union { - raw: u2, - value: enum(u2) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - _, - }, - }, - padding: u30, - }), - /// Input pin select - PSEL: mmio.Mmio(packed struct(u32) { - /// Analog pin select - PSEL: packed union { - raw: u3, - value: enum(u3) { - /// AIN0 selected as analog input - AnalogInput0 = 0x0, - /// AIN1 selected as analog input - AnalogInput1 = 0x1, - /// AIN2 selected as analog input - AnalogInput2 = 0x2, - /// AIN3 selected as analog input - AnalogInput3 = 0x3, - /// AIN4 selected as analog input - AnalogInput4 = 0x4, - /// AIN5 selected as analog input - AnalogInput5 = 0x5, - /// AIN6 selected as analog input - AnalogInput6 = 0x6, - /// AIN7 selected as analog input - AnalogInput7 = 0x7, - }, - }, - padding: u29, - }), - /// Reference select - REFSEL: mmio.Mmio(packed struct(u32) { - /// Reference select - REFSEL: packed union { - raw: u4, - value: enum(u4) { - /// VDD * 1/8 selected as reference - Ref1_8Vdd = 0x0, - /// VDD * 2/8 selected as reference - Ref2_8Vdd = 0x1, - /// VDD * 3/8 selected as reference - Ref3_8Vdd = 0x2, - /// VDD * 4/8 selected as reference - Ref4_8Vdd = 0x3, - /// VDD * 5/8 selected as reference - Ref5_8Vdd = 0x4, - /// VDD * 6/8 selected as reference - Ref6_8Vdd = 0x5, - /// VDD * 7/8 selected as reference - Ref7_8Vdd = 0x6, - /// External analog reference selected - ARef = 0x7, - /// VDD * 1/16 selected as reference - Ref1_16Vdd = 0x8, - /// VDD * 3/16 selected as reference - Ref3_16Vdd = 0x9, - /// VDD * 5/16 selected as reference - Ref5_16Vdd = 0xa, - /// VDD * 7/16 selected as reference - Ref7_16Vdd = 0xb, - /// VDD * 9/16 selected as reference - Ref9_16Vdd = 0xc, - /// VDD * 11/16 selected as reference - Ref11_16Vdd = 0xd, - /// VDD * 13/16 selected as reference - Ref13_16Vdd = 0xe, - /// VDD * 15/16 selected as reference - Ref15_16Vdd = 0xf, - }, - }, - padding: u28, - }), - /// External reference select - EXTREFSEL: mmio.Mmio(packed struct(u32) { - /// External analog reference select - EXTREFSEL: packed union { - raw: u1, - value: enum(u1) { - /// Use AIN0 as external analog reference - AnalogReference0 = 0x0, - /// Use AIN1 as external analog reference - AnalogReference1 = 0x1, - }, - }, - padding: u31, - }), - reserved1312: [16]u8, - /// Analog detect configuration - ANADETECT: mmio.Mmio(packed struct(u32) { - /// Analog detect configuration - ANADETECT: packed union { - raw: u2, - value: enum(u2) { - /// Generate ANADETECT on crossing, both upward crossing and downward crossing - Cross = 0x0, - /// Generate ANADETECT on upward crossing only - Up = 0x1, - /// Generate ANADETECT on downward crossing only - Down = 0x2, - _, - }, - }, - padding: u30, - }), - reserved1336: [20]u8, - /// Comparator hysteresis enable - HYST: mmio.Mmio(packed struct(u32) { - /// Comparator hysteresis enable - HYST: packed union { - raw: u1, - value: enum(u1) { - /// Comparator hysteresis disabled - Disabled = 0x0, - /// Comparator hysteresis enabled - Enabled = 0x1, - }, - }, - padding: u31, - }), - }; - - /// Event Generator Unit 0 - pub const EGU0 = extern struct { - /// Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event - TASKS_TRIGGER: [16]mmio.Mmio(packed struct(u32) { - /// Trigger n for triggering the corresponding TRIGGERED[n] event - TASKS_TRIGGER: packed union { - raw: u1, - value: enum(u1) { - /// Trigger task - Trigger = 0x1, - _, - }, - }, - padding: u31, - }), - reserved256: [192]u8, - /// Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task - EVENTS_TRIGGERED: [16]mmio.Mmio(packed struct(u32) { - /// Event number n generated by triggering the corresponding TRIGGER[n] task - EVENTS_TRIGGERED: packed union { - raw: u1, - value: enum(u1) { - /// Event not generated - NotGenerated = 0x0, - /// Event generated - Generated = 0x1, - }, - }, - padding: u31, - }), - reserved768: [448]u8, - /// Enable or disable interrupt - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable interrupt for event TRIGGERED[0] - TRIGGERED0: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[1] - TRIGGERED1: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[2] - TRIGGERED2: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[3] - TRIGGERED3: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[4] - TRIGGERED4: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[5] - TRIGGERED5: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[6] - TRIGGERED6: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[7] - TRIGGERED7: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[8] - TRIGGERED8: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[9] - TRIGGERED9: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[10] - TRIGGERED10: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[11] - TRIGGERED11: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[12] - TRIGGERED12: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[13] - TRIGGERED13: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[14] - TRIGGERED14: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - /// Enable or disable interrupt for event TRIGGERED[15] - TRIGGERED15: packed union { - raw: u1, - value: enum(u1) { - /// Disable - Disabled = 0x0, - /// Enable - Enabled = 0x1, - }, - }, - padding: u16, - }), - /// Enable interrupt - INTENSET: mmio.Mmio(packed struct(u32) { - /// Write '1' to enable interrupt for event TRIGGERED[0] - TRIGGERED0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[1] - TRIGGERED1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[2] - TRIGGERED2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[3] - TRIGGERED3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[4] - TRIGGERED4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[5] - TRIGGERED5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[6] - TRIGGERED6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[7] - TRIGGERED7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[8] - TRIGGERED8: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[9] - TRIGGERED9: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[10] - TRIGGERED10: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[11] - TRIGGERED11: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[12] - TRIGGERED12: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[13] - TRIGGERED13: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[14] - TRIGGERED14: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to enable interrupt for event TRIGGERED[15] - TRIGGERED15: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u16, - }), - /// Disable interrupt - INTENCLR: mmio.Mmio(packed struct(u32) { - /// Write '1' to disable interrupt for event TRIGGERED[0] - TRIGGERED0: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[1] - TRIGGERED1: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[2] - TRIGGERED2: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[3] - TRIGGERED3: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[4] - TRIGGERED4: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[5] - TRIGGERED5: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[6] - TRIGGERED6: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[7] - TRIGGERED7: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[8] - TRIGGERED8: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[9] - TRIGGERED9: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[10] - TRIGGERED10: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[11] - TRIGGERED11: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[12] - TRIGGERED12: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[13] - TRIGGERED13: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[14] - TRIGGERED14: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - /// Write '1' to disable interrupt for event TRIGGERED[15] - TRIGGERED15: packed union { - raw: u1, - value: enum(u1) { - /// Read: Disabled - Disabled = 0x0, - /// Read: Enabled - Enabled = 0x1, - }, - }, - padding: u16, - }), - }; - - /// Software interrupt 0 - pub const SWI0 = extern struct { - /// Unused. - UNUSED: u32, - }; - - /// Programmable Peripheral Interconnect - pub const PPI = extern struct { - reserved1280: [1280]u8, - /// Channel enable register - CHEN: mmio.Mmio(packed struct(u32) { - /// Enable or disable channel 0 - CH0: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 1 - CH1: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 2 - CH2: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 3 - CH3: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 4 - CH4: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 5 - CH5: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 6 - CH6: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 7 - CH7: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 8 - CH8: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 9 - CH9: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 10 - CH10: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 11 - CH11: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 12 - CH12: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 13 - CH13: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 14 - CH14: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 15 - CH15: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 16 - CH16: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 17 - CH17: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 18 - CH18: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 19 - CH19: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 20 - CH20: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 21 - CH21: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 22 - CH22: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 23 - CH23: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 24 - CH24: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 25 - CH25: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 26 - CH26: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 27 - CH27: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 28 - CH28: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 29 - CH29: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 30 - CH30: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - /// Enable or disable channel 31 - CH31: packed union { - raw: u1, - value: enum(u1) { - /// Disable channel - Disabled = 0x0, - /// Enable channel - Enabled = 0x1, - }, - }, - }), - /// Channel enable set register - CHENSET: mmio.Mmio(packed struct(u32) { - /// Channel 0 enable set register. Writing '0' has no effect - CH0: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 1 enable set register. Writing '0' has no effect - CH1: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 2 enable set register. Writing '0' has no effect - CH2: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 3 enable set register. Writing '0' has no effect - CH3: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 4 enable set register. Writing '0' has no effect - CH4: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 5 enable set register. Writing '0' has no effect - CH5: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 6 enable set register. Writing '0' has no effect - CH6: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 7 enable set register. Writing '0' has no effect - CH7: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 8 enable set register. Writing '0' has no effect - CH8: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 9 enable set register. Writing '0' has no effect - CH9: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 10 enable set register. Writing '0' has no effect - CH10: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 11 enable set register. Writing '0' has no effect - CH11: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 12 enable set register. Writing '0' has no effect - CH12: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 13 enable set register. Writing '0' has no effect - CH13: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 14 enable set register. Writing '0' has no effect - CH14: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 15 enable set register. Writing '0' has no effect - CH15: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 16 enable set register. Writing '0' has no effect - CH16: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 17 enable set register. Writing '0' has no effect - CH17: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 18 enable set register. Writing '0' has no effect - CH18: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 19 enable set register. Writing '0' has no effect - CH19: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 20 enable set register. Writing '0' has no effect - CH20: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 21 enable set register. Writing '0' has no effect - CH21: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 22 enable set register. Writing '0' has no effect - CH22: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 23 enable set register. Writing '0' has no effect - CH23: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 24 enable set register. Writing '0' has no effect - CH24: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 25 enable set register. Writing '0' has no effect - CH25: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 26 enable set register. Writing '0' has no effect - CH26: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 27 enable set register. Writing '0' has no effect - CH27: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 28 enable set register. Writing '0' has no effect - CH28: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 29 enable set register. Writing '0' has no effect - CH29: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 30 enable set register. Writing '0' has no effect - CH30: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 31 enable set register. Writing '0' has no effect - CH31: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - }), - /// Channel enable clear register - CHENCLR: mmio.Mmio(packed struct(u32) { - /// Channel 0 enable clear register. Writing '0' has no effect - CH0: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 1 enable clear register. Writing '0' has no effect - CH1: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 2 enable clear register. Writing '0' has no effect - CH2: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 3 enable clear register. Writing '0' has no effect - CH3: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 4 enable clear register. Writing '0' has no effect - CH4: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 5 enable clear register. Writing '0' has no effect - CH5: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 6 enable clear register. Writing '0' has no effect - CH6: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 7 enable clear register. Writing '0' has no effect - CH7: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 8 enable clear register. Writing '0' has no effect - CH8: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 9 enable clear register. Writing '0' has no effect - CH9: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 10 enable clear register. Writing '0' has no effect - CH10: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 11 enable clear register. Writing '0' has no effect - CH11: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 12 enable clear register. Writing '0' has no effect - CH12: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 13 enable clear register. Writing '0' has no effect - CH13: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 14 enable clear register. Writing '0' has no effect - CH14: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 15 enable clear register. Writing '0' has no effect - CH15: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 16 enable clear register. Writing '0' has no effect - CH16: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 17 enable clear register. Writing '0' has no effect - CH17: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 18 enable clear register. Writing '0' has no effect - CH18: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 19 enable clear register. Writing '0' has no effect - CH19: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 20 enable clear register. Writing '0' has no effect - CH20: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 21 enable clear register. Writing '0' has no effect - CH21: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 22 enable clear register. Writing '0' has no effect - CH22: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 23 enable clear register. Writing '0' has no effect - CH23: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 24 enable clear register. Writing '0' has no effect - CH24: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 25 enable clear register. Writing '0' has no effect - CH25: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 26 enable clear register. Writing '0' has no effect - CH26: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 27 enable clear register. Writing '0' has no effect - CH27: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 28 enable clear register. Writing '0' has no effect - CH28: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 29 enable clear register. Writing '0' has no effect - CH29: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 30 enable clear register. Writing '0' has no effect - CH30: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - /// Channel 31 enable clear register. Writing '0' has no effect - CH31: packed union { - raw: u1, - value: enum(u1) { - /// Read: channel disabled - Disabled = 0x0, - /// Read: channel enabled - Enabled = 0x1, - }, - }, - }), - reserved2048: [756]u8, - /// Description collection: Channel group n - CHG: [6]mmio.Mmio(packed struct(u32) { - /// Include or exclude channel 0 - CH0: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 1 - CH1: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 2 - CH2: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 3 - CH3: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 4 - CH4: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 5 - CH5: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 6 - CH6: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 7 - CH7: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 8 - CH8: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 9 - CH9: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 10 - CH10: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 11 - CH11: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 12 - CH12: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 13 - CH13: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 14 - CH14: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 15 - CH15: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 16 - CH16: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 17 - CH17: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 18 - CH18: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 19 - CH19: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 20 - CH20: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 21 - CH21: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 22 - CH22: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 23 - CH23: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 24 - CH24: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 25 - CH25: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 26 - CH26: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 27 - CH27: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 28 - CH28: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 29 - CH29: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 30 - CH30: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - /// Include or exclude channel 31 - CH31: packed union { - raw: u1, - value: enum(u1) { - /// Exclude - Excluded = 0x0, - /// Include - Included = 0x1, - }, - }, - }), - }; - - /// Non Volatile Memory Controller - pub const NVMC = extern struct { - reserved1024: [1024]u8, - /// Ready flag - READY: mmio.Mmio(packed struct(u32) { - /// NVMC is ready or busy - READY: packed union { - raw: u1, - value: enum(u1) { - /// NVMC is busy (on-going write or erase operation) - Busy = 0x0, - /// NVMC is ready - Ready = 0x1, - }, - }, - padding: u31, - }), - reserved1032: [4]u8, - /// Ready flag - READYNEXT: mmio.Mmio(packed struct(u32) { - /// NVMC can accept a new write operation - READYNEXT: packed union { - raw: u1, - value: enum(u1) { - /// NVMC cannot accept any write operation - Busy = 0x0, - /// NVMC is ready - Ready = 0x1, - }, - }, - padding: u31, - }), - reserved1284: [248]u8, - /// Configuration register - CONFIG: mmio.Mmio(packed struct(u32) { - /// Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. - WEN: packed union { - raw: u2, - value: enum(u2) { - /// Read only access - Ren = 0x0, - /// Write enabled - Wen = 0x1, - /// Erase enabled - Een = 0x2, - _, - }, - }, - padding: u30, - }), - /// Register for erasing a page in code area - ERASEPAGE: mmio.Mmio(packed struct(u32) { - /// Register for starting erase of a page in code area - ERASEPAGE: u32, - }), - /// Register for erasing all non-volatile user memory - ERASEALL: mmio.Mmio(packed struct(u32) { - /// Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. - ERASEALL: packed union { - raw: u1, - value: enum(u1) { - /// No operation - NoOperation = 0x0, - /// Start chip erase - Erase = 0x1, - }, - }, - padding: u31, - }), - /// Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. - ERASEPCR0: mmio.Mmio(packed struct(u32) { - /// Register for starting erase of a page in code area. Equivalent to ERASEPAGE. - ERASEPCR0: u32, - }), - /// Register for erasing user information configuration registers - ERASEUICR: mmio.Mmio(packed struct(u32) { - /// Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. - ERASEUICR: packed union { - raw: u1, - value: enum(u1) { - /// No operation - NoOperation = 0x0, - /// Start erase of UICR - Erase = 0x1, - }, - }, - padding: u31, - }), - /// Register for partial erase of a page in code area - ERASEPAGEPARTIAL: mmio.Mmio(packed struct(u32) { - /// Register for starting partial erase of a page in code area - ERASEPAGEPARTIAL: u32, - }), - /// Register for partial erase configuration - ERASEPAGEPARTIALCFG: mmio.Mmio(packed struct(u32) { - /// Duration of the partial erase in milliseconds - DURATION: u7, - padding: u25, - }), - reserved1344: [32]u8, - /// I-code cache configuration register. - ICACHECNF: mmio.Mmio(packed struct(u32) { - /// Cache enable - CACHEEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable cache. Invalidates all cache entries. - Disabled = 0x0, - /// Enable cache - Enabled = 0x1, - }, - }, - reserved8: u7, - /// Cache profiling enable - CACHEPROFEN: packed union { - raw: u1, - value: enum(u1) { - /// Disable cache profiling - Disabled = 0x0, - /// Enable cache profiling - Enabled = 0x1, - }, - }, - padding: u23, - }), - reserved1352: [4]u8, - /// I-code cache hit counter. - IHIT: mmio.Mmio(packed struct(u32) { - /// Number of cache hits - HITS: u32, - }), - /// I-code cache miss counter. - IMISS: mmio.Mmio(packed struct(u32) { - /// Number of cache misses - MISSES: u32, - }), - }; - }; -}; From 1e490a3d67c1f22e953fe2f36f4a4147584c7420 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= Date: Thu, 4 Jan 2024 08:53:39 +0100 Subject: [PATCH 20/20] Moves nrf5x to board-support/nordic-nrf5x --- README.adoc => board-support/nordic-nrf5x/README.adoc | 0 build.zig => board-support/nordic-nrf5x/build.zig | 0 build.zig.zon => board-support/nordic-nrf5x/build.zig.zon | 0 .../nordic-nrf5x/src}/boards/nrf52840-dongle.zig | 0 {src => board-support/nordic-nrf5x/src}/chips/nrf52.json | 0 {src => board-support/nordic-nrf5x/src}/chips/nrf52840.json | 0 {test => board-support/nordic-nrf5x/test}/nrf52840.robot | 0 {test => board-support/nordic-nrf5x/test}/programs/minimal.zig | 0 8 files changed, 0 insertions(+), 0 deletions(-) rename README.adoc => board-support/nordic-nrf5x/README.adoc (100%) rename build.zig => board-support/nordic-nrf5x/build.zig (100%) rename build.zig.zon => board-support/nordic-nrf5x/build.zig.zon (100%) rename {src => board-support/nordic-nrf5x/src}/boards/nrf52840-dongle.zig (100%) rename {src => board-support/nordic-nrf5x/src}/chips/nrf52.json (100%) rename {src => board-support/nordic-nrf5x/src}/chips/nrf52840.json (100%) rename {test => board-support/nordic-nrf5x/test}/nrf52840.robot (100%) rename {test => board-support/nordic-nrf5x/test}/programs/minimal.zig (100%) diff --git a/README.adoc b/board-support/nordic-nrf5x/README.adoc similarity index 100% rename from README.adoc rename to board-support/nordic-nrf5x/README.adoc diff --git a/build.zig b/board-support/nordic-nrf5x/build.zig similarity index 100% rename from build.zig rename to board-support/nordic-nrf5x/build.zig diff --git a/build.zig.zon b/board-support/nordic-nrf5x/build.zig.zon similarity index 100% rename from build.zig.zon rename to board-support/nordic-nrf5x/build.zig.zon diff --git a/src/boards/nrf52840-dongle.zig b/board-support/nordic-nrf5x/src/boards/nrf52840-dongle.zig similarity index 100% rename from src/boards/nrf52840-dongle.zig rename to board-support/nordic-nrf5x/src/boards/nrf52840-dongle.zig diff --git a/src/chips/nrf52.json b/board-support/nordic-nrf5x/src/chips/nrf52.json similarity index 100% rename from src/chips/nrf52.json rename to board-support/nordic-nrf5x/src/chips/nrf52.json diff --git a/src/chips/nrf52840.json b/board-support/nordic-nrf5x/src/chips/nrf52840.json similarity index 100% rename from src/chips/nrf52840.json rename to board-support/nordic-nrf5x/src/chips/nrf52840.json diff --git a/test/nrf52840.robot b/board-support/nordic-nrf5x/test/nrf52840.robot similarity index 100% rename from test/nrf52840.robot rename to board-support/nordic-nrf5x/test/nrf52840.robot diff --git a/test/programs/minimal.zig b/board-support/nordic-nrf5x/test/programs/minimal.zig similarity index 100% rename from test/programs/minimal.zig rename to board-support/nordic-nrf5x/test/programs/minimal.zig